Processor peripheral settings loading method and server system

Abstract

This application discloses a method for loading processor peripheral settings and a server system, relating to the field of server technology. The method reads the base address of a bidirectional two-wire serial bus and writes memory read / write capability enable and transmission configuration enable to a preset offset address space corresponding to the base address. Subsequently, it reads data from a specific address in memory using a multi-byte read method of the bidirectional two-wire serial bus protocol, verifies the read data, and updates motherboard variable information upon successful verification. It compares the actual processor model installed on the server with the processor model read from memory. If they match, the processor is correct, and the server will correctly load and configure the processor's peripheral settings according to the processor model specified in memory. This solves the problem of how to avoid incorrect configuration during server startup due to processor model mismatch, causing some motherboard functions to malfunction.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a method for loading peripheral settings of a processor and a server system. Background Technology

[0002] Existing motherboard solutions do not perform EEPROM (Electrically Erasable Programmable Read-Only Memory) security checks during startup. This can lead to incorrect configurations during server system startup due to CPU (Central Processing Unit, a key component of a computer) model incompatibility. Consequently, some motherboard functions may malfunction or the motherboard may be damaged, affecting subsequent motherboard operation.

[0003] In other words, the existing solution cannot avoid the possibility that the server will execute the wrong configuration when it starts up due to the mismatch of CPU models, which will cause some motherboard functions to fail to work properly. Summary of the Invention

[0004] This application provides a method for loading peripheral settings of a processor and a server system to at least solve the problem of how to avoid some motherboard functions from being unable to function properly due to incorrect configurations executed during server startup caused by processor model mismatch.

[0005] This application provides a method for loading peripheral settings of a processor, comprising: storing a motherboard mapping relationship in a memory based on a bidirectional two-wire serial bus protocol, wherein the motherboard mapping relationship is a mapping relationship between the motherboard model, motherboard type, and corresponding supported processor models; when the server system is started, assigning all motherboard variable information to undefined types, wherein the motherboard variable information includes the current motherboard model, current motherboard type, and current processor model; reading the peripheral parallel bus base address of the bidirectional two-wire serial bus, and writing the memory read / write capability enable and transmission configuration enable into the space of the sum of the peripheral parallel bus base address and a preset offset address, respectively; reading the address data to be verified from the memory using a multi-byte reading method based on the bidirectional two-wire serial bus protocol, performing a checksum processing on the address data to be verified, and performing a crash processing based on the first checksum result, or updating the motherboard variable information according to the motherboard mapping relationship, and determining whether to load the peripheral settings of the current processor based on the updated motherboard variable information and the actual processor model.

[0006] This application also provides a server system, including: a motherboard controller, a processor, and a memory, wherein the motherboard controller and the processor communicate with each other, the processor and the memory are electrically connected via a bidirectional two-wire serial bus, and the motherboard controller is used to execute a method for loading peripheral settings of any processor.

[0007] This application reads the base address of a bidirectional two-wire serial bus and writes the memory read / write capability enable and transmission configuration enable to the preset offset address space of the corresponding base address. Then, it reads data from a specific address in memory using the multi-byte read method of the bidirectional two-wire serial bus protocol, verifies the read data, and updates the motherboard variable information when the verification is successful. It compares the processor model actually installed on the server with the processor model read from the memory. If they match, it means that the processor is correct. The server will correctly load and configure the processor's peripheral settings according to the processor model specified in the memory, thereby solving the problem of how to avoid some motherboard functions from not working properly due to incorrect configuration when the server starts up because of processor model mismatch. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A flowchart illustrating a method for loading peripheral settings of a processor, provided in an embodiment of this application;

[0010] Figure 2 A flowchart illustrating another method for loading peripheral settings of a processor provided in an embodiment of this application;

[0011] Figure 3 A structural block diagram of a motherboard controller provided in an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the structure of a server system provided in an embodiment of this application.

[0013] The above figures include the following reference numerals:

[0014] 100. Motherboard controller; 200. Processor; 300. Memory. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] Embodiments of this application provide a method for loading processor peripheral settings, such as... Figure 1 As shown, the method includes the following steps:

[0019] Step S101: Store the motherboard mapping relationship in the memory based on the bidirectional two-wire serial bus protocol. The motherboard mapping relationship is the mapping relationship between the motherboard model, motherboard type and the corresponding supported processor models.

[0020] BIOS, short for Basic Input Output System, is a set of programs that run when a server starts up. It is usually stored in a read-only memory (ROM) chip on the computer's motherboard.

[0021] Step S102: When the server system is started, all motherboard variable information is assigned the value of undefined type. The motherboard variable information includes the current motherboard model, the current motherboard type, and the current processor model.

[0022] The current motherboard model refers to the specific model of the server's motherboard; the current motherboard type refers to the category or form factor of the motherboard, and each motherboard type includes multiple motherboard models; the current processor model refers to the specific model of the server's central processing unit.

[0023] Step S103: Read the base address of the peripheral parallel bus of the bidirectional two-wire serial bus, and write the memory read / write capability enable and the transmission configuration enable into the space of the sum of the peripheral parallel bus base address and the preset offset address, respectively.

[0024] The preset offset address can be 0x20.

[0025] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard.

[0026] When referring to reading the PCI (Peripheral Component Interconnect) base address space of the I2C bus (an Inter-Integrated Circuit, a two-wire serial bus used for data transmission between microcontrollers and passive components) via the BUS, DEV, and FUN numbers, the specific meaning is as follows:

[0027] BUS number: refers to the PCI bus number. A server may have multiple PCI buses, each with its own unique number. The BUS number is used to identify the target PCI bus.

[0028] Device Number: On a given PCI bus, each slot or device has its own unique number, called the Device Number. A PCI bus can have multiple devices, typically numbered starting from 0.

[0029] FUN number (Function number): In PCI devices, a single physical device may support multiple functions (or multiple logical devices). For example, a PCIe network card may simultaneously support network and management functions. Each function has its own unique number, called the Function number. Generally, the basic function number of a device is 0.

[0030] A device in the PCI configuration space can be uniquely located using its BUS number, DEV number, and FUN number. The configuration space contains various configuration information for the device, including the location of its I2C controller's Base Address Register (BAR). Reading the PCI base address of the I2C bus means reading the BAR of the corresponding PCI device's I2C controller, thereby determining the starting address of the I2C controller in memory mapping. This address is the interface between the I2C controller and the CPU; through it, the CPU can control I2C bus read and write operations.

[0031] Enabling I2C memory read capability means that I2C devices can be accessed directly through memory mapping, rather than just through I / O ports. This improves data transfer efficiency because memory access is generally faster than I / O access, and in some architectures, memory access can use caching to further accelerate the read and write process. Enabling the host function of the I2C bus (i.e., the function of transferring configuration) means that the CPU or master controller can actively control communication on the I2C bus, rather than just passively responding. This allows the host to manage slave devices more flexibly, such as performing fast read and write operations, configuring slave device parameters, or performing bus fault detection and management.

[0032] Step S104: Read the address data to be verified from the memory using a multi-byte read method based on a bidirectional two-wire serial bus protocol, perform checksum processing on the address data to be verified, and execute crash processing based on the first checksum result; or, update the motherboard variable information according to the motherboard mapping relationship, and determine whether to load the current processor's peripheral settings based on the updated motherboard variable information and the actual processor model.

[0033] A checksum is a method used to detect errors during data transmission or storage. It involves performing a mathematical operation (usually summation) on the data and appending the result to the data before transmission or storage. The receiver or reader applies the same mathematical operation to the original data again and compares the result to the received checksum. If they match, the data is considered unchanged during transmission or storage; if they do not match, it indicates that the data may have been corrupted or tampered with.

[0034] In the above steps, the server's memory (such as EEPROM) stores the mapping relationship between the motherboard model, motherboard type, and corresponding supported processor models using a bidirectional two-wire serial bus (i.e., I2C bus) protocol. This means that each motherboard records a list of CPU models it can perfectly work with, thus establishing the association between the motherboard and the CPU. When the server system starts up, the BIOS sets the critical variable information such as motherboard model, motherboard type, and processor model to "undefined type," meaning that the server is completely unaware of its own motherboard's characteristics before actually reading the memory information. Next, the BIOS reads the base address of the I2C bus and activates the I2C bus function by writing the memory read / write capability enable and transfer configuration enable to the preset offset address space of the corresponding base address. Subsequently, it uses the multi-byte read method of the I2C protocol to read data from a specific address in the memory. This data contains the motherboard's mapping relationship information. The BIOS verifies the read data. If the verification fails (e.g., checksum verification fails), it indicates that the data in the memory may have been tampered with or corrupted, and the server will directly execute a crash to prevent potential security risks. If the verification is successful, the BIOS will parse the data and update the motherboard variable information to reflect the correct motherboard model, type, and processor model. Crucially, the BIOS will also read the actual processor model installed on the server and compare this information with the processor model read from memory. If they do not match, it means the current motherboard and CPU (current processor) are incompatible, and the server will continue to execute crash procedures to avoid incorrect peripheral configurations. If they match, it means the CPU is correct, and the server will correctly load and configure the CPU's peripheral settings according to the processor model specified in the EEPROM, such as the number of PCI lanes (Peripheral Component Interconnect lane refers to the number of data transfer channels within a PCI Express interface), USB ports (Universal Serial Bus port, a standard interface on computer systems used to connect external devices such as keyboards, mice, printers, external hard drives, USB flash drives, mobile phones, and other electronic devices), network ports, etc. This ensures that all functions operate normally, avoiding functional deficiencies or abnormalities caused by CPU and motherboard incompatibility. This solves the problem of how to prevent incorrect configurations during server startup due to processor model incompatibility, which could cause some motherboard functions to malfunction.

[0035] This application can confirm the actual peripheral settings of the motherboard by reading the information in the EEPROM. These settings must be consistent with the peripherals supported by the CPU. If the EEPROM is damaged by human intervention or the installed CPU model is inconsistent with the CPU supported by the motherboard, the system will crash. This ensures the safety, reliability, and stability of the CPU and motherboard, avoids the technical problem of some motherboard interfaces becoming unusable due to incorrect CPU installation, guarantees the consistency of peripheral information between the motherboard and the CPU, improves the efficiency of motherboard use, and has significant beneficial effects and obvious technical advantages.

[0036] In one embodiment of this application, based on a first checksum result, a crash process is executed, or the motherboard variable information is updated according to the motherboard mapping relationship. This includes: preprocessing the first checksum result to obtain a first sum value, wherein the preprocessing includes: taking the remainder of the first checksum result to obtain a first remainder, and determining the first sum value as the sum of the first remainder and the last byte of data of the address data to be checked; if the first sum value is 0, a crash process is executed; if the first sum value is not 0, byte data at a preset offset address of the memory address is read, and the byte data is checked to obtain a second checksum result, and based on the second checksum result, a crash process is executed, or the motherboard variable information is updated according to the motherboard mapping relationship.

[0037] This application also provides a specific use case for performing crash handling or updating motherboard variable information based on motherboard mapping relationships: In a data center environment, maintenance personnel need to regularly maintain and upgrade servers, including BIOS and CPU updates. During this process, misoperation or insufficient compatibility checks may result in incompatible CPUs being installed on the server motherboard, or the BIOS image being incorrectly flashed onto an unsupported motherboard. For example, on a server motherboard that supports CPU model A, a CPU model B may be mistakenly installed, even though the number of PCI lanes and USB ports of CPU model B differs significantly from model A. In this situation, if the server continues to boot, there may be risks of instability, peripheral compatibility issues, and even data loss.

[0038] Preprocessing and Verification Logic: When reading data from the EEPROM for verification, a first sum is obtained by calculating the checksum and performing preprocessing. This process includes first calculating the remainder of the first checksum result, and then using the remainder to calculate the sum with the last byte. This preprocessing ensures data integrity, allowing for timely detection and crash handling even with slight data interference, preventing system anomalies caused by data errors. Multiple Verification Mechanism: In addition to the initial checksum check, there is further verification based on the second checksum result. This multiple verification mechanism increases the system's fault tolerance, ensuring that even in complex environments, the server can accurately determine hardware compatibility and configuration correctness, preventing misjudgments or system risks caused by single-point verification failures.

[0039] The beneficial effects of implementing crash handling, or updating motherboard variable information based on motherboard mapping relationships, in specific use cases include: determining CPU and motherboard compatibility at the initial server startup stage, avoiding startup attempts with incompatible hardware, and significantly improving system stability and reliability. Crash handling can immediately prevent potential problems from occurring, preventing the server from operating in an unstable state and protecting server and data security. In data centers, rapid identification and isolation of problematic hardware can significantly reduce troubleshooting time. This invention can identify the problem at the startup stage, allowing maintenance personnel to quickly pinpoint whether it's a CPU installation error or a BIOS flashing error, thus taking appropriate remedial measures and avoiding subsequent complex fault diagnosis processes, saving significant manpower and time costs. Hardware compatibility and configuration control are crucial in server and data center security strategies. This invention ensures that only the correct CPU and BIOS configuration can enable server startup, preventing potential security vulnerabilities such as unauthorized access or data leakage caused by configuration errors. Crash handling, as a last-line security barrier, can prevent unauthorized or non-compliant hardware startup, enhancing overall system security. For customers using servers, hardware stability and security are key factors determining their long-term trust in a particular brand. This invention ensures the reliability and security of the server at the hardware level through a rigorous verification mechanism, thereby increasing users' trust in the server and the management strategies behind it.

[0040] In one embodiment of this application, based on the second checksum result, a crash process is performed, or the motherboard variable information is updated according to the motherboard mapping relationship, including: preprocessing the second checksum result to obtain a second sum value; if the second sum value is 0, a crash process is performed; if the second sum value is not 0, the target product is determined to be the product of the data at the preset offset address and 2 to the power of n, and the target read address is determined to be the sum of the target product and a preset byte, where n is an integer and n≥0; the data at the target read address is read from the memory, and the data at the target read address is preprocessed to obtain a third sum value, and based on the third sum value, a crash process is performed, or the motherboard variable information is updated according to the motherboard mapping relationship.

[0041] By calculating the checksum and performing preprocessing, it is possible to effectively detect whether the data in the EEPROM has been tampered with or corrupted. If the second checksum value is 0, this usually means that the data verification has failed, possibly due to malicious modification of the data in the EEPROM or damage for other reasons. In this case, a shutdown can prevent the server from starting, preventing the use of corrupt or incorrect configuration information, thereby avoiding potential system failures or security risks. In practice, if the data format stored in the EEPROM is incorrect or the data is lost, direct reading may not immediately trigger a shutdown, but subsequent system initialization and configuration may fail due to data errors, leading to server instability. By checking the checksum before reading the data, such problems can be detected in advance, and a shutdown can be executed immediately, avoiding unnecessary subsequent misoperations and system anomalies. Determining the target product as the product of the data at a preset offset address and 2 to the power of n, and based on this, the target read address can be determined, allowing precise location of specific information stored in the EEPROM regarding the motherboard model, type, and CPU model. This process ensures that the read data is critical information compatible with the motherboard and CPU, thus preventing peripheral malfunctions caused by using incompatible CPUs and improving server stability and reliability. Determining the target read address as the product of a preset offset address and a power of 2 plus a preset number of bytes allows for targeted reading of critical data from the EEPROM, avoiding unnecessary data reads and improving read efficiency. Furthermore, based on this reading strategy, even with a large amount of data stored in the EEPROM, the required information can be quickly located and read, reducing system startup time. Based on the result of the third sum, motherboard variable information can be selectively updated. If the third sum verification is correct, the read data is valid, and the motherboard variable information can be safely updated according to the read motherboard mapping relationship, ensuring accurate configuration at server startup. If the verification fails, a crash is initiated; this process is simple and clear, avoiding complex data comparison and error handling logic.

[0042] In one embodiment of this application, the method further includes: preprocessing the second checksum result to obtain a second sum value; performing a crash process when the second sum value is 0; performing an AND operation on the data at a preset offset address when the second sum value is not 0 to obtain an AND operation result, and setting the target read address as the sum of the AND operation result and a preset value; reading the data at the target read address from the memory, preprocessing the data at the target read address to obtain a fourth sum value, and performing a crash process based on the fourth sum value, or updating the motherboard variable information according to the motherboard mapping relationship.

[0043] Specifically, preprocessing the checksum stored in the EEPROM allows for further checks to ensure the data has not been tampered with or corrupted. If the second sum is 0, it typically indicates a check failure, meaning the data may be invalid. Therefore, performing a crash test prevents the server from operating under incorrect or unexpected configurations, protecting system stability and security. By combining the processing result with a preset offset address and numerical value to calculate a new target read address, this method can precisely locate the motherboard model, type, and CPU model information stored in the EEPROM, ensuring the read data is correct and unaltered by external interference. If the second sum is not 0, it indicates the data stored in the EEPROM has passed the initial integrity check. Next, the data at the target read address is preprocessed to obtain a fourth sum. If this fourth sum also passes the check, the motherboard variables in the BIOS can be securely updated based on the read motherboard information, ensuring the server can correctly identify and configure hardware resources upon startup. These preprocessing steps effectively increase the complexity of accessing sensitive information in the EEPROM, making it difficult for unauthorized users to modify this information without leaving a trace. This helps prevent malicious attackers from gaining control of the server by modifying the BIOS image or data in the EEPROM. This automatic verification during server startup quickly identifies problems caused by incompatibility between motherboard variable information and the actual installed hardware, preventing potential compatibility issues and maintenance difficulties, and reducing customer complaints and operational costs. It also compares the CPU model information in the EEPROM with the actual installed CPU model to ensure consistency. If an inconsistency is detected, the server immediately shuts down, preventing functional abnormalities or performance degradation that may result from using an incompatible CPU, thus improving the overall stability and performance of the server.

[0044] In one embodiment of this application, a crash is performed based on the fourth sum value, or the motherboard variable information is updated according to the motherboard mapping relationship, including: performing a crash when the fourth sum value is 0; determining the target processor model based on the data of the motherboard mapping relationship and the target read address when the fourth sum value is not 0; and updating the current processor model of the motherboard variable information to the target processor model at least.

[0045] Specifically, if the data in the EEPROM is tampered with or accidentally deleted, resulting in a fourth sum of 0, it indicates that the data integrity of the EEPROM may be compromised. Downtime handling prevents the server from booting with incomplete or incorrect configurations, thus protecting system security and avoiding potential security threats, such as a replaced boot image or malicious alteration of CPU model information. By verifying that the CPU model matches the model recorded in the EEPROM, this mechanism ensures that the server uses the correct BIOS configuration and peripheral settings. This is crucial because different CPU models (such as models A, B, C, and D) may support different numbers of PCI lanes, USB ports, etc. If the CPU model is incompatible, even if the server boots, peripherals may malfunction or not at all, leading to data loss, performance degradation, or inaccessibility of certain functions. Downtime handling avoids these problems in such cases, ensuring functional correctness and system reliability. Downtime handling immediately interrupts the boot process upon detecting a mismatch between the CPU model and EEPROM information, which helps to quickly locate problems and reduce debugging time and costs. For server users, this mechanism provides clear fault information, guiding them to check for incorrect CPU installations or EEPROM data errors, allowing for swift and appropriate corrective action. When the current processor model in the motherboard variable information is correctly updated to the target processor model, the BIOS will initialize the correct peripheral settings based on the CPU's actual specifications. This means all hardware resources will be fully utilized, with no peripherals idle due to misconfiguration, thereby improving overall server performance and resource utilization.

[0046] In one embodiment of this application, determining whether to load the peripheral settings of the current processor based on the updated motherboard variable information and the actual processor model includes: loading the peripheral settings of the current processor if the current processor model in the updated motherboard variable information and the actual processor model are the same; and determining that the peripheral settings of the current processor do not need to be loaded if the current processor model in the updated motherboard variable information and the actual processor model are different.

[0047] Verifying processor model consistency ensures that the peripheral settings loaded by the BIOS match the actual installed CPU, thus preventing system instability, functional deficiencies, or performance degradation caused by peripheral mismatches. Different CPUs may support different numbers and types of peripherals, such as PCI lanes and USB ports. Loading the correct peripheral settings after successful processor model verification ensures the compatibility and functionality of all hardware components, preventing boot failures or system malfunctions due to hardware incompatibility. This mechanism prevents unauthorized modification of the BIOS image or booting with an incorrect CPU, protecting the server from security threats caused by reverse engineering, malware, or hardware incompatibility. The execution of crash handling in case of mismatch enhances the physical and logical security of the server. When the server fails to boot, crash handling immediately alerts the user to the CPU model mismatch, facilitating rapid problem identification, avoiding lengthy troubleshooting and potential misdiagnosis, and reducing maintenance costs and customer complaint rates. Accurately loading processor peripheral settings maximizes the utilization of CPU peripheral resources, preventing the unavailability of some resources due to improper settings, and ensuring the full and rational utilization of server hardware resources.

[0048] In one embodiment of this application, after updating the motherboard variable information, the method further includes: disabling the memory read / write capability and transmission configuration function of the bidirectional two-wire serial bus.

[0049] Specifically, immediately disabling advanced I2C bus functions after completing the necessary information reading can prevent potential attackers from using the I2C bus for further unauthorized access or tampering. For example, attackers might attempt to modify other devices stored on the I2C bus (such as sensors, power management units, etc.); disabling these functions can effectively prevent such attacks. Disabling unnecessary functions reduces system power consumption, especially in high-performance computing environments like servers, where every milliwatt saved can have a significant impact in large-scale deployments. Furthermore, this reduces contention for I2C bus resources, allowing other devices that need to use the bus to operate more smoothly. Prolonged use of advanced I2C functions can introduce instability, such as communication errors due to external interference or bus deadlocks caused by software errors. Timely disabling of these functions helps maintain stable system operation and reduces the risk of server failures during startup.

[0050] In one embodiment of this application, storing the motherboard mapping relationship in memory based on a bidirectional two-wire serial bus protocol includes: storing the motherboard mapping relationship in memory in binary form based on a bidirectional two-wire serial bus protocol.

[0051] Specifically, a bidirectional two-wire serial bus (such as I2C) uses only two lines for data transmission (one for data and the other for clock). Compared to traditional parallel buses, this significantly reduces the number of signal lines on the motherboard, simplifying hardware design, lowering production costs, and reducing the risk of electromagnetic interference. The binary format can compactly and efficiently store motherboard mappings, including configuration information for various peripherals (such as the number of PCI lanes supported by the CPU, the number of USB ports, etc.). This approach not only saves storage space but also makes the reading and parsing process faster, facilitating rapid boot and system configuration.

[0052] In one embodiment of this application, determining the peripheral settings of the current processor includes: setting a corresponding number of interfaces on the link peripheral settings of the current processor's peripheral parallel bus according to the processor model in the memory.

[0053] Specifically, by verifying the processor model, it ensures that the BIOS configuration matches the actual installed processor, avoiding system instability or security vulnerabilities caused by incorrect BIOS image flashing, such as misconfigured peripheral interfaces, which could be maliciously exploited to gain system control. Each processor may support different peripherals (such as the number of PCI lanes, USB ports, etc.), and correct processor model information ensures the system can initialize the correct peripheral links, preventing hardware malfunctions or performance degradation due to mismatched configurations. For server manufacturers, using a unified BIOS image can significantly reduce management and maintenance complexity, especially when supporting multiple CPUs. Processor model information stored in EEPROM can automatically adjust the BIOS configuration, eliminating the need to prepare a separate BIOS version for each processor model.

[0054] like Figure 2 As shown, the specific steps of the method in this application include:

[0055] The server motherboard burns the mapping relationship between the motherboard model, motherboard type, and CPU (processor) model into the EEPROM (memory) image physically connected to the I2C bus;

[0056] When the server starts, it first assigns the motherboard model, motherboard type, and processor model the value of "Unknown", which means undefined type.

[0057] Continue to start and execute the reading of EEPROM information. The EEPROM information needs to be obtained through the I2C bus. First, read the peripheral parallel bus base address space of the bidirectional two-wire serial bus through the BUS number, DEV number, and FUN number of the I2C bus.

[0058] The memory read / write capability enable and the transfer configuration enable are written into the space of the sum of the peripheral parallel bus base address and the preset offset address, respectively. That is, the data of the I2C bus PCI base address space + 0x20 is read and stored. At this time, it is the I2C bus PCI address space. The I2C bus address mounted by EEPROM is written into the PCI address space to initialize the I2C bus I / O read / write capability. Then, the I2C bus memory read capability is enabled by adding the I / O enable offset address 0x04 to the I2C bus PCI base address. Finally, the I2C bus host function of the address offset register of the I2C bus PCI base address + 0x40 is enabled.

[0059] The multi-byte read method based on the bidirectional two-wire serial bus protocol reads the address data to be verified from the memory and performs checksum processing on the address data to be verified. That is, the EEPROM address and I2C bus address, the starting offset address 0x00 and the multi-byte length (8 bytes) are read through the multi-byte read method of the I2C protocol. The preset condition indicates that the read 8 bytes of data will be checked. That is, the read 8 bytes are checked. If the check value is 256, the remainder is taken and added to the eighth byte of data to determine whether it is 0.

[0060] If the result is 0, the EEPROM data format is considered incorrect, and the system will crash immediately (this checks the EEPROM data format). If the result is not 0, the system continues to read the processor model information at the offset address. Specifically, it reads one byte of data at offset 0x03 of the EEPROM address and checks the return value. If the return value is 0, the system will crash immediately if the data does not exist. If the return value is not 0, the value at offset 0x03 is shifted left by 3 bits and an offset of 6 bytes is added to read the motherboard's supported CPU model information. If the result is 0, the system will crash. If the value is not 0, continue to AND the data at offset address 0x03 with the data at 0x3F (i.e., perform AND processing) and add 1 as the offset address. Read the motherboard type information of EEPROM byte by byte. If the return value is 0, the system will crash. If it is not 0, read the data at offset address 0x03 with the length of data at 0x3F based on the above offset address plus 1. If the return value is 0, the system will crash. If it is not 0, continue to execute and disable the I / O read / write capability of the I2C bus, write back the stored data, and disable the host function of the I2C bus.

[0061] The motherboard model, motherboard type, and CPU model are read via I2C and then assigned actual values. At the same time, the BIOS directly reads the actual installed CPU model information and compares it. If the information read from the CPU signal EEPROM is inconsistent with the actual CPU model, a crash is executed. If the comparison results are consistent, the corresponding number of PCI link peripherals is set according to the CPU model in the EEPROM.

[0062] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0063] Embodiments of this application also provide a motherboard controller, such as Figure 3 As shown, the motherboard controller includes:

[0064] The first processing unit 31 is used to store the motherboard mapping relationship into the memory based on the bidirectional two-wire serial bus protocol. The motherboard mapping relationship is the mapping relationship between the motherboard model, motherboard type and corresponding supported processor models.

[0065] The second processing unit 32 is used to assign all motherboard variable information to undefined types when the server system starts up. The motherboard variable information includes the current motherboard model, the current motherboard type, and the current processor model.

[0066] The third processing unit 33 is used to read the peripheral parallel bus base address of the bidirectional two-wire serial bus, and write the memory read / write capability enable and the transmission configuration enable into the space of the sum of the peripheral parallel bus base address and the preset offset address, respectively.

[0067] The fourth processing unit 34 is used to read the address data to be verified from the memory using a multi-byte read method based on a bidirectional two-wire serial bus protocol, perform checksum processing on the address data to be verified, and execute crash processing based on the first checksum result, or update the motherboard variable information according to the motherboard mapping relationship, and determine whether to load the peripheral settings of the current processor according to the updated motherboard variable information and the actual processor model.

[0068] In the aforementioned motherboard controller, the server's memory (such as EEPROM) stores the mapping relationship between the motherboard model, motherboard type, and corresponding supported processor models using a bidirectional two-wire serial bus (i.e., I2C bus) protocol. This means that each motherboard records a list of CPU models it can perfectly work with, thus establishing a correlation between the motherboard and the CPU. When the server system starts up, the BIOS sets key variable information such as motherboard model, motherboard type, and processor model to "undefined type," meaning that the server is completely unaware of its own motherboard's characteristics before actually reading the memory information. Next, the BIOS reads the base address of the I2C bus and activates the I2C bus function by writing memory read / write capability enable and transfer configuration enable to the preset offset address space of the corresponding base address. Subsequently, it uses the multi-byte read method of the I2C protocol to read data from a specific address in the memory. This data contains the motherboard's mapping relationship information. The BIOS verifies the read data. If the verification fails (e.g., checksum verification fails), it indicates that the data in the memory may have been tampered with or corrupted, and the server will directly execute a crash to prevent potential security risks. If the verification is successful, the BIOS will parse the data and update the motherboard variable information to reflect the correct motherboard model, type, and processor model. Crucially, the BIOS will also read the actual processor model installed on the server and compare this information with the processor model read from memory. If they do not match, it means the current motherboard and CPU (current processor) are incompatible, and the server will continue to execute crash procedures to avoid incorrect peripheral configuration. If they match, it means the CPU is correct, and the server will correctly load and configure the CPU's peripheral settings according to the processor model specified in the EEPROM, such as the number of PCI lanes (Peripheral Component Interconnect lanes), USB ports (Universal Serial Bus ports, a standard interface on computer systems used to connect external devices such as keyboards, mice, printers, external hard drives, USB flash drives, mobile phones, and other electronic devices), network ports, etc., thereby ensuring that all functions operate normally and avoiding functional deficiencies or abnormalities caused by CPU and motherboard incompatibility. This solves the problem of how to prevent incorrect configuration during server startup due to processor model incompatibility, which could cause some motherboard functions to malfunction.

[0069] In one embodiment of this application, the fourth processing unit includes: a first processing module for preprocessing the first checksum result to obtain a first sum value, wherein the preprocessing includes: taking the remainder of the first checksum result to obtain a first remainder, and determining the first sum value as the sum of the first remainder and the last byte of data of the address data to be checked; a second processing module for performing a crash process when the first sum value is 0; and a third processing module for reading byte data at a preset offset address of the memory address when the first sum value is not 0, performing checksum processing on the byte data to obtain a second checksum result, and performing a crash process based on the second checksum result, or updating motherboard variable information according to the motherboard mapping relationship.

[0070] In one embodiment of this application, the third processing module includes: a first processing submodule for preprocessing the second checksum result to obtain a second sum value; a second processing submodule for performing a crash process when the second sum value is 0; and a third processing submodule for determining, when the second sum value is not 0, the target product is the product of the data at a preset offset address and 2 to the power of n, and determining the target read address is the sum of the target product and a preset byte, where n is an integer and n≥0; reading the data at the target read address from the memory, preprocessing the data at the target read address to obtain a third sum value, and performing a crash process based on the third sum value, or updating the motherboard variable information according to the motherboard mapping relationship.

[0071] In one embodiment of this application, the motherboard controller further includes: a fifth processing unit for preprocessing the second checksum result to obtain a second sum value; and performing a crash process when the second sum value is 0; a sixth processing unit for performing an AND operation on the data at a preset offset address to obtain an AND operation result when the second sum value is not 0, and setting the target read address as the sum of the AND operation result and the preset value; and a seventh processing unit for reading the data at the target read address from the memory, preprocessing the data at the target read address to obtain a fourth sum value, and performing a crash process based on the fourth sum value, or updating the motherboard variable information according to the motherboard mapping relationship.

[0072] In one embodiment of this application, the seventh processing unit includes: a fourth processing module for performing a crash process when the fourth sum is 0; a fifth processing module for determining the target processor model based on the motherboard mapping relationship and the target read address when the fourth sum is not 0; and a sixth processing module for updating the current processor model of the motherboard variable information to the target processor model.

[0073] In one embodiment of this application, the fourth processing unit includes: a loading module for loading the peripheral settings of the current processor when the current processor model in the updated motherboard variable information is the same as the actual processor model; and a determining module for determining that the peripheral settings of the current processor do not need to be loaded when the current processor model in the updated motherboard variable information is different from the actual processor model.

[0074] In one embodiment of this application, the motherboard controller includes: an eighth processing unit configured to disable the memory read / write capability and configuration transmission function of the bidirectional two-wire serial bus after updating the motherboard variable information.

[0075] In one embodiment of this application, the first processing unit includes: a storage module for storing the motherboard mapping relationship in binary form to a memory based on a bidirectional two-wire serial bus protocol.

[0076] In one embodiment of this application, the fourth processing unit includes: a setting module for setting a corresponding number of interfaces on the link peripherals of the current processor's peripheral parallel bus according to the processor model in the memory.

[0077] For a description of the features in the embodiment corresponding to the motherboard controller, please refer to the relevant description of the embodiment corresponding to the loading method of the processor's peripheral settings, which will not be repeated here.

[0078] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the peripheral settings loading method embodiments of any of the above-described processors.

[0079] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiment of the peripheral settings loading method for any of the above-described processors when it is run.

[0080] This application also provides a server system, such as Figure 4As shown, the system includes a motherboard controller 100, a processor 200, and a memory 300. The motherboard controller and the processor communicate with each other, and the processor and memory are electrically connected via a bidirectional two-wire serial bus. The motherboard controller is used to execute a method for loading peripheral settings for any processor. It reads the base address of the bidirectional two-wire serial bus and writes the memory read / write capability enable and transmission configuration enable to the preset offset address space of the corresponding base address. Subsequently, it reads data from a specific address in the memory using the multi-byte read method of the bidirectional two-wire serial bus protocol. The read data is verified; if the verification is successful, the motherboard variable information is updated. The actual processor model installed on the server is compared with the processor model read from the memory. If they match, the processor is correct, and the server will correctly load and configure the processor's peripheral settings according to the processor model specified in the memory. This solves the problem of how to avoid incorrect configuration during server startup due to processor model mismatch, causing some motherboard functions to malfunction.

[0081] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0082] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the loading method embodiments of any of the processor's peripheral settings.

[0083] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the loading method embodiment of any of the processor's peripheral settings described above.

[0084] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0085] The foregoing has provided a detailed description of a method for loading peripheral settings for a processor and a server system provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for loading peripheral settings of a processor, characterized in that, include: The motherboard mapping relationship is stored in the memory based on the bidirectional two-wire serial bus protocol. The motherboard mapping relationship is the mapping relationship between the motherboard model, motherboard type and corresponding supported processor models. When the server system is started, all motherboard variable information is assigned the value of undefined type. The motherboard variable information includes the current motherboard model, the current motherboard type, and the current processor model. Read the base address of the peripheral parallel bus of the bidirectional two-wire serial bus, and write the memory read / write capability enable and the transmission configuration enable into the space of the sum of the peripheral parallel bus base address and the preset offset address, respectively; The system reads the address data to be verified from the memory using the multi-byte read method based on the bidirectional two-wire serial bus protocol, performs checksum processing on the address data to be verified, and executes crash processing based on the first checksum result. Alternatively, it updates the motherboard variable information according to the motherboard mapping relationship, and determines whether to load the current processor's peripheral settings based on the updated motherboard variable information and the actual processor model.

2. The method for loading processor peripheral settings according to claim 1, characterized in that, Based on the first checksum result, perform a crash handling procedure, or update the motherboard variable information according to the motherboard mapping relationship, including: The first checksum result is preprocessed to obtain a first sum value, wherein the preprocessing includes: taking the remainder of the first checksum result to obtain a first remainder, and determining the first sum value as the sum of the first remainder and the last byte of the address data to be checked; If the first sum is 0, a crash procedure is executed; If the first sum is not 0, read the byte data at the preset offset address of the memory address, perform checksum processing on the byte data to obtain a second checksum result, and perform a crash processing based on the second checksum result, or update the motherboard variable information according to the motherboard mapping relationship.

3. The method for loading processor peripheral settings according to claim 2, characterized in that, Based on the second checksum result, perform a crash handling procedure, or update the motherboard variable information according to the motherboard mapping relationship, including: The second checksum result is preprocessed to obtain the second sum value; If the second sum is 0, a crash procedure is executed; If the second sum is not 0, the target product is determined to be the product of the data at the preset offset address and 2 to the power of n, and the target read address is determined to be the sum of the target product and the preset byte, where n is an integer and n≥0; Data at the target read address is read from the memory, and the data at the target read address is preprocessed to obtain a third sum value. Based on the third sum value, a crash handling is performed, or the motherboard variable information is updated according to the motherboard mapping relationship.

4. The method for loading processor peripheral settings according to claim 2, characterized in that, The method further includes: The second checksum result is preprocessed to obtain the second sum value; If the second sum is 0, a crash procedure is executed; If the second sum is not 0, the data at the preset offset address is ANDed to obtain the AND processing result, and the target read address is the sum of the AND processing result and the preset value. Data at the target read address is read from the memory, and the data at the target read address is preprocessed to obtain a fourth sum value. Based on the fourth sum value, a crash handling is performed, or the motherboard variable information is updated according to the motherboard mapping relationship.

5. The method for loading processor peripheral settings according to claim 4, characterized in that, Based on the fourth sum, perform a crash handling procedure, or update the motherboard variable information according to the motherboard mapping relationship, including: If the fourth sum is 0, a crash procedure is executed; If the fourth sum is not 0, the target processor model is determined based on the motherboard mapping relationship and the target read address data; At least the current processor model in the motherboard variable information should be updated to the target processor model.

6. The method for loading processor peripheral settings according to claim 1, characterized in that, Based on the updated motherboard variable information and the actual processor model, determine whether to load the current processor's peripheral settings, including: If the current processor model in the updated motherboard variable information is the same as the actual processor model, load the peripheral settings of the current processor; If the current processor model in the updated motherboard variable information is different from the actual processor model, it is determined that the peripheral settings of the current processor do not need to be loaded.

7. The method for loading peripheral settings of a processor according to claim 1, characterized in that, After updating the motherboard variable information, the method further includes: The memory read / write capability and transmission configuration function of the bidirectional two-wire serial bus are disabled.

8. The method for loading processor peripheral settings according to claim 1, characterized in that, The motherboard mapping relationship is stored in memory based on a bidirectional two-wire serial bus protocol, including: Based on the bidirectional two-wire serial bus protocol, the motherboard mapping relationship is stored in the memory in binary form.

9. The method for loading peripheral settings of a processor according to any one of claims 1 to 8, characterized in that, Determine the current processor's peripheral settings to load, including: According to the processor model in the memory, a corresponding number of interfaces are set on the link peripherals of the current processor's peripheral parallel bus.

10. A server system, characterized in that, include: The system includes a motherboard controller, a processor, and a memory. The motherboard controller and the processor communicate with each other, and the processor and the memory are electrically connected via a bidirectional two-wire serial bus. The motherboard controller is used to execute the method for loading peripheral settings of the processor as described in any one of claims 1 to 9.

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