100pin AI core board

Abstract

The utility model belongs to the technical field of circuit boards of artificial intelligence equipment, in particular to a 100pin AI core board, which is characterized in that a plurality of pins are arranged on a side plate of a PCB (printed circuit board) of the 100pin AI core board, data interfaces formed by the pins comprise a microphone interface, a loudspeaker interface, a UART (universal asynchronous receiver / transmitter) interface and a GPIO (general purpose input / output) interface, the model of a processor on the PCB is RV1106G3, and the model of the processor on the PCB is RV1106G3. The processor has remarkable advantages in the aspects of computing power, image processing, coding, audio processing, low power consumption and the like, can meet operation and intelligent processing requirements when being used in the fields of security and protection equipment, image acquisition equipment, face recognition equipment and the like by being matched with different data interfaces, has good video data acquisition and processing functions, and can be widely applied to the fields of security and protection equipment, image acquisition equipment, face recognition equipment and the like. And various framework network models can be efficiently converted, and the requirements of intelligent equipment on data processing, image optimization and multi-camera cooperative work can be met.

Description

Technical Field

[0001] This utility model belongs to the field of circuit board technology for artificial intelligence devices, specifically relating to a 100-pin AI core board. Background Technology

[0002] The current market demand for core boards is highly diversified and dynamic. As digitalization continues across industries, expectations for core board functionality are constantly rising in sectors such as smart homes, industrial applications, and smart security. Simultaneously, consumer expectations for smart device functionality are also continuously increasing. The technology field is undergoing profound changes and rapid evolution, with cutting-edge technologies such as artificial intelligence, the Internet of Things, and big data accelerating their integration, and emerging technologies such as new sensor technologies and edge computing architectures constantly emerging. This requires devices to achieve high-speed data processing, multi-source fusion, and intelligent decision-making within limited space and energy consumption constraints. However, most existing core boards are designed for fixed application scenarios based on specific customer requirements, resulting in limited interface types and quantities. They struggle to meet complex and ever-changing demands in terms of computing performance, intelligent algorithm integration, and multi-device collaborative adaptation, falling short in addressing the comprehensive challenges of multi-scenario, multi-functional applications. Utility Model Content

[0003] This invention aims to provide a 100-pin AI core board to solve the problems in the field of artificial intelligence and the Internet of Things (AIIoT) where, in low-power scenarios, the insufficient computing and intelligent processing capabilities of devices, limited video data acquisition and processing functions, and difficulty in efficiently converting various framework network models, fail to meet the data processing, image optimization, and multi-camera collaborative work requirements of intelligent devices.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] A 100-pin AI core board is provided, comprising a PCB board, on which a processor and a memory are mounted. The PCB board has multiple pins, each containing multiple interfaces with different functions. The PCB board also has peripheral circuitry corresponding to the processor, memory, and each interface. There are a total of 100 pins, with 25 pins distributed on each of the four sides of the PCB board. The interfaces include a microphone interface, a speaker interface, an ADC interface, a MIPI_CSI interface, a USB interface, an SDIO interface, an I2C interface, an I2S interface, an SPI interface, a UART interface, and a GPIO interface. The processor is an RV1106G3. A power input interface is also provided among the 100 pins.

[0006] Preferably, the 100 pins are numbered 1 to 100, and the pins 1 to 100 are arranged counterclockwise on the four sides of the PCB board in sequence; wherein, pins 15 to 25, pins 27 and 28, pins 37 to 50, pins 52 to 59, pins 61 to 75, pins 77 to 81, pins 83 to 90, and pin 94 are all GPIO-reusable pins.

[0007] Preferably, the microphone interface is composed of pins 97, 98, 99, and 100; the speaker interface is composed of pins 9, 10, and 96; the MIPI_CSI interface is composed of pins 61 to 75; the USB interface is composed of pins 11, 12, and 13; the SDIO interface is composed of pins 83 to 89; the I2C interface is composed of pins 16, 17, 77, and 78; the UART interface is composed of pins 18 to 25 and pins 27 and 28; and the ADC interface, I2S interface, and SPI interface are composed of pins selected from the GPIO multiplexable pins.

[0008] Preferably, the pin is a gold finger arranged on the side of the PCB board.

[0009] Preferably, the gold fingers are stamp hole pins located on the side of the PCB board.

[0010] Preferably, the PCB board is square with a side length of 36mm; each pin is evenly distributed on the four sides of the PCB board, and the distance between adjacent pins on the same side is 1.27mm; the distance between the outermost pin on the same side of the PCB board and the adjacent side is 2.76mm.

[0011] Compared with the prior art, the beneficial effects of this utility model are as follows: The onboard devices of this 100-pin AI core board include a processor and a memory. Stamp hole pins for interfacing with an external base plate are provided on the side of the PCB board. Multiple pins corresponding to data interfaces are defined on the stamp hole pins. These data interfaces include a microphone interface, a speaker interface, an ADC interface, a MIPI_CSI interface, a USB interface, an SDIO interface, an I2C interface, an I2S interface, an SPI interface, a UART interface, and a GPIO interface. The processor model is RV1106G3. This processor has significant advantages in computing power, image processing, encoding, audio processing, and low power consumption. Combined with the different data interfaces configured in the 100-pin AI core board, the development performance of the core board is improved to meet the multi-scenario development needs of users and the functional expansion needs in specific scenarios. When used in security equipment, image acquisition equipment, face recognition equipment, and other fields, it can meet the computing and intelligent processing needs, has good video data acquisition and processing functions, and can efficiently convert various framework network models, thus meeting the needs of intelligent devices for data processing, image optimization, and multi-camera collaborative work. Attached Figure Description

[0012] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:

[0013] Figure 1 This is a front structural diagram of an embodiment of the 100-pin AI core board of this utility model.

[0014] Figure 2 This is a schematic diagram of the reverse side structure of an embodiment of the 100-pin AI core board of this utility model.

[0015] Figure 3 This is a schematic diagram of the pin numbers of an embodiment of the 100-pin AI core board of this utility model.

[0016] Figure 4 This is a front view of an embodiment of the 100-pin AI core board of this utility model.

[0017] Figure 5 This is a reverse dimension view of an embodiment of the 100-pin AI core board of this utility model.

[0018] Figure 6 This is a pin circuit diagram of an embodiment of the 100-pin AI core board of this utility model. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0020] In one embodiment, a 100-pin AI core board is provided; please refer to [link / reference]. Figures 1 to 6 .

[0021] like Figure 1 As shown, the 100-pin AI core board includes a PCB board 1, on which a processor 2 and a memory 3 are mounted. The memory 3 is electrically connected to the processor 2 through the internal circuitry of the PCB board 1. The processor 2 can read and write data from the memory 3. The PCB board 1 has multiple pins 11, which are used to connect the 100-pin AI core board to other circuit boards or sockets for power supply and signal transmission. The pins have multiple interfaces with different functions, which implement different communication functions. There are a total of 100 pins 11, with 25 pins distributed on each of the four sides of the PCB board. These interfaces with different functions include a microphone interface, a speaker interface, an ADC interface, a MIPI_CSI interface, a USB interface, an SDIO interface, an I2C interface, an I2S interface, an SPI interface, a UART interface, and a GPIO interface.

[0022] The functions of each data interface are as follows: The microphone interface is mainly used to connect a microphone to input sound signals. The speaker interface is used to connect a speaker or other audio output devices to convert the audio signal processed by the core board into sound output. The ADC interface is used to acquire analog signals and can connect to devices such as temperature and humidity sensors and pressure sensors.

[0023] The MIPI_CSI interface is used to connect cameras; it can also be converted to an HDMI interface via a converter chip, which is another display interface. The USB interface can be used to connect devices such as USB flash drives and mice, and can also be converted to different functional interfaces via a converter chip, such as 100Mbps Ethernet or TTL. The SDIO interface is mainly used to connect storage devices such as SD cards. The I2S interface (also written as IIS or I²S) is used to transmit audio signals; the IIC interface (also written as I2C or I²C), SPI interface, and UART interface are all general-purpose communication protocol interfaces that can be used to connect to many devices, such as laptops, ID card readers, OLED displays, and RTC modules, and have a wide range of applications. The GPIO interface can simulate most of the above hardware interfaces through software, specifically simulating IIC, SPI, UART, PWM, etc. One GPIO is one pin; when simulating other interfaces with GPIO, multiple GPIOs may need to work together. The GPIO interface is the most versatile chip pin resource.

[0024] In this embodiment, the processor 2 in the 100-pin AI core board is model RV1106G3. This processor has significant advantages in computing power, image processing, encoding, audio processing, and low power consumption. Combined with the different data interfaces configured in the 100-pin AI core board, it can meet the computing and intelligent processing requirements when used in security equipment, image acquisition equipment, face recognition equipment, and other fields. It has good video data acquisition and processing functions, and can efficiently convert various framework network models, thus meeting the needs of intelligent devices for data processing, image optimization, and multi-camera collaborative work.

[0025] In this embodiment, the 100 pins of the 100-pin AI core board are pins 1 to 100, respectively. Figure 3 As shown, starting from the upper left corner of PCB board 1, pins 1 to 100 are arranged counterclockwise on the four sides of the PCB board. Among them, as shown in Table 1 below, pins 15 to 25, pins 27 and 28, pins 37 to 50, pins 52 to 59, pins 61 to 75, pins 77 to 81, pins 83 to 90, and pin 94 are all GPIO multiplexed pins. By configuring a rich set of GPIO multiplexed pins, different types of interfaces can be simulated according to usage requirements.

[0026] Specifically, as shown in Table 1 below, the microphone interface consists of pins 97, 98, 99, and 100. These pins form two microphone interfaces for connecting different microphones. The speaker interface consists of pins 9, 10, and 96. The MIPI_CSI interface consists of pins 61-75; the USB interface consists of pins 11, 12, and 13; the SDIO interface consists of pins 83-89; the I2C interface consists of pins 16, 17, 77, and 78; the UART interface consists of pins 18-25 and pins 27 and 28; and the ADC, I2S, and SPI interfaces consist of pins selected from those that can be multiplexed by GPIO.

[0027] Among these 100 pins, a power input interface is also provided to supply power to the processor, memory, and other components on the 100-pin AI core board. This power input interface consists of pins 1 through 4. Additionally, peripheral circuits corresponding to the processor, memory, and each interface are located on PCB 1. For example, a clock circuit is also present on PCB 1. These peripheral circuits enable the processor 2 and memory 3 to function properly. A power output interface can also be configured using GPIO-multiplexable pins.

[0028] like Figure 1-2 As shown, the pins in this 100-pin AI core board are gold fingers located on the side of the PCB board. These gold fingers are stamp-hole pins located on the side of the PCB board, facilitating the mating of the 100-pin AI core board with the PCB base plate. PCB board 1 is square with a side length of 36mm. The pins are evenly distributed on the four sides of the PCB board, with a spacing of 1.27mm between adjacent pins on the same side. The distance between the outermost pin on the same side of the PCB board and the adjacent side is 2.76mm. The compact size and layout ensure that there is no interference between the pins, making it suitable for devices with limited space and energy consumption requirements.

[0029] The correspondence between the terminals (pins) of these interfaces and the stamp hole pins on the edge of the AI ​​core board is shown in Table 1 below. Multiple stamp hole pins are distributed along the edge of the core board. In the table below, pin numbers range from 1 to 100. "CPU pin" indicates which pin on the core board is directly connected to the processor 2 pin; "--" indicates that the pin on the core board is not connected to the CPU. The functions of all pins on the core board are defined according to the "Default Functions" in Table 1 below.

[0030] For example, in Table 1 below, 84 represents pin number 84 on the core board, which is electrically connected to pin 15 of the processor; pins on the core board represent the stamp hole pins around the edge of the core board. For example, 2 represents pin number 2 on the core board, which is used for power supply; for example, 83 represents pin number 83 on the core board, which is a terminal of the SDIO interface.

[0031] Table 1 - Core Board Pin Description Table

[0032] pin label Default function I / O direction Default function description Voltage / Level Reusable GPIO Processor pins 1 VCC5V0_BASE I Core board 5V power supply input 5V ~ ~ 2 VCC5V0_BASE I Core board 5V power supply input 5V ~ ~ 3 VCC5V0_BASE I Core board 5V power supply input 5V ~ ~ 4 VCC5V0_BASE I Core board 5V power supply input 5V ~ ~ 5 GND B systematically ~ ~ ~ 6 GND B systematically ~ ~ ~ 7 GND B systematically ~ ~ ~ 8 GND B systematically ~ ~ ~ 9 VCC1V8_MICBIAS O Audio bias voltage output 1.8V ~ 32 10 LINEOUT O Audio output ~ ~ 29 11 USB_DP B USB Differential+ ~ ~ 27 12 USB_DM B USB Differential- ~ ~ 26 13 USB_DET I USB insertion detection 3.3V ~ 25 14 GND B systematically ~ ~ ~ 15 GPIO0_A4 B GPIO 3.3V GPIO0_A4 63 16 I2C1_SCL_M0 O I2C1 clock signal 3.3V GPIO0_A5 64 17 I2C1_SDA_M0 B I2C1 data signal 3.3V GPIO0_A6 65 18 UART0_RX_M0 I Serial port 0 receives signals 3.3V GPIO0_A0 58 19 UART0_TX_M0 O Serial port 0 sends signals 3.3V GPIO0_A1 59 20 UART3_RX_M0 I Serial port 3 receives signals 3.3V GPIO1_A1 73 21 UART3_TX_M0 O Serial port 3 sends signals 3.3V GPIO1_A0 72 22 UART1_RX_M0 I Serial port 1 receives signals 3.3V GPIO1_A4 76 23 UART1_TX_M0 O Serial port 1 sends signals 3.3V GPIO1_A3 75 24 UART4_RX_M0 I Serial port 4 receives signals 3.3V GPIO1_B0 77 25 UART4_TX_M0 O Serial port 4 sends signals 3.3V GPIO1_B1 78 26 GND B systematically ~ ~ ~ 27 UART2_RX I Serial port 2 receiver 3.3V GPIO1_B3 80 28 UART2_TX O Serial port 2 send 3.3V GPIO1_B2 79 29 WDT_EN I Watchdog enable signal input 3.3V ~ ~ 30 RST_KEY I CPU reset signal input 3.3V ~ ~ 31 GND B systematically ~ ~ ~ 32 ETH_TP O 100Mbps Ethernet differential output+ ~ ~ 100 33 ETH_TN O 100Mbps Ethernet Differential Output - ~ ~ 99 34 ETH_RP I 100Mbps Ethernet Differential Input + ~ ~ 98 35 ETH_RN I 100Mbps Ethernet Differential Input - ~ ~ 97 36 GND B systematically ~ ~ ~ 37 LCD_VSYNC O RGB display field synchronization 3.3V GPIO1_D2 86 38 LCD_HSYNC O RGB display horizontal synchronization 3.3V GPIO1_D1 87 39 LCD_DEN O RGB display data gating 3.3V GPIO1_D0 89 40 LCD_CLK O RGB display clock 3.3V GPIO1_D3 85 41 LCD_D0 O RGB display data 0 3.3V GPIO1_C7 84 42 LCD_D1 O RGB display data 1 3.3V GPIO1_C6 83 43 LCD_D2 O RGB display data 2 3.3V GPIO1_C5 90 44 LCD_D3 O RGB display data 3 3.3V GPIO1_C4 91 45 LCD_D4 O RGB display data 4 3.3V GPIO1_C3 92 46 LCD_D5 O RGB display data 5 3.3V GPIO1_C2 93 47 LCD_D6 O RGB display data 6 3.3V GPIO1_C1 94 48 LCD_D7 O RGB display data 7 3.3V GPIO1_C0 95 49 LCD_D8 O RGB display data 8 3.3V GPIO2_A0 109 50 LCD_D9 O RGB display data 9 3.3V GPIO2_A1 110 51 GND B systematically ~ ~ ~ 52 LCD_D10 O RGB display data 10 3.3V GPIO2_A2 111 53 LCD_D11 O RGB display data 11 3.3V GPIO2_A3 112 54 LCD_D12 O RGB display data 12 3.3V GPIO2_A4 113 55 LCD_D13 O RGB display data 13 3.3V GPIO2_A5 114 56 LCD_D14 O RGB display data 14 3.3V GPIO2_A6 107 57 LCD_D15 O RGB display data 15 3.3V GPIO2_A7 106 58 PWM6_M1 O PWM6 output 3.3V GPIO2_B1 104 59 PWM5_M1 O PWM5 output 3.3V GPIO2_B0 105 60 GND B systematically ~ ~ ~ 61 MIPI / LVDS_D3N O MIPI / LVDS Differential Data 3- ~ GPIO3_B0 117 62 MIPI / LVDS_D3P O MIPI / LVDS Differential Data 3+ ~ GPIO3_B1 118 63 MIPI / LVDS_CLK1N O MIPI / LVDS Differential Clock 1- ~ GPIO3_B2 119 64 MIPI / LVDS_CLK1P O MIPI / LVDS Differential Clock 1+ ~ GPIO3_B3 120 65 MIPI / LVDS_D2N O MIPI / LVDS Differential Data 2- ~ GPIO3_B4 121 66 MIPI / LVDS_D2P O MIPI / LVDS Differential Data 2+ ~ GPIO3_B5 122 67 MIPI / LVDS_D1N O MIPI / LVDS Differential Data 1- ~ GPIO3_B6 123 68 MIPI / LVDS_D1P O MIPI / LVDS Differential Data 1+ ~ GPIO3_B7 124 69 MIPI / LVDS_CLK0N O MIPI / LVDS Differential Clock 0- ~ GPIO3_C0 125 70 MIPI / LVDS_CLK0P O MIPI / LVDS Differential Clock 0+ ~ GPIO3_C1 126 71 MIPI / LVDS_D0N O MIPI / LVDS Differential Data 0- ~ GPIO3_C2 127 72 MIPI / LVDS_D0P O MIPI / LVDS differential data 0+ ~ GPIO3_C3 128 73 MIPI / LVDS_MCLK0 O MIPI / LVDS Master Clock 0 1.8V GPIO3_C4 2 74 MIPI / LVDS_MCLK1 O MIPI / LVDS Master Clock 1 1.8V GPIO3_C6 4 75 MIPI / LVDS_RST O MIPI / LVDS reset pin 1.8V GPIO3_C5 3 76 GND B systematically ~ ~ ~ 77 I2C3_SCL_M2 O I2C3 clock pin 1.8V GPIO3_D1 6 78 I2C3_SDA_M2 B I2C3 data pin 1.8V GPIO3_D2 8 79 GPIO3_C7 B GPIO 1.8V GPIO3_C7 5 80 GPIO3_D0 B GPIO 1.8V GPIO3_D0 7 81 GPIO3_D3 B GPIO 1.8V GPIO3_D3 9 82 GND B systematically ~ ~ ~ 83 SDMMC_DET I SDMMC card insertion detection signal 1.8V / 3.3V GPIO3_A1 11 84 SDMMC_CLK O SDMMC clock signal 1.8V / 3.3V GPIO3_A4 15 85 SDMMC_CMD O SDMMC command control signal 1.8V / 3.3V GPIO3_A5 16 86 SDMMC_D0 O SDMMC data signal 0 1.8V / 3.3V GPIO3_A3 14 87 SDMMC_D1 O SDMMC data signal 1 1.8V / 3.3V GPIO3_A2 12 88 SDMMC_D2 O SDMMC data signal 2 1.8V / 3.3V GPIO3_A7 18 89 SDMMC_D3 O SDMMC data signal 3 1.8V / 3.3V GPIO3_A6 17 90 RECOVERY_KEY I Firmware download button input 1.8V / 3.3V GPIO4_C0 23 91 VCC3V3_RTC I CPU RTC power clock 1.8V / 3.3V ~ ~ 92 RTC_XOUT O CPU RTC clock pin ~ ~ ~ 93 RTC_XIN I CPU RTC clock pin ~ ~ ~ 94 PWM1_M1 O PWM1 output 1.8V GPIO4_C1 22 95 GND B systematically ~ ~ ~ 96 AGND B audio ~ ~ ~ 97 MIC0_N I Microphone 0 signal input negative ~ ~ 33 98 MIC0_P I Microphone 0 signal input positive ~ ~ 34 99 MIC1_N I Microphone 1 signal input negative ~ ~ 35 100 MIC1_P I Microphone 1 signal input positive ~ ~ 36

[0033] Based on the above embodiments, it can be seen that the 100-pin AI core board has good development performance and can meet the user's multi-scenario development needs and functional expansion needs in specified scenarios.

[0034] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A 100-pin AI core board, comprising a PCB board, wherein a processor and a memory are disposed on the PCB board, the PCB board has multiple pins, and multiple interfaces with different functions are arranged in the pins; the PCB board also has peripheral circuits corresponding to the processor, the memory and each interface, characterized in that: The system has a total of 100 pins, with 25 pins distributed on each of the four sides of the PCB board. The interfaces include a microphone interface, a speaker interface, an ADC interface, a MIPI_CSI interface, a USB interface, an SDIO interface, an I2C interface, an I2S interface, an SPI interface, a UART interface, and a GPIO interface. The processor model is RV1106G3. A power input interface is also provided among the 100 pins.

2. The 100-pin AI core board according to claim 1, characterized in that: The 100 pins are numbered 1 to 100, and are arranged counterclockwise on the four sides of the PCB board. Among them, pins 15 to 25, 27 and 28, 37 to 50, 52 to 59, 61 to 75, 77 to 81, 83 to 90, and 94 are GPIO-reusable pins.

3. The 100-pin AI core board according to claim 2, characterized in that: The microphone interface is composed of pins 97, 98, 99, and 100; the speaker interface is composed of pins 9, 10, and 96; the MIPI_CSI interface is composed of pins 61 to 75; the USB interface is composed of pins 11, 12, and 13; the SDIO interface is composed of pins 83 to 89; the I2C interface is composed of pins 16, 17, 77, and 78; the UART interface is composed of pins 18 to 25 and pins 27 and 28; the ADC interface, I2S interface, and SPI interface are composed of pins selected from the GPIO multiplexable pins.

4. The 100-pin AI core board according to claim 1, characterized in that: The pin is a gold finger located on the side of the PCB board.

5. The 100-pin AI core board according to claim 4, characterized in that: The gold fingers are stamp hole pins located on the side of the PCB board.

6. The 100-pin AI core board according to claim 1, characterized in that: The PCB board is square with a side length of 36mm; each pin is evenly distributed on the four sides of the PCB board, with a spacing of 1.27mm between adjacent pins on the same side; the distance between the outermost pin on the same side of the PCB board and the adjacent side is 2.76mm.

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