Grid-connected test data automatic processing method for photovoltaic inverter built-in energy storage system

Abstract

The present application relates to a grid-connected test data automatic processing method of photovoltaic inverter built-in energy storage system, and belongs to the field of photovoltaic inverter testing. In order to solve the problem that multiple test standards cannot be implemented for parallel computing and original data dynamic correlation verification, the present application receives original test data files and test standard chapter identifiers and test parameters input through a web page interface through a web server; a distributed computing framework is called, corresponding data processing algorithm templates are matched according to the identifiers, and original data is parsed in parallel based on the parameters; the parsed data is input into multiple independent computing threads to execute each standard chapter process using multithreading: key performance indicator fields are extracted to generate structured result data tables, support cursor hovering display data point coordinates and interactive charts are generated; the data is stored in a time sequence database, and when a response instruction is received, the test report is automatically filled into a Word template. The method is used to significantly improve the efficiency of multiple standard parallel testing and the accuracy of result verification.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic inverter testing. More specifically, this invention relates to an automated method for processing grid-connected test data of a photovoltaic inverter with built-in energy storage system. Background Technology

[0002] Grid connection testing of photovoltaic inverters with built-in energy storage systems is a crucial step in ensuring that the equipment complies with international standards (such as IEC 62116, UL1741, etc.). Traditional testing procedures rely on manual processing, which has significant limitations. The main problems are concentrated in two aspects:

[0003] Firstly, the efficiency bottleneck of executing multiple test standards serially.

[0004] 1. Inability to process multiple standards in parallel: Testers need to import raw data files (including time series such as DC bus voltage and AC output current) separately for different standards (such as ripple coefficient requirements of IEC 62116 and grid response requirements of UL 1741), and execute independent data parsing processes for each one. For example, after completing the analysis of the IEC standard, the data needs to be re-imported before the UL standard can be processed, causing the task processing time to increase linearly with the number of standards.

[0005] 2. Data disconnect leads to verification difficulties: The generated result charts (such as static efficiency curves) have no dynamic correlation with the original sampled values. When anomalies are found (such as excessive ripple coefficient), it is necessary to relocate the original data corresponding to the timestamp across platforms (such as MATLAB). Manual tracing is too time-consuming and prone to errors.

[0006] The root cause lies in the fact that the data processing logic of different standards is independent of each other, and there is a lack of a unified framework to realize the dynamic matching of algorithm templates and the parallel injection of tasks.

[0007] Secondly, the timing mismatch problem in multi-threaded parallel processing.

[0008] To improve efficiency, some solutions attempt to use multi-threaded parallel computing (such as allocating separate threads for DC voltage fluctuation rate and AC current response). However, this approach introduces new technical drawbacks:

[0009] 1. Timing discrepancies caused by transmission and scheduling differences: There is a hardware transmission delay difference (measured at ±20ms) between DC voltage data (usually transmitted via CAN bus) and AC current data (transmitted via Ethernet); the randomness of thread scheduling in the operating system leads to timestamp deviations in data collected at the same time (e.g., ±15ms). In a 50Hz power grid environment, these deviations are equivalent to a phase error of 27°, causing key indicators (such as charge / discharge cycle efficiency η=P) to be affected. out / P in The DC voltage and AC current data are misaligned during the calculation, resulting in distorted calculation results (measurement error > 5%).

[0010] 2. Accumulated error in fixed time windows: Traditional solutions trigger calculations at fixed time intervals (e.g., 1 second), without considering the integrity of the power grid cycle. When the data window is not aligned with an integer multiple of the cycle, the phase accumulation error further amplifies the performance deviation. The challenge lies in aligning multi-source heterogeneous data streams with millisecond-level accuracy while maintaining real-time compatibility with high-frequency sampling (e.g., 10kHz) scenarios.

[0011] The aforementioned issues further trigger a chain of challenges, including derivative problems related to resource allocation and high-frequency data processing:

[0012] 1. High-frequency data retrieval latency: When the original data sampling rate reaches 10kHz, a single anomaly verification requires traversing millions of data points. The disk I / O bottleneck causes an interaction latency of >15ms, which cannot meet the requirements of real-time waveform verification.

[0013] 2. Imbalance between storage and computing resources: Under the fixed thread allocation strategy, the thread idle rate of lightweight tasks (such as power grid response detection) is >65%, while the overall latency of computationally intensive tasks (such as ripple analysis) increases by 210% due to insufficient resources.

[0014] Therefore, existing technologies suffer from three major drawbacks: multi-standard serial processing mechanisms, multi-threaded timing mismatch, and high-frequency data retrieval latency, making it difficult to balance testing efficiency and result accuracy. Especially in scenarios involving high sampling rates (>10kHz) and multiple standard compliance requirements, the cost of manual intervention and the risk of computational distortion increase significantly. Summary of the Invention

[0015] One object of the present invention is to solve at least the above-mentioned problems and to provide at least the advantages that will be described later.

[0016] To achieve these objectives and other advantages according to the present invention, an automated processing method for grid-connected test data of a photovoltaic inverter-embedded energy storage system is provided, comprising:

[0017] The system receives raw test data files via a web server, which include time-series data of DC bus voltage, AC output current, and battery charge and discharge power.

[0018] Receive the test standard section identifier selected through the web interface and the input test parameters;

[0019] The distributed computing framework is invoked to match the corresponding data processing algorithm template according to the test standard chapter identifier, and the original test data file is parsed in parallel based on the test parameters. The data processing algorithm template includes ripple coefficient calculation logic and power grid frequency response threshold determination logic. The ripple coefficient calculation logic is used to separate the ripple signal in the 0-100Hz frequency band, and the power grid frequency response threshold determination logic is executed based on the target power grid standard.

[0020] Multithreading is used to simultaneously input the parsed data into multiple independent computing threads. Each computing thread corresponds to a data processing flow of a test standard section, and performs the following operations in each computing thread:

[0021] Extract key performance indicator fields from the parsed data, execute numerical calculation logic according to the data processing algorithm template, and generate a structured result data table. Key performance indicator fields include DC voltage fluctuation rate and charge-discharge cycle efficiency.

[0022] Based on the structured result data table, interactive charts are generated through the Canvas application interface combined with the Web graphics library rendering engine. The interactive charts support real-time display of data point coordinate information and the original data sample value with the corresponding timestamp triggered by cursor hover.

[0023] The structured result data tables and interactive charts are categorized and stored in the time series database according to the test standard chapter identifiers. In response to the report generation command, the structured result data tables and interactive charts of the specified test standard chapters are extracted from the time series database and automatically filled into the preset Word report template to generate a test report file.

[0024] Preferably, parallel computation is performed using multiple threads, specifically including:

[0025] Create thread groups equal to the number of chapters in the test standard. Each thread group is bound to an independent circular buffer with a capacity of 1024 records. Each record contains a millisecond-level timestamp, DC bus voltage, and AC output current fields.

[0026] The time alignment engine performs the following: sorts the parsed data in ascending order by the timestamp field, and establishes a mapping relationship between timestamp, DC voltage value, and AC current value in a hash table using the millisecond timestamp as the key.

[0027] When the data of 10 complete power grid cycles accumulates in the circular buffer, the charge and discharge cycle efficiency calculation of the corresponding thread group is triggered.

[0028] If a missing DC voltage or AC current value is detected at the same timestamp, an interrupt signal is sent to the exception handling coroutine and the data completion interface is invoked.

[0029] Preferably, the step of displaying the raw data sample values ​​corresponding to the timestamp in real time includes:

[0030] When uploading the original test data file, a full file memory mapping is established through the mmap memory mapping system call, generating a read-only binary memory view;

[0031] Build a Bloom filter index table, map timestamps to file storage offset addresses, and load the index table into the browser's IndexedDB cache;

[0032] When the cursor hover event is triggered, the timestamp value is parsed from the data point coordinates, and the offset address is located within 1ms using a Bloom filter; and the instantaneous value of the original DC bus voltage of 64 consecutive sampling points before and after the offset address is extracted.

[0033] The waveform is reconstructed by executing the Catmull-Rom cubic spline interpolation algorithm through a Web Worker thread, and then superimposed and rendered onto a Canvas layer.

[0034] The interpolation waveform peak value and ripple coefficient calculation results are dynamically displayed at the cursor position.

[0035] Preferably, the storage steps of the time-series database include:

[0036] The structured result data table is encoded in columnar storage format. The timestamp field is encoded using differential compression, and the DC voltage fluctuation rate field is converted to 32-bit floating-point numbers and then compressed using ZSTD lossless compression.

[0037] Create a separate element storage partition for interactive diagrams, and name the element storage partition according to the standard chapter number;

[0038] Data is written using a dynamic time-slicing strategy. When the DC voltage fluctuation rate data sampling rate is greater than 10kHz, it automatically switches to writing in batches every 5 seconds. Each batch of data is encapsulated in a protocol buffer format message body and includes a CRC32 checksum.

[0039] A hierarchical cache structure is built in memory, including: a first-level cache, which stores the raw volatility data of the most recent 2 minutes; and a second-level cache, which loads data blocks of adjacent hours according to the access frequency.

[0040] When creating a bidirectional B+ tree index, DC voltage fluctuation data with a frequency > 100Hz in the leaf nodes are marked as high-frequency bands and allocated independent solid-state drive storage blocks.

[0041] Preferably, the execution of the ripple coefficient calculation logic includes:

[0042] Extract the instantaneous value sequence of DC bus voltage from key performance indicator fields;

[0043] Noise and real ripple signals are separated by a two-stage filtering unit, including: a first-stage high-pass filter unit to filter out high-frequency noise components generated by switching devices, and a second-stage low-pass filter unit to retain the real ripple signal in the 0-100Hz frequency band.

[0044] A sliding window peak-to-peak value detection is performed on the instantaneous value sequence of the filtered DC bus voltage, wherein the window width is synchronized with the grid cycle;

[0045] The basic threshold is set based on the rated voltage of the DC bus, and the actual judgment threshold is dynamically adjusted according to the state of charge of the battery: when the state of charge of the battery deviates from the median value, the basic threshold is adjusted proportionally to generate the actual judgment threshold.

[0046] When the detected peak-to-peak value exceeds the actual judgment threshold, an anomaly is marked in the structured result data table, and an interactive chart is triggered to highlight the abnormal frequency band as a spectrum waterfall plot.

[0047] Preferably, the steps for generating a Word report template include:

[0048] Embed dynamic field codes for IEC standard chapter numbers in the DOCX template file;

[0049] Write DC voltage fluctuation data to a specified table using the XWPF table interface of the Apache Document Processing Toolkit.

[0050] When calling the enhanced metafile conversion interface, execute the resolution setting method to set the output resolution;

[0051] When a chart is inserted, a standard chapter number text label is automatically added below the chart.

[0052] Preferably, after generating an interactive chart, an abnormal data tracing process is executed:

[0053] Receive data anomaly location instructions triggered by users through the visual interface, including the pixel coordinates of the cursor on the chart;

[0054] The process involves mapping pixel coordinates back to the associated record rows in the structured result data table, including: extracting the logical coordinates of data points using the pixel reading method of the Web graphics library, querying the inverse index table of the time series database using the logical coordinates of the data points as the key, and obtaining the primary key of the record row.

[0055] Based on the associated record rows, a three-level timestamp alignment retrieval is performed in the original test data file, including: main retrieval, which performs a binary search based on the record row timestamp field; secondary retrieval, which scans adjacent records with a time window of ±10ms if the main retrieval fails; and fault-tolerant retrieval, which calls a Bloom filter to verify the existence of timestamps.

[0056] The retrieved raw data records and their context data from 32 sampling points before and after them are synchronously marked using a heatmap layer in an interactive chart. The heatmap color level reflects the data's deviation from the standard deviation.

[0057] Preferably, the distributed computing framework performs dynamic resource allocation including:

[0058] For each data processing algorithm template, a computational complexity weight is predefined. The weight value is determined based on the benchmark test duration and stored in the metadata database.

[0059] When creating a thread group, initial thread resources are allocated according to weight ratios, with thread groups having higher complexity weights being allocated more threads;

[0060] The runtime dynamically balances the load through a work-stealing mechanism, specifically including: when the idle rate of the circular buffer of a thread group reaches a first preset threshold, stealing data blocks carrying the original timestamp sequence from the thread group whose buffer load exceeds a second preset threshold, and migrating them to the idle thread group through atomic operations;

[0061] Real-time monitoring of computation latency for each thread group; if the latency of a high-weight thread group exceeds the third preset threshold, dynamically allocate available threads from the public resource pool for elastic scaling.

[0062] Preferably, the first preset threshold, the second preset threshold, and the third preset threshold are 40%, 80%, and 200ms, respectively.

[0063] Preferably, the target power grid standard includes IEC 62116 and / or UL 1741.

[0064] The present invention has at least the following beneficial effects:

[0065] First, this invention achieves, for the first time, parallel parsing and calculation of multiple international standards (such as IEC / UL) in photovoltaic inverter testing by dynamically matching multi-standard algorithm templates through a distributed framework. It employs multi-threaded independent processing of each standard section, completely eliminating the time overhead of traditional serial processing. A key innovation lies in the deep integration of Canvas and WebGL engines when generating interactive charts, enabling real-time display of raw sample values ​​upon cursor hover, thus solving the challenge of dynamically verifying the correlation between test results and raw data. Finally, through time-series database categorized storage and automatic Word template filling, a fully closed-loop automated process from data processing to report generation is formed, significantly improving the efficiency of multi-standard compliance testing.

[0066] Secondly, to address the AC-DC data timing mismatch issue caused by multi-threaded parallelism, this invention innovatively designs a timing alignment engine and a circular buffer triggering mechanism. A hash table is used to establish a precise mapping between millisecond-level timestamps and physical quantities, eliminating transmission delay differences. Calculation triggering conditions are based on integer multiples of the power grid cycle (replacing fixed intervals), ensuring phase synchronization within the window and fundamentally resolving efficiency calculation distortions caused by thread scheduling deviations. Combined with a three-level fault-tolerant process (primary / secondary retrieval + Lagrange interpolation completion), the spatiotemporal consistency of physical quantities is maintained even when data is missing, significantly improving the accuracy of key indicators such as charge / discharge cycle efficiency.

[0067] Third, to address the interaction lag caused by high-frequency raw data retrieval latency, this invention constructs a three-tiered acceleration architecture: memory mapping technology circumvents disk I / O bottlenecks, improving the efficiency of direct reading of raw data by orders of magnitude; Bloom filter indexing achieves microsecond-level timestamp positioning, breaking through the performance limits of traditional linear scanning; and the Catmull-Rom spline interpolation algorithm, through parallel computation using Web Workers, reconstructs local waveforms in real time when the cursor hovers. The synergy of these three technologies enables raw sample value verification to achieve a latency imperceptible to the human eye, completely changing the current situation where high-frequency test data cannot be dynamically interacted with.

[0068] Fourth, addressing resource imbalance in heterogeneous tasks, this invention pioneers a weight-driven dynamic resource allocation model. Initial threads are allocated according to the weight ratio of algorithm complexity, laying the foundation for load balancing; a work-stealing mechanism (stealing data blocks from thread groups with a load >80% when idle rate >40%) breaks down resource barriers; and an elastic scaling model (scaling up according to weight / latency ratio when latency >200ms) achieves millisecond-level adjustment of computing resources. This three-tiered adjustment system reduces latency for high-load tasks by more than 75%, bringing resource utilization close to the theoretical limit.

[0069] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Attached Figure Description

[0070] Figure 1 This is a schematic diagram of the overall process of one of the technical solutions of the present invention. Detailed Implementation

[0071] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description.

[0072] like Figure 1 As shown, this invention provides an automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system. Traditional photovoltaic inverter testing uses a single-threaded processing mode, such as the LabVIEW processing flow:

[0073] 1. Manually import raw test data in CSV format (including time series such as DC bus voltage and AC current) one by one.

[0074] 2. Develop dedicated parsing scripts for individual IEC standard chapters (such as clause 7.2.3 of IEC 62116);

[0075] 3. It took 45 minutes to generate static charts and reports;

[0076] 4. You need to switch to MATLAB and re-import the original data to verify the outliers.

[0077] This solution has two major drawbacks: it cannot process multiple standards in parallel. When multiple standards such as IEC 62116 and UL 1741 need to be met simultaneously, multiple data processing steps need to be executed serially; the original data is disconnected, and the resulting charts are not dynamically related to the original sampled values, requiring cross-platform timestamp retrieval for manual traceability.

[0078] Implementation scheme of the present invention:

[0079] Step 1: Parallel Injection of Multiple Standard Tasks

[0080] The system receives raw test data files (binary format, sampling rate 10kHz) via a web server. The file structure includes: timestamp (millisecond precision), DC bus voltage (unit: V), AC output current (unit: A), and battery charging and discharging power (unit: kW).

[0081] Users select the test standard chapter identifiers that need to be tested in parallel on the web interface (for example, simultaneously selecting clause 7.3.1 of IEC 62116 and clause 15.2 of UL 1741), and enter the test parameters: rated grid frequency 50Hz, rated DC bus voltage 800V.

[0082] Step 2: Algorithm Template Matching in Distributed Frameworks

[0083] The Apache Spark distributed computing framework is invoked to load pre-stored data processing algorithm templates based on standard identifiers.

[0084] IEC 62116 template: Built-in ripple coefficient calculation logic, the core algorithm is a discretized implementation based on Parseval's theorem, the original formula is: In the power calculation formula, P represents the average power of the signal, reflecting the average intensity of the signal energy over time; N represents the total number of sampling points of the signal, and the formula calculates for N discrete sampling points from n=0 to n=N-1; n represents the discrete time index. x[n] represents the sampled value of the discrete-time signal at time n; where square brackets [] and index n are the standard representation of discrete signals, used to distinguish them from parentheses () in continuous-time signals x(t) and continuous-time variables t. Improvement of this invention: Only extract the DFT (Discrete Fourier Transform) coefficients corresponding to k=0 to k=100 in the 0-100Hz frequency band, where k represents the discrete frequency index, calculate the sum of power (average of the sum of squares) within the selected frequency range, where the power (square of the amplitude) of each frequency component is calculated, the sum of all powers is divided by the number of points N to obtain the average power, and the square root of the ripple power is compared with the DC component to obtain the dimensionless ripple coefficient. The purpose is to calculate the ripple coefficient of the signal in the 0-100Hz frequency range.

[0085] UL 1741 template: Power grid frequency response determination logic, using a sliding window peak-to-peak detection algorithm.

[0086] Step 3: Multi-threaded real-time processing and dynamic association

[0087] Create independent thread groups (number = number of selected standard chapters), and execute the following in each thread group:

[0088] 1. Calculation of key indicators:

[0089] DC voltage fluctuation rate = (V max -V min ) / V 额定 (Results are dimensionless percentages), V max The maximum value of the DC bus voltage, V, is measured within a complete power grid cycle (or a specified observation window). min The minimum value of the DC bus voltage, V, is measured within the same complete power grid cycle (or a specified observation window). 额定 The rated or nominal value of the DC bus voltage is a fixed parameter determined by system design and testing standards.

[0090] Charge-discharge cycle efficiency = (discharge energy / charge energy) × 100% (energy units are all kWh);

[0091] 2. Dynamic association of raw data:

[0092] Render interactive line charts using HTML5 Canvas;

[0093] When the cursor hovers over the cursor, the following logic chain is triggered:

[0094] A. Cursor pixel coordinates

[0095] Input: The cursor position (x, y pixel values) on the screen; its function is to serve as the starting point of the process, obtain the origin of the coordinates of user interaction, and query real-time data when clicking / hovering in the line chart.

[0096] B. WebGL coordinate transformation

[0097] Processing: Convert pixel coordinates to normalized coordinates in the WebGL coordinate system; the purpose is to establish a mapping relationship between screen coordinates and the data time axis (e.g., the x-axis corresponds to time, and the y-axis corresponds to voltage).

[0098] C. Timestamp t

[0099] Generation: Calculate the corresponding timestamp t based on WebGL coordinates; for example, if the x-axis represents 1 second / screen width, then pixel x=100 corresponds to t=0.25 seconds, which serves to determine the time reference point for data retrieval.

[0100] D. Bloom filter retrieval

[0101] A Bloom filter can be used to quickly determine whether data exists at time t. Its advantages are high space efficiency and support for fast queries (with controllable false positive rate). It requires presetting the number of hash functions k and the size of the bit array m.

[0102] E. Locate the file offset address

[0103] Mapping: Convert the timestamp t into a byte offset in the binary file; the calculation method is to convert the time into the index of the corresponding sample point, and then multiply it by the number of bytes of each sample to obtain the position of the target time point in the original byte stream, and the sampling rate (e.g., 10kHz) and data format (e.g., 16-bit integer) must be known.

[0104] F. Read the original voltage value from t-32ms to t+32ms.

[0105] Range: Centered on t, read data 32ms before and after (64ms window in total); if the sampling rate is 10kHz, read 640 sample points to obtain enough historical data to ensure waveform smoothness.

[0106] G, Catmull-Rom spline interpolation

[0107] Algorithm: Using the quartic spline interpolation formula P(t) = 0.5 × ((2-P)Q + (RP)t + (2Q-RS)t) 2 + (RQ)t 3 P, Q, R, and S are the four control points of the curve, and t is a parameter. The value range is usually 0 ≤ t ≤ 1. When t = 0, P(0) = Q, and when t = 1, P(1) = R. Its advantage is to ensure the continuity of the curve (C1 continuity), avoid step-like distortion, and convert discrete sampling points into a smooth curve.

[0108] H. Overlay rendering of dynamic waveforms

[0109] By overlaying new waveforms using WebGL fragment shaders and using off-screen rendering (FrameBufferObject) to reduce redraw overhead, the waveform near the cursor is highlighted, creating a dynamic interactive effect.

[0110] The above logic chain represents a complete data processing flow from the user's cursor position to dynamic waveform rendering. The flow achieves dynamic interaction between the cursor position and waveform data through five core stages: coordinate mapping, timestamp association, data retrieval, interpolation calculation, and graphics rendering. Performance optimizations include setting the Bloom filter false positive rate to 0.01% to balance space and accuracy, employing a block loading strategy (e.g., data in blocks of 1 second), accelerating interpolation calculations using WebGL's GPU parallel computing, using LOD (Level of Detail) technology for waveform rendering, and reducing the sampling rate in far-cursor areas. This logic chain, through the combination of multiple technologies, achieves efficient processing from user interaction to data visualization, with its core being the accurate mapping of time-space coordinates and the rapid retrieval of massive amounts of data.

[0111] To achieve a false positive rate of 0.01% with the Bloom filter, the following technical measures are adopted:

[0112] Bit array size calculation: Assume the maximum number of timestamps n=10 6 (Millions of cases), an acceptable false positive rate p = 0.0001, according to the formula m = -n × lnp / (ln2). 2 The calculated bit array size m ≈ 19.17 MB, but the actual memory allocation is rounded down to 20 MB to be compatible with the hardware page size.

[0113] Optimal number of hash functions: k = m / n × ln2 = k≈7. Select 7 independent MurmurHash3 functions (seed values ​​0-6) to ensure hash uniformity.

[0114] Block loading strategy: The original test file is divided into blocks with a duration of 1 second (10,000 sampling points / block), and each block is independently indexed by a Bloom filter to avoid bit array overload caused by full file indexing.

[0115] Runtime error compensation: When the Bloom filter returns "existent", the timestamp difference (|t) is checked. query -t actual A secondary verification is performed for values ​​≤1μs. If the value exceeds the tolerance, a secondary search process is initiated. query The query timestamp refers to the target time point that the user wants to query by hovering the cursor over it. This value comes from the calculation result of the previous coordinate transformation. actual The actual timestamp refers to the timestamp corresponding to the actual stored data point located in the original binary data file through Bloom filter indexing and file offset address. Secondary verification estimates t through linear interpolation of adjacent timestamps. actual .

[0116] Step 4: Automatic Report Generation

[0117] Extract structured results (such as the ripple coefficient table of IEC 62116) and related charts from the time-series database, and inject them into a preset Word template:

[0118] The dynamic field code is automatically replaced with the standard section number "IEC 62116 Clause 7.3.1";

[0119] Write the volatility data matrix using the Apache POI XWPFTable interface.

[0120] Example: Test data of photovoltaic inverter under 50Hz grid (10,000 sampling points).

[0121] Traditional approach:

[0122] 1. Data was manually segmented and analyzed according to IEC and UL standards, taking 92 minutes;

[0123] 2. When an abnormal ripple is detected, the original file needs to be re-imported to locate the problematic timestamp, which takes an additional 15 minutes.

[0124] This plan will be implemented as follows:

[0125] 1. Select the IEC 62116 and UL 1741 standard identifiers and submit the task;

[0126] 2. Spark starts two independent thread groups for parallel computation (computation time 11.3 seconds).

[0127] 3. When the user hovers over the point of ripple anomaly, the instantaneous value of the original voltage at t=1532ms is displayed in real time;

[0128] 4. Automatically generate a report containing bi-standard results (total time 23 seconds).

[0129] This solution, through a distributed framework and dynamic indexing mechanism, achieves for the first time multi-standard parallel computing and real-time interoperability with raw data, eliminating the bottleneck of manual serial processing.

[0130] In another embodiment of the present invention, the traditional multi-threaded parallel scheme suffers from severe timing mismatch, including: thread scheduling delay, where differences in operating system scheduling cause a data timestamp deviation of ±15ms (equivalent to a 27° phase difference under a 50Hz power grid) between the DC voltage thread (thread A) and the AC current thread (thread B) acquired simultaneously; and transmission asynchrony, where differences in transmission delay between the CAN bus and Ethernet cause the DC bus voltage data to arrive 20ms later than the AC current. This results in a misalignment between DC voltage and AC current when calculating charge-discharge cycle efficiency, leading to distorted efficiency values ​​(measured error >5%).

[0131] This implementation plan includes:

[0132] Step 1: Design of the Timing Alignment Engine

[0133] A hash table is used to establish a precise timestamp-physical quantity mapping relationship: DC voltage V and AC current are stored with millisecond timestamp t as the key. The timestamp unit is millisecond (ms), the voltage unit is volt (V), and the current unit is ampere (A). The three are independent and conflict-free.

[0134] Step 2: Circular Buffer Trigger Mechanism

[0135] The core innovation is to use the power grid cycle as a benchmark for calculation, replacing the fixed time interval: 1. Define the complete power grid cycle T=1 / f grid f grid 1. The power grid frequency is expressed in Hz; 2. When the data accumulation time in the circular buffer is ≥10T, the thread group calculation is triggered. The physical meaning is to ensure that the calculation window contains an integer number of cycles, eliminating phase accumulation errors.

[0136] Step 3: Data Missing Fault Tolerance

[0137] The three-level fault-tolerant process includes: main retrieval, which queries the hash table using timestamp t0 as the key; secondary retrieval, which scans the [t0-Δt, t0+Δt] window (Δt=10ms) if t0 is missing; and data completion, which calls the Lagrange interpolation algorithm based on t0. （k-1） t k t （k+1） Reconstructing missing values ​​from time-series data. , where L i (t0) is the Lagrange basis function: , , Time term t i The unit is millisecond (ms), and the unit of voltage V is volt (V). The dimensions of both sides of the formula are volt (V).

[0138] Example

[0139] Experimental setup: The photovoltaic inverter model is SMA Sunny Boy Storage 3.7; test conditions: grid frequency 50Hz (T=20ms), sampling rate 10kHz; artificially injected data delay, DC voltage lags AC current by 15ms.

[0140] Traditional approach (OpenMP parallel):

[0141] 1. The DC voltage thread and the AC current thread operate independently;

[0142] 2. Calculate the charge / discharge efficiency at t=1000ms: η=P out / P in =V dc(1000)×I ac (1000) / P bat P out For output power, P is the active power P that the inverter outputs to the grid during the discharge process. in Input power, V, is the active power input from the grid or photovoltaic terminal to the energy storage battery during the charging process. dc I is the DC bus voltage. ac It is the AC output current.

[0143] Actual error: V dc (1000) corresponds to a real time of 985ms, while Iac(1000) corresponds to a real time of 1000ms, resulting in an efficiency distortion of 8.7%.

[0144] This implementation plan:

[0145] 1. The timing alignment engine will adjust the V at t=1000ms. dc with I ac Forced matching (finding V in the [990,1010]ms window via secondary search) dc (1015));

[0146] 2. Rebuild the data completion interface V dc (1000):

[0147] Given point: V dc (990) = 799.2V, V dc (1015) = 800.1V, V dc (1040) = 799.8V, substituting this into the Lagrange interpolation formula, we obtain V. dc (1000) = 799.5V, Calculation efficiency: η = 799.5V × I ac (1000) / P bat The error was reduced to 0.3%.

[0148] This implementation uses forced timestamp alignment, establishes millisecond-level precise mapping using a hash table (to resolve transmission delays), triggers power grid cycles, uses a 10T calculation window (to eliminate thread scheduling bias), completes the data using Lagrange interpolation, and employs third-order approximation to ensure the physical rationality of the reconstructed data.

[0149] In another embodiment of the present invention, to address the latency issue in retrieving high-frequency raw data during dynamic verification, traditional testing systems employ a full-file linear scanning mechanism to process high-frequency raw data. When the sampling rate increases to the 200kHz level, a single retrieval requires traversing millions of data points, and the combined disk I / O and memory search results in a latency exceeding 15 milliseconds. This latency renders the cursor hover interaction function ineffective, preventing users from observing waveform details in real time. Furthermore, anomaly analysis still requires manually exporting the raw file for offline location, significantly hindering testing efficiency.

[0150] This solution reconstructs the data retrieval process through a three-tiered acceleration architecture. First, a full-file memory mapping is established during the data upload phase, directly mapping binary test data to the memory address space, forming a read-only, contiguous memory view and completely bypassing disk access bottlenecks. Then, a Bloom filter index structure is built, converting millisecond-level timestamps into bit array markers and loading them into the browser's IndexedDB cache, achieving microsecond-level existence prediction. When a user triggers a cursor hover event, the target timestamp is parsed based on screen coordinates. The Bloom filter confirms data validity and locates the file offset address within 1 millisecond, directly jumping to the memory-mapped area to extract the raw instantaneous voltage values ​​of 64 sampling points before and after the target time point.

[0151] Finally, the Catmull-Rom spline interpolation algorithm is used to reconstruct the local waveform, and parallel computation is performed through WebWorker threads to eliminate interface lag. The smooth curve generated by interpolation is superimposed and rendered onto the Canvas interactive layer in real time, while the peak value of the ripple coefficient is dynamically marked at the cursor. The entire process, through the collaboration of direct memory reading, probabilistic indexing, and parallel interpolation, transforms high-frequency data retrieval from file scanning to memory addressing, enabling the dynamic verification of the original waveform to achieve a latency level imperceptible to the human eye.

[0152] In another embodiment of this invention, traditional time-series database solutions face severe challenges in handling DC voltage fluctuation data with a sampling rate of 10kHz, addressing the disk throughput bottleneck caused by high-frequency volatility data storage. Existing technologies such as InfluxDB employ a row-based storage structure, requiring each timestamp record to be written to disk independently. When the sampling interval is shortened to 0.1 milliseconds, the system generates 10,000 disk write requests per second. Real-world testing shows that the peak disk IOPS demand under this architecture exceeds 50,000, far exceeding the capacity of mechanical hard drives. Even with solid-state drives, frequent small file writes trigger write amplification, ultimately leading to data throughput saturation. More seriously, continuous high-load writes can block query operations, causing delays in data extraction during report generation.

[0153] This solution restructures the data writing process through a three-tier storage optimization architecture. First, a data encoding and compression strategy is implemented, converting the structured result data table into a columnar storage format: the timestamp field uses a differential compression algorithm, storing only the quadratic difference between adjacent timestamps instead of the original value; the DC voltage fluctuation rate field is uniformly converted to 32-bit floating-point numbers and then stream-compressed using the ZSTD lossless compression engine. This design reduces the storage space per record by approximately 70%, significantly reducing the basic write volume. Second, a dynamic time sharding mechanism is introduced. When the fluctuation rate sampling rate exceeds the 10kHz threshold, it automatically switches to batch aggregation write mode—the original data is accumulated in memory for 5 seconds, then encapsulated into a protocol buffer format message body, appended with a CRC32 checksum, and submitted for storage in batches. This mechanism drastically reduces the number of writes per second from 10,000 to 0.2, completely alleviating the pressure of high-frequency writes.

[0154] Finally, a hierarchical caching system is constructed to intercept disk access. The first-level cache resides directly in memory, retaining the raw volatility data from the most recent two minutes for real-time analysis. The second-level cache dynamically loads hot data blocks from the adjacent hour based on an LRU strategy. For high-frequency volatility data exceeding 100Hz, it is marked as a special type when building the bidirectional B+ tree index and independently allocated to high-speed solid-state drive storage blocks. When a query request arrives, the system prioritizes searching the memory cache layer, triggering disk access only if a cache miss occurs. This design allows over 95% of data requests to be responded to at the memory layer, with the disk only handling low-frequency batch write tasks. In actual tests, the disk IOPS load was reduced to less than 1 / 20 of the traditional solution.

[0155] In another embodiment of the present invention, to address the problem of misjudgment of ripple coefficient caused by switching device noise, the traditional detection scheme directly performs sliding window peak-to-peak value detection on the original DC bus voltage sequence. This scheme fails to effectively isolate high-frequency switching noise (such as the 20kHz noise generated by IGBT devices), causing the true ripple signal to be submerged. Actual measurement data shows that when the switching noise amplitude reaches three times the ripple signal, the misjudgment rate of the traditional method is as high as 18%, severely interfering with the accuracy of grid-connected test conclusions.

[0156] This scheme reconstructs the ripple coefficient calculation process using a two-stage adaptive filtering and dynamic threshold correction mechanism, as detailed below:

[0157] 1. Basic Algorithm

[0158] Step 1: Frequency band separation filtering

[0159] First-stage high-pass filtering: A second-order Butterworth high-pass filter is used, with a cutoff frequency set at 10kHz. Its transfer function is derived from the analog filter prototype through a bilinear transformation.

[0160]

[0161] Among them, H hp (s) represents the filter's transfer function, describing the filter's response to the input signal in the complex frequency domain. The subscript hp indicates high-pass, and ω... c =2π×10 4 rad / s represents the cutoff angular frequency. After discretization, real-time filtering is performed, which physically means filtering out high-frequency noise components (>10kHz) generated by the switching devices. s is a complex frequency variable, which is a variable in the Laplace transform, defined as s=σ+jω, where σ is the attenuation coefficient, j is the imaginary unit, and ω is the angular frequency.

[0162] Second-stage low-pass filtering: A Chebyshev Type I low-pass filter is used, with a cutoff frequency of 100Hz. The transfer function is:

[0163]

[0164] Where T n Let n be a Chebyshev polynomial, n be the filter order, and ε be the ripple coefficient. After discretization, the 0-100Hz baseband ripple signal is retained, and ω is the angular frequency variable, which is related to the frequency f by ω=2πf.

[0165] Step 2: Ripple Feature Extraction

[0166] Perform sliding window peak-to-peak value detection of the synchronous power grid cycle on the filtered sequence:

[0167] Window width W = 1 / f grid (Grid cycle), ensuring the window contains an integer number of ripple cycles, f grid This is the fundamental frequency of the power grid;

[0168] Peak-to-peak value calculation: V pp =max(V filtered [k:k+W])-min(V filtered [k:k+W]), this is the standard peak-to-peak value algorithm in the field of signal processing, with the dimension being volts (V). pp The peak-to-peak value of the ripple voltage is the final measurement result, representing the maximum amplitude of voltage fluctuation within a window of width W, in V. filtered The filtered DC bus voltage sequence is the output signal of the original DC voltage signal after being processed by two-stage filters (high-pass + low-pass). It contains only the target ripple component of 0-100Hz, and high-frequency noise has been filtered out. k represents the starting index of the data sequence, which is an integer value pointing to a certain position in the data array. k+W represents the ending index of the data sequence.

[0169] Step 3: Dynamic Threshold Correction

[0170] Basic threshold setting: (1% of rated voltage), in volts (V).

[0171] Dynamic correction of state of charge (SOC):

[0172]

[0173] Derivation Explanation: When SOC = 50%, the correction coefficient is 1, and the threshold remains at the base value; when SOC deviates from 50%, the threshold is increased linearly according to the degree of deviation (e.g., when SOC = 30%, the coefficient = 1.2); the coefficient 0.5 is calibrated experimentally to ensure dimensional consistency. It is a dimensionless ratio, and remains dimensionless after multiplying by the constant 0.5, and is also dimensionless with V. th_base (V) After multiplication, the dimension remains volt (V), V th_Actual The actual threshold used is a dynamic threshold, adjusted for battery state of charge (SOC), ultimately used to determine whether the ripple peak-to-peak value is abnormal. V th_base The basic judgment threshold is a fixed reference value that is preset based on the system's rated voltage and test standard requirements.

[0174] 2. Validation of Algorithm Implementation Results

[0175] Experimental setup: Inverter model: SMA Sunny Boy Storage 3.7; Noise source: IGBT switching noise (20kHz, amplitude 3V); Real ripple: 100Hz power frequency ripple (amplitude 1V); Comparison group: Traditional single-stage low-pass filter scheme (cutoff frequency 1kHz).

[0176] The traditional solution detected a ripple amplitude of 3.2V with a noise false positive rate of 18%. This new solution, with its two-stage filtering, detected a ripple amplitude of 1.05V with a noise false positive rate of 0%. This demonstrates that the traditional solution, by not filtering out high-frequency noise, inflated the peak-to-peak detection result due to noise. This new solution accurately separates the 100Hz ripple signal. By designing a two-stage filter to separate the target frequency band and combining it with SOC dynamic threshold correction, the false positive rate was reduced from 18% to nearly 0. Abnormal frequency bands are highlighted on the interactive interface using a spectrum waterfall plot (a standard visualization method in signal processing), further demonstrating the effectiveness of the solution.

[0177] In another embodiment of this invention, the traditional report generation process suffers from severe human intervention defects, particularly regarding the mandatory requirements of certification bodies on the accuracy of report charts and the labeling of standard clauses. Engineers must manually paste screenshots of charts generated by MATLAB into a Word report and then modify the standard clause numbers page by page. This method leads to two key problems: the chart resolution is severely degraded due to multiple transfers, resulting in a loss of over 30% in the accuracy of the original data; and the manual labeling error rate is as high as 12% (e.g., mislabeling UL 1741 clause as IEC 62116), causing certification bodies to reject test reports.

[0178] This solution restructures the report generation process through a fully automated annotation and precision control mechanism. First, dynamic field codes are pre-embedded in the DOCX template, automatically replacing standard chapter identifiers when test results are injected into the system. For example, the IEC standard chapter number field code "IEC_Clause" is replaced with "IEC 62116 Clause 7.3.1" during execution, eliminating manual annotation bias. Second, the volatility data matrix is ​​directly written via the Apache POI XWPFTable interface, skipping the intermediate Excel transfer step and ensuring lossless transmission of 32-bit floating-point precision to the final report.

[0179] To address the high printing accuracy requirements of charts, a resolution setting method is enforced when calling the enhanced metafile conversion interface. The system automatically locks the output resolution to 600 dpi, meeting the mandatory printing accuracy requirements of the IEC certification guidelines. When an interactive chart is inserted, a standard chapter number text label is dynamically generated below the chart, with the font and size strictly adhering to the certification template specifications. This label is stored in conjunction with the chart, avoiding the misalignment risks caused by the separation of text and graphics in traditional solutions.

[0180] The final test report undergoes triple automatic verification: consistency between the clause number and the standard identifier selected during task submission; verification of the actual resolution of chart values; and verification of floating-point rounding errors in data tables. The entire process eliminates manual intervention, ensuring zero-format rejections during certification body review.

[0181] In another embodiment of this invention, existing technologies face significant obstacles in tracing the source of data link breaks caused by traditional parallel computing schemes. When a user discovers an anomaly in an interactive chart, they must manually record the timestamp and then query the original data file, the structured results database, and the computation log system. This process involves cross-platform operation: locating the original sampled value in MATLAB, retrieving the computation result record in MySQL, and finally verifying the Spark execution log. Actual testing shows that a single anomaly tracing requires switching between three software interfaces, taking over 45 minutes, and due to the disordered timing of parallel execution of thread groups, the error rate of manual verification is as high as 32%.

[0182] This solution reconstructs the traceability process by establishing a fully automated mapping link from pixel coordinates to raw data. When a user triggers an anomaly location command in the chart panel, the system automatically extracts the cursor's pixel coordinates and converts them into logical coordinates for data points (e.g., time axis t=1532ms) using the WebGL built-in coordinate transformer. Using these logical coordinates as the key, the system queries the inverted index table of the time-series database in real time to directly obtain the primary key of the associated record row in the structured result data table. This step establishes a precise association between "screen position" and "calculation result."

[0183] Based on the obtained record row primary key, the system performs a three-level timestamp alignment retrieval in the original binary file: first, a binary search method is used to accurately match the target timestamp; if the match fails due to clock drift, a ±10ms time window is initiated to scan adjacent records; finally, the existence of the timestamp is verified through a Bloom filter. This mechanism ensures that even with micro-offsets (<1ms) in timestamps caused by parallel computing, the true original data can still be located.

[0184] The source tracing results are dynamically visualized through a heatmap layer. The system extracts contextual data from 32 sampling points before and after the target time point, calculates the deviation of each point from the standard deviation, and maps it to a red-blue gradient. As the cursor moves, the heatmap refreshes in real time, with abnormal areas highlighted. The entire process is completed within 0.2 seconds, completely eliminating the need for manual verification and achieving 100% source tracing accuracy.

[0185] In another embodiment of this invention, existing OpenMP thread pools employ a fixed thread allocation strategy, distributing thread resources evenly across each computational task (such as ripple coefficient calculation and power grid response analysis). This approach has two major drawbacks: resource idleness, where the allocated threads become idle (measured idle rate reaches 65%) when the power grid response calculation (a lightweight task) is completed, while ripple coefficient calculation (a computationally intensive task) experiences task backlog due to insufficient threads; and blocking propagation, where lightweight tasks are blocked waiting for heavyweight tasks to complete before releasing the thread pool, leading to resource deadlock. Actual measurements show that when both types of tasks are performed concurrently, the overall computational latency increases by 210%.

[0186] The dynamic resource allocation technology solution of this invention:

[0187] 1. Calculate predefined weights

[0188] Weight formula derivation explanation: It represents the single execution time (in milliseconds) of algorithm template i on the benchmark hardware, which is pre-stored in the metadata database.

[0189] The formula is essentially a normalization process: the weight of the template with the shortest execution time is set to 1, and the weights of the other templates are increased proportionally according to their execution time.

[0190] Dimensional verification: Both the numerator and denominator are in the dimension of time (ms), therefore Wi It is a dimensionless proportionality coefficient.

[0191] 2. Work Stealing Mechanism (Algorithm Basis: Cilk Language Task Stealing Theory)

[0192] Triggering condition: When thread group G x The free rate of the circular buffer I x ≥40% (first preset threshold), and there exists thread group G. y buffer load L y When ≥80% (second preset threshold), cross-group theft is performed.

[0193] The theft process: from G y The system steals consecutive data blocks (including the original timestamp sequence) from the tail of the circular buffer. These data blocks are then migrated to G using atomic operations (Compare-and-Swap). x The buffer header. G x Immediately start computing threads to process the stolen data. The physical meaning is to break down resource barriers between thread groups and convert idle threads into effective computing power.

[0194] 3. Elastic scaling (Algorithm basis: Cloud computing elastic scaling model)

[0195] Expansion conditions: High-weight thread groups (W) are detected. i The computational delay D (>1.0) i ≥200ms (third preset threshold).

[0196] Expansion logic:

[0197] Allocate available threads from the public resource pool The public resource pool uses a Docker container cluster managed by Kubernetes, N add This indicates the number of threads that need to be dynamically increased for elastic scaling. W i D represents the computational complexity weight of the i-th data processing algorithm template, and its execution time in benchmark tests is determined. i This represents the computation delay of the i-th thread group, in milliseconds (ms), and is used to determine whether to trigger resizing.

[0198] Bind the new thread to the circular buffer of the target thread group.

[0199] Dimensional verification: W i (Dimensionless) and D i Multiplying by (ms) and dividing by 200 (ms) still results in a dimensionless value, which meets the requirement of an integer number of threads.

[0200] Scenario example:

[0201] Ripple calculation group G1: The weight W1 = 150 / 50 = 3.0 is derived from the baseline duration;

[0202] Grid response group G2: The weight W2=50 / 50=1.0 is derived from the baseline duration;

[0203] Total number of threads = 8, initial allocation: G1 thread count = 8 × 3.0 / (3.0 + 1.0) = 6, G2 thread count = 2.

[0204] Events: G2 completes computation, its buffer free rate I2 = 100% > 40%. G1 buffer load L1 = 90% > 80%; the system migrates data blocks stolen from G1 to G2, and G2 uses idle threads to process the data; when G1 latency rises to D1 = 210ms > 200ms, expansion is triggered: N add =4, adding 4 new threads to G1.

[0205] The system ensures a reasonable initial resource distribution through weighted allocation (mathematical basis: normalization model); eliminates idle and blocked resources through work stealing (an improvement on classic computer algorithms); and supports elastic expansion (using the dimensional consistency formula N). add =f(W i D i This achieves millisecond-level resource adjustment. Real-world testing shows that resource utilization increased to 98%, and latency for high-weight tasks decreased by 76%.

[0206] 4. Benchmark environment for dynamic resource allocation weighting formula

[0207] Hardware configuration: compute nodes, 2×Intel Xeon Gold 6248R (3.0GHz / 24 cores); memory, 256GB DDR4 ECC; storage: NVMe SSD RAID 0 (read speed 6GB / s);

[0208] Benchmark datasets: DC voltage fluctuation, sampling rate 10kHz, duration 24 hours (864 million data points); power grid frequency response, sampling rate 1kHz, duration 24 hours (86.4 million data points).

[0209] Weight formula calibration method: Perform 10 full calculations for each algorithm template, and take the average time as T. i ,

[0210] Ripple coefficient calculation logic, T 纹波 =150ms; Power grid response determination logic, T 电网 =50ms; Weight calculation: W i =T i / min(T1, T2, ...). In the example, W 纹波 =150 / 50=3.0, W电网 =50 / 50=1.0.

[0211] Threshold verification scenario: When the simulated load peak is 80%, the actual test results show that the latency of the high-weight thread group (ripple calculation) is reduced from 315ms in the traditional solution to 72ms, and the resource utilization rate is increased from 65% to 95%.

[0212] The Chinese definitions of technical terms and abbreviations are shown in the table below:

[0213] Table 1. Chinese Definitions of Technical Terms and Abbreviations

[0214]

[0215]

[0216]

[0217] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. An automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system, characterized in that, include: The system receives raw test data files via a web server, which include time-series data of DC bus voltage, AC output current, and battery charge and discharge power. Receive the test standard section identifier selected through the web interface and the input test parameters; The distributed computing framework is invoked to match the corresponding data processing algorithm template according to the test standard chapter identifier, and the original test data file is parsed in parallel based on the test parameters. The data processing algorithm template includes ripple coefficient calculation logic and power grid frequency response threshold determination logic. The ripple coefficient calculation logic is used to separate the ripple signal in the 0-100Hz frequency band, and the power grid frequency response threshold determination logic is executed based on the target power grid standard. Multithreading is used to simultaneously input the parsed data into multiple independent computing threads. Each computing thread corresponds to a data processing flow of a test standard section, and performs the following operations in each computing thread: Extract key performance indicator fields from the parsed data, execute numerical calculation logic according to the data processing algorithm template, and generate a structured result data table. Key performance indicator fields include DC voltage fluctuation rate and charge-discharge cycle efficiency. Based on the structured result data table, interactive charts are generated through the Canvas application interface combined with the Web graphics library rendering engine. The interactive charts support real-time display of data point coordinate information and the original data sample value with the corresponding timestamp triggered by cursor hover. The structured result data tables and interactive charts are categorized and stored in the time series database according to the test standard chapter identifiers. In response to the report generation command, the structured result data tables and interactive charts of the specified test standard chapters are extracted from the time series database and automatically filled into the preset Word report template to generate a test report file. The steps for displaying the raw data sample values ​​corresponding to the timestamp in real time include: When uploading the original test data file, a full file memory mapping is established through the mmap memory mapping system call, generating a read-only binary memory view; Build a Bloom filter index table, map timestamps to file storage offset addresses, and load the index table into the browser's IndexedDB cache; When the cursor hover event is triggered, the timestamp value is parsed from the data point coordinates, and the offset address is located within 1ms using a Bloom filter; and the instantaneous value of the original DC bus voltage of 64 consecutive sampling points before and after the offset address is extracted. The waveform is reconstructed by executing the Catmull-Rom cubic spline interpolation algorithm through a Web Worker thread, and then superimposed and rendered onto a Canvas layer. The interpolation waveform peak value and ripple coefficient calculation results are dynamically displayed at the cursor position.

2. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 1, characterized in that, Parallel computation is performed using multiple threads, specifically including: Create thread groups equal to the number of chapters in the test standard. Each thread group is bound to an independent circular buffer with a capacity of 1024 records. Each record contains a millisecond-level timestamp, DC bus voltage, and AC output current fields. The time alignment engine performs the following: sorts the parsed data in ascending order by the timestamp field, and establishes a mapping relationship between timestamp, DC voltage value, and AC current value in a hash table using the millisecond timestamp as the key. When the data of 10 complete power grid cycles accumulates in the circular buffer, the charge and discharge cycle efficiency calculation of the corresponding thread group is triggered. If a missing DC voltage or AC current value is detected at the same timestamp, an interrupt signal is sent to the exception handling coroutine and the data completion interface is invoked.

3. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 1, characterized in that, The storage steps for a time-series database include: The structured result data table is encoded in columnar storage format. The timestamp field is encoded using differential compression, and the DC voltage fluctuation rate field is converted to 32-bit floating-point numbers and then compressed using ZSTD lossless compression. Create a separate element storage partition for interactive diagrams, and name the element storage partition according to the standard chapter number; Data is written using a dynamic time-slicing strategy. When the DC voltage fluctuation rate data sampling rate is greater than 10kHz, it automatically switches to writing in batches every 5 seconds. Each batch of data is encapsulated in a protocol buffer format message body and includes a CRC32 checksum. A hierarchical cache structure is built in memory, including: a first-level cache, which stores the raw volatility data of the most recent 2 minutes; and a second-level cache, which loads data blocks of adjacent hours according to the access frequency. When creating a bidirectional B+ tree index, DC voltage fluctuation data with a frequency > 100Hz in the leaf nodes are marked as high-frequency bands and allocated independent solid-state drive storage blocks.

4. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 1, characterized in that, The execution of the ripple coefficient calculation logic includes: Extract the instantaneous value sequence of DC bus voltage from key performance indicator fields; Noise and real ripple signals are separated by a two-stage filtering unit, including: a first-stage high-pass filter unit to filter out high-frequency noise components generated by switching devices, and a second-stage low-pass filter unit to retain the real ripple signal in the 0-100Hz frequency band. A sliding window peak-to-peak value detection is performed on the instantaneous value sequence of the filtered DC bus voltage, wherein the window width is synchronized with the grid cycle; The basic threshold is set based on the rated voltage of the DC bus, and the actual judgment threshold is dynamically adjusted according to the state of charge of the battery: when the state of charge of the battery deviates from the median value, the basic threshold is adjusted proportionally to generate the actual judgment threshold. When the detected peak-to-peak value exceeds the actual judgment threshold, an anomaly is marked in the structured result data table, and an interactive chart is triggered to highlight the abnormal frequency band as a spectrum waterfall plot.

5. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 1, characterized in that, The steps to generate a Word report template include: Embed dynamic field codes for IEC standard chapter numbers in the DOCX template file; Write DC voltage fluctuation data to a specified table using the XWPF table interface of the Apache Document Processing Toolkit. When calling the enhanced metafile conversion interface, execute the resolution setting method to set the output resolution; When a chart is inserted, a standard chapter number text label is automatically added below the chart.

6. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 2, characterized in that, After generating interactive charts, execute the abnormal data tracing process: Receive data anomaly location instructions triggered by users through the visual interface, including the pixel coordinates of the cursor on the chart; The process involves mapping pixel coordinates back to the associated record rows in the structured result data table, including: extracting the logical coordinates of data points using the pixel reading method of the Web graphics library, querying the inverse index table of the time series database using the logical coordinates of the data points as the key, and obtaining the primary key of the record row. Based on the associated record rows, a three-level timestamp alignment retrieval is performed in the original test data file, including: main retrieval, which performs a binary search based on the record row timestamp field; secondary retrieval, which scans adjacent records with a time window of ±10ms if the main retrieval fails; and fault-tolerant retrieval, which calls a Bloom filter to verify the existence of timestamps. The retrieved raw data records and their context data from 32 sampling points before and after them are synchronously marked using a heatmap layer in an interactive chart. The heatmap color level reflects the data's deviation from the standard deviation.

7. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 1, characterized in that, The distributed computing framework performs dynamic resource allocation, including: For each data processing algorithm template, a computational complexity weight is predefined. The weight value is determined based on the benchmark test duration and stored in the metadata database. When creating a thread group, initial thread resources are allocated according to weight ratios, with thread groups having higher complexity weights being allocated more threads; The runtime dynamically balances the load through a work-stealing mechanism, specifically including: when the idle rate of the circular buffer of a thread group reaches a first preset threshold, stealing data blocks carrying the original timestamp sequence from the thread group whose buffer load exceeds a second preset threshold, and migrating them to the idle thread group through atomic operations; Real-time monitoring of computation latency for each thread group; if the latency of a high-weight thread group exceeds the third preset threshold, dynamically allocate available threads from the public resource pool for elastic scaling.

8. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 7, characterized in that, The first preset threshold, the second preset threshold, and the third preset threshold are 40%, 80%, and 200ms, respectively.

9. The automated processing method for grid-connected test data of a photovoltaic inverter with built-in energy storage system as described in claim 1, characterized in that, The target power grid standards include IEC 62116 and / or UL 1741.

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