A design method, device and storage medium for a counter

Abstract

This invention relates to the field of data processing technology, specifically to a design method, apparatus, and storage medium for a counter. The method includes: when the counter's count value changes abruptly, adjusting an abnormal signal to a preset signal to determine the current counting state of the counter; if the current counting state satisfies the preset counting state, transferring the current count value to the previous count value; determining the difference between the current count value and the previous count value; if the difference is greater than a preset threshold, adjusting the abnormal signal and generating an interrupt signal to stop updating the previous count value; if a self-recovery function is configured, the hardware transfers the previous count value to the current count value and restores the abnormal signal to start counting; if a self-recovery function is not configured, the software processes the counter in response to the interrupt signal. This method reduces labor and hardware costs.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a design method, apparatus, and storage medium for a counter in the field of data processing technology. Background Technology

[0002] In software drivers, timers are commonly used for various delay operations. When the count value meets a certain condition, the process continues to the next step or is interrupted. Normally, the timer counts sequentially. However, if the timer's clock is unstable or has glitches, causing the timer count value to jump, it may not reach the threshold determined by the software within the predetermined time, thus preventing the normal software processing flow from proceeding. Summary of the Invention

[0003] The purpose of this invention is to provide a design method, device, and storage medium for a counter, and the specific technical solution adopted is as follows:

[0004] In a first aspect, embodiments of the present invention provide a method for designing a counter, the method comprising:

[0005] An abnormal signal is generated when the counter value changes abruptly.

[0006] The abnormal signal is adjusted to a preset signal to determine the current counting state of the counter;

[0007] If the current counting state satisfies the preset counting state, the current count value of the counter is passed to the previous count value;

[0008] Determine the difference between the current count value and the previous count value;

[0009] If the difference is greater than a preset threshold, the abnormal signal is adjusted to generate an interrupt signal to stop updating the previous count value;

[0010] If the counter is configured with a self-recovery function, the previous count value is passed to the current count value via hardware, and the abnormal signal is restored to start counting; if the counter is not configured with a self-recovery function, the counter is processed by software in response to the interrupt signal.

[0011] Secondly, embodiments of the present invention provide a counter design apparatus, the apparatus comprising:

[0012] The generation module is used to generate an abnormal signal when the counter value changes abruptly.

[0013] The first determining module is used to adjust the abnormal signal to a preset signal and determine the current counting state of the counter;

[0014] The transmission module is used to transmit the current count value of the counter to the previous count value if the current count state satisfies the preset count state.

[0015] The second determining module is used to determine the difference between the current count value and the previous count value;

[0016] An adjustment module is used to adjust the abnormal signal and generate an interrupt signal if the difference is greater than a preset threshold, so as to stop updating the previous count value.

[0017] The recovery module is used to, when the counter is configured with a self-recovery function, transmit the previous count value to the current count value via hardware and recover the abnormal signal to start counting; when the counter is not configured with a self-recovery function, it processes the counter via software in response to the interrupt signal.

[0018] Thirdly, a computer program product is provided, comprising: computer program code, which, when run on a computer, causes the computer to perform the method described in the first aspect.

[0019] Fourthly, a computer-readable storage medium is provided that stores computer program code, which, when executed on a computer, causes the computer to perform the method described in the first aspect.

[0020] This invention has the following beneficial effects: When the counter's count value jumps, an abnormal signal (i.e., an error signal) is generated; if the detected abnormal signal meets a preset signal, the current counting state of the counter is determined; if the current counting state meets the preset counting state, the current count value of the counter is passed to the previous count value; thus, by generating an abnormal signal when the counter's count value jumps, and detecting the abnormal signal and the current counting state of the counter, counting continues while the current count value is passed to the previous count value when both the abnormal signal and the current counting state meet the conditions, thereby achieving real-time updating of the count value. Then, the difference between the current count value and the previous count value is determined; if the difference is greater than a preset threshold, the abnormal signal is adjusted, and an interrupt signal is generated to stop updating the previous count value; if the counter is configured with a self-recovery function, the previous count value is passed to the current count value through hardware, and the abnormal signal is restored to start counting; if the counter is not configured with a self-recovery function, the counter is processed by software in response to the interrupt signal. In this way, an error signal can be sent when the counter value changes, which can be easily detected by the software. Moreover, a self-correcting function can be implemented when the counter value changes, reducing the probability of counter counting errors; thereby reducing the human and hardware costs introduced by problems caused by clock fluctuations. Attached Figure Description

[0021] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram illustrating the implementation flow of a counter design method provided in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of another implementation flow of a counter design method provided in an embodiment of the present invention;

[0024] Figure 3 This is another schematic diagram of the implementation process of a counter design method provided in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the composition structure of a counter design device provided in an embodiment of the present invention;

[0026] Figure 5This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0027] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a counter design method proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments may be combined by any suitable form.

[0028] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more.

[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0031] This invention provides a method for designing a counter. The specific scheme of this counter design method is described below with reference to the accompanying drawings. Please refer to... Figure 1 The diagram illustrates a flowchart of a counter design method according to an embodiment of the present invention, the method comprising:

[0032] 101. An abnormal signal is generated when the counter value changes abruptly.

[0033] Here, when a jump in the count value is detected during the counting process, an abnormal signal (i.e., an error signal) is generated.

[0034] 102. Adjust the abnormal signal to a preset signal to determine the current counting state of the counter.

[0035] Here, the preset signal can be custom-defined, for example, a preset signal of 1 or 0. Taking a preset signal of 0 as an example, the initial state of the abnormal signal is the same as the normal counting state. When an abnormality occurs, the state of the abnormal signal is reversed from the initial state. For example, if the initial state of the abnormal signal is 0 (low level), then when an abnormality occurs, the abnormal signal is pulled high, that is, the abnormal signal is adjusted to 1. At the same time, the current counting state of the counter is obtained, which is used to characterize whether the counter can count normally.

[0036] 103. If the current counting state satisfies the preset counting state, the current count value of the counter is passed to the previous count value.

[0037] Here, the preset counting state can be a custom state, such as a normal counting state. If the current counting state is a normal counting state, it is determined that the current counting state satisfies the preset counting state, and the current count value of the counter is assigned to the previous count value, while the counter continues counting. In this way, the previous count value can be updated in real time while the counter is counting, and the accuracy of the count value is improved.

[0038] In some possible implementations, step 103 above can be achieved through hardware processing. When the counting is normal (i.e., there is no error signal), the current count value (timer_value_now) is assigned to the previous count value (timer_value_last).

[0039] 104. Determine the difference between the current count value and the previous count value.

[0040] Here, while controlling the counter to count normally, the difference between the current count value and the previous count value is calculated.

[0041] In some possible implementations, during multiple consecutive counts, it is determined whether the current counting state of the counter is in a normal counting state. Multiple consecutive counts can be understood as, after the counter experiences a jump, generates an abnormal signal, and pulls the abnormal signal low, in subsequent multiple consecutive counts, the current counting state of the counter is statistically analyzed to determine whether the counter can count normally. If the current counting state of the counter is normal in all multiple consecutive counts, it is determined whether the abnormal signal was detected during these multiple counts; that is, whether an abnormal signal was received during the multiple consecutive counts. If no abnormal signal was detected, the current count value of the counter is passed to the previous count value, and counting continues, with a synchronous comparison between the current count value and the previous count value. Thus, by determining whether the counter is continuously in a normal counting state during multiple consecutive counts, and assigning the current count value to the previous count value when the counter is continuously in a normal counting state, counting continues, and the current count value is synchronously compared with the previous count value, thereby improving counting accuracy.

[0042] 105. If the difference is greater than a preset threshold, adjust the abnormal signal and generate an interrupt signal to stop updating the previous count value.

[0043] Here, the preset threshold can be a custom value, for example, a preset threshold of n. The initial state of the abnormal signal is the same as the normal counting state. When an abnormality occurs, the state of the abnormal signal is reversed from the initial state. If the difference is greater than the preset threshold, the abnormal signal, which is currently at a low level, is pulled high, and an interrupt signal is generated to stop updating the previous count value, i.e., to stop assigning the current count value to the previous count value. If the difference is less than the preset threshold, the abnormal signal remains at a low level, i.e., the abnormal signal is 0.

[0044] In some possible implementations, step 105 above can be achieved through... Figure 2 The steps shown are to be implemented as follows:

[0045] 201, determine a candidate signal that is opposite to the preset signal.

[0046] Here, if the preset signal is 0, then the candidate signal is 1; if the preset signal is 1, then the candidate signal is 0.

[0047] 202. If the difference is greater than a preset threshold, the abnormal signal is adjusted from the preset signal to the candidate signal, and the interrupt signal is output to the CPU, so that the counter stops updating the previous count value through hardware control.

[0048] Here, if the difference is less than a preset threshold, the error signal is 0 (i.e., error == 0), and the current count value is assigned to the previous count value to continue updating the previous count value. If the difference is greater than the preset threshold and the preset signal is 0, the error signal is pulled high, making the error signal 1, and an interrupt signal is output to the CPU. Thus, without a self-recovery function, the CPU processes the counter through the callback function bound to the interrupt signal and the current processing state of the software corresponding to the counter. With a self-recovery function configured, the counter is stopped from updating the previous count value through hardware control. In this way, when a difference greater than the preset threshold is detected, the state of the error signal is changed, an interrupt signal is output to the CPU, and the assignment of the current count value to the previous count value is stopped simultaneously, thereby ensuring the accuracy of the current count value.

[0049] The update process for the abnormal signal is as follows: if the difference between the current count value and the previous count value is greater than the preset threshold, then the abnormal signal is raised to 1; if the difference between the current count value and the previous count value is less than the preset threshold, then the abnormal signal is 0.

[0050] The update process for the previous count value (timer_value_last) is as follows: if the exception signal is 0, then the current count value is assigned to the previous count value; if the exception signal is 1, then the previous count value is not modified.

[0051] The update process for the current count value (timer_value_now) is as follows: If the error signal is 1, determine whether the self-recovery function is configured. If the self-recovery function is configured, assign the previous count value to the current count value. If the self-recovery function is not configured, do not make any changes.

[0052] 106. If the counter is configured with a self-recovery function, the previous count value is transmitted to the current count value via hardware, and the abnormal signal is restored to start counting.

[0053] Here, when configured with self-recovery, no interrupt is needed; the hardware can directly perform the repair, and the software doesn't need to be aware of it. That is, if the software is configured with self-recovery, the hardware automatically transfers the value of `timer_value_last` to `timer_value_now`, starts counting, and pulls the error signal low (the state is not limited to being low; it just needs to be different from the state when the error occurred).

[0054] 107. In the absence of a self-recovery function configured for the counter, the counter is processed by software in response to the interrupt signal.

[0055] Here, when the self-recovery function is not required, an interrupt signal needs to be generated so that the software can detect the abnormality through the interrupt signal and perform corresponding processing through the CPU, such as reconfiguring the timer to count.

[0056] In some possible implementations, the self-recovery function of the timer can be configured through the following process:

[0057] First, in the preset register, determine the setting bit used to determine whether to automatically recover when the counter jumps.

[0058] Here, the preset register can be a control register. The set bit can be any bit set in the preset register. By setting a bit in the control register, it is used to determine whether to perform automatic recovery when a transition occurs.

[0059] Then, based on the setting bit, a self-recovery function is configured in the counter.

[0060] Here, a preset value for controlling the automatic recovery of the counter is obtained, and this preset value is assigned to the setting bit to configure the self-recovery function in the counter. This preset value can be 0 or 1. By writing 1 to the setting bit, it indicates that the self-recovery function is configured in the counter, and the hardware can automatically assign the current count value to the previous count value and start counting, while simultaneously pulling up an abnormal signal.

[0061] In some embodiments, by determining a bit value opposite to the preset value and assigning that bit value to the setting bit, the counter stops updating the previous count value when a transition occurs and maintains the current data state of the counter.

[0062] For example, the default value is 1, which means that the counter will automatically resume when it changes. When the software writes 0 to this bit (i.e., the bit value opposite to the default value), it means that when the counter changes, only the update of timer_value_last will be stopped, and no other values ​​will be processed.

[0063] In some possible implementations, if the counter is not configured with a self-recovery function, the current processing state of the callback function bound to the interrupt signal and the software corresponding to the counter is determined; and the counter is processed based on the callback function and the current processing state of the software.

[0064] Here, if the software does not have a self-recovery function, appropriate handling can be performed in the interrupt handler function after receiving an interrupt caused by an error signal. When the CPU receives the interrupt signal, it executes the callback function bound to that interrupt. The specific function implementation can be determined according to the software flow; it can skip directly after an error occurs, or the timer can be reconfigured to restart the counting.

[0065] In this embodiment of the invention, when the counter's count value jumps, an abnormal signal (i.e., an error signal) is generated. If the detected abnormal signal satisfies a preset signal, the current counting state of the counter is determined. If the current counting state satisfies the preset counting state, the current count value of the counter is passed to the previous count value. Thus, by generating an abnormal signal when the counter's count value jumps, and detecting both the abnormal signal and the current counting state of the counter, counting continues while the current count value is passed to the previous count value when both conditions are met, thereby achieving real-time updates to the count value. Then, the difference between the current count value and the previous count value is determined. If the difference is greater than a preset threshold, the abnormal signal is adjusted, and an interrupt signal is generated to stop updating the previous count value. If the counter is configured with a self-recovery function, the previous count value is passed to the current count value via hardware, and the abnormal signal is restored to start counting again. If the counter is not configured with a self-recovery function, the counter is processed by software in response to the interrupt signal. In this way, an error signal can be sent when the counter value changes, which can be easily detected by the software. Moreover, a self-correcting function can be implemented when the counter value changes, reducing the probability of counter counting errors; thereby reducing the human and hardware costs introduced by problems caused by clock fluctuations.

[0066] In some possible implementations, it can be achieved through Figure 3 The process shown is implemented as follows:

[0067] First, the error signal is pulled low (i.e., error == 0). Second, the current count value (timer_value_now) is passed to the previous count value (timer_value_last), and counting continues. Third, each time the timer counts, it simultaneously calculates |timer_value_last - timer_value_now|. When the difference is greater than a preset threshold, the error signal is pulled high (i.e., error == 1), sending an interrupt to the CPU (not limited to interrupts, it can be any form of signal), and the value of timer_value_last stops updating. When the difference is less than the preset threshold, the error signal is 0 (i.e., error == 0), and the previous count value is updated again.

[0068] Secondly, the software can be configured via registers to determine whether self-recovery is required when a count value jump occurs. If the software is configured with self-recovery, the hardware automatically transfers the previous count value to the current count value, starts counting, and pulls the error signal low (the state is not limited to being low, as long as it is different from the state when the error occurred). If the software is not configured with self-recovery, appropriate handling can be performed in the interrupt handler function after receiving an error interrupt.

[0069] This invention provides a design apparatus for a counter, such as... Figure 4 As shown, the device 400 includes:

[0070] The generation module 401 is used to generate an abnormal signal when the counter value changes abruptly.

[0071] The first determining module 402 is used to adjust the abnormal signal to a preset signal and determine the current counting state of the counter;

[0072] The transmission module 403 is used to transmit the current count value of the counter to the previous count value if the current count state satisfies the preset count state.

[0073] The second determining module 404 is used to determine the difference between the current count value and the previous count value;

[0074] The adjustment module 405 is used to adjust the abnormal signal and generate an interrupt signal if the difference is greater than a preset threshold, so as to stop updating the previous count value.

[0075] The recovery module 406 is used to, when the counter is configured with a self-recovery function, transmit the previous count value to the current count value through hardware and recover the abnormal signal to start counting; when the counter is not configured with a self-recovery function, it processes the counter through software in response to the interrupt signal.

[0076] In some possible implementations, the transmission module 403 is further configured to determine that the current counting state satisfies a preset counting state if the current counting state is a normal counting state; assign the current counting value of the counter to the previous counting value; and control the counter to continue counting.

[0077] In some possible implementations, the adjustment module 405 is further configured to determine a candidate signal opposite to the preset signal; if the difference is greater than a preset threshold, the abnormal signal is adjusted from the preset signal to the candidate signal, and the interrupt signal is output to the CPU, thereby controlling the counter to stop updating the previous count value through the hardware.

[0078] In some possible implementations, the recovery module 406 is further configured to, if the counter is not configured with a self-recovery function, determine the callback function bound to the interrupt signal and the current processing state of the software corresponding to the counter; and process the counter based on the callback function and the current processing state of the software.

[0079] In some possible implementations, the recovery module 406 is further configured to determine a setting bit in a preset register for determining whether to perform automatic recovery when the counter jumps; and to configure an automatic recovery function in the counter based on the setting bit.

[0080] In some possible implementations, the recovery module 406 is further configured to acquire a preset value for controlling the automatic recovery of the counter; and assign the preset value to the setting bit to configure the self-recovery function in the counter.

[0081] In some possible implementations, the recovery module 406 is further configured to determine a bit value opposite to the preset value; assign the bit value to the setting bit so that the counter stops updating the previous count value when a transition occurs, and maintains the current data state of the counter.

[0082] In some possible implementations, the transmission module 403 is further configured to determine whether the current counting state of the counter is a normal counting state during multiple consecutive counts; if the current counting state of the counter is a normal counting state during multiple consecutive counts, determine whether the abnormal signal is detected during multiple consecutive counts; if the abnormal signal is not detected during multiple consecutive counts, transmit the current count value of the counter to the previous count value, continue counting, and synchronously compare the current count value and the previous count value.

[0083] Optionally, the transmission medium can be a wired link (e.g., but not limited to, coaxial cable, optical fiber, and Digital Subscriber Line (DSL)) or a wireless link (e.g., but not limited to, Wireless Fidelity (WIFI), Bluetooth, and mobile device networks). It should be noted that the system provided in the above embodiments is only an example illustrating the division of the functional modules described above. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, and will not be repeated here.

[0084] Figure 5This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. For example, as shown... Figure 5 As shown, the computer device 500 includes: a memory 501, a processor 502, and a computer program 503 stored in the memory 501 and running on the processor 502, wherein when the processor 502 executes the computer program 503, the computer device can execute any of the counter design methods described above.

[0085] Furthermore, this embodiment of the invention also protects a system that may include a memory and a processor. The memory stores executable program code, and the processor is used to call and execute the executable program code to perform a counter design method provided by this embodiment of the invention. This embodiment can divide the system into functional modules based on the above method example. For example, each module can correspond to a specific function, or two or more functions can be integrated into a single processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division; other division methods may exist in actual implementation. It should also be noted that all relevant content of each step involved in the above method embodiment can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0086] It should be understood that the system provided in this embodiment is used to execute the above-described counter design method, and therefore can achieve the same effect as the above-described implementation method. When using integrated units, the system may include a processing module and a storage module. When the system is applied to a device, the processing module can be used to control and manage the device's operations. The storage module can be used to support the device in executing relevant program code, etc. The processing module may be a processor or a controller, which can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of Digital Signal Processing (DSP) and a microprocessor, etc., and the storage module may be a memory.

[0087] Furthermore, the system provided in the embodiments of the present invention may specifically be a chip, component, or module. The chip may include a connected processor and a memory. The memory stores instructions, and when the processor calls and executes the instructions, the chip can execute a counter design method provided in the above embodiments. This embodiment also provides a computer-readable storage medium storing computer program code. When the computer program code is run on a computer, the computer executes the aforementioned method steps to implement the counter design method provided in the above embodiments.

[0088] This embodiment also provides a computer program product. When the computer program product is run on a computer, it causes the computer to execute the aforementioned related steps to implement the counter design method provided in the above embodiment. The system, computer-readable storage medium, computer program product, or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here. Through the description of the above embodiments, those skilled in the art can understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by this invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, system or unit, and can be electrical, mechanical or other forms.

[0089] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multiple task processing and parallel processing are also possible. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The above content is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for designing a counter, characterized in that, The method includes: An abnormal signal is generated when the counter value changes abruptly. The abnormal signal is adjusted to a preset signal, which is 0 or 1, to determine the current counting state of the counter; If the current counting state satisfies the preset counting state, the current count value of the counter is passed to the previous count value, and the counter is controlled to continue counting; the current counting state is a normal counting state. Determine the difference between the current count value and the previous count value; If the difference is less than a preset threshold, the previous count value is assigned to the current count value to continue updating the previous count value; If the difference is greater than a preset threshold, the abnormal signal is adjusted from the preset signal to a candidate signal, which is the opposite of the preset signal. An interrupt signal is generated and transmitted to the CPU to stop updating the previous count value. If the counter is configured with a self-recovery function, the previous count value is passed to the current count value via hardware, and the abnormal signal is recovered to start counting. If the counter is not configured with a self-recovery function, determine the callback function bound to the interrupt signal and the current processing state of the software corresponding to the counter, and process the counter based on the callback function and the current processing state of the software.

2. The design method of a counter according to claim 1, characterized in that, The method further includes: In the preset register, a setting bit is determined to determine whether to perform automatic recovery when the counter jumps; Based on the setting bit, a self-recovery function is configured in the counter.

3. The counter design method according to claim 2, characterized in that, The step of configuring a self-recovery function in the counter based on the setting bit includes: Obtain a preset value for controlling the self-recovery of the counter; A preset value is assigned to the setting bit to configure a self-recovery function in the counter.

4. The counter design method according to claim 3, characterized in that, The method further includes: Determine a bit value that is opposite to the preset value; The bit value is assigned to the setting bit so that the counter stops updating the previous count value when a transition occurs, and maintains the current data state of the counter.

5. The design method of a counter according to claim 1, characterized in that, The method further includes, if the current counting state satisfies a preset counting state, passing the current count value of the counter to the previous count value; In multiple consecutive counts, it is determined whether the current counting state of the counter is a normal counting state; If the current counting state of the counter is normal in all of the consecutive counts, determine whether the abnormal signal was detected in the consecutive counts. If the abnormal signal is not detected in the consecutive counts, the current count value of the counter is passed to the previous count value, the counting continues, and the current count value and the previous count value are compared synchronously.

6. A design device for a counter, characterized in that, The design device for the counter includes: The generation module is used to generate an abnormal signal when the counter value changes abruptly. The first determining module is used to adjust the abnormal signal to a preset signal, wherein the preset signal is 0 or 1, and to determine the current counting state of the counter; The transmission module is used to transmit the current count value of the counter to the previous count value and control the counter to continue counting if the current counting state meets the preset counting state; the current counting state is a normal counting state. The second determining module is used to determine the difference between the current count value and the previous count value; An adjustment module is used to assign the previous count value to the current count value if the difference is less than a preset threshold, so as to continue updating the previous count value; if the difference is greater than the preset threshold, adjust the abnormal signal, change the abnormal signal from the preset signal to a candidate signal, the candidate signal being opposite to the preset signal, generate an interrupt signal and transmit it to the CPU to stop updating the previous count value. The recovery module is used to, when the counter is configured with a self-recovery function, transmit the previous count value to the current count value via hardware and recover the abnormal signal to start counting; when the counter is not configured with a self-recovery function, it determines the callback function bound to the interrupt signal and the current processing state of the software corresponding to the counter, and processes the counter based on the callback function and the current processing state of the software.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on an electronic device, cause the electronic device to perform the method as described in any one of claims 1 to 5.

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