UVM verification platform and method for RDMA data path
Through the design of the UVM verification platform, the first agent and the second agent are used to process and convert transaction data on the RDMA data path, which solves the problems of complexity and low efficiency of existing RDMA network card verification and achieves efficient verification and platform reusability.
Patent Information
- Application Number
- CN202510908892.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-01
- Publication Date
- 2025-10-17
AI Technical Summary
Existing RDMA network card verification methods are complex and inefficient, and cannot effectively simulate the continuous working state of RDMA, resulting in inaccurate and inefficient verification, and poor reusability of the verification platform.
Using the UVM verification platform, transaction data is sent to the design under test (DUT) through the first agent. The DUT parses and sends the data to the second agent. The second agent performs transaction conversion. The scoreboard verifies the DUT based on the transaction data, simplifying the intermediate processing steps.
The verification efficiency of the RDMA data path and the reusability of the verification platform are improved, ensuring that the verification logic is consistent with the actual working status and reducing unnecessary intermediate processing steps.
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Figure CN120803832A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of functional verification, in particular to a UVM verification platform and method of RDMA data path. BACKGROUND
[0002] Remote Direct Memory Access (RDMA) is a technology that directly accesses remote memory, that is, data can be directly migrated from one system to another remote system memory. Reduces the consumption of central processing unit in the process of data transmission, liberates CPU processing period, and further improves the system processing performance. At present, the RDMA network card on the market is all using PCIe (PCI-express) standard interface, and in the process of RDMA request message, PCIe protocol needs to be converted for many times, so that RDMA can directly access CPU memory.
[0003] Due to the complexity of conversion between PCIe and CPU protocol, it is very complex and troublesome to form different kinds of data packets by PCIe in verification, and temporary programming is prone to error. If the verification personnel randomly test by this method, various unallowed abnormal situations of PCIe module may occur, which causes the verification to be unable to proceed. Another verification method is to respectively verify the results in the state of four independent channels of AXI4-Stream interface. However, this method has defects. On the one hand, the verification is sent to the opposite end, and then the opposite end receives and directly compares once, and then returns to compare again, which is equivalent to comparing multiple times. The overall logic does not conform to the continuous working state of RDMA, that is, it does not conform to the actual working logic of RDMA network card. RDMA network communication usually needs to consider the interaction between multiple channels, and independent verification cannot reflect the actual system behavior. On the other hand, the efficiency is low, multiple result comparisons are needed, which increases the verification time and complexity, and reduces the reusability of the verification platform. SUMMARY
[0004] Therefore, the present application provides a UVM verification platform and method of RDMA data path, which can completely simulate and verify the working logic of the design under test DUT in the process of data transmission and reading, reduce unnecessary intermediate processing steps, and improve the verification efficiency and the reusability of the verification platform.
[0005] According to an aspect of the present application, the embodiment of the present application provides a UVM verification platform of an RDMA data channel, the UVM verification platform comprising: a top layer; the top layer encapsulating a test environment class; wherein the test environment class comprises a DUT, a first agent, a second agent and a score board; the DUT is an RDMA;
[0006] The first agent is used for issuing first transaction data to the DUT.
[0007] The DUT is used for parsing the first transaction data and sending the parsed first transaction data to the second agent.
[0008] The second agent is used for performing transaction conversion on the parsed first transaction data to generate new transaction data and feeding back the new transaction data to the first agent through the DUT.
[0009] The score board is used for verifying the DUT based on the first transaction data and the new transaction data.
[0010] According to another aspect of the present application, the embodiment of the present application further provides a UVM verification method of an RDMA data channel, which is suitable for the UVM verification platform according to any of the embodiments of the present application, and the UVM verification method comprises:
[0011] The first agent issues first transaction data to the DUT; wherein the first test stimulus defines an issuing format of the first transaction data.
[0012] The DUT parses the first transaction data and sends the parsed first transaction data to the second agent.
[0013] The second agent performs transaction conversion on the parsed first transaction data to generate new transaction data and feeds back the new transaction data to the first agent through the DUT.
[0014] The score board verifies the DUT based on the first transaction data and the new transaction data.
[0015] According to another aspect of the present application, the embodiment of the present application further provides a computer device, which comprises:
[0016] at least one processor; and
[0017] a memory connected with the at least one processor in communication; wherein
[0018] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the UVM verification method of the RDMA data path according to any one of the embodiments of the application.
[0019] According to another aspect of the application, the embodiments of the application further provide a computer readable storage medium storing computer instructions for enabling a processor to implement the UVM verification method of the RDMA data path according to any one of the embodiments of the application when executed by the processor.
[0020] According to another aspect of the application, the embodiments of the application further provide a computer program product comprising a computer program for implementing the UVM verification method of the RDMA data path according to any one of the embodiments of the application when executed by a processor.
[0021] The technical effect of the application is that the first proxy end issues first transaction data to the DUT, and then the DUT parses the first transaction data after receiving the first transaction data and sends the parsed first transaction data to the second proxy end. Thus, the second proxy end converts the parsed first transaction data into new transaction data through transaction conversion, and feeds back the new transaction data through the DUT. Finally, the score board verifies the DUT based on the first transaction data and the new transaction data. The above technical solution processes the first transaction data through the first proxy end and the DUT, and then converts the processed first transaction data into new transaction data through the second proxy end. Thus, the score board verifies the DUT based on the first transaction data and the new transaction data, which can completely simulate and verify the working logic of the DUT in the data transmission and reading process, reduce unnecessary intermediate processing steps, and improve the verification efficiency and the reusability of the verification platform.
[0022] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0024] Figure 1A schematic diagram of the architecture of a UVM verification platform for an RDMA data path provided by one embodiment of the present invention;
[0025] Figure 2 A schematic diagram of the architecture of a UVM verification platform for an RDMA data path provided by an embodiment of the present invention;
[0026] Figure 3 A schematic diagram of the structure of the connection between ports on both sides of an RDMA network according to an embodiment of the present invention;
[0027] Figure 4 A flowchart of a UVM verification method for an RDMA data path provided by one embodiment of the present invention;
[0028] Figure 5 A schematic structural diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0029] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0031] In one embodiment, Figure 1 The following is a schematic diagram of the architecture of a UVM verification platform for an RDMA data path provided by an embodiment of the present invention. This embodiment is applicable to situations when verifying an RDMA data path.
[0032] like Figure 1As shown, the UVM verification platform of the RDMA data channel in the embodiment includes a top layer, and the top layer encapsulates a test environment class. The test environment class includes a first agent 110, a design under test (DUT) 120, a second agent 130, and a score board 140. The DUT 120 is an RDMA.
[0033] The first agent 110 is configured to issue first transaction data to the DUT 120.
[0034] The DUT 120 is configured to parse the first transaction data and send the parsed first transaction data to the second agent 130.
[0035] The second agent 130 is configured to perform transaction conversion on the parsed first transaction data to generate new transaction data, and feed the new transaction data back to the first agent 110 through the DUT.
[0036] The score board 140 is configured to verify the DUT based on the first transaction data and the new transaction data.
[0037] The data information included in the first transaction data at least includes original data content, a sequence number, and a destination address. The original data content can include a TLP packet and a payload, and the TLP packet includes tag information. The tag information is a key field in a TLP header and is used to identify a transaction. The new transaction data refers to new transaction data after transaction signal conversion, and the new transaction data in the embodiment includes second data information and reception status information. The second data information at least includes new data content, message length information, a sequence number, and address information returned by the second agent. The reception status information represents feedback of whether the second agent successfully receives the first transaction data. Of course, the new data content of the new transaction data also includes a TLP packet and a payload, except that the signal state is different.
[0038] In the embodiment, the design under test (DUT) is a remote direct memory access (RDMA). The RDMA has two side ports, which are connected to the first agent and the second agent, respectively. For example, the first agent is a local Host side port, and the second agent is a Mac side port. Of course, the local Host side port can also be connected to a local device, and the Mac side port can be connected to a switch.
[0039] In the embodiment, the first agent 110 is connected with one end of the DUT 120, and issues the first transaction data to the DUT 120. The other end of the DUT 120 is connected with the second agent 130. After receiving the first transaction data issued by the DUT 120, the first transaction data is parsed, and the parsed first transaction data is sent to the second agent 130. In the embodiment, the first agent is connected with the DUT, the DUT is also connected with the second agent, and the communication mode between them is a handshake signal carrying protocol. In the embodiment, the handshake signal carrying protocol can include but is not limited to AXI4-Stream protocol, AXI4 protocol, AXI4-Lite protocol, and Quick Path Interconnect (QPI) protocol. For example, the communication is performed through the AXI4-Stream protocol. In the AXI4-Stream protocol, the Tvalid and Tready signals are a pair of handshake signals. When the Tready signal transmitted by the second agent is at a high level, it indicates that the Tready signal is valid, and the second agent is ready to receive data. At this time, the first agent can generate the first test stimulus required by the DUT at the AXI port. Since the first test stimulus specifies the issuing format of the first transaction data, the first transaction data can be issued according to the issuing format specified by the first test stimulus. It can be understood that Tvalid represents sending valid, Tready represents receiving valid, and it indicates that the second agent is ready to receive data. In the embodiment, valid can be understood as a state at a high level. For example, only in the same clock cycle when Tvalid = 1 and Tready = 1, the data is successfully transmitted.
[0040] In the embodiment, the second agent 130 is connected with the DUT 120. After receiving the parsed first transaction data transmitted by the DUT 120, the parsed first transaction data is transaction converted, so as to generate new transaction data. The new transaction data is fed back to the first agent 110 through the DUT. At this time, since the first agent 110 includes a plurality of monitors, one of the monitors can monitor and obtain the new transaction data transmitted by the DUT 120 from the second agent 130 in real time, and transmit the new transaction data to the score board 140. In addition, after the first agent 110 issues the first transaction data to the DUT 120, another monitor included in the first agent 110 can also monitor and obtain the first transaction data transmitted to the DUT 120 in real time, and transmit the first transaction data to the score board. Therefore, the score board 140 verifies the DUT based on the first transaction data and the new transaction data, so as to complete the verification.
[0041] In an embodiment, the first agent end is a host agent end, and the second agent end is a MAC agent end; or the first agent end is a MAC agent end, and the second agent end is a host agent end. It can be understood that the first agent end and the second agent end can be interchanged. If the first agent end is a host agent end, the scoreboard is connected with the host agent end; if the first agent end is a MAC agent end, the scoreboard is connected with the MAC agent end.
[0042] The above technical solution of the embodiment of the application can process the first transaction data by the first agent end and the DUT, convert the processed first transaction data into new transaction data by the second agent end, and thus verify the DUT based on the first transaction data and the new transaction data, so that the working logic of the DUT in the data transmission and reading process can be completely simulated and verified, unnecessary intermediate processing steps are reduced, and the verification efficiency and the reusability of the verification platform are improved.
[0043] In an embodiment, the first agent end comprises a first sequence transmitter, a first driver, a first monitor and a second monitor.
[0044] The first sequence transmitter is connected with the first sequence generator and the first driver respectively; the first driver is connected with the DUT; the first monitor and the second monitor are connected with the scoreboard respectively; and the first monitor and the second monitor are also connected with the DUT respectively.
[0045] The first sequence generator is configured to generate a first test stimulus corresponding to the first agent end, redefine the first transaction data according to the first test stimulus, and transmit the redefined first transaction data to the first sequence transmitter; wherein the first test stimulus comprises a first transaction data delivery format.
[0046] The first sequence transmitter is configured to transmit the first transaction data to the first driver.
[0047] The first driver is configured to transmit the first transaction data to the DUT.
[0048] The first monitor is configured to monitor and acquire the first transaction data transmitted by the first driver to the DUT, and transmit the first transaction data to the scoreboard.
[0049] The second monitor is configured to monitor and acquire the new transaction data transmitted by the DUT, and transmit the new transaction data to the scoreboard.
[0050] The first test stimulus specifies the format of the first transaction data, which can include but is not limited to the maximum data length of the first transaction data. The first transaction data is user-defined related transaction data, such as data content that needs to be transmitted, and then the first transaction data is redefined according to the format and template specified by the first test stimulus to form transaction data, so as to transmit the redefined first transaction data to the first sequence transmitter.
[0051] In this embodiment, the first sequence generator generates the first test stimulus corresponding to the first agent, and then redefines the first transaction data according to the first test stimulus, so as to form the first transaction data in a specified format, and transmits the redefined first transaction data to the first sequence transmitter. After the first sequence transmitter receives the first transaction data, the first transaction data is transmitted to the first driver. It can be understood that the first sequence transmitter is equivalent to a transmission channel between the first sequence generator and the first driver, which transmits the transaction data required by the first driver, and then drives the first transaction data to the DUT to be tested by the first driver. In addition, the first sequence transmitter can also play a role in cutting the amount of transaction-level data. The verification platform needs a certain time to complete the generation of one stimulus to the comparison of the results. The sequence transmitter needs to arbitrate the data flow before and after the two times to complete the sending of the data flow in sequence.
[0052] In this embodiment, the first driver is responsible for transmitting the first transaction data to the DUT to be tested, so that the DUT to be tested performs signal state conversion on the first transaction data.
[0053] In this embodiment, when the first driver transmits the first transaction data to the DUT to be tested, the first monitor in the first agent monitors and obtains the first driver transmission, and the second monitor monitors and obtains the new transaction data transmitted from the second agent to the DUT to be tested, so as to process the data of the score board. It can be understood that the first monitor monitors and obtains the first transaction data transmitted by the first driver to the DUT to be tested, and transmits the first transaction data to the score board. The second monitor monitors and obtains the new transaction data transmitted from the second agent to the DUT to be tested, and transmits the new transaction data to the score board. Based on this, the score board verifies the DUT to be tested based on the first transaction data and the new transaction data.
[0054] It can be understood that the first monitor monitors the input interface of the DUT to collect the valid data passing through the input interface. In this embodiment, the first monitor needs to collect the data of the input interface according to the AXI4-Stream protocol. Similarly, the second monitor monitors the output interface of the DUT to collect the valid data passing through the output interface. Similarly, the second monitor needs to collect the data of the output interface according to the AXI4-Stream protocol.
[0055] In an embodiment, the second agent includes a second sequence transmitter, a second driver and a third monitor; the second sequence transmitter is connected with the second sequence generator, and the second sequence generator is configured to generate a second test stimulus corresponding to the second agent; the second driver is connected with the DUT and the second sequence transmitter respectively; and the third monitor is connected with the second sequence transmitter and the DUT respectively.
[0056] The third monitor is configured to monitor the parsed data information transmitted by the DUT, re-encapsulate the parsed data information as transaction-level signal data, and send the transaction-level signal data to the second sequence transmitter.
[0057] The second sequence transmitter is configured to generate new transaction data according to the parameter information corresponding to the transaction-level signal data and the second test stimulus; wherein the second test stimulus defines the delivery format of the new transaction data.
[0058] The second driver is configured to feed back the new transaction data to the DUT, so that the DUT feeds back the new transaction data to the first agent.
[0059] The second test stimulus defines the delivery format of the new transaction data, and the second sequence transmitter redefines the new transaction data according to the delivery format defined by the second test stimulus, and then sends the new transaction data.
[0060] In this embodiment, the parameter information at least includes a sequence number, a transaction completion state, a total number of bytes, message length information and data integrity; wherein the transaction completion state includes success, failure, and whether to time out.
[0061] In the embodiment, after the DUT parses the first transaction data, the parsed first transaction data is sent to the second agent, specifically, the DUT extracts data information in the first transaction data, and parses the data information, and sends the parsed data information to the second agent, the third monitor in the second agent monitors the parsed data information transmitted from the DUT in real time, re-encapsulates the parsed data information into transaction-level signal data, and sends the transaction-level signal data to the second sequence transmitter, at this time, the second sequence transmitter receives the transaction-level signal data, generates new transaction data according to the parameter information corresponding to the transaction-level signal data and the second test stimulus, and transmits the new transaction data to the second driver, so that the second driver feeds back the new transaction data to the DUT, so that the DUT feeds back the new transaction data to the first agent.
[0062] In the embodiment, the second driver feeds back the new transaction data to the DUT, and then feeds back the new transaction data to the first agent through the output port of the DUT, and the second monitor in the first agent monitors the data stream transmitted by the output interface of the DUT in real time, so the second monitor in the first agent can obtain the new transaction data.
[0063] In the embodiment, in order to better understand the UVM verification platform of the RDMA data channel, Figure 2 An architecture diagram of another UVM verification platform of the RDMA data channel is provided for an embodiment of the present application.
[0064] In this embodiment, the first agent end is taken as the host agent end, referred to as Host_agent, the second agent end is taken as the MAC agent end, referred to as Mac_agent, and the scoreboard is taken as an example for description. The Host_agent includes Host_sqr, Host_driver, Host_imon and Host_oMon components; the Mac_agent encapsulates Mac_sqr, Mac_driver and Mac_oMon; wherein, the Host_seq is connected to the Host_sqr, and is the excitation of the Host side; the Mac_seq is connected to the Mac_sqr, and is the excitation of the Mac side. In this embodiment, the Host_seq represents the first sequence generator in the above embodiment, the Host_sqr represents the first sequence transmitter in the above embodiment, the Host_driver represents the first driver in the above embodiment, the Host_imon represents the first monitor in the above embodiment, and the Host_oMon represents the second monitor in the above embodiment; the Mac_seq represents the second sequence generator in the above embodiment, the Mac_sqr represents the second sequence transmitter in the above embodiment, the Mac_driver represents the second driver in the above embodiment, and the Mac_oMon represents the third monitor in the above embodiment.
[0065] As shown in Figure 2 , the operation performed by the UVM verification platform of the RDMA data path specifically includes the following steps:
[0066] a1, when the Tready signal is valid from the remote end to the local end, the Host side will issue a transaction (i.e. the first transaction data in the above embodiment), which includes a TLP packet and a payload; the transaction is driven to the Host_sqr through the Host_sqe, the Host_sqr sends the transaction to the Host_Driver, the Host_Driver sends the transaction to the DUT to be tested, and at the same time, the Host_imon monitors and obtains the transaction sent by the Host_Driver.
[0067] a2, the data information in the first transaction data is extracted, and the data information is parsed and processed, and the parsed data information is sent to the Mac side.
[0068] a3. Mac_oMon on the Mac side monitors the parsed data information transmitted by the design under test DUT, repackages the parsed data information into transaction-level signal data, generates new transaction data based on the second test stimulus through Mac_sqr, and is driven by Mac_driver to return to the design under test DUT.
[0069] a4. The DUT feeds the new transaction data back to the local Host_oMon and compares it with the first transaction data initially received by Host_iMon in the scoreboard to check whether the message length information, sequence number, and other information are correct. If correct, it indicates that the RDMA read is successful.
[0070] In this embodiment, by comparing data and status on the Host side, intermediate processing steps are reduced, ensuring that the verification logic is consistent with the actual working mechanism of RDMA. In this embodiment, the Mac side is only responsible for receiving and forwarding data, simplifying the logic and ensuring its clear responsibilities. The verification process on the sending and receiving side is highly reusable and can efficiently verify the complete functionality of the RDMA module. Through the above process design, the verification framework can fully cover the key behaviors of RDMA in the data transmission and processing process, while improving verification efficiency and platform reusability.
[0071] In one embodiment, to better understand the connection between RDMA and local Host side ports, Figure 3 FIG3 is a schematic diagram of a structure of connecting ports on both sides of an RDMA provided by an embodiment of the present invention. The RDMA in this embodiment is the DUT under test in the above embodiment. The PICe IP end is equivalent to the Mac_agent in the above embodiment; the MAC end is equivalent to the Mac_agent in the above embodiment. In this embodiment, one end of the RDMA is connected to the PICe IP end, and the other end is connected to the MAC end. The PICe IP end is also connected to the local device, and the MAC end can also be connected to a switch to achieve communication with remote users.
[0072] In one embodiment, Figure 4 A flowchart of a UVM verification method for an RDMA data path provided in one embodiment of the present invention is provided. This embodiment is applicable to situations when verifying an RDMA data path. This verification method is applicable to any of the UVM verification platforms described in the embodiments of the present invention. The explanations of terms that have already appeared in the above embodiments are not repeated in this embodiment.
[0073] like Figure 4 As shown, the UVM verification method of the RDMA data path in this embodiment specifically includes the following steps:
[0074] S410, the first agent end sends first transaction data to the DUT; wherein the first test stimulus defines the sending format of the first transaction data.
[0075] S420, the DUT analyzes the first transaction data and sends the analyzed first transaction data to the second agent end.
[0076] In this embodiment, the DUT analyzes the first transaction data to obtain analyzed first transaction data, the data information corresponding to the analyzed first transaction data can include but is not limited to original data content, a serial number and a destination address, and the analyzed first transaction data is sent to the second agent end. It can be understood that the DUT extracts data information in the first transaction data and further analyzes and processes the data information, and sends the analyzed data information to the second agent end.
[0077] In some embodiments, since the original data content of the DUT can also include a TLP packet and a payload, in this embodiment, the tag information carried in the sent TLP header can be processed to obtain a processed new TLP packet, and the new TLP packet and the payload are taken as the first transaction data obtained after analysis and sent to the second agent end. In some embodiments, when the DUT receives the TLP packet, the Tag information in the TLP header is processed as follows: the DUT extracts the Tag field from the TLP header and records the association between the Tag and the transaction.
[0078] In an embodiment, the DUT analyzes the first transaction data and sends the analyzed first transaction data to the second agent end, including: the DUT extracts data information in the first transaction data and analyzes and processes the data information, and sends the analyzed data information to the second agent end. Specifically, the specific implementation of the analysis and processing includes: when the RDMA receives a data packet, the virtual address in the data packet is converted, so as to convert the virtual address into a physical address, the data is directly read according to the physical address, and the read data is added to the transmission protocol header and then transmitted through the physical network.
[0079] S430, the second agent end converts the analyzed first transaction data to generate new transaction data and feeds back the new transaction data to the first agent end through the DUT.
[0080] S440, the score board verifies the DUT based on the first transaction data and the new transaction data.
[0081] In the embodiment, the scoreboard is connected with the first monitor and the second monitor in the first transaction respectively. Since the first monitor monitors and acquires the first transaction data transmitted by the first driver to the DUT, and the second monitor monitors and acquires the new transaction data transmitted by the second agent to the DUT, the scoreboard can acquire the first transaction data transmitted by the first agent to the DUT from the first monitor, and acquire the new transaction data transmitted by the second agent from the second monitor, so as to compare the first transaction data with the new transaction data to obtain a comparison result, and verify according to the comparison result. It can be understood that the main function of the scoreboard is to compare the data comparison between the first transaction data transmitted by the first agent to the DUT and the new transaction data transmitted by the second agent. Specifically, the scoreboard acquires the first transaction data transmitted by the first agent to the DUT from the first monitor, and acquires the new transaction data transmitted by the second agent from the second monitor, and then compares the first transaction data with the new transaction data.
[0082] In an embodiment, the first transaction data includes first data information, and the first data information includes at least original data content, a sequence number and a destination address; the new transaction data includes second data information and receiving state information; the second data information includes at least new data content, message length information, a sequence number and address information returned by the second agent; and the receiving state information represents a feedback of whether the second agent successfully receives the first transaction data.
[0083] Correspondingly, the scoreboard verifies the DUT based on the first transaction data and the new transaction data, including:
[0084] In the case that the receiving state information is successful, the first data information and the second data information are compared to obtain a comparison result, and a verification result of the DUT is determined according to the comparison result.
[0085] In the case that the receiving state information is unsuccessful, it is determined that the verification of the DUT fails.
[0086] In the embodiment, if the receiving status information is receiving success, the first data information and the second data information are compared to obtain a comparison result, and the verification result of the DUT is determined according to the comparison result. Specifically, in the case of consistent comparison result, it is determined that the DUT verification is successful; in the case of inconsistent comparison result, it is determined that the DUT verification fails, and the reason is traced back according to the feedback of the verification failure information. It can be understood that the scoreboard verifies each function of the DUT according to the comparison result, and the function can be represented as the data transmission capability of RDMA. It can be understood that the behavior of the DUT is judged by comparing the two, and in the embodiment, if the comparison of the two is correct, it means that the RDMA reading is successful.
[0087] In the embodiment, if the receiving status information is receiving success, the first data information and the second data information are compared to obtain a comparison result, and the verification result of the DUT is determined according to the comparison result. Specifically, in the case of consistent comparison result, it is determined that the DUT verification is successful; in the case of inconsistent comparison result, it is determined that the DUT verification fails, and the reason is traced back according to the feedback of the verification failure information. It can be understood that the scoreboard verifies each function of the DUT according to the comparison result, and the function can be represented as the data transmission capability of RDMA. It can be understood that the behavior of the DUT is judged by comparing the two, and in the embodiment, if the comparison of the two is correct, it means that the RDMA reading is successful.
[0088] In an embodiment, Figure 5 A structural schematic diagram of a computer device is provided for the embodiment of the present application. The computer device 10 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The computer device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices (such as headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections, and their functions, as well as their implementation, are merely examples and are not intended to limit the implementations of the present application described and / or claimed herein.
[0089] As Figure 5 shown, the computer device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11, wherein the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the computer device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0090] A plurality of components in the computer device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the computer device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.
[0091] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the UVM verification method of the RDMA data path.
[0092] In some embodiments, the UVM verification method of the RDMA data path can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the computer device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded onto the RAM 13 and executed by the processor 11, one or more steps of the UVM verification method of the RDMA data path described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the UVM verification method of the RDMA data path by any other appropriate means, such as by means of firmware.
[0093] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
[0094] Computer programs used to implement the methods of the present application can be written in any combination of one or more programming languages. These computer programs can be implemented in a specialized computer or other programmable apparatus to produce measurements, to display information in various media, or to perform calculations according to the methods as described in the flow charts and / or block diagrams. The computer programs can be implemented entirely on a machine, partially on a machine, partially on a machine and partially on a remote machine or entirely on a remote machine or server.
[0095] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store computer programs for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of electrical connections, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0096] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.
[0097] The systems and techniques described herein can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described herein, or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0098] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.
[0099] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in different orders, as long as the desired results of the technical solutions of the present disclosure can be achieved, and the present disclosure is not limited herein.
[0100] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A UVM verification platform for RDMA data paths, characterized in that: The UVM verification platform includes: a top layer; the top layer encapsulates a test environment class; wherein the test environment class includes a design under test (DUT), a first agent terminal, a second agent terminal, and a scoreboard; the design under test (DUT) is RDMA; The first agent is used to send the first transaction data to the design under test (DUT); The DUT is configured to parse the first transaction data and send the parsed first transaction data to the second agent. The second agent is configured to perform transaction conversion on the parsed first transaction data to generate new transaction data, and feed the new transaction data back to the first agent through the DUT; The scoreboard is used to verify the design under test (DUT) based on the first transaction data and the new transaction data.
2. The UVM verification platform according to claim 1, wherein The first agent terminal includes: a first sequence transmitter, a first driver, a first monitor and a second monitor; The first sequence transmitter is connected to the first sequence generator and the first driver respectively; the first driver is connected to the DUT; the first monitor and the second monitor are connected to the scoreboard respectively; the first monitor and the second monitor are also connected to the DUT respectively; The first sequence generator is configured to generate a first test stimulus corresponding to the first agent, redefine the first transaction data according to a specification of the first test stimulus, and transmit the redefined first transaction data to the first sequence transmitter; wherein the specification of the first test stimulus includes a sending format of the first transaction data; the first sequence transmitter is configured to transmit the first transaction data to the first driver; The first driver is configured to transmit the first transaction data to the DUT; The first monitor is configured to monitor and obtain first transaction data transmitted from the first driver to the DUT, and transmit the first transaction data to the scoreboard; The second monitor is used to monitor and obtain the new transaction data transmitted by the design under test (DUT), and transmit the new transaction data to the scoreboard.
3. The UVM verification platform according to claim 1, wherein The second agent terminal includes: a second sequence transmitter, a second driver, and a third monitor; the second sequence transmitter is connected to a second sequence generator, and the second sequence generator is used to generate a second test stimulus corresponding to the second agent terminal; the second driver is respectively connected to the DUT and the second sequence transmitter; the third monitor is respectively connected to the second sequence transmitter and the DUT; The third monitor is used to monitor the parsed data information transmitted by the design under test (DUT), re-encapsulate the parsed data information into transaction-level signal data, and send the transaction-level signal data to the second sequence transmitter; The second sequence transmitter is configured to generate new transaction data according to parameter information corresponding to the transaction-level signal data and a second test stimulus; wherein the second test stimulus specifies a format for sending the new transaction data; The second driver is configured to feed back the new transaction data to the DUT, so that the DUT feeds back the new transaction data to the first agent.
4. The UVM verification platform according to claim 1, wherein When the first agent is a host agent, the second agent is a MAC agent; When the first agent terminal is a MAC agent terminal, the second agent terminal is a host agent terminal.
5. A UVM verification method for an RDMA data path, characterized in that: The UVM verification method is adapted to the UVM verification platform according to any one of claims 1 to 4, and the UVM verification method includes: The first agent sends the first transaction data to the DUT; The design under test (DUT) parses the first transaction data and sends the parsed first transaction data to the second agent; The second agent performs transaction conversion on the parsed first transaction data to generate new transaction data and feeds the new transaction data back to the first agent through the design under test (DUT); The scoreboard verifies the design under test (DUT) based on the first transaction data and the new transaction data.
6. UVM verification method according to claim 5, characterized in that, The DUT parses the first transaction data and sends the parsed first transaction data to the second agent, including: The design under test (DUT) extracts data information from the first transaction data, parses the data information, and sends the parsed data information to the second agent.
7. UVM verification method according to claim 6, is characterized in that, The first transaction data includes first data information including at least original data content, a sequence number, and a destination address; the new transaction data includes second data information and reception status information; the second data information includes at least new data content, message length information, a sequence number, and address information returned by the second agent; the reception status information indicates feedback from the second agent on whether the first transaction data was successfully received; Accordingly, the scoreboard verifies the design under test (DUT) based on the first transaction data and the new transaction data, including: When the reception status information indicates successful reception, the first data information and the second data information are compared to obtain a comparison result, and a verification result of the design under test (DUT) is determined based on the comparison result; When the receiving status information indicates that the reception is unsuccessful, it is determined that the design under test (DUT) verification fails.
8. A computer device, characterized in that: The computer device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the UVM verification method for the RDMA data path according to any one of claims 5 to 7.
9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the UVM verification method for the RDMA data path according to any one of claims 5 to 7 when executed.
10. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the UVM verification method for the RDMA data path according to any one of claims 5 to 7.