Request processing method, secondary merging device and request processing system

Abstract

The embodiment of the invention discloses a request processing method, a secondary merging device and a request processing system.The request processing method comprises the steps that primary merging is conducted on a plurality of original requests of a to-be-processed instruction, and a plurality of primary merged requests are obtained; performing second-level merging on the plurality of first-level merging requests to obtain a plurality of second-level merging requests, and issuing the second-level merging requests to a downstream module to enable the downstream module to execute operations corresponding to the plurality of second-level merging requests; the granularity of the second-stage combination is greater than that of the first-stage combination; when a disturbance request is received in the second-level merging process, whether the disturbance request is interpolated into a second-level merging request or not is determined based on the empty and full conditions of a second-level merging area corresponding to the original request, so that the second-level merging request is issued to a downstream module, and the downstream module executes operation corresponding to the disturbance request; and the second-level merging area is used for caching the first-level merging requests to the cache layer according to the determination sequence of the first-level merging requests.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of computer, and particularly relates to a request processing method, a two-stage merging device, and a request processing system. BACKGROUND

[0002] In a modern processor design, multiple address length smaller requests are merged into an address longer request to reduce the number of requests accessing a downstream module (such as a cache). However, this request merging scheme is only applicable to single source request merging, and the scope of application is narrow. SUMMARY

[0003] Therefore, the embodiments of the present disclosure provide at least a request processing method, a two-stage merging device, and a request processing system.

[0004] The technical scheme of the embodiments of the present disclosure is implemented as follows: In one aspect, the embodiments of the present disclosure provide a request processing method, comprising: performing one-stage merging on multiple original requests of a to-be-processed instruction to obtain multiple one-stage merging requests; performing two-stage merging on the multiple one-stage merging requests to obtain multiple two-stage merging requests, and issuing the two-stage merging requests to a downstream module, so that the downstream module performs operations corresponding to the multiple two-stage merging requests; the granularity of the two-stage merging is greater than the granularity of the one-stage merging; when a disturbance request is received in the process of the two-stage merging, determining whether to interpose the disturbance request into the two-stage merging requests based on the fullness of a two-stage merging area corresponding to the original request, and issuing the disturbance request to the downstream module, so that the downstream module performs an operation corresponding to the disturbance request; the two-stage merging area is used to cache the multiple one-stage merging requests to a cache layer in a determined order of the one-stage merging requests.

[0005] In another aspect, the embodiments of the present disclosure provide a two-stage merging device, comprising: a two-stage merging area, configured to cache multiple one-stage merging requests to a cache layer in a determined order of the one-stage merging requests, to implement two-stage merging on the multiple one-stage merging requests to obtain multiple two-stage merging requests; the multiple one-stage merging requests are obtained by performing one-stage merging on multiple original requests of a to-be-processed instruction, and the granularity of the two-stage merging is greater than the granularity of the one-stage merging; an additional cache area, configured to cache other requests except read requests and write requests; an order storage area, configured to record an order of requests arriving at the two-stage merging device; the two-stage merging device, configured to issue the multiple two-stage merging requests to a downstream module, so that the downstream module performs operations corresponding to the multiple two-stage merging requests; The secondary merging device is further configured to determine, when a disturbance request is received in the process of secondary merging, whether to insert the disturbance request into the secondary merging request based on the fullness of the secondary merging area corresponding to the original request, and send the downstream module to execute the operation corresponding to the disturbance request.

[0006] In another aspect, the embodiments of the present disclosure provide a request processing system, comprising: The primary merging device is configured to perform primary merging on a plurality of original requests of to-be-processed instructions to obtain a plurality of primary merging requests. The secondary merging device is configured to perform secondary merging on the plurality of primary merging requests to obtain a plurality of secondary merging requests, and when a disturbance request is received in the process of secondary merging, determine whether to insert the disturbance request into the secondary merging request based on the fullness of the secondary merging area corresponding to the original request, and send the downstream module to execute the operation corresponding to the disturbance request. The granularity of secondary merging is greater than that of primary merging. The secondary merging area is configured to cache the plurality of primary merging requests to a cache layer in a determined order of the primary merging requests. The downstream module is configured to execute the operation corresponding to the plurality of secondary merging requests to implement the processing of the to-be-processed instructions.

[0007] In another aspect, the embodiments of the present disclosure provide a computer device, comprising a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0008] In another aspect, the embodiments of the present disclosure provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps of the above method.

[0009] In another aspect, the embodiments of the present disclosure provide a computer program, comprising computer readable code, when the computer readable code is running in a computer device, a processor in the computer device executes part or all of the steps for implementing the above method.

[0010] In another aspect, the embodiments of the present disclosure provide a computer program product, the computer program product comprises a non-transitory computer readable storage medium storing a computer program, and the computer program is read and executed by a computer to implement part or all of the steps of the above method.

[0011] In the embodiments of the present disclosure, when a disturbance request is received in the process of secondary merging, it is determined whether to interpose the disturbance request into the secondary merging request based on the fullness of the secondary merging area corresponding to the original request, and the following is sent to the downstream module. In this way, in the case of a disturbance request and a main branch request, the disturbance request can be sent to the downstream module in different ways based on the fullness of the secondary merging area corresponding to the original request, while ensuring that the requests of the main branch are in order, the requests of the disturbance branch are in order with the requests of the main branch, and thus the secondary merging device can achieve better performance in any mode.

[0012] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0014] Figure 1 A schematic diagram of the composition structure of a request processing system provided by an embodiment of the present disclosure Figure 1 ; Figure 2 A schematic diagram of the composition structure of a request processing system provided by an embodiment of the present disclosure Figure 2 ; Figure 3(a) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 1 ; Figure 3(b) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 2 ; Figure 4 A schematic diagram of the implementation process of a request processing method provided by an embodiment of the present disclosure Figure 1 ; Figure 5 A schematic diagram of the implementation process of a request processing method provided by an embodiment of the present disclosure Figure 2 ; Figure 6(a) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 6(b) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 4 ; Figure 6(c) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 5 ; Figure 7A hardware entity schematic diagram of a computer device provided by an embodiment of the present disclosure is shown in FIG. 1. DETAILED DESCRIPTION

[0015] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are described in further detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0016] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0017] The terms "first / second / third" referred to are only to distinguish similar objects, and do not represent a specific order for the objects, and it can be understood that "first / second / third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure and are not intended to limit the present disclosure.

[0019] An embodiment of the present disclosure provides a request processing system, which comprises: A first-level merging device configured to perform first-level merging on a plurality of original requests of to-be-processed instructions to obtain a plurality of first-level merged requests; A second-level merging device configured to perform second-level merging on the plurality of first-level merged requests to obtain a plurality of second-level merged requests; when a disturbance request is received during the second-level merging, determining whether to interpose the disturbance request into the second-level merged requests based on whether the second-level merging area corresponding to the original request is empty or full, and sending the second-level merged requests to a downstream module; the granularity of the second-level merging is greater than the granularity of the first-level merging; the second-level merging area is configured to cache the plurality of first-level merged requests in a determined order to a cache layer; A downstream module configured to perform operations corresponding to the plurality of second-level merged requests to implement processing of the to-be-processed instructions; and perform operations corresponding to the disturbance request.

[0020] The request processing system can be deployed in a computer device, which can be a device containing a graphics processing unit (GPU) or a device containing an artificial intelligence (AI) cluster, etc. In some embodiments, the request processing system can also be referred to by other names, such as a request merging system, a request issuing system, a request response system, etc.

[0021] The request processing system is used to merge original requests with small address length into requests with longer length, or to merge requests with repeated addresses into one request, thereby reducing the number of requests accessed to the downstream module. The request merging module can be set as one module or divided into multiple levels for progressive merging modules according to design requirements.

[0022] The embodiments of the present disclosure select a multi-level merging module design. As shown in Figure 1 The first-level merging device (first-level merging module) is used to merge original requests with length less than or equal to R Byte into requests with R Byte granularity. The second-level merging device (second-level merging module) is used to merge the requests with R Byte granularity into requests with R*N Byte granularity; N is a positive integer greater than 1.

[0023] The first-level merging device generally performs parallel address comparison and request merging on many original requests (1 shot can receive and process multiple original requests). The input of the second-level merging device is generally the output of one first-level merging device, that is, 1 shot can only receive and process one request of the previous merging module. The second-level merging device needs to receive the request of the first-level merging device at most N times, and then output one request with length of R*N Byte.

[0024] The downstream module is used to perform the operation corresponding to the second-level merging request to implement the instruction on the to-be-processed instruction. For example, the downstream module can be a cache, a memory, etc.

[0025] The disturbance module is used to receive requests other than read requests and write requests. In addition to read requests and write requests, there are also some requests for maintaining the consistency of the system memory, such as fence / flush / invalidate / barrier requests, which can be collectively referred to as coherent requests. Due to the consistency requirements of these requests, the requests between the first-level merging device and the second-level merging device, and the second-level merging device and the downstream module need to be in order.

[0026] Figure 1 In some embodiments, as shown in FIG. 1, the branch of the primary merging device to the secondary merging device, the secondary merging device to the downstream module is a main branch, the branch of the disturbance module to the secondary merging device, the secondary merging module to the downstream module is a disturbance branch, and the request sent by the disturbance module is a disturbance request.

[0027] The read-write request of the main branch has a high occurrence frequency, and the disturbance request of the disturbance branch has a low occurrence frequency, for example, the disturbance request can be a load request. The disturbance request generally has no merging requirement, and has no order preserving requirement with the read-write request of the main branch, and has an order preserving requirement with the coherent request of the main branch.

[0028] In some embodiments, as shown in FIG. 1, the branch of the primary merging device to the secondary merging device, the secondary merging device to the downstream module is a main branch, the branch of the disturbance module to the secondary merging device, the secondary merging module to the downstream module is a disturbance branch, and the request sent by the disturbance module is a disturbance request. Figure 2 The secondary merging area is configured to cache a plurality of primary merging requests to a cache layer in a determined order of the primary merging requests, so as to implement secondary merging of the plurality of primary merging requests, and obtain a plurality of secondary merging requests. The plurality of primary merging requests are obtained by performing primary merging on a plurality of original requests of to-be-processed instructions. The granularity of the secondary merging is greater than the granularity of the primary merging. The additional cache area is configured to cache other requests except the read request and the write request. The order storage area is configured to record the order of the requests arriving at the secondary merging device. The secondary merging device is configured to send the plurality of secondary merging requests to the downstream module, so that the downstream module performs operations corresponding to the plurality of secondary merging requests. When a disturbance request is received in the process of the secondary merging, the secondary merging device is further configured to determine whether to interpose the disturbance request into the secondary merging requests based on the fullness of the secondary merging area corresponding to the original request, and then send the disturbance request to the downstream module, so that the downstream module performs an operation corresponding to the disturbance request.

[0029] The secondary merging device is divided into a secondary merging area, an additional cache area, and an order storage area. The read-write request after the primary merging can be secondarily merged through the secondary merging area. Other requests (disturbance requests) except the read request and the write request can be cached through the additional cache area. In this way, the secondary merging of the read-write request and the caching of the disturbance request are separated, which can prevent the disturbance request from interfering with the secondary merging, so as to interpose the disturbance request into the secondary merging requests for sending without interfering with the secondary merging. In addition, the order storage area stores the order of each request (including the primary merging request and the disturbance request) arriving at the secondary merging device, so that the ordered sending of the requests can be realized through the order storage area.

[0030] ​Interleaving the disturbance request to the secondary coalescing request refers to inserting the disturbance request into the current secondary coalescing request after the secondary coalescing is completed, and then continuing to process the unfinished secondary coalescing.

[0031] The coalescing granularity of the secondary coalescing area can be R*N Byte, that is, N read type primary coalescing requests from the primary coalescing device can be coalesced into one secondary coalescing request.

[0032] The other coalesce buffer is used to buffer the coherent request and the noise request.

[0033] The order table is used to record the order of the secondary coalescing device entry request.

[0034] In some embodiments, when the type of the original request is a read type, the secondary coalescing area is a read request coalescing area; when the type of the original request is a write type, the secondary coalescing is a write request coalescing area; the read request coalescing area is used for secondary coalescing of the primary coalescing request of the read type; the write request coalescing area is used for secondary coalescing of the primary coalescing request of the write type; the depth of the cache layer of the read request coalescing area, the write request coalescing area and the other cache area is determined based on the number of primary coalescing requests that can be received by the secondary coalescing device at one time and the number threshold; the depth of the order table is the sum of the depths of the read request coalescing area, the write request coalescing area and the other cache area.

[0035] The coalescing granularity of the read request coalescing area (Read cmd coalesce buffer) is R*N Byte, that is, N read type primary coalescing requests from the primary coalescing device can be coalesced into one read type secondary coalescing request.

[0036] The coalescing granularity of the write request coalescing area (Write cmd coalesce buffer) is R*N Byte, that is, N write type primary coalescing requests from the primary coalescing device can be coalesced into one write type secondary coalescing request.

[0037] The write request coalesce buffer is responsible for two-level coalescing of write requests, coalescing R byte length write requests into N*R byte. The read request coalesce buffer is responsible for two-level coalescing of read requests, coalescing R byte length read requests into N*R byte. Since it is two-level coalescing, the coalescing function can be simplified to only coalesce consecutive requests, and once a newly received request does not belong to the same N*R range as the previous buffer request, the cache layer stops request coalescing.

[0038] The number of one-level coalesced requests that the two-level coalescing device can receive at a time is N. The number threshold can be set to 1.

[0039] The depth of the write request coalesce buffer is set to N+1. Depth N corresponds to the coalescing granularity R*N byte of the two-level coalescing device; +1 is to prevent the one-level coalescing device from being blocked in the scenario of receiving consecutive write requests from the one-level coalescing device.

[0040] The depth of the read request coalesce buffer is set to N+1. Depth N corresponds to the coalescing granularity R*N byte of the two-level coalescing device; +1 is to prevent the one-level coalescing device from being blocked in the scenario of receiving consecutive read requests from the one-level coalescing device.

[0041] The depth of the other cmd coalesce buffer is set to N+1. In this scenario: N write requests, at least N coherent or noise requests, N write requests, if the two-level coalescing device outlet request is to be guaranteed not to appear broken, the depth of the other cmd coalesce buffer needs to be set to at least N+1.

[0042] As shown in FIG. 3(a) to 3(b), write1beat0, write1beat1, write1beat2, write1beat3 are 4 beat (tap) write requests belonging to the same N * R length, which can be combined into 1 N * R length write1. Similarly, write2beat0, write2beat1, write2beat2, write2beat3 are 4 beat (tap) write requests belonging to the same N * R length, which can be combined into 1 N * R length write2. The difference between the write request beat 0 / 1 / 2 / 3 of the secondary coalesce device entrance and the secondary coalesce device exit is that the entrance is 4 requests, and the length of 1 request is R; the exit is 1 request with length = N * R, and 4 taps are transmitted on the interface.

[0043] As shown in FIG. 3(a), assuming N = 4, the depth of the additional cache area (other cmd coalesce buffer) is set to 5, and the above scenario is encountered, which can ensure that the secondary coalesce device exit is continuously flowing. As shown in FIG. 3(b), if the depth of the additional cache area (other cmd coalesce buffer) is set to 2, then under the above scenario, the secondary coalesce device entrance will be full due to the cmd coalesce buffer, which will block the secondary coalesce device entrance (entrance back pressure) for 3 taps, and thus the secondary coalesce device exit request will also have 3 null taps (null in FIG. 3(b)).

[0044] The depth of the order storage area (order table) is 3N + 3. The request type received by the secondary coalesce device entrance can be divided into write request, read request, coherent request, and noise request. The internal storage of each layer of the order table is 2-bit request type, which is used to mark the four types of request. For example: write request, read request, coherent request, noise request are marked as 2’b00, 2’b01, 2’b10, 2’b11 respectively.

[0045] In some embodiments, each cache layer of the write request coalesce buffer and the read request coalesce buffer is provided with a 1-bit coalesce flag (collect_finish_flag) for identifying whether the request of the layer has completed coalesce, and the initial value is 0. If collect_finish_flag = 0, it indicates that coalesce has not ended and the subsequent request needs to be waited for coalesce; if collect_finish_flag = 1, it indicates that coalesce has ended.

[0046] In some embodiments, in addition to carrying the request address, the request information sent by the first-level coalesce device to the second-level coalesce device can also carry an end identifier. The end identifier (end_of_instruction) is used to identify whether the second-level coalesce device ends the coalesce of the request; when the second-level coalesce device receives end_of_instruction == 1 of 1 request (assuming 1 as the end identifier), it will stop coalesce even if some requests may not be coalesced to N * R length.

[0047] One instruction can correspond to multiple read requests or write requests, but the type of multiple requests corresponding to one instruction is the same. One coherent request is one instruction, which corresponds to 1 cycle on the interface; the last request of one instruction carries an end identifier (end_of_instruction == 1). The request received by the second-level coalesce device from the first-level coalesce device is in order, that is, after encountering end_of_instruction == 1 of one instruction, the type of request can be switched. The noise request sent by the disturbance module can be inserted into any position of the entry request of the second-level coalesce device, and one noise request corresponds to 1 cycle (1 cycle). The noise request inserted will not affect the coalesce of the write request and the read request; at the same time, at the outlet of the second-level coalesce device, the noise request is not inserted into the middle of multiple beats of one write request.

[0048] If the newly received request does not belong to the same N * R range as the request in the previous buffer, the request in the previous buffer stops coalescing, and the collect_finish_flag corresponding to the previous request is set to 1. If the newly received request in the buffer belongs to the same N * R range as the request in the previous buffer, the collect_finish_flag is maintained as 0; if the end_of_instruction of the newly received request in the buffer is 1, it indicates that the instruction ends, and coalescing is stopped, at which time the collect_finish_flag of the request and the previous request in the buffer is set to 1.

[0049] After the secondary merging device entrance receives a request, if it is a write request, it is pushed into the write request merging area (write cmd coalesce buffer) and recorded in the order table; if the write request merging area (write cmd coalesce buffer) is full, the secondary merging device entrance is blocked. If it is a read request, it is pushed into the read request merging area (Read cmd coalesce buffer) and recorded in the order table; if the read request merging area (Read cmd coalesce buffer) is full, the secondary merging device entrance is blocked. If it is a coherent request, it is pushed into the other cmd coalesce buffer and recorded in the order table; if the other cmd buffer is full, the secondary merging device entrance is blocked.

[0050] If it is a noise request, it needs to be sent to the downstream module based on the empty / full condition of the secondary merging area corresponding to the original request (for a specific description of the request merging method below).

[0051] Specifically, if it is a noise request, the collect_finish_flag of all requests in the corresponding write request merging area (write cmd coalesce buffer) / read request merging area (Read cmd coalesce buffer) is checked.

[0052] 1. If there is a request with collect_finish_flag == 0 in these requests, then this noise request is very likely to be inserted into the write / read request of the same N * R length multi-beat. Since the noise request and the coherent request of the main branch have the order requirement, at this time, the other cmd buffer and the order table are checked, a) If the other cmd buffer is not empty, block the secondary merging device entrance, wait for the other cmd buffer to be empty, and the request corresponding to collect_finish_flag == 1 in the order table has been popped (removed from the secondary merging device to the downstream module), then bypass the noise request to the secondary merging device exit, at the same time, release the secondary merging device entrance to allow receiving new requests. This noise request is not recorded in the order table.

[0053] b) If the other cmd buffer is empty, but the request corresponding to collect_finish_flag == 1 in the order table has not been popped completely, block the secondary merging device entrance, wait for the request corresponding to collect_finish_flag == 1 in the order table to be popped completely, then bypass the noise request to the secondary merging device exit. In this scenario, the noise request is not recorded in the order table.

[0054] c) If the other cmd buffer is empty and the request corresponding to collect_finish_flag == 1 in the order table has been popped, then bypass the noise request to the secondary merging device exit. In this scenario, the noise request is not recorded in the order table.

[0055] 2. If all the collect_finish_flag of the requests in the write cmd coalesce buffer and the read cmd coalesce buffer are 1, the noise request enters the other cmd buffer, and is recorded in the order table. If the other cmd buffer is full, the secondary coalescing device entrance is blocked.

[0056] The embodiment of the present disclosure provides a request processing method, which can be applied to a request processing system. As shown in the figure, the method comprises the following steps 401 to 403: Figure 4 Step 401: primary coalescing is performed on a plurality of original requests of a to-be-processed instruction, to obtain a plurality of primary coalesced requests.

[0057] The to-be-processed instruction refers to an instruction that needs to be processed at present. One instruction can correspond to a plurality of original requests. The original request can be a read request or a write request. The primary coalesced request refers to a request after primary coalescing. The primary coalescing is used to coalesce requests smaller than R (bytes) Byte into R Byte granularity requests; wherein the request smaller than R byte is the original request, and the R Byte granularity request is the first coalesced request.

[0058] In some embodiments, the specific implementation of step 401 can be: performing primary coalescing on a plurality of original requests of a to-be-processed instruction based on a first coalescing granularity, to obtain a plurality of primary coalesced requests. Specifically, the primary coalescing device can be used to perform primary coalescing on a plurality of original requests of a to-be-processed instruction based on a first coalescing granularity. The first coalescing granularity can reflect the address length of the primary coalesced request, for example: the first coalescing granularity can be R Byte.

[0059] In a feasible implementation, the primary coalescing device can be used to coalesce original requests with addresses in the same cache line, to obtain a plurality of primary coalesced requests. The size of the cache line is equal to the granularity of the primary coalescing.

[0060] In another feasible implementation, the primary coalescing device can be used to cache original requests with smaller address lengths in order of arrival to the cache line (the size of the cache line is R Byte) of the primary coalescing device. In this way, one cache line corresponds to one primary coalesced request of R Byte. Here, the order of arrival refers to the order of arrival of the original request to the primary coalescing device.

[0061] ​In step 402, the plurality of first-level merge requests are second-level merged to obtain a plurality of second-level merge requests, and the second-level merge requests are sent to a downstream module to enable the downstream module to perform operations corresponding to the second-level merge requests; the granularity of the second-level merge is greater than the granularity of the first-level merge.

[0062] The second-level merge request refers to a request after second-level merge. The second-level merge is used to merge R Byte granularity requests into R*N Byte (N>1) granularity requests.

[0063] In some embodiments, the implementation of step 402 can be that the first-level merge requests are second-level merged based on a second merge granularity to obtain a plurality of second-level merge requests. Specifically, the first-level merge requests can be second-level merged by a second-level merge device based on a second merge granularity. The second merge granularity can reflect the address length of the second-level merge request, for example, the second merge granularity can be R*N Byte.

[0064] In a feasible implementation, the first-level merge requests can be second-level merged by the second-level merge device based on the second merge granularity in the order of arrival of the first-level merge requests. Here, the order of arrival refers to the order of arrival of the first-level merge requests at the second-level merge device.

[0065] For example, the first-level merge requests are sequentially cached to a cache line (here, the size of the cache line is R*N Byte) of the second-level merge device in the determined order of the first-level merge requests, so that one cache line corresponds to one R*N Byte second-level merge request.

[0066] In step 403, when a disturbance request is received during the second-level merge, it is determined whether to interpose the disturbance request into the second-level merge requests based on the fullness of a second-level merge area corresponding to the original request, and then send the second-level merge requests to the downstream module to enable the downstream module to perform operations corresponding to the disturbance request; the second-level merge area is used to cache a plurality of first-level merge requests to a cache layer in the determined order of the first-level merge requests.

[0067] The fullness of the second-level merge area corresponding to the original request is determined based on the type of the original request. If the original request is a read request, the fullness of the second-level merge area corresponding to the original request refers to the fullness of the read request merge area; if the original request is a write request, the fullness of the second-level merge area corresponding to the original request refers to the fullness of the write request merge area. The fullness refers to whether the cache layer of the merge area is full of data.

[0068] In some embodiments, the specific implementation of step 403 can be: in the case that there is a cache layer in the secondary merging area corresponding to the original request that has not completed request merging, interpose the disturbance request into the secondary merging request and send it to the downstream module; in the case that all cache layers in the secondary merging area corresponding to the original request have completed request merging, send the disturbance request to the downstream module through an additional cache area.

[0069] In the embodiments of the present disclosure, when a disturbance request is received in the process of secondary merging, it is determined whether to interpose the disturbance request into the secondary merging request and send it to the downstream module based on the fullness of the secondary merging area corresponding to the original request. In this way, in the case of a disturbance request and a main branch request, the disturbance request can be sent to the downstream module in different ways based on the fullness of the secondary merging area corresponding to the original request, while ensuring that the requests of the main branch are in order and the requests of the disturbance branch are in order with the requests of the main branch, thereby ensuring that the secondary merging device can achieve better performance in any mode.

[0070] The embodiments of the present disclosure provide a request processing method, which can be applied to a request processing system. As shown in Figure 5 The method comprises the following steps 501 to 505: Step 501: primary merging is performed on a plurality of original requests of to-be-processed instructions to obtain a plurality of primary merging requests.

[0071] Here, step 501 corresponds to step 401, and the specific implementation of step 401 can be referred to in implementation.

[0072] Step 502: secondary merging is performed on the plurality of primary merging requests to obtain a plurality of secondary merging requests, and the secondary merging requests are sent to a downstream module to enable the downstream module to perform operations corresponding to the plurality of secondary merging requests; the granularity of the secondary merging is greater than the granularity of the primary merging.

[0073] Here, step 502 corresponds to step 402, and the specific implementation of step 402 can be referred to in implementation.

[0074] Step 503: when a disturbance request is received in the process of secondary merging, a secondary merging area corresponding to the original request is determined; the secondary merging area is used to cache a plurality of primary merging requests to a cache layer in a determined order of the primary merging requests.

[0075] The secondary merging area refers to a merging area used for secondary merging of original requests.

[0076] In some embodiments, the specific implementation of step 503 can be: determining the secondary merge area corresponding to the original request based on the type of the original request.

[0077] In some embodiments, the specific implementation of step 503 can be: in the case that the type of the original request is a read type, taking the read request merge area as the secondary merge area; in the case that the type of the original request is a write type, taking the write request merge area as the secondary merge area.

[0078] Step 504: in the case that the secondary merge area has a cache layer with uncompleted request merging, interposing the disturbance request into the secondary merge request based on whether the additional cache area is empty and the issue of the target secondary merge request corresponding to the cache layer with completed request merging in the secondary merge area, and then issuing the disturbance request to the downstream module; the additional cache area is used to cache requests other than read requests and write requests.

[0079] In some embodiments, since each cache layer of the secondary merge area corresponds to a merge identifier (collect_finish_flag), the presence of a cache layer with uncompleted request merging in the secondary merge area can be determined according to the identifier value of the merge identifier of the secondary merge area. Specifically, if the identifier value of the merge identifier of the secondary merge area is a first identifier value (such as 0), it is determined that the secondary merge area has a cache layer with uncompleted request merging; if the identifier value of the merge identifier of the secondary merge area is a second identifier value (such as 1), it is determined that the secondary merge area does not have a cache layer with uncompleted request merging.

[0080] Case one, the specific implementation of step 504 can be: in the case that the additional cache area is not empty, suspending the operation of the secondary merge; in the case that the requests in the additional cache area and the target secondary merge request are all issued to the downstream module, issuing the disturbance request to the downstream module and continuing the operation of the secondary merge.

[0081] Suspending the operation of the secondary merge means blocking the entrance of the secondary merge device, that is, no longer receiving the primary merge request. The requests in the additional cache area and the target secondary merge request are all issued to the downstream module, which means that the other cmdbuffer is empty and the requests corresponding to collect_finish_flag == 1 in the order table have all been popped.

[0082] Specifically, if the coalesce buffer corresponding to the original request exists a cache line with collect_finish_flag == 0, and the other cmd buffer is not empty, the entrance of the secondary coalescing device is blocked, and after the other cmd buffer is empty and the requests corresponding to collect_finish_flag == 1 in the order table are all popped, the noise request is bypassed to the exit of the secondary coalescing device, and at the same time, the entrance of the secondary coalescing device is released to allow receiving new requests. In this way, the noise request is interleaved between the secondary coalescing requests, and then sent to the downstream module, and the order of the main branch requests is ensured.

[0083] In case two, the specific implementation of step 504 can be: in the case that the additional cache area is empty, but the target secondary coalescing requests are not all sent to the downstream module, suspending the operation of the secondary coalescing; in the case that the target secondary coalescing requests are all sent to the downstream module, sending the noise request to the downstream module and continuing the operation of the secondary coalescing.

[0084] Specifically, if the coalesce buffer corresponding to the original request exists a cache line with collect_finish_flag == 0, and the other cmd buffer is empty, but the requests corresponding to collect_finish_flag == 1 in the order table are not all popped, the entrance of the secondary coalescing device is blocked, and after the requests corresponding to collect_finish_flag == 1 in the order table are all popped, the noise request is bypassed to the exit of the secondary coalescing device. At the same time, the entrance of the secondary coalescing device is released to allow receiving new requests. In this way, the noise request is interleaved between the secondary coalescing requests, and then sent to the downstream module, and the order of the main branch requests is ensured.

[0085] As shown in FIG. 6(a), if the noise request is not sent to the downstream module through the bypass path in the above case one, the request pattern of the secondary coalescing device exit is that the noise request is interleaved between the multiple beats of 1 read or write request, and the secondary coalescing device exit is back-pressured for 3 beats. As shown in FIG. 6(b), if the noise request is not sent to the downstream module through the bypass path in the above case two, the secondary coalescing device entrance is back-pressured.

[0086] The reason for bypassing the noise request to the downstream module instead of pushing it into the other cmd buffer is that the order table must be popped in order, and there are already some requests in the order table that have not been completed coalesced. If the noise request is pushed into the other cmd buffer (which implies that it is recorded in the order table), the request pattern at the exit of the secondary coalescing device will be noise requests inserted into the multi-beat of one read or write request, which is not allowed. If the inserted noise request exceeds five, it will also cause a deadlock problem: the noise request will fill the other cmd buffer, blocking the entrance of the secondary coalescing device, and the previous incomplete coalesced request will be waiting for the subsequent request, the order table will not be released, and a deadlock will occur.

[0087] In case three, the specific implementation of step 504 can be: in the case that the additional cache area is empty and the target secondary coalescing request is completely issued to the downstream module, the disturbance request is issued to the downstream module, and the operation of the secondary coalescing is continued.

[0088] Specifically, if the coalesce buffer corresponding to the original request has a cache line with collect_finish_flag == 0, and the other cmd buffer is empty, and the request corresponding to collect_finish_flag == 1 in the order table has been popped, the noise request is bypassed to the exit of the secondary coalescing device.

[0089] As shown in FIG. 6(c), if the noise request is not bypassed to the downstream module in case three, the secondary coalescing device exit will appear empty.

[0090] It should be noted that case one, case two and case three are bypassing the noise request to the exit of the secondary coalescing device directly in the case that the additional cache area is empty and the target secondary coalescing request is all issued to the downstream module, so as to ensure that the noise request inserted will not affect the request coalescing and order preserving of the main branch, and at the same time ensure that the noise request will not be inserted into the middle of the multi-beat of 1 write request. In addition, the noise request processed in case one, case two and case three is not recorded in the order table.

[0091] In step 505, in the case that the cache layer of the secondary coalescing area has completed request coalescing, but there is free space in the additional cache area, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to issue the disturbance request to the downstream module based on the receiving order of the disturbance request.

[0092] The cache layer of the secondary coalescing area has completed request coalescing, which means that the disturbance request cannot be inserted into the secondary coalescing request for issuing, therefore, the additional cache area is used for issuing the disturbance request. Since the additional cache area is also used for caching coherent requests, and the coherent request has order preserving requirement, the arrival order of the disturbance request needs to be recorded in the order storage area, so as to issue the disturbance request to the downstream module according to the arrival order of the disturbance request.

[0093] It should be noted that, as shown in FIG. 6(c), in the case that the cache layer of the secondary coalescing area has completed request coalescing, but there is free space in the additional cache area (case four), the additional cache area (othercmdcoalesce buffer) can be waited for empty as in case one and case two, and the bypass path is continued, but this will cause back pressure to the entrance of the secondary coalescing device, causing performance degradation. The disturbance request is issued through the additional cache area, which will not affect the processing of the main branch request, so as to realize the issuing of the disturbance request.

[0094] In step 506, in the case that the cache layer of the secondary coalescing area has completed request coalescing, and there is no free space in the additional cache area, the operation of the secondary coalescing is suspended.

[0095] In step 507, in the case that the requests in the secondary coalescing area and the additional cache area are all issued to the downstream module, the disturbance request is issued to the downstream module, and the operation of the secondary coalescing is continued.

[0096] Based on the foregoing embodiments, the request processing method provided by the embodiments of the present disclosure further includes the following steps 508 to 510: Step 508: In the case that the new acquired primary merge request and the request of the secondary merge area corresponding to the original request belong to the same granularity of the secondary merge, the merge identifier of the cache layer of the secondary merge area is kept as a first identifier value; the first identifier value represents that the request merge of the corresponding cache layer is not completed.

[0097] Step 509: In the case that the new acquired primary merge request and the request of the secondary merge area do not belong to the same granularity of the secondary merge, the merge identifier of the cache layer of the secondary merge area is set as a second identifier value; the second identifier value represents that the request merge of the corresponding cache layer is completed.

[0098] Step 510: In the case that a primary merge request carrying an end identifier is received, the merge identifier of the cache layer of the secondary merge area is set as a second identifier value; the second identifier value represents that the request merge of the corresponding cache layer is completed; the end identifier is used to represent the end of the request merge of the to-be-processed instruction.

[0099] In the embodiments of the present disclosure, when a disturbance request is received in the process of secondary merge, based on the empty or full condition of the secondary merge area corresponding to the original request, it is determined whether to interpose the disturbance request into the secondary merge request and then send it to the downstream module. In this way, in the case that there is a disturbance request and a main branch request, based on the empty or full condition of the secondary merge area corresponding to the original request, the disturbance request can be sent to the downstream module in different ways, while ensuring that the requests of the main branch are in order and the requests of the disturbance branch are in order with the requests of the main branch, thereby ensuring that the secondary merge device can achieve better performance in any mode, and in such a scenario, N write requests, at least N coherent or noise requests, and N write requests also ensure that the exit request of the secondary merge device does not appear to be interrupted.

[0100] The application of the request processing method provided by the embodiments of the present disclosure in an actual scenario is described below.

[0101] In addition to the request address, the request information sent by the primary merge module (corresponding to the primary merge device) to the secondary merge module (corresponding to the secondary merge device) also has an end identifier (end_of_instruction), which is used to identify whether the secondary merge module ends the request merge of the current instruction or switches the request type. When the secondary merge module receives 1 request end_of_instruction==1, even if some requests may not be merged into N*R length, it will stop merging.

[0102] One instruction can correspond to multiple A to B read or write requests, and the request type corresponding to one instruction is the same. A coherent request is one instruction, which corresponds to 1 cycle on the interface; the last request of one instruction carries end_of_instruction == 1. The request received by the secondary coalescing module from the primary coalescing module is in order, that is, it is necessary to encounter end_of_instruction == 1 of one instruction before the request type can be switched. The noise request sent by the disturbance module can be inserted into any position of the secondary coalescing module entrance request, one noise request corresponds to 1 cycle (1 cycle), and the noise request inserted will not affect the coalesce of the write / read request. At the same time, it is expected that at the outlet of the secondary coalescing module, the noise request will not be inserted between the multiple beats of one write request.

[0103] In the secondary coalescing module, a write request coalescing area (Write cmd coalesce buffer) is set, and the depth is set to N+1. The depth N corresponds to the coalescing granularity R*N Byte of the secondary coalescing module, that is, N write requests from the primary coalescing module can be coalesced into one write request; +1 is to receive the continuous write request scenario sent by the primary coalescing module, so as not to back pressure the primary coalescing module.

[0104] In the secondary coalescing module, a read request coalescing area (Read cmd coalesce buffer) is set, and the depth is set to N+1. The depth N corresponds to the coalescing granularity R*N Byte of the secondary coalescing module, that is, N read requests from the primary coalescing module can be coalesced into one read request; +1 is to receive the continuous read request scenario sent by the primary coalescing module, so as not to back pressure the primary coalescing module.

[0105] Each layer of the write request coalescing area (Write cmd coalesce buffer) and the read request coalescing area (Read cmd coalesce buffer) corresponds to a coalescing identifier (collect_finish_flag) of 1 bit, which is used to identify whether the request of the layer has completed coalescing, and the initial value is 0 (assuming that 0 indicates that coalescing has not ended and needs to wait for subsequent requests to coalesce together).

[0106] The write request coalescing area (Write cmd coalesce buffer) and the read request coalescing area (Read cmd coalesce buffer) are respectively responsible for second-level coalescing of write requests and read requests, and coalescing R byte length requests into N * R bytes; since it is second-level coalescing, the coalescing function is simplified to only coalesce consecutive received requests, and once a newly received request does not belong to the same N * R range as the request in the previous buffer, the coalescing of the request in the previous buffer stops, and the collect_finish_flag corresponding to the previous request is set to 1. If the newly received request in the buffer belongs to the same N * R range as the request in the previous buffer, the collect_finish_flag is kept as 0; if the newly received request in the buffer has end_of_instruction == 1, it indicates that the instruction ends and coalescing stops, at this time the collect_finish_flag of the request and the request in the buffer is set to 1.

[0107] In the second-level coalescing module, an additional buffer area (other cmd coalesce buffer) is set up to buffer coherent requests and noise requests, and the depth is set to N + 1. In this scenario: N write requests, at least N coherent or noise requests, N write requests, if the exit request of the second-level coalescing module is to be ensured not to appear broken, the depth of the additional buffer area (other cmd coalesce buffer) must be set to at least N + 1.

[0108] As shown in FIG. 3(a), assuming N = 4, if the depth of the additional cache area (other cmd coalesce buffer) is set to 5, the above-mentioned scenario can be encountered, and it can be ensured that the exit of the secondary coalescing module is continuous; as shown in FIG. 3(b), if the depth of the additional cache area (other cmd coalesce buffer) is set to 2, the secondary coalescing module entrance will be blocked (back pressure of the entrance) for 3 beats due to fullness of the cmd coalesce buffer in the above-mentioned scenario, and thus the secondary coalescing module exit request will also have 3 beats of null (as shown in the figure). Among them, the write request beats 0 / 1 / 2 / 3 are 4 beats of write request belonging to the same N * R length, which can form one piece of N * R length request.

[0109] In the secondary coalescing module, an order storage area (order table) is set to record the order (arrival order) of the secondary coalescing module entrance request, and the depth is 3N + 3. The types of the requests received by the secondary coalescing module entrance include write request, read request, coherent request, and noise request. The internal storage of each layer of the order storage area (order table) is 2-bit request type, which is used to mark the four types of request.

[0110] After the secondary coalescing module entrance receives one piece of request, if it is a write request, it is pushed into the write cmd coalesce buffer and recorded in the order storage area (order table); if the write cmd coalesce buffer is full, the secondary coalescing module entrance is blocked. If it is a read request, it is pushed into the read request coalescing area (Read cmd coalesce buffer) and recorded in the order storage area (order table); if the order storage area is full, the secondary coalescing module entrance is blocked. If it is a coherent request, it is pushed into the additional cache area (other cmd coalesce buffer) and recorded in the order storage area (order table); if the additional cache area (other cmd coalesce buffer) is full, the secondary coalescing module entrance is blocked.

[0111] If it is a noise request, special processing is required. First, check the collect_finish_flag of all requests in the write request coalescing area (Write cmd coalesce buffer) and the read request coalescing area (Read cmd coalesce buffer): 1. If it is found that there is a request with a coalescing identifier collect_finish_flag == 0 among these requests, then this noise is very likely to have been inserted between the write / read requests belonging to the same N * R length multi-beat. Since the noise request and the coherent request of the main branch have the order preserving requirement, at this time, the other cmd buffer and the order table are checked. a) (case one) If the additional buffer (other cmd coalesce buffer) is not empty, block the secondary coalescing module entrance, wait for the additional buffer (other cmd coalesce buffer) to be empty, and the coalescing identifier collect_finish_flag == 1 corresponding request in the order storage area (order table) has been popped, then bypass the noise request to the secondary coalescing module exit, at the same time, release the secondary coalescing module entrance, allow to receive new requests. This noise request is not recorded in the order table.

[0112] b) (case two) If the additional buffer (other cmd coalesce buffer) is empty but the coalescing identifier collect_finish_flag == 1 corresponding request in the order storage area (order table) has not been popped completely, then block the secondary coalescing module entrance, wait for the coalescing identifier collect_finish_flag == 1 corresponding request in the order storage area (order table) to be popped completely, then bypass the noise request to the secondary coalescing module exit. This noise request is not recorded in the order table.

[0113] c) If the other cmd coalesce buffer is empty and all requests in the order table have been popped, then the current noise request is bypassed to the exit of the second coalesce module. The current noise request is not recorded in the order table.

[0114] 2) If all requests in the write cmd coalesce buffer and the read cmd coalesce buffer have been coalesced, then the current noise request is recorded in the order table and enters the other cmd coalesce buffer. If the other cmd coalesce buffer is full, then the second coalesce module is blocked.

[0115] The bypass of the noise request in steps 1.a and 1.b is because the order table must be popped in order, and there are some requests in the order table that have not been coalesced. If the noise request is pushed into the other cmd coalesce buffer (which implies that the noise request is recorded in the order table), then the request pattern at the exit of the second coalesce module will be noise requests interleaved in the multi-beat of one read or write request, which is not allowed. If the number of interleaved noise requests exceeds 5, then a deadlock will occur: the noise request will fill the other cmd coalesce buffer, the second coalesce module will be blocked, the requests that have not been coalesced will wait for the following requests, the order table will not be released, and a deadlock will occur.

[0116] The step 2 above can also wait for the other cmd coalesce buffer to be empty as in 1.a / 1.b, and continue to walk the bypass path, but this will cause back pressure to the secondary coalesce module entry, causing some performance degradation.

[0117] The protection points of the embodiments of the present disclosure include at least: 1. In the secondary coalesce module, a write request coalesce buffer is set, and the depth is set to N+1.

[0118] 2. In the secondary coalesce module, a read request coalesce buffer is set, and the depth is set to N+1.

[0119] 3. The write request coalesce buffer and the read request coalesce buffer each correspond to 1 bit of collect_finish_flag, which is used to identify whether the request of the layer has completed the coalesce.

[0120] 4. The write request coalesce buffer and the read request coalesce buffer are responsible for the secondary coalesce of the write / read request, and the R byte length request is coalesced to N*R byte. Since it is the secondary coalesce, the coalesce can be simplified to only coalesce the continuously received request. Once the newly received request does not belong to the same N*R range as the request in the buffer, the request in the buffer stops coalescing, and the coalesce identifier collect_finish_flag corresponding to the previous request in the buffer is set to 1. If the newly received request in the buffer belongs to the same N*R range as the request in the buffer, the collect_finish_flag is maintained as 0. If the end identifier end_of_instruction of the newly received request in the buffer is 1, it indicates that the instruction ends, and the coalesce stops. At this time, the collect_finish_flag of the request and the previous request in the buffer is set to 1.

[0121] 5. In the second level coalesce module, an additional buffer (other cmd coalesce buffer) is set up to buffer coherent request and noise request, and its depth is set to N + 1.

[0122] 6. In the second level coalesce module, an order table is set up to record the order of the requests received by the second level coalesce module, and its depth is 3N + 3. The types of the requests received by the second level coalesce module include write request, read request, coherent request and noise request. The internal storage of each layer of the order table is 2-bit request type, which is used to mark the four types of requests.

[0123] 7. After the second level coalesce module receives a request, if it is write request, it is pushed into the write request coalesce buffer and recorded in the order table. If the write request coalesce buffer is full, the second level coalesce module is blocked. If it is read request, it is pushed into the read request coalesce buffer and recorded in the order table. If the read request coalesce buffer is full, the second level coalesce module is blocked. If it is coherent request, it is pushed into the other cmd coalesce buffer and recorded in the order table. If the other cmd coalesce buffer is full, the second level coalesce module is blocked.

[0124] 8、After the secondary coalesce module entry receives a request, if it is a noise request, special processing is required. First, check the merge identifier (collect_finish_flag) of all requests in the write request coalesce buffer and the read request coalesce buffer. If a collect_finish_flag == 0 is found in these requests, the noise is likely to be inserted into a multi-beat write / read request belonging to the same N * R length. Since the noise request and the coherent request of the main branch have the requirement of maintaining the order, at this time, check the other cmd buffer and the order table, a) If the additional buffer (other cmd coalesce buffer) is not empty, block the secondary coalesce module entry, wait for the additional buffer (other cmd coalesce buffer) to be empty, and the request corresponding to collect_finish_flag == 1 in the order storage area (order table) to be popped, then bypass the noise request to the secondary coalesce module exit, and at the same time, release the secondary coalesce module entry to allow receiving new requests. In this scenario, the noise request is not recorded in the order table.

[0125] b) If the additional buffer (other cmd coalesce buffer) is empty but the request corresponding to collect_finish_flag == 1 in the order storage area (order table) has not been completely popped, block the secondary coalesce module entry, wait for the request corresponding to collect_finish_flag == 1 in the order storage area (order table) to be completely popped, and then bypass the noise request to the secondary coalesce module exit. In this scenario, the noise request is not recorded in the order table.

[0126] c) If the other cmd coalesce buffer is empty and all requests in the order table with collect_finish_flag == 1 have been popped, then the current noise request is bypassed to the exit of the second level coalescing module. The current noise request is not recorded in the order table.

[0127] 9) After the second level coalescing module entry receives a request, if it is a noise request, and all requests in the write cmd coalesce buffer and the read cmd coalesce buffer have collect_finish_flag == 1, then the current noise request enters the other cmd coalesce buffer, and is recorded in the order table. If the other cmd coalesce buffer is full, the second level coalescing module entry is blocked.

[0128] It should be noted that, in the embodiments of the present disclosure, if the request processing method described above is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product in essence or the part that contributes to the related art, which is stored in a storage medium, includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods described in the embodiments of the present disclosure. The storage medium mentioned above includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various program code storage media. Thus, the embodiments of the present disclosure are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0129] The embodiments of the present disclosure provide a computer device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0130] The computer readable storage medium can be transitory or non-transitory.

[0131] The computer program includes computer readable code, and when the computer readable code runs in a computer device, a processor in the computer device performs part or all steps of the above method.

[0132] The computer program product includes a non-transitory computer readable storage medium storing a computer program, and when the computer program is read and executed by a computer, part or all steps of the above method are implemented. The computer program product can be implemented by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) or the like.

[0133] It should be noted that the above description of various embodiments tends to emphasize the differences between various embodiments, and the same or similar parts can be referred to each other. The above description of the device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the device, storage medium, computer program and computer program product embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure.

[0134] It should be noted that, Figure 7 A hardware entity of a computer device in an embodiment of the present disclosure is shown in FIG. 7, which includes a processor 701, a communication interface 702 and a memory 703, wherein: Figure 7 The processor 701 generally controls the overall operation of the computer device 700. The processor 701 generally controls the overall operation of the computer device 700.

[0135] The communication interface 702 can enable the computer device to communicate with other terminals or servers through a network.

[0136] The memory 703 is configured to store instructions and application programs executable by the processor 701, and can also cache data (for example, image data, audio data, voice communication data, and video communication data) to be processed by the processor 701 and modules in the computer device 700. The memory 703 can be implemented by FLASH or Random Access Memory (RAM). The processor 701, the communication interface 702, and the memory 703 can transmit data through the bus 704.

[0137] It should be understood that every feature, structure, or characteristic mentioned herein in relation to an embodiment can be combined with any other feature, structure, or characteristic from another embodiment in the disclosure. Therefore, the occurrence of the phrase "in one embodiment" or "in an embodiment" in various places in the specification does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence number of each step / process in various embodiments of the disclosure does not mean the order of execution, and the execution order of each step / process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence number of the above embodiments of the disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0138] It should be noted that the terms "comprising", "including", or any other variant thereof in this document are intended to cover a non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article, or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or device including the element.

[0139] In several embodiments provided by the disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are only illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interfaces, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0140] The units described as separate components above can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0141] In addition, each functional unit in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional units.

[0142] Those skilled in the art can understand that all or part of the steps of the above method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps including the above method embodiments when executed; and the foregoing storage medium includes mobile storage devices, read only memory (Read Only Memory, ROM), magnetic discs or optical discs, and various storage medium that can store program codes.

[0143] Alternatively, the integrated units of the present disclosure, if implemented in the form of software functional modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present disclosure. The foregoing storage medium includes mobile storage devices, ROM, magnetic discs or optical discs, and various storage medium that can store program codes.

[0144] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A request processing method, characterized in that: The request processing method includes: Performing a first-level merge on multiple original requests for the instructions to be processed to obtain multiple first-level merged requests; Performing a secondary merge on the plurality of primary merge requests to obtain a plurality of secondary merge requests, and sending the secondary merge requests to a downstream module so that the downstream module performs operations corresponding to the plurality of secondary merge requests; the granularity of the secondary merge is greater than the granularity of the primary merge; When a disturbance request is received during the secondary merging process, it is determined whether to insert the disturbance request into the secondary merging request based on the fullness or emptyness of the secondary merging area corresponding to the original request, and then send it to the downstream module so that the downstream module performs the operation corresponding to the disturbance request; the secondary merging area is used to cache multiple first-level merge requests to the cache layer in the determined order of the first-level merge requests.

2. The request processing method according to claim 1, wherein: When a disturbance request is received during the secondary merging process, determining whether to insert the disturbance request into the secondary merging request based on whether the secondary merging area corresponding to the original request is full or empty, and then sending the disturbance request to the downstream module includes: Determine the secondary merge area corresponding to the original request; In the case that there is a cache layer in the secondary merge area that has not completed the request merge, based on whether the additional cache area is empty and the issuance of the target secondary merge request corresponding to the cache layer in the secondary merge area that has completed the request merge, the disturbance request is inserted into the secondary merge request and issued to the downstream module; the additional cache area is used to cache other requests except read requests and write requests.

3. The request processing method according to claim 2, wherein: Determining the secondary merge area corresponding to the original request includes: In a case where the type of the original request is a read type, using the read request merge area as the secondary merge area; In the case that the type of the original request is a write type, the write request merge area is used as the secondary merge area.

4. The request processing method according to claim 2, wherein: The method of inserting the disturbance request into the secondary merge request based on whether the additional cache area is empty and the issuance status of the target secondary merge request corresponding to the cache layer in the secondary merge area that has completed the request merging, and then issuing the disturbance request to the downstream module includes: If the additional buffer area is not empty, suspending the secondary merging operation; In a case where both the request in the additional buffer area and the target secondary merge request are sent to the downstream module, the disturbance request is sent to the downstream module to continue the secondary merge operation.

5. The request processing method according to claim 2, wherein: The method of inserting the disturbance request into the secondary merge request based on whether the additional cache area is empty and the issuance status of the target secondary merge request corresponding to the cache layer in the secondary merge area that has completed the request merging, and then issuing the disturbance request to the downstream module includes: When the additional buffer area is empty but the target secondary merge request has not been fully sent to the downstream module, suspending the secondary merge operation; In the case that all the target secondary merge requests are sent to the downstream module, the disturbance request is sent to the downstream module to continue the secondary merge operation.

6. The request processing method according to claim 2, wherein: The method of inserting the disturbance request into the secondary merge request based on whether the additional cache area is empty and the issuance status of the target secondary merge request corresponding to the cache layer in the secondary merge area that has completed the request merging, and then issuing the disturbance request to the downstream module includes: When the additional buffer area is empty and all the target secondary merge requests are sent to the downstream module, the disturbance request is sent to the downstream module to continue the secondary merge operation.

7. The request processing method according to claim 2, wherein: The request processing method further includes: When all cache layers in the secondary merging area have completed request merging but the additional cache area is idle, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so that the disturbance request is sent to the downstream module based on the arrival order of the disturbance request.

8. The request processing method according to claim 2, wherein: The request processing method further includes: When all cache layers of the secondary merging area have completed the requested merging and there is no idle area in the additional cache area, suspending the secondary merging operation; In the case where both the requests in the secondary merging area and the additional cache area are sent to the downstream module, the disturbance request is sent to the downstream module to continue the secondary merging operation.

9. The request processing method according to any one of claims 1 to 8, characterized in that: The request processing method further includes: When the newly acquired first-level merge request and the request of the second-level merge zone corresponding to the original request belong to the same second-level merge granularity, the merge identifier of the cache layer of the second-level merge zone is maintained as the first identifier value; the first identifier value indicates that the corresponding cache layer has not completed the request merge; When the newly acquired first-level merge request and the request of the second-level merge area do not belong to the same second-level merge granularity, the merge identifier of the cache layer of the second-level merge area is set to a second identifier value; the second identifier value indicates that the corresponding cache layer has completed the request merge.

10. The request processing method according to any one of claims 1 to 8, characterized in that: The request processing method further includes: When a first-level merge request carrying an end identifier is received, the merge identifiers of the cache layers of the second-level merge area are all set to a second identifier value; the second identifier value indicates that the corresponding cache layer has completed the request merge; the end identifier is used to indicate the end of the request merge for the pending instruction.

11. A two-stage merging device, characterized in that: The secondary merging device comprises: a second-level merge area for caching the plurality of first-level merge requests in a cache layer according to a determined order of the first-level merge requests, so as to perform second-level merging of the plurality of first-level merge requests to obtain a plurality of second-level merge requests; the plurality of first-level merge requests are obtained by performing first-level merging of the plurality of original requests for the instructions to be processed, and the granularity of the second-level merging is greater than the granularity of the first-level merging; An additional buffer area, used to buffer other requests except the read request and the write request; An order storage area for recording the order in which requests arrive at the secondary merging device; The secondary merging device is configured to send the plurality of secondary merging requests to a downstream module, so that the downstream module performs operations corresponding to the plurality of secondary merging requests; When a disturbance request is received during the secondary merging process, the secondary merging device is further used to determine whether to insert the disturbance request into the secondary merging request based on the empty or full status of the secondary merging area corresponding to the original request, and send it to the downstream module so that the downstream module performs the operation corresponding to the disturbance request.

12. The secondary merging device according to claim 11, characterized in that: In the case where the type of the original request is a read type, the secondary merge area is a read request merge area; In the case where the type of the original request is a write type, the secondary merge is a write request merge area; The read request merging area is used to perform a second-level merge on the first-level merge requests of the read type; The write request merging area is used to perform a second-level merge on the first-level merge requests of the write type; The depth of the cache layers of the read request merging area, the write request merging area, and the additional cache area is related to the number and number threshold of the first-level merging requests that the second-level merging device can receive at one time; The depth of the sequential storage area is the sum of the depths of the read request merging area, the write request merging area, and the additional cache area.

13. A request processing system, characterized in that: The request processing system includes: a first-level merging device for performing first-level merging on a plurality of original requests for instructions to be processed to obtain a plurality of first-level merged requests; A secondary merging device is configured to perform secondary merging on the plurality of primary merge requests to obtain a plurality of secondary merge requests; upon receiving a disturbance request during the secondary merging process, determine whether to insert the disturbance request into the secondary merge request based on the fullness of the secondary merge area corresponding to the original request, and then send it to a downstream module; the granularity of the secondary merging is greater than the granularity of the primary merging; the secondary merging area is configured to cache the plurality of primary merge requests in a cache layer according to the determined order of the primary merge requests; The downstream module is used to execute operations corresponding to the multiple secondary merge requests to realize processing of the pending instructions; and execute operations corresponding to the disturbance request.

Images