Instruction processing method and device, terminal equipment and program product

Abstract

The invention is suitable for the technical field of computer processor design, and provides an instruction processing method and device, terminal equipment and a program product, and the method comprises the steps: obtaining instruction information of a to-be-processed instruction set in a processor; generating an index vector corresponding to the to-be-processed instruction set based on the original effective vector; each index value in the index vector is subjected to one-hot code conversion, a one-hot code matrix corresponding to the instruction set to be processed is generated, and each row of one-hot code vector in the one-hot code matrix corresponds to each path of input instruction; and according to the original effective vector and the one-hot code matrix, sorting operation codes of each path of input instruction to obtain processed operation code information, so that a processor executes corresponding operation based on the processed operation code information. The method can meet the requirement that the high-performance processor completes instruction processing in a single cycle, the processing delay is low, and therefore the instruction execution efficiency of the processor is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer processor design, and particularly relates to an instruction processing method and device, a terminal device and a program product. BACKGROUND

[0002] With the development of computer technology, the performance of processors is continuously improved, and the efficiency of instruction processing becomes one of the key factors affecting the performance of processors. In modern high-performance processors, simultaneously dispatching multiple instructions is an important means to improve the parallel processing capability of processors, but in actual application, there may be invalid instructions among these simultaneously dispatched multiple instructions, resulting in a sparse state of instruction flow (i.e., valid instructions are discontinuous and are interspersed with invalid instructions). Therefore, there is an urgent need for an instruction processing method to effectively sort and compress instructions to improve the efficiency of instruction execution.

[0003] However, the traditional instruction processing method usually adopts a serial shift method to compress and sort instructions, which has a high delay and cannot meet the demand of high-performance processors to complete instruction processing within a single cycle, resulting in a relatively low efficiency of instruction execution of the processor. SUMMARY

[0004] The embodiments of the present application provide an instruction processing method, device, terminal device and program product, which can meet the demand of high-performance processors to complete instruction processing within a single cycle and improve the efficiency of instruction execution of the processor.

[0005] In a first aspect, the embodiments of the present application provide an instruction processing method, comprising: obtaining instruction information of a set of to-be-processed instructions in a processor, wherein the instruction information comprises an original valid vector corresponding to the set of to-be-processed instructions and an operation code of each input instruction in the set of to-be-processed instructions, and each element in the original valid vector is used to represent the validity of each input instruction; generating an index vector corresponding to the set of to-be-processed instructions based on the original valid vector, wherein each index value in the index vector is used to represent an initial arrangement position of each input instruction; performing one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the set of to-be-processed instructions, wherein each row of one-hot code vectors in the one-hot code matrix corresponds to each input instruction; sorting the operation code of each input instruction according to the original valid vector and the one-hot code matrix to obtain processed operation code information, so that the processor executes corresponding operations based on the processed operation code information.

[0006] In a possible implementation manner of the first aspect, the processed operation code information comprises a target operation code vector and a target valid vector. According to the original effective vector and the one-hot code matrix, the operation codes of each input instruction are sorted to obtain processed operation code information, including: According to the effective elements in the original effective vector and each column vector in the one-hot code matrix, a target operation code vector corresponding to the to-be-processed instruction set is generated, and the target operation code vector is used to represent the operation codes of each input instruction arranged in sequence according to the execution order. The original effective vector and each column vector in the one-hot code matrix are subjected to logical operation to generate a target effective vector corresponding to the target operation code vector, and each element in the target effective vector is used to represent the validity of the operation code at the corresponding position in the target operation code vector.

[0007] In a possible implementation manner of the first aspect, according to the effective elements in the original effective vector and each column vector in the one-hot code matrix, the target operation code vector corresponding to the to-be-processed instruction set is generated, including: For each column vector in the one-hot code matrix, if it is detected that there is an effective element in each column vector, the target input instruction corresponding to each column vector is determined according to the row identifier of the effective element in each column vector and the element identifier of the effective element in the original effective vector, and the operation code of the target input instruction is determined as the target operation code corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no effective element in each column vector, a null operation instruction is determined as the target input instruction corresponding to each column vector, and the operation code of the null operation instruction is determined as the target operation code corresponding to each column vector. Based on the target operation codes corresponding to the plurality of column vectors, the target operation code vector corresponding to the to-be-processed instruction set is generated.

[0008] In a possible implementation manner of the first aspect, the original effective vector and each column vector in the one-hot code matrix are subjected to logical operation to generate the target effective vector corresponding to the target operation code vector, including: For each column vector in the one-hot code matrix, each element in each column vector and each element in the original effective vector are subjected to logical AND operation to obtain each first operation result corresponding to each column vector. For each column vector in the one-hot code matrix, each first operation result corresponding to each column vector is subjected to logical OR operation to obtain a second operation result corresponding to each column vector. Based on the second operation results corresponding to the plurality of column vectors, the target effective vector corresponding to the to-be-processed instruction set is generated.

[0009] In a possible implementation manner of the first aspect, the index vector corresponding to the to-be-processed instruction set is generated based on the original effective vector, including: For each element in the original effective vector, the number of effective elements in all elements before each element is counted to obtain an index value of the input instruction corresponding to each element; Based on the index values of the input instructions corresponding to the plurality of elements, an index vector corresponding to the set of instructions to be processed is generated.

[0010] In a possible implementation manner of the first aspect, the one-hot code conversion is performed on each index value in the index vector respectively to generate a one-hot code matrix corresponding to the set of instructions to be processed, including: Each index value in the index vector is used to perform left shift processing on the set binary value to obtain a one-hot code vector corresponding to each index value; Based on the one-hot code vectors corresponding to the plurality of index values, a one-hot code matrix corresponding to the set of instructions to be processed is generated.

[0011] In a possible implementation manner of the first aspect, the bit width of the set binary value is equal to the number of input instructions in the set of instructions to be processed.

[0012] The second aspect, the embodiments of the present application provide an instruction processing device, including: The acquisition module is used for acquiring instruction information of a set of instructions to be processed in a processor, wherein the instruction information includes an original effective vector corresponding to the set of instructions to be processed, and an operation code of each input instruction in the set of instructions to be processed, each element in the original effective vector is used for indicating the validity of each input instruction respectively; The first generation module is used for generating an index vector corresponding to the set of instructions to be processed based on the original effective vector, each index value in the index vector is used for representing an initial arrangement position of each input instruction respectively; The second generation module is used for performing one-hot code conversion on each index value in the index vector respectively to generate a one-hot code matrix corresponding to the set of instructions to be processed, each row of one-hot code vectors in the one-hot code matrix corresponds to each input instruction respectively; The processing module is used for performing sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, so that the processor performs corresponding operations based on the processed operation code information.

[0013] The third aspect, the embodiments of the present application provide a terminal device, including a memory, a processor and a computer program stored in the memory and executable on the processor, when the processor executes the computer program, the method of any one of the first aspect is realized.

[0014] The fourth aspect, the embodiments of the present application provide a computer readable storage medium, the computer readable storage medium stores a computer program, when the computer program is executed by the processor, the method of any one of the first aspect is realized.

[0015] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when running on a terminal device, causes the terminal device to perform the method of any one of the first aspect.

[0016] An embodiment of the present application provides an instruction processing method and device, a terminal device and a program product. The method comprises: obtaining instruction information of a set of to-be-processed instructions in a processor, wherein the instruction information comprises an original effective vector corresponding to the set of to-be-processed instructions and an operation code of each input instruction in the set of to-be-processed instructions, and each element in the original effective vector is used to represent the effectiveness of each input instruction; generating an index vector corresponding to the set of to-be-processed instructions based on the original effective vector, wherein each index value in the index vector is used to represent an initial arrangement position of each input instruction; performing one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the set of to-be-processed instructions, wherein each row of one-hot code vectors in the one-hot code matrix corresponds to each input instruction; and performing sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, so that the processor performs corresponding operations based on the processed operation code information. By performing one-hot code conversion on each index value in the index vector generated based on the original effective vector to generate a one-hot code matrix corresponding to the set of to-be-processed instructions, and performing sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, the demand of a high-performance processor for completing instruction processing within a single cycle can be met, the processing delay is low, and thus the instruction execution efficiency of the processor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0018] Figure 1 is a flowchart of an instruction processing method provided by an embodiment of the present application; Figure 2 is a flowchart of an instruction processing method provided by another embodiment of the present application; Figure 3 is a schematic diagram of the overall architecture of an instruction processing method provided by another embodiment of the present application; Figure 4 is a structural block diagram of an instruction processing device provided by an embodiment of the present application; Figure 5is a structural schematic diagram of a terminal device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular architectures, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0020] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", "including", "containing", "having" and / or "comprises" when used in the present specification and in the accompanying claims, specifies the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] It is also to be understood that the terminology "and / or" when used in the present specification and in the accompanying claims, refers to both a combination of any of the associated listed items and all possible combinations of those items, and includes the combination of these.

[0022] As used in the present specification and in the accompanying claims, the term "if" can be interpreted as meaning "when" or "upon" or "in response to a determination" or "in response to a detection" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "upon determining" or "in response to a determining" or "upon detecting [the described condition or event]" or "in response to a detection [of the described condition or event]" depending on the context.

[0023] In addition, in the description of the present specification and in the accompanying claims, the terms "first", "second", "third", etc. are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0024] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, although it can. The terms "comprising", "including", "having" and their variants, mean "including but not limited to", unless otherwise expressly specified and / or limited by the context.

[0025] It can be considered that in modern high-performance processors, especially in superscalar processors, usually multiple instructions are simultaneously dispatched to different execution units in each clock cycle in the instruction dispatch stage. However, due to the dependence between instructions or resource conflicts, there may be invalid instructions in these simultaneously dispatched multiple instructions, resulting in a sparse instruction stream (i.e., valid instructions are discontinuous and are interspersed with invalid instructions). However, subsequent processing stages, such as the reorder buffer or the execution unit queue, usually expect to receive a continuous, gap-free valid instruction stream to simplify the logic design, improve resource utilization, and reduce power consumption. Therefore, there is an urgent need for an instruction processing method to effectively sort and compress instructions to improve the efficiency of instruction execution.

[0026] However, the prior art has some problems in processing sparse multi-path input instructions. First, the traditional instruction processing method usually adopts a serial shift method to compress and sort instructions, which has high delay and cannot meet the demand of high-performance processors to complete instruction processing in a single cycle. Second, some technical solutions use a complex multi-stage selector network to implement instruction compression and sorting, but the circuit area and wiring complexity of this method will increase sharply with the increase of the number of instructions processed, which is not conducive to the expansion and optimization of the processor. In addition, when processing sparse instruction streams, the prior art often has difficulty in maintaining the execution order of instructions while ensuring efficient processing, which may affect the execution of programs that rely on instruction order.

[0027] In summary, the prior art cannot efficiently compress sparse multi-path input instructions into compact forward-aligned output in a single cycle, and the circuit implementation is complex, has high delay, and is not easy to expand, which makes it difficult to meet the requirements of modern high-performance processors for instruction processing efficiency and flexibility. Therefore, how to efficiently sort and compress multi-path input instructions and easily expand the processor is a problem that needs to be solved.

[0028] Based on this, the embodiment of the present application provides an instruction processing method, which divides the entire processing process into three logically closely connected stages, and realizes the parallel compression and sorting of multi-path instructions through a leading valid count-based index generation mechanism combined with a one-hot code mapping matrix and a parallel selection network. The entire compression and sorting process is realized through a pure combinational logic circuit, and the conversion from disordered sparse input to ordered compact output is completed in a single cycle, thereby improving the instruction execution efficiency of the processor.

[0029] Figure 1 is a flowchart of an instruction processing method provided by an embodiment of the present application, which is an example and is not limited. The method can be applied in a terminal device, and the specific type of the terminal device is not limited, including but not limited to mobile phones, tablet computers and other devices. As shown in Figure 1As shown, the method comprises: S101, obtaining instruction information of a set of to-be-processed instructions in a processor.

[0030] The instruction information comprises an original effective vector corresponding to the set of to-be-processed instructions, and an operation code of each input instruction in the set of to-be-processed instructions, each element in the original effective vector being used to represent the effectiveness of each input instruction.

[0031] For example, the original effective vector can be a binary vector, and an element value of 1 indicates that the input instruction of the corresponding lane is valid, and an element value of 0 indicates that the input instruction of the corresponding lane is invalid. Further, for a 3-lane instruction set, when the original effective vector is [1, 0, 1], it indicates that the input instructions of the 0th lane and the 2nd lane are valid, and the input instruction of the 1st lane is invalid. The operation code of each input instruction can be a field in each input instruction, which is used to specify a specific operation or command to be executed.

[0032] S102, generating an index vector corresponding to the set of to-be-processed instructions based on the original effective vector.

[0033] Each index value in the index vector is used to represent the initial arrangement position of each input instruction.

[0034] In this step, the index value of each element corresponding to the input instruction can be determined through a series of accumulation calculations for subsequent adjustment of the final arrangement position of each input instruction based on the effectiveness of the input instruction. Alternatively, a pre-trained neural network model can be used to directly obtain the index vector corresponding to the set of to-be-processed instructions by inputting the original effective vector into the neural network model. Alternatively, when the number of input instructions is small, the position of each input instruction in the final compressed output result can be directly calculated by sequentially detecting the effectiveness of each input instruction. For example, when the set of to-be-processed instructions includes 3 input instructions, and the original effective vector corresponding to the set of to-be-processed instructions is [1, 0, 1], the first bit in the index vector is detected, the index value is “1”, and the corresponding 0th input instruction is determined to be at position 0 in the final compressed output result. Then, the second bit index value is detected, which is “0”, and the corresponding first input instruction is configured at the last position (i.e., position 2) in the final compressed output result. Finally, the third bit index value is detected, which is “1”, and the corresponding second input instruction is configured at position 1 in the final compressed output result.

[0035] As a feasible implementation, the index vector corresponding to the to-be-processed instruction set is generated based on the original effective vector, including: for each element in the original effective vector, counting the number of effective elements in all elements located before each element to obtain an index value of an input instruction corresponding to each element; and generating the index vector corresponding to the to-be-processed instruction set based on the index values of the input instructions corresponding to the plurality of elements.

[0036] For example, an effective signal vector with a bit width of N is Vld[N-1:0], wherein each bit Vld[i] represents the validity of the i-th input instruction ("1" represents valid and "0" represents invalid), and the calculation method of the index value Index[i] of the i-th instruction (i is from 0 to N-1) can be to accumulate the effective signal values of the input instructions with index values less than i, that is, the value of Index[i] is equal to the number of valid instructions located before the i-th instruction, which is expressed by a mathematical formula as follows: Index[i]=∑(Vld[j]), wherein the value range of the summation variable j is from 0 to i-1.

[0037] Therefore, an index vector Index[N-1:0] can be output, and each element Index[i] indicates the position to which the corresponding i-th valid instruction should be placed at the output end. The index value of the invalid instruction is determined by the number of valid instructions in front of it, but it will be filtered in the subsequent stage.

[0038] Further, each element Index[i] is an M-bit binary number, and M=ceil(log2(N)), for example, when N=5, M=3, and ceil() is a rounding-up function.

[0039] More specifically, assuming that the effective signal vector is [1, 0, 1, 0, 1], which indicates that the 0th, 2nd and 4th input instructions are valid, and the 1st and 3rd input instructions are invalid, then for the first element "1", there is no element in front of it, so the index value of the 0th input instruction is 0; for the second element "0", there is one valid element in front of it, so the index value of the 1st input instruction is 1; similarly, the index value of the 2nd input instruction is also 1; for the fourth element "0", there are two valid elements in front of it, so the index value of the 3rd input instruction is 2; similarly, the index value of the 4th input instruction is also 2. Therefore, the generated index vector is [0, 1, 1, 2, 2], and the meaning of the index vector is that the 0th instruction should be placed at position 0, the 2nd instruction should be placed at position 1, and the 4th instruction should be placed at position 2.

[0040] In practical applications, this step can be implemented by a parallel prefix sum calculation network composed of a series of adders, which can simultaneously calculate the index values of all input instructions, achieving low latency.

[0041] S103, respectively, each index value in the index vector is converted into one-hot code to generate a one-hot code matrix corresponding to the set of instructions to be processed.

[0042] Each row of the one-hot code matrix corresponds to each input instruction.

[0043] This step is used to convert the index vector calculated in the previous step into a one-hot code matrix, providing clear gating signals for subsequent data selection. The specific processing process can include: for each index value Index[i], it is converted into an N-bit one-hot code vector OneHotVec[i], and then combined to obtain a one-hot code matrix corresponding to the set of instructions to be processed. Here, the means of converting the index value are not limited, such as one-hot code is a binary encoding form, its characteristic is that only one bit is 1 and the rest are 0, so according to the parity of each index value, different conversion means are used, or the index value can be analyzed to convert it into a one-hot code vector, such as for index value , its corresponding one-hot code vector can be 00100, and for index value , its corresponding one-hot code vector can be 01000.

[0044] As a feasible implementation, respectively, each index value in the index vector is converted into one-hot code to generate a one-hot code matrix corresponding to the set of instructions to be processed, including: respectively, each index value in the index vector is used to left shift a set binary value to obtain a one-hot code vector corresponding to each index value; based on the one-hot code vectors corresponding to the plurality of index values, a one-hot code matrix corresponding to the set of instructions to be processed is generated.

[0045] In this embodiment, the specific conversion rule of the index value is: first, generate an N-bit binary number (i.e. set binary value), which has only one bit as 1 and the rest as 0, then left shift the binary number by Index[i] bits to realize the one-hot code conversion of each index value, and obtain a one-hot code vector corresponding to each index value; and then form an N*N one-hot code matrix OneHotVec, each row OneHotVec[i] of the one-hot code matrix corresponds to one original input instruction, and the position of "1" in the one-hot code matrix indicates which position of the output end is "contributed" by the input instruction corresponding to the row.

[0046] For example, when the binary value is set as a constant "1" with a bit width of 5, and the index vector is [0, 1, 1, 2, 2], the one-hot code vector corresponding to the 0th input instruction is 00001 << Index[0] =

[00001] ; the one-hot code vector corresponding to the 1st input instruction is 00001 << Index[1] =

[00010] ; the one-hot code vector corresponding to the 2nd input instruction is 00001 << Index[1] =

[00010] ; the one-hot code vector corresponding to the 3rd input instruction is 00001 << Index[2] =

[00100] ; and the one-hot code vector corresponding to the 4th input instruction is 00001 << Index[2] =

[00100] , thereby forming the one-hot code matrix OneHotVec = [00001, 00010, 00010, 00100, 00100]. .

[0047] In actual applications, this step can be essentially implemented by a parallel decoder array to decode the M-bit index value into an N-bit one-hot code, which is regular in circuit and easy to implement.

[0048] Optionally, in order to subsequently sort the operation codes of each input instruction according to the original effective vector and the one-hot code matrix, the bit width of the binary value can be equal to the number of input instructions in the instruction set to be processed.

[0049] S104, sort the operation codes of each input instruction according to the original effective vector and the one-hot code matrix, to obtain processed operation code information, so that the processor executes the corresponding operation based on the processed operation code information.

[0050] This step can be implemented by sorting the operation codes of each input instruction, and the specific process can be, for example, rearranging the operation codes of each input instruction according to the positions and effectiveness indicated by the one-hot code matrix, thereby obtaining a sorted operation code sequence, or the processed operation code information can also be obtained by performing certain logical operations on the elements in the original effective vector and the one-hot code matrix. This embodiment will not be further expanded, as long as the processed operation code information can be obtained.

[0051] The instruction processing method provided in this embodiment can generate a one-hot code matrix corresponding to the instruction set to be processed by converting each index value in the index vector generated based on the original effective vector into one-hot code, and can sort the operation codes of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, thereby meeting the demand of high-performance processors to complete instruction processing within a single cycle, reducing processing delay, and improving the instruction execution efficiency of the processor.

[0052] Figure 2 is a flowchart of an instruction processing method provided by another embodiment of the present application. In this embodiment, the processed opcode information includes: a target opcode vector and a target valid vector; and the opcodes of each input instruction are sorted according to the original valid vector and the OneHot matrix to obtain the processed opcode information, which is further optimized as follows: generating a target opcode vector corresponding to the set of instructions to be processed according to the valid elements in the original valid vector and each column vector in the OneHot matrix, the target opcode vector being used to represent the opcodes of each input instruction arranged in sequence according to the execution order; and performing logical operation on each element in the original valid vector and each column vector in the OneHot matrix to generate a target valid vector corresponding to the target opcode vector, each element in the target valid vector being used to represent the validity of the opcode at the corresponding position in the target opcode vector. As shown in Figure 2 the method comprises the following steps. S201, obtaining instruction information of a set of instructions to be processed in a processor.

[0053] S202, generating an index vector corresponding to the set of instructions to be processed based on an original valid vector.

[0054] S203, respectively converting each index value in the index vector into OneHot to generate a OneHot matrix corresponding to the set of instructions to be processed.

[0055] S204, generating a target opcode vector corresponding to the set of instructions to be processed according to the valid elements in the original valid vector and each column vector in the OneHot matrix.

[0056] The target opcode vector is used to represent the opcodes of each input instruction arranged in sequence according to the execution order.

[0057] In this embodiment, the opcode PackedOp[k] of each bit after compression and sorting can be generated by an N-to-1 multiplexer, and the selection signal of the multiplexer is specifically determined by the valid elements in the original valid vector and each column vector in the OneHot matrix, for example, can be composed of the operation results of OneHotVec[j][k]&Vld[j] for all j. Due to the characteristics of OneHot, at any moment, at most only one instruction j satisfies (OneHotVec[j][k]&Vld[j]) is true, so this step is logically equivalent to a data selector that selects only one correct instruction opcode from all input instructions to assign to PackedOp[k].

[0058] As a feasible implementation manner, generating a target opcode vector corresponding to the set of instructions to be processed according to the valid elements in the original valid vector and each column vector in the OneHot matrix comprises: For each column vector in the OneHot matrix, if it is detected that there is a valid element in each column vector, then according to the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector, the target input instruction corresponding to each column vector is determined, and the operation code of the target input instruction is determined as the target operation code corresponding to each column vector; For each column vector in the OneHot matrix, if it is detected that there is no valid element in each column vector, then the null operation instruction is determined as the target input instruction corresponding to each column vector, and the operation code of the null operation instruction is determined as the target operation code corresponding to each column vector; Based on the target operation codes corresponding to the plurality of column vectors, a target operation code vector corresponding to the to-be-processed instruction set is generated.

[0059] Specifically, the target input instruction corresponding to each column vector can be determined in different ways according to whether there is a valid element in the column vector in the OneHot matrix, and the operation code of the determined target input instruction is determined as the target operation code corresponding to each column vector, and then the target operation codes can be sequentially compressed and sorted according to the order of the column identifiers to form a target operation code vector corresponding to the to-be-processed instruction set. For example, if there is a valid element in a column vector, then the row identifier of the valid element and the element identifier of the valid element in the original valid vector can be detected to determine whether there is a same identifier between the two, if there is a same identifier, then the input instruction corresponding to the same identifier can be determined as the target input instruction corresponding to the column vector; if there is no same identifier, or there is no valid element in the column vector, then the null operation instruction can be determined as the target input instruction corresponding to the column vector. The null operation instruction can be a command in a computer instruction system that does not perform actual operation but occupies an instruction position, in the embodiment, the null operation instruction can be understood as an invalid input instruction.

[0060] For example, when the input instruction is Opcode[N-1:0], for k=0 (the first position after compression and sorting), that is, for the first column vector

[00001] in the OneHot matrix, the row identifier of the valid element is j=0, and the element identifier of the valid element in the original valid vector [1, 0, 1, 0, 1] is j=0, j=2, j=4, that is, only OneHotVec[0][0] ==1 and Vld[0] ==1, at this time, the operation code of the 0th input instruction can be placed in the first position of the target operation code vector.

[0061] For k = 1 (the second position after compressed sorting): that is, for the second column vector

[01100] in the OneHot matrix, the row identifiers of the valid elements are j = 1, j = 2, and the element identifiers of the valid elements in the original valid vector [1, 0, 1, 0, 1] are j = 0, j = 2, j = 4, that is, OneHotVec[1][1], [2][1] are both 1, but only the second input instruction (j = 2) is valid, so the operation code of the second input instruction is finally selected and placed in the second position of the target operation code vector.

[0062] For k = 2 (the third position after compressed sorting): for the third column vector

[00011] in the OneHot matrix, the row identifiers of the valid elements are j = 3, j = 4, and the element identifiers of the valid elements in the original valid vector [1, 0, 1, 0, 1] are j = 0, j = 2, j = 4, that is, OneHotVec[3][2], [4][2] are both 1, but only the fourth input instruction (j = 4) is valid, so the operation code of the fourth input instruction is finally selected and placed in the third position of the target operation code vector.

[0063] For k = 3, 4: since there is no valid element in the third and fourth column vectors in the OneHot matrix, the operation code of the null instruction can be placed in the fourth and fifth positions of the target operation code vector, such as 0.

[0064] In summary, the target operation code vector PackedOp = [Op0, Op2, Op4, 0, 0] represents the operation code of each input instruction arranged in the order of execution.

[0065] S205, performing logical operation on each element in the original valid vector and each column vector in the OneHot matrix to generate a target valid vector corresponding to the target operation code vector.

[0066] Each element in the target valid vector is used to represent the validity of the operation code in the corresponding position of the target operation code vector.

[0067] In this embodiment, the compressed and sorted valid signal PackedVld[k] can be obtained by performing logical OR operation on all signals satisfying the condition (OneHotVec[j][k]&Vld[j]) being true, which means that as long as any instruction j is mapped to position k and itself is valid, PackedVld[k] is valid.

[0068] As a feasible implementation, performing logical operation on each element in the original valid vector and each column vector in the OneHot matrix to generate a target valid vector corresponding to the target operation code vector comprises: For each column vector in the one-hot code matrix, logical AND operation is respectively performed on each element in each column vector and each element in the original effective vector, to obtain each first operation result corresponding to each column vector; For each column vector in the one-hot code matrix, logical OR operation is performed on each first operation result corresponding to each column vector, to obtain each second operation result corresponding to each column vector; Based on the second operation results corresponding to the plurality of column vectors, the target effective vector corresponding to the set of to-be-processed instructions is generated.

[0069] Specifically, the target effective vector can be obtained by performing logical AND operation on each element of each column in the one-hot code matrix and the corresponding element in the original effective vector to obtain each first operation result, and then performing logical OR operation on each first operation result to obtain each second operation result corresponding to each column, so as to form the target effective vector PackedVld. Exemplarily, each element of the target effective vector can be calculated in the following manner: PackedVld[0]=OneHotVec[0][0]&Vld[0]+OneHotVec[1][0]&Vld[1]+OneHotVec[2][0]&Vld[2]+OneHotVec[3][0]&Vld[3]+OneHotVec[4][0]&Vld[4]=1.

[0070] PackedVld[1]=OneHotVec[0][1]&Vld[0]+OneHotVec[1][1]&Vld[1]+OneHotVec[2][1]&Vld[2]+OneHotVec[3][1]&Vld[3]+OneHotVec[4][1]&Vld[4]=1.

[0071] PackedVld[2]=OneHotVec[0][2]&Vld[0]+OneHotVec[1][2]&Vld[1]+OneHotVec[2][2]&Vld[2]+OneHotVec[3][2]&Vld[3]+OneHotVec[4][2]&Vld[4]=1.

[0072] PackedVld[3]=OneHotVec[0][3]&Vld[0]+OneHotVec[1][3]&Vld[1]+OneHotVec[2][3]&Vld[2]+OneHotVec[3][3]&Vld[3]+OneHotVec[4][3]&Vld[4]=0.

[0073] PackedVld[4] = OneHotVec[0][4] & Vld[0] + OneHotVec[1][4] & Vld[1] + OneHotVec[2][4] & Vld[2] + OneHotVec[3][4] & Vld[3] + OneHotVec[4][4] & Vld[4] = 0.

[0074] In summary, the target valid vector PackedVld = [1, 1, 1, 0, 0] is used to represent the validity of the operation code in the corresponding position of the target operation code vector, that is, the first three positions are valid.

[0075] It can be seen that the compressed target valid vector PackedVld[N-1:0] has the characteristic that all valid bits "1" are arranged continuously in the low bit (front alignment) of the vector, and the high bit is invalid bit "0"; the compressed target operation code vector PackedOp[N-1:0] is obtained, wherein the content of PackedOp[k] is the operation code of the kth valid instruction in the original input. On this basis, when there is a valid element (value 1) in a column vector of the one-hot code matrix, and the element in the corresponding row of the original valid vector is also valid (value 1), the element in the corresponding position of the target valid vector is valid (value 1). This ensures that only the truly valid operation code in the target operation code vector is marked as valid.

[0076] The instruction processing method provided in this embodiment can effectively generate a compact and ordered target operation code vector by filtering each column vector in the one-hot code matrix with the original valid vector bit by bit, and identify the validity of each operation code through the target valid vector, thereby providing a clear data structure for subsequent execution of instructions, further improving the efficiency of instruction processing, and simplifying the subsequent processing logic.

[0077] Figure 3 is a schematic diagram of the overall architecture of an instruction processing method provided by another embodiment of the present application, as shown in Figure 3As shown, the input data can include the operation codes and original valid vectors of N input instructions, and the specific instruction processing process can be sequentially composed of three core stages, and the hardware device can correspondingly include three main logic modules, i.e., a parallel position index calculation module, a one-hot code mapping matrix generation module, and a parallel multi-path selection output module. The parallel position index calculation module is used to calculate the index vector of each input instruction in the final compressed and sorted result, and the specific means can be to calculate how many valid instructions are in front of each input instruction, and the number is the position index of the input instruction after compression. The one-hot code mapping matrix generation module is used to convert the index vector calculated in the first stage into a one-hot code matrix to provide clear selection signals for subsequent data selection, such as converting each index value in the index vector into a one-hot code vector to generate a one-hot code matrix, for example, the index value 2 at position 2 can be converted into a one-hot code vector

[00100] .

[0078] The parallel multi-path selection output module is used to select the result of each compressed output from all input instructions in parallel according to the one-hot code matrix, such as filtering the one-hot code matrix and the original valid vector by bit to output a compact and ordered instruction group (target operation code vector; target valid vector), so that the subsequent processing stage can perform corresponding operations on the operation code in the corresponding bit of the target operation code vector according to the validity of each bit in the target valid vector. The target operation code vector can be determined according to the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector; and the target valid vector can be determined by performing logical AND operation on each column element in the one-hot code matrix and the corresponding element in the original valid vector, and then performing logical OR operation.

[0079] As can be seen from the above description, the instruction processing method provided by the embodiment can dynamically compress and sort the multiple possible out-of-order valid input instructions into a continuous and compact forward alignment format, and eliminate the gap between invalid instructions, thereby solving the problem that the prior art cannot efficiently compress the sparse multi-path input instructions into a compact forward alignment output in a single cycle, and realizing the problems of complex circuit, high delay, and difficulty in expansion.

[0080] Specifically, the beneficial effects of the instruction processing method provided by the embodiment are as follows: 1. High performance and low delay: the entire compression and sorting process is realized by pure combinational logic circuit, which can be completed in one clock cycle, suitable for high-frequency operation of the processor pipeline, and significantly reduces the delay of instruction dispatch.

[0081] 2. True parallel processing: unlike the serial shift method, the three stages of the embodiment all adopt parallel computing structure, and the processing of each path of instructions is performed simultaneously, and the path delay is relatively balanced and does not change with the valid mode of the input instruction.

[0082] 3. Structure is regular and easy to expand: The structures of the above three hardware devices are very regular (adder array, decoder array, selector array), and when the number of paths N to be processed increases, the size of each array can be expanded in proportion, and the expandability is strong.

[0083] 4. Strong function correctness: The index generation algorithm based on the leading effective count ensures that the order of the compressed instructions is completely consistent with the order of the effective instructions in the original input, and lossless compression sorting is achieved.

[0084] 5. Simplify subsequent design: The compact forward alignment output format generated by the embodiment greatly simplifies the design of subsequent processing units (such as execution unit queue, renaming logic, etc.).

[0085] The instruction processing method corresponding to the above embodiment, Figure 4 is a structural block diagram of an instruction processing device provided by an embodiment of the present application. Only parts related to the embodiments of the present application are shown for ease of illustration.

[0086] Referring to Figure 4 The device comprises: An acquisition module 301 is configured to acquire instruction information of a set of instructions to be processed in a processor, wherein the instruction information comprises an original effective vector corresponding to the set of instructions to be processed and an operation code of each input instruction in the set of instructions to be processed, and each element in the original effective vector is used to represent the validity of each input instruction. A first generation module 302 is configured to generate an index vector corresponding to the set of instructions to be processed based on the original effective vector, and each index value in the index vector is used to represent the initial arrangement position of each input instruction. A second generation module 303 is configured to perform one-hot code conversion on each index value in the index vector respectively to generate a one-hot code matrix corresponding to the set of instructions to be processed, and each row of one-hot code vectors in the one-hot code matrix corresponds to each input instruction. A processing module 304 is configured to perform sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, so that the processor performs corresponding operations based on the processed operation code information.

[0087] The embodiment provides an instruction processing device, which comprises an obtaining module configured to obtain instruction information of a to-be-processed instruction set in a processor, wherein the instruction information comprises an original effective vector corresponding to the to-be-processed instruction set and an operation code of each input instruction in the to-be-processed instruction set, and each element in the original effective vector is used for representing the validity of each input instruction; a first generating module configured to generate an index vector corresponding to the to-be-processed instruction set based on the original effective vector, wherein each index value in the index vector is used for representing an initial arrangement position of each input instruction; a second generating module configured to perform one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the to-be-processed instruction set, wherein each one-hot code vector in the one-hot code matrix corresponds to each input instruction; and a processing module configured to perform sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, so that the processor performs corresponding operations based on the processed operation code information. By performing one-hot code conversion on each index value in the index vector generated based on the original effective vector to generate a one-hot code matrix corresponding to the to-be-processed instruction set, and performing sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, the demand of a high-performance processor for completing instruction processing in a single cycle can be met, the processing delay is low, and thus the instruction execution efficiency of the processor is improved.

[0088] Optionally, the processed operation code information comprises a target operation code vector and a target effective vector. The processing module comprises: a first vector generating unit configured to generate a target operation code vector corresponding to the to-be-processed instruction set according to the valid elements in the original effective vector and each column vector in the one-hot code matrix, wherein the target operation code vector is used for representing the operation code of each input instruction arranged continuously in the execution order; a second vector generating unit configured to perform logical operation on each element in the original effective vector and each column vector in the one-hot code matrix to generate a target effective vector corresponding to the target operation code vector, wherein each element in the target effective vector is used for representing the validity of the operation code at the corresponding position in the target operation code vector.

[0089] Optionally, the first vector generating unit is specifically configured to: for each column vector in the one-hot code matrix, if it is detected that there is a valid element in each column vector, the target input instruction corresponding to each column vector is determined according to the row identifier of the valid element in each column vector and the element identifier of the valid element in the original effective vector, and the operation code of the target input instruction is determined as the target operation code corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no valid element in each column vector, the no-operation instruction is determined as a target input instruction corresponding to each column vector, and an operation code of the no-operation instruction is determined as a target operation code corresponding to each column vector; Based on the target operation codes corresponding to the plurality of column vectors, a target operation code vector corresponding to the set of to-be-processed instructions is generated.

[0090] Optionally, the second vector generating unit is specifically configured to: For each column vector in the one-hot code matrix, a logical AND operation is respectively performed on each element in each column vector and each element in the original valid vector, to obtain a first operation result corresponding to each column vector; For each column vector in the one-hot code matrix, a logical OR operation is performed on the first operation results corresponding to each column vector, to obtain a second operation result corresponding to each column vector; Based on the second operation results corresponding to the plurality of column vectors, a target valid vector corresponding to the set of to-be-processed instructions is generated.

[0091] Optionally, the first generating module is specifically configured to: For each element in the original valid vector, the number of valid elements among all elements located before each element is counted, to obtain an index value of an input instruction corresponding to each element; Based on the index values of the input instructions corresponding to the plurality of elements, an index vector corresponding to the set of to-be-processed instructions is generated.

[0092] Optionally, the second generating module is specifically configured to: Each index value in the index vector is respectively used to perform left shift processing on the set binary value, to obtain a one-hot code vector corresponding to each index value; Based on the one-hot code vectors corresponding to the plurality of index values, a one-hot code matrix corresponding to the set of to-be-processed instructions is generated.

[0093] Optionally, the bit width of the set binary value is equal to the number of input instructions in the set of to-be-processed instructions.

[0094] It should be noted that the information interaction, execution process and the like between the above-described apparatuses / units are based on the same concept as the method embodiments of the present application, and specific functions and technical effects brought by the same can be referred to the method embodiments part, which will not be described herein again.

[0095] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0096] Figure 5 This is a schematic diagram of the structure of a terminal device provided in one embodiment of this application, as shown below. Figure 5 As shown, the terminal device 500 of this embodiment includes: at least one processor 502 ( Figure 5 (Only one is shown) a processor, a memory 501, and a computer program 503 stored in the memory 501 and executable on at least one processor 502. When the processor 502 executes the computer program 503, it implements the steps in the control method embodiments of any of the above-described application programs.

[0097] Terminal device 500 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This terminal device may include, but is not limited to, a processor 502 and a memory 501. Those skilled in the art will understand that... Figure 5 This is merely an example of terminal device 500 and does not constitute a limitation on terminal device 500. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0098] The processor 502 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0099] The memory 501 can be an internal storage unit of the terminal device 500 in some embodiments, for example, a hard disk or a memory of the terminal device 500. The memory 501 can also be an external storage device of the terminal device 500 in other embodiments, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal device 500. Further, the memory 501 can include both the internal storage unit and the external storage device of the terminal device 500. The memory 501 is used to store an operating system, application programs, a boot loader, data and other programs, for example, program codes of computer programs, etc. The memory 501 can also be used to temporarily store data that has been output or will be output.

[0100] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program. The computer program is executed by the processor 502 to implement the steps in the above-mentioned various method embodiments.

[0101] The embodiments of the present application provide a computer program product. When the computer program product is run on a terminal device, the terminal device is enabled to implement the steps in the above-mentioned various method embodiments.

[0102] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods through a computer program to instruct the relevant hardware to complete, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by the processor 502, the steps of the above-mentioned various method embodiments can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms. The computer readable storage medium at least includes any entity or device capable of carrying the computer program code to the apparatus / terminal device, recording medium, computer memory, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), electrical carrier signal, telecommunication signal, and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc.

[0103] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0104] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0105] In the embodiments provided in the present application, it should be understood that the disclosed apparatus / terminal device and method can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are only schematic, and the division of the modules or units is only a logical function division, and there can be another division in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0106] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0107] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. An instruction processing method, characterized in that, include: Obtain instruction information of the instruction set to be processed in the processor, wherein the instruction information includes the original valid vector corresponding to the instruction set to be processed, and the opcode of each input instruction in the instruction set to be processed, and each element in the original valid vector is used to represent the validity of each input instruction. Based on the original valid vector, an index vector corresponding to the instruction set to be processed is generated, and each index value in the index vector is used to represent the initial arrangement position of each input instruction. Each index value in the index vector is converted into a one-hot code to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. Based on the original valid vector and the one-hot code matrix, the opcodes of each input instruction are sorted to obtain processed opcode information, so that the processor can execute the corresponding operation based on the processed opcode information.

2. The instruction processing method as described in claim 1, characterized in that, The processed opcode information includes: the target opcode vector and the target valid vector; The step of sorting the opcodes of each input instruction based on the original valid vector and the one-hot code matrix to obtain processed opcode information includes: Based on the valid elements in the original valid vector and each column vector in the one-hot code matrix, a target opcode vector corresponding to the instruction set to be processed is generated. The target opcode vector is used to represent the opcode of each input instruction arranged consecutively in the execution order. Logical operations are performed on each element of the original valid vector and each column vector of the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector. Each element of the target valid vector is used to characterize the validity of the opcode at the corresponding position in the target opcode vector.

3. The instruction processing method as described in claim 2, characterized in that, The step of generating the target opcode vector corresponding to the instruction set to be processed based on the valid elements in the original valid vector and each column vector in the one-hot code matrix includes: For each column vector in the one-hot code matrix, if a valid element is detected in each column vector, the target input instruction corresponding to each column vector is determined according to the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector, and the opcode of the target input instruction is determined as the target opcode corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no valid element in each column vector, then the no-operation instruction is used to determine the target input instruction corresponding to each column vector, and the opcode of the no-operation instruction is used to determine the target opcode corresponding to each column vector. Based on the target opcodes corresponding to the multiple column vectors, a target opcode vector corresponding to the instruction set to be processed is generated.

4. The instruction processing method as described in claim 2, characterized in that, The step of performing logical operations on each element of the original valid vector and each column vector of the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector includes: For each column vector in the one-hot code matrix, perform a logical AND operation between each element in each column vector and each element in the original valid vector to obtain the first operation result corresponding to each column vector; For each column vector in the one-hot code matrix, perform a logical OR operation on each of the first operation results corresponding to each column vector to obtain the second operation result corresponding to each column vector; Based on the second operation results corresponding to the multiple column vectors, a target effective vector corresponding to the instruction set to be processed is generated.

5. The instruction processing method according to any one of claims 1-4, characterized in that, The step of generating the index vector corresponding to the instruction set to be processed based on the original valid vector includes: For each element in the original valid vector, count the number of valid elements among all elements preceding each element to obtain the index value of the input instruction corresponding to each element; Based on the index values ​​of the input instructions corresponding to the multiple elements, an index vector corresponding to the instruction set to be processed is generated.

6. The instruction processing method according to any one of claims 1-4, characterized in that, The step of performing one-hot code transformation on each index value in the index vector to generate the one-hot code matrix corresponding to the instruction set to be processed includes: Each index value in the index vector is used to shift the set binary value to the left to obtain the one-hot code vector corresponding to each index value. Based on the one-hot code vectors corresponding to the multiple index values, a one-hot code matrix corresponding to the instruction set to be processed is generated.

7. The instruction processing method as described in claim 6, characterized in that, The bit width of the set binary value is equal to the number of input instructions in the instruction set to be processed.

8. An instruction processing apparatus, characterized in that, include: The acquisition module is used to acquire instruction information of the instruction set to be processed in the processor. The instruction information includes the original valid vector corresponding to the instruction set to be processed and the opcode of each input instruction in the instruction set to be processed. Each element in the original valid vector is used to represent the validity of each input instruction. The first generation module is used to generate an index vector corresponding to the instruction set to be processed based on the original valid vector, wherein each index value in the index vector is used to characterize the initial arrangement position of each input instruction. The second generation module is used to perform one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. The processing module is used to sort the opcodes of each input instruction according to the original valid vector and the one-hot code matrix to obtain processed opcode information, so that the processor can perform the corresponding operation based on the processed opcode information.

9. A terminal device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it causes the terminal device to implement the method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the computer program product is run on a terminal device, it causes the terminal device to perform the method as described in any one of claims 1-7.

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