Data processor, data processing device, electronic device and data processing method

Abstract

This disclosure provides a data processor, relating to the field of computer technology, and more particularly to the field of chip technology and processor technology. The processor includes: an instruction fetch unit configured to fetch a plurality of instructions to be processed; and a decoding unit configured to: determine at least one operand for each of the plurality of instructions to be processed; in response to determining that there is a target instruction among the plurality of instructions to be processed whose operands have a bit width of a first preset bit width, split the operands of the target instruction to be processed into at least two target sub-operands; and transmit at least two target sub-operands using at least two data channels, wherein the bit width of the target sub-operands is a second preset bit width, and the first preset bit width is at least twice the second preset bit width. This disclosure also provides a data processing apparatus, method, electronic device, and storage medium.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of chip technology and processor technology. More specifically, this disclosure provides a data processor, a data processing apparatus, an electronic device, a data processing method, and a storage medium. Background Technology

[0002] With the development of computer technology and artificial intelligence technology, artificial intelligence chips can support 64-bit operands or 32-bit operands. Summary of the Invention

[0003] This disclosure provides a data processor, a data processing apparatus, an electronic device, a data processing method, and a storage medium.

[0004] According to one aspect of this disclosure, a data processor is provided, the processor comprising: an instruction fetch unit configured to fetch a plurality of instructions to be processed; and a decoding unit configured to: determine at least one operand for each of the plurality of instructions to be processed; in response to determining that there is a target instruction to be processed among the plurality of instructions to be processed whose operand has a bit width of a first preset bit width, splitting the operand of the target instruction to be processed into at least two target sub-operands; and transmitting at least two target sub-operands respectively using at least two data channels, wherein the bit width of the target sub-operands is a second preset bit width, and the first preset bit width is at least twice the second preset bit width.

[0005] According to another aspect of this disclosure, a data processing apparatus is provided, including the data processor provided in this disclosure.

[0006] According to another aspect of this disclosure, an electronic device is provided, including the data processing apparatus provided in this disclosure.

[0007] According to another aspect of this disclosure, a data processing method is provided, the method comprising: determining at least one operand of each of a plurality of instructions to be processed; in response to determining that there is a target instruction to be processed among the plurality of instructions to be processed whose operand has a bit width of a first preset bit width, splitting the operand of the target instruction to be processed into at least two target sub-operands; and transmitting at least two target sub-operands respectively using at least two data channels, wherein the bit width of the target sub-operands is a second preset bit width, and the first preset bit width is at least twice the second preset bit width.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method provided according to this disclosure.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform the methods provided according to this disclosure.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method provided according to this disclosure.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0013] Figure 1 This is a schematic block diagram of a data processor according to an embodiment of the present disclosure;

[0014] Figure 2 This is a schematic diagram of a processor in the current launch cycle according to an embodiment of the present disclosure;

[0015] Figure 3A This is a schematic diagram of a data processor according to another embodiment of the present disclosure during the current launch cycle;

[0016] Figure 3B This is a schematic diagram of a data processor in a subsequent transmission cycle of the current transmission cycle according to another embodiment of the present disclosure;

[0017] Figure 4 This is a schematic diagram of a data processor according to an embodiment of the present disclosure;

[0018] Figure 5 This is a schematic block diagram of a data processing apparatus according to an embodiment of the present disclosure;

[0019] Figure 6 This is a schematic block diagram of an electronic device according to an embodiment of the present disclosure;

[0020] Figure 7 This is a flowchart of a data processing method according to an embodiment of the present disclosure; and

[0021] Figure 8 This is a block diagram of an electronic device to which a data processing method can be applied, according to an embodiment of the present disclosure. Detailed Implementation

[0022] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0023] In artificial intelligence scenarios, instructions corresponding to 64-bit operands can be scalar instructions. These instructions are relatively few in number. Instructions related to artificial intelligence scenarios typically have 32-bit operands.

[0024] In some embodiments, to execute instructions corresponding to 64-bit operands, the processor's data channel can be expanded to 64 bits. Two 32-bit operands are read from two consecutive registers based on the register number associated with the instruction. These two 32-bit operands are then concatenated to form a 64-bit operand. This 64-bit operand can then be issued to a reservation station using the 64-bit data channel. In multi-issue scenarios, multiple data channels operate independently. The reservation station's entry can be 192 bits. However, with a 64-bit data channel, the chip area overhead is significant. Furthermore, in artificial intelligence scenarios, the number of instructions corresponding to 64-bit operands is relatively small, while the number of instructions corresponding to 32-bit operands is large, resulting in lower benefits from expanding the data channel to 64 bits.

[0025] Based on this, this disclosure provides a data processor, which will be described below.

[0026] Figure 1 This is a schematic block diagram of a data processor according to an embodiment of the present disclosure.

[0027] like Figure 1 As shown, the processor 100 may include an instruction fetch unit 110 and a decoding unit 120.

[0028] The instruction fetch unit 110 can be configured to fetch multiple instructions to be processed. For example, the multiple instructions to be processed may include a first instruction to be processed and a second instruction to be processed.

[0029] The decoding unit 120 can be configured to determine at least one operand for each of a plurality of instructions to be processed. For example, it can determine at least one operand for a first instruction to be processed, or it can determine at least one operand for a second instruction to be processed.

[0030] The decoding unit 120 can also be configured to: in response to determining that among a plurality of pending instructions there exists a target pending instruction with an operand bit width of a first preset bit width, split the operand of the target pending instruction into at least two target sub-operands. In this embodiment of the present disclosure, the bit width of the target sub-operand is a second preset bit width. The first preset bit width can be at least twice the second preset bit width. For example, the first preset bit width can be 64 bits. The second preset bit width can be 32 bits. Taking the example that the bit width of the operand of the first pending instruction is 64 bits and the bit width of the operand of the second pending instruction is 32 bits, the operand of the first pending instruction can be split into two target sub-operands. The bit width of the target sub-operands can be 32 bits.

[0031] The decoding unit 120 can also be configured to transmit at least two target suboperands using at least two data channels respectively. In this embodiment, the bit width of the data channel can be a second preset bit width. For example, the bit width of the data channel can be 32 bits. Two target suboperands can be transmitted using two data channels.

[0032] Through the embodiments of this disclosure, when the operand bit width is a first preset bit width, the target suboperand of the operand can be transmitted using multiple data channels. Therefore, when the data channel bit width is 32 bits, the processor can support instructions with an operand bit width of 64 bits. Compared to a processor that only supports operand bit widths of 32 bits, the increase in processor pipeline area is smaller, reducing processor area overhead. Furthermore, it can efficiently process a large number of instructions with operand bit widths of 32 bits, and also efficiently process instructions with operand bit widths of 64 bits, expanding the processor's application scenarios.

[0033] As can be understood, the processor disclosed herein has been described in detail above, and the following will further explain the various instructions to be processed in this disclosure.

[0034] In some embodiments, among multiple pending instructions in multiple current transmit cycles, there are K subsequent pending instructions with transmit priority lower than the target pending instruction, and M target suboperands. For example, K can be an integer greater than or equal to 0. M can be an integer greater than or equal to 2.

[0035] In this embodiment of the disclosure, K can be greater than or equal to M-1, which will be discussed below. Figure 2 Further explanation is needed.

[0036] Figure 2 This is a schematic diagram of a processor in the current launch cycle according to an embodiment of the present disclosure.

[0037] like Figure 2As shown, the processor 200 may include an instruction fetch unit 210, a decoding unit 220, a reservation station 230, and an execution unit 240.

[0038] In some embodiments, the instruction fetch unit 210 may be configured to fetch a plurality of instructions to be processed. For example, the plurality of instructions to be processed may include instructions to be processed instr20 and instructions to be processed instr21. In the current transmit cycle, the transmit priority of instructions to be processed instr20 may be higher than the transmit priority of instructions to be processed instr21.

[0039] In some embodiments, the decoding unit 220 may be configured to determine at least one operand for each of a plurality of instructions to be processed. For example, the decoding unit 220 may include decoder 221 and decoder 222. Based on the instruction to be processed instr20, decoder 221 may determine an operand R201 of the instruction to be processed instr20 from register file 201. Based on the instruction to be processed instr21, decoder 222 may determine an operand R211 of the instruction to be processed instr21 from register file 201.

[0040] In some embodiments, the decoding unit 220 may further be configured to: in response to determining that there is a target instruction to be processed among a plurality of instructions to be processed with an operand having a bit width of a first preset bit width, split the operand of the target instruction to be processed into at least two target sub-operands. For example, the bit width of the operand R211 of the instruction to be processed, instr21, may be 32 bits. If the decoding unit 220 determines that the bit width of the operand R201 is 64 bits, the instruction to be processed, instr20, can be taken as the target instruction to be processed. The operand R201 of the instruction to be processed, instr20, can be split into two target sub-operands, namely target sub-operand R2010 and target sub-operand R2011. The bit width of each of the target sub-operands, R2010 and R2011, is 32 bits. That is, in this embodiment, M = 2. Next, taking K = 1 as an example, some methods of the processor of this disclosure transmitting at least two target sub-operands using at least two data channels will be further described. It can be understood that when K = 1, K = M - 1.

[0041] In this embodiment, the decoding unit 220 can also be configured to block M-1 operands of subsequent pending instructions during the current transmit cycle. For example, the pending instruction instr21 can be a subsequent pending instruction with a lower transmit priority than the pending instruction instr20. During the current transmit cycle, a stall signal can be generated to block the transmission of operand R211. By blocking the transmission of operands of subsequent pending instructions in this embodiment, the target sub-operand can be transmitted using the data channel corresponding to the subsequent pending instructions, enabling the processor to support operands with an operand width of 64 bits.

[0042] In this embodiment of the disclosure, the decoding unit 220 can also be configured to: transmit M target sub-operands in the current transmission cycle using the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to the M-1 subsequent instructions to be processed. For example, the target sub-operand R2010 can be transmitted using the data channel corresponding to the instruction to be processed instr20, or the target sub-operand R2011 can be transmitted using the data channel corresponding to the instruction to be processed instr21. The data channel corresponding to the instruction to be processed instr20 can be used as the target data channel.

[0043] In some embodiments, the retention station 230 may include a target buffer. The target buffer may be configured to receive at least two target suboperands. Based on the at least two target suboperands, an operand for a target instruction to be processed is obtained. The operand for the target instruction to be processed is then emitted. For example, the retention station 230 may include multiple buffers. A first buffer among the multiple buffers may serve as the target buffer. The first buffer may be configured to receive target suboperands R2010 and R2011. Based on target suboperands R2010 and R2011, the operand for the instruction to be processed, instr20, can be concatenated. This operand can then be emitted. Through these embodiments, the retention station can receive target suboperands and concatenate at least two target suboperands into the operand for the target instruction to be processed, effectively and accurately storing the instruction's operand, thus helping to improve the processor's accuracy.

[0044] In this embodiment of the disclosure, the sum of the first preset bit width and the second preset bit width is consistent with the capacity of the target buffer. For example, as described above, the first preset bit width is 64 bits, and the second preset bit width is 32 bits. The sum of the first preset bit width and the second preset bit width can be 96 bits. The capacity of the first buffer can be consistent with this sum of bit widths, which is 96 bits.

[0045] In some embodiments, execution unit 240 may be configured to receive an operand of a target instruction to be processed. For example, execution unit 240 may receive an operand of an instruction instr20 to be processed from reservation station 230.

[0046] In some embodiments, the execution unit 240 may also be configured to perform an operation corresponding to the operand of the target instruction to be processed. For example, the execution unit 240 may perform an operation corresponding to the operand of the instruction to be processed, instr20, in order to obtain the write-back data corresponding to the operand of the instruction to be processed, instr20.

[0047] It is understood that the processor disclosed herein has been described above in conjunction with the current launch cycle, and the processor disclosed herein will be described below in conjunction with the subsequent launch cycles of the current launch cycle.

[0048] In this embodiment of the disclosure, the decoding unit 220 can also be configured to: transmit M-1 operands of subsequent instructions to be processed in a subsequent transmission cycle of the current transmission cycle. For example, in a subsequent transmission cycle of the current transmission cycle, the operand R211 of the instruction to be processed, instr21, can be transmitted using the data channel corresponding to the instruction to be processed, instr21. Through this embodiment of the disclosure, the processor is suitable for processing operands of various bit widths.

[0049] In this embodiment of the disclosure, the multiple buffers of the reservation station 230 may further include a second buffer. The second buffer may be configured to receive the operand R211 of the instruction to be processed, instr21.

[0050] In this embodiment of the disclosure, the execution unit 240 can perform an operation corresponding to the operand R211 of the instruction to be processed instr21 in order to obtain the data to be written back corresponding to the operand R211 of the instruction to be processed instr21.

[0051] It is understood that the above description of the processor of this disclosure uses K being greater than or equal to M-1 as an example. However, this disclosure is not limited to this; K may be less than M-1, as will be explained below.

[0052] Figure 3A This is a schematic diagram of a data processor in the current launch cycle according to an embodiment of the present disclosure.

[0053] like Figure 3A As shown, the processor 300 may include an instruction fetch unit 310, a decoding unit 320, a reservation station 330, and an execution unit 340.

[0054] In some embodiments, the instruction fetch unit 310 may be configured to fetch a plurality of instructions to be processed. For example, the plurality of instructions to be processed may include instructions to be processed instr32 and instructions to be processed instr33. In the current transmit cycle, the transmit priority of instructions to be processed instr32 may be higher than the transmit priority of instructions to be processed instr33.

[0055] In some embodiments, the decoding unit 320 may be configured to determine at least one operand for each of a plurality of instructions to be processed. For example, the decoding unit 320 may include decoder 321 and decoder 322. Based on the instruction to be processed instr32, decoder 321 may determine an operand R321 of the instruction to be processed instr32 from register file 301. Based on the instruction to be processed instr32, decoder 322 may determine an operand R331 of the instruction to be processed instr32 from register file 301.

[0056] In some embodiments, the decoding unit 320 may further be configured to: in response to determining that there is a target instruction to be processed among a plurality of instructions to be processed with an operand having a bit width of a first preset bit width, split the operand of the target instruction to be processed into at least two target sub-operands. For example, the bit width of the operand of the instruction to be processed, instr32, may be 32 bits. If the decoding unit 320 determines that the bit width of the operand R331 of the instruction to be processed, instr33, is 64 bits, the instruction to be processed, instr33, may be taken as the target instruction to be processed. The operand R331 of the instruction to be processed, instr33, may be split into two target sub-operands, namely target sub-operand R3310 and target sub-operand R3311. The bit width of each of the target sub-operands, R3310 and R3311, is 32 bits. That is, in this embodiment, M = 2. Next, taking K = 0 as an example, some methods of the processor of this disclosure transmitting at least two target sub-operands using at least two data channels will be further described. It can be understood that when K = 0, K is less than M-1.

[0057] In this embodiment of the disclosure, the decoding unit 320 can also be configured as an operand for transmitting a preceding instruction to be processed. For example, the instruction to be processed, instr32, can be transmitted as a preceding instruction to be processed with a higher priority than the instruction to be processed, instr33. In the current transmission cycle, the operand R321 of the instruction to be processed, instr32, can be transmitted.

[0058] In this embodiment of the disclosure, the holding station 330 may include multiple buffers. A third buffer among the multiple buffers may be configured to receive the operand R321 of the pending instruction instr32. Next, the operand R321 of the pending instruction instr32 may be issued.

[0059] In this embodiment of the disclosure, the execution unit 340 may be configured to: receive the operand R321 of the instruction to be processed instr32, and perform the operation corresponding to the operand R321 of the instruction to be processed instr32, so as to obtain the data to be written back corresponding to the operand R321.

[0060] It is understood that the processor disclosed herein has been described above in conjunction with the current launch cycle, and the processor disclosed herein will be described below in conjunction with the subsequent launch cycles of the current launch cycle.

[0061] Figure 3B This is a schematic diagram of a data processor in a subsequent transmission cycle of the current transmission cycle according to an embodiment of the present disclosure.

[0062] In this embodiment, the decoding unit 320 can also be configured to: in a later transmission cycle of the current transmission cycle, utilize the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to the M-1 preceding instructions to be processed to transmit M target suboperands respectively. The transmission priority of any preceding instruction to be processed is higher than that of the target instruction to be processed. For example, the target suboperand R3310 can be transmitted using the data channel corresponding to the instruction to be processed instr32, or the target suboperand R3311 can be transmitted using the data channel corresponding to the instruction to be processed instr33. The data channel corresponding to the instruction to be processed instr33 can be used as the target data channel. Through this embodiment, the preceding instructions to be processed can block the transmission of the operands of the target instruction to be processed, and the target suboperands can be transmitted using the data channels corresponding to the preceding instructions to be processed, enabling the processor to support operands with an operand width of 64 bits.

[0063] In some embodiments, the holding station 330 may include a target buffer. The target buffer may be configured to receive at least two target suboperands. Based on the at least two target suboperands, the operand of the target instruction to be processed is obtained. The operand of the target instruction to be processed is then emitted. For example, as described above, the holding station 330 may include multiple buffers. A fourth buffer among the multiple buffers may serve as the target buffer. The fourth buffer may be configured to receive target suboperands R3310 and R3311. Based on target suboperands R3310 and R3311, the operand of the instruction to be processed, instr33, can be concatenated. This operand can then be emitted.

[0064] In this embodiment, the sum of the first preset bit width and the second preset bit width is consistent with the capacity of the target buffer. For example, as described above, the first preset bit width is 64 bits, and the second preset bit width is 32 bits. The sum of the first preset bit width and the second preset bit width can be 96 bits. The capacity of the fourth buffer can be consistent with this sum of bit widths, which is 96 bits.

[0065] In some embodiments, the execution unit 340 may be configured to receive the operand of the target instruction to be processed. For example, the execution unit 340 may receive the operand of the instruction instr33 to be processed.

[0066] In some embodiments, the execution unit 340 may also be configured to perform an operation corresponding to the operand of the target instruction to be processed. For example, the execution unit 340 may perform an operation corresponding to the operand of the instruction to be processed, instr33, in order to obtain the write-back data corresponding to the operand of the instruction to be processed, instr33.

[0067] It is understandable that, given that the buffer capacity is the same as the sum of the bit widths mentioned above, the buffer can store one operand with a bit width of the first preset bit width. Therefore, the decoding unit can also be configured to: determine whether an operand with a bit width of the first preset bit width exists in the target buffer. This will be further explained below.

[0068] In this embodiment, the decoding unit can further be configured to block the decoding of the target instruction to be processed in response to determining that an operand with a bit width of a first preset bit width exists in the target buffer. For example, the decoding unit can determine the bit width of the operand of the instruction to be processed. If the bit width of the operand is determined to be the first preset bit width and a preceding operand with a bit width of the first preset bit width exists in the target buffer, the decoding of the instruction to be processed can be blocked to postpone the determination of the value of the operand of the instruction to be processed. Through this embodiment, the determined operand can be issued in a timely manner, the buffer of the reserved station can be fully utilized, and the processor performance can be improved.

[0069] In this embodiment of the disclosure, the decoding unit may further be configured to: determine the operand of the target instruction to be processed in response to the issuance of an operand with a bit width of a first preset bit width in the target buffer. For example, after the preceding operand with a bit width of the first preset bit width is issued to the execution unit, the target instruction to be processed can be decoded to obtain the operand of the target instruction to be processed.

[0070] It is understood that the above describes the execution method related to the instruction to be processed. However, this disclosure is not limited to this. The processor may also include a write-back unit. After the execution unit performs the operation related to the operand, it can obtain the data to be written back. The write-back unit can write back the data to be written back. The write-back unit will be described below.

[0071] In this embodiment, the write-back unit can be configured to: determine at least two write-back sub-data based on the write-back data corresponding to the operand of the target instruction to be processed. The bit width of the write-back sub-data is a second preset bit width. For example, if the bit width of the operand of the target instruction to be processed is 64 bits, the bit width of the corresponding write-back data can also be 64 bits. The write-back data can be split into two write-back sub-data. The bit width of the write-back sub-data can be 32 bits.

[0072] In this embodiment, the write-back unit can be further configured to write back at least two sub-data items to be written back in at least two write-back cycles. For example, the first sub-data item to be written back can be written back in the current write-back cycle. In a subsequent write-back cycle, the second sub-data item to be written back can be written back. Through this embodiment, the bit width of the read and write ports of the register file can both be 32 bits, which can effectively improve the performance of the processor.

[0073] It is understood that the above description of the processor of this disclosure uses a target instruction for processing in which the bit width of the operands among multiple instructions to be processed is a first preset bit width. However, this disclosure is not limited to this; the bit width of the operands of any instruction to be processed can be a second preset bit width, as will be further explained below.

[0074] Figure 4 This is a schematic diagram of a data processor according to an embodiment of the present disclosure.

[0075] like Figure 4 As shown, the processor 400 may include an instruction fetch unit 410, a decoding unit 420, a reservation station 430, and an execution unit 440.

[0076] In some embodiments, the instruction fetch unit 410 may be configured to fetch a plurality of instructions to be processed. For example, the plurality of instructions to be processed may include instructions to be processed instr44 ​​and instructions to be processed instr45. In the current transmit cycle, the transmit priority of instructions to be processed instr44 ​​may be higher than the transmit priority of instructions to be processed instr45.

[0077] In some embodiments, the decoding unit 420 may be configured to determine at least one operand for each of a plurality of instructions to be processed. For example, the decoding unit 420 may include decoder 421 and decoder 422. Based on the instruction to be processed instr44, decoder 421 may determine an operand R441 of the instruction to be processed instr44 ​​from register file 401. Based on the instruction to be processed instr45, decoder 422 may determine an operand R451 of the instruction to be processed instr45 from register file 401.

[0078] In some embodiments, the decoding unit 420 may further be configured to: in response to determining that the bit width of the operand of any instruction to be processed is a second preset bit width, transmit multiple operands of the instructions to be processed using multiple data channels in the current transmission cycle. For example, the bit width of the operand R441 of the instruction to be processed, instr44, may be 32 bits. The bit width of the operand R451 of the instruction to be processed, instr45, may also be 32 bits. The operand R441 may be transmitted using the data channel corresponding to the instruction to be processed, instr44, or the operand R451 may be transmitted using the data channel corresponding to the instruction to be processed, instr45.

[0079] In some embodiments, the holding station 430 may include multiple buffers. The multiple buffers may be configured to: receive operands of multiple pending instructions respectively; and transmit operands of the multiple pending instructions respectively. For example, the multiple buffers may include a fifth buffer and a sixth buffer. The fifth buffer may be configured to receive operand R441. The sixth buffer may be configured to receive operand R451. Operands R441 and R451 may then be transmitted respectively.

[0080] In some embodiments, the execution unit 440 may be configured to: receive operands for each of a plurality of pending instructions, and execute operations corresponding to the operations of the plurality of pending instructions. For example, the execution unit 440 may receive operands R441 and R451 from the reservation station 430. The execution unit 440 may execute the operation corresponding to operand R441 to obtain the write-back data corresponding to operation S441. The execution unit 440 may execute the operation corresponding to operand R451 to obtain the write-back data corresponding to operation S451.

[0081] In some embodiments, the write-back unit can write back the data to be written back corresponding to operation S441, or it can write back the data to be written back corresponding to operation S451.

[0082] It is understood that the processor of this disclosure has been described above using two instructions to be processed as an example. In the embodiments of this disclosure, the processor can process more than two instructions simultaneously, and this disclosure does not impose any limitation on this.

[0083] It is understood that the above description uses a first preset bit width of 64 bits and a second preset bit width of 32 bits as examples to illustrate this disclosure. However, this disclosure is not limited to this; the first preset bit width can also be 96 bits, 128 bits, etc., and the second preset bit width can also be 16 bits.

[0084] It is understood that the processor of this disclosure has been described above, and the processing apparatus including the processor will be described below.

[0085] Figure 5 This is a schematic block diagram of a data processing apparatus according to an embodiment of the present disclosure.

[0086] like Figure 5 As shown, the data processing device 50 may include a data processor 500. The data processor 500 may be, for example, a processor 100.

[0087] It is understood that the processing apparatus of this disclosure has been described above, and the equipment including the processing apparatus will be described below.

[0088] Figure 6 This is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0089] like Figure 6 As shown, electronic device 6000 may include data processing device 60. Data processing device 60 may be, for example, data processing device 50.

[0090] It is understood that the above has described the electronic device of this disclosure, and the data processing method of this disclosure will be described below.

[0091] Figure 7 This is a flowchart of a data processing method according to an embodiment of the present disclosure.

[0092] like Figure 7 As shown, the method 700 may include operations S710 to S730.

[0093] In operation S710, at least one operand for each of a plurality of instructions to be processed is determined.

[0094] In operation S720, in response to determining that there is a target instruction to be processed among a plurality of instructions to be processed whose operand bit width is a first preset bit width, the operand of the target instruction to be processed is split into at least two target sub-operands.

[0095] In operation S730, at least two target suboperands are transmitted using at least two data channels respectively. In this embodiment of the disclosure, the bit width of the target suboperand is a second preset bit width, and the first preset bit width is at least twice the second preset bit width.

[0096] It is understandable that the processor 100 described above can be used to execute method 700.

[0097] In some embodiments, among the multiple pending instructions in the current transmission cycle, there are K pending instructions with a transmission priority lower than the target pending instruction, and M target suboperands, where M is an integer greater than or equal to 2 and K is an integer greater than or equal to 0.

[0098] In some embodiments, transmitting at least two target suboperands using at least two data channels includes: blocking M-1 operands of subsequent pending instructions in the current transmission cycle when K is greater than or equal to M-1. M target suboperands are transmitted in the current transmission cycle using the target data channel corresponding to the target pending instruction and the M-1 data channels corresponding to the M-1 subsequent pending instructions.

[0099] In some embodiments, transmitting at least two target suboperands using at least two data channels further includes: transmitting M-1 operands of subsequent pending instructions in a subsequent transmission cycle of the current transmission cycle.

[0100] In some embodiments, K = 1, M = 2.

[0101] In some embodiments, transmitting at least two target suboperands using at least two data channels includes: when K is less than M-1, in a later transmission cycle of the current transmission cycle, transmitting M target suboperands using the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to M-1 preceding instructions to be processed, wherein the transmission priority of any preceding instruction to be processed is higher than that of the target instruction to be processed.

[0102] In some embodiments, transmitting at least two target suboperands using at least two data channels further includes: transmitting the operand of the preceding pending instruction in the current transmission cycle.

[0103] In some embodiments, K = 0, M = 2.

[0104] In some embodiments, the first preset bit width is 64 bits and the second preset bit width is 32 bits.

[0105] In some embodiments, method 700 may further include: receiving at least two target suboperands using a target buffer at a reservation station; obtaining the operands of a target instruction to be processed based on the at least two target suboperands; and transmitting the operands of the target instruction to be processed using a reservation station. For example, the sum of the bit widths of a first preset bit width and a second preset bit width is consistent with the capacity of the target buffer.

[0106] In some embodiments, determining at least one operand of each of a plurality of instructions to be processed includes: determining the operand of a target instruction to be processed in response to the emission of an operand in a target buffer having a bit width of a first preset bit width.

[0107] In some embodiments, method 700 may further include: receiving an operand of a target instruction to be processed from a reserved station using an execution unit; and performing an operation corresponding to the operand of the target instruction to be processed using the execution unit.

[0108] In some embodiments, method 700 may further include: determining at least two write-back sub-data based on the write-back data corresponding to the operand of the target instruction to be processed. Writing back the at least two write-back sub-data in at least two write-back cycles. For example, the bit width of the write-back sub-data is a second preset bit width.

[0109] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0110] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0111] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0112] like Figure 8 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0113] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0114] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform data processing methods by any other suitable means (e.g., by means of firmware).

[0115] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0116] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0117] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0118] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) monitor or an LCD (liquid crystal display)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0119] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0120] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data processor, comprising: The instruction fetch unit is configured to read multiple instructions to be processed. The decoding unit is configured as follows: Determine at least one operand for each of the plurality of instructions to be processed; In response to determining that among the multiple instructions to be processed there is a target instruction whose operand has a bit width of a first preset bit width, the operand of the target instruction to be processed is split into M target sub-operands; as well as M target sub-operands are transmitted using M data channels, wherein the bit width of each target sub-operand is a second preset bit width, and the first preset bit width is M times the second preset bit width. Among the multiple pending instructions in the current launch cycle, there are K pending instructions with a launch priority lower than the target pending instruction, where M is an integer greater than or equal to 2 and K is an integer greater than or equal to 0.

2. The processor according to claim 1, wherein, The decoding unit is also configured to: If K is greater than or equal to M-1, block M-1 operands of the subsequent pending instructions in the current transmit cycle; and Using the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to the M-1 subsequent instructions to be processed, M target suboperands are transmitted respectively in the current transmission cycle.

3. The processor according to claim 2, wherein, The decoding unit is also configured to: In the subsequent transmission cycle of the current transmission cycle, M-1 operands of the subsequent pending instructions are transmitted.

4. The processor according to claim 2 or 3, wherein, K=1, M=2.

5. The processor according to claim 1, wherein, The decoding unit is configured as follows: When K is less than M-1, in the subsequent transmission cycle of the current transmission cycle, M target suboperands are transmitted using the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to the M-1 preceding instructions to be processed, respectively, wherein the transmission priority of any preceding instruction to be processed is higher than that of the target instruction to be processed.

6. The processor according to claim 4, wherein, The decoding unit is further configured to: In the current launch cycle, the operands of the preceding pending instructions are launched.

7. The processor according to claim 5 or 6, wherein, K=0, M=2.

8. The processor according to claim 1, wherein, The first preset bit width is 64 bits, and the second preset bit width is 32 bits.

9. The processor according to claim 1, further comprising: The reserved station includes a target buffer, which is configured as follows: Receive M of the target suboperands; Based on the M target sub-operands, the operands of the target instruction to be processed are obtained; as well as The operand for transmitting the target instruction to be processed, wherein the sum of the bit widths of the first preset bit width and the second preset bit width is consistent with the capacity of the target buffer.

10. The processor according to claim 9, wherein, The decoding unit is further configured to: In response to the issuance of an operand with a first preset bit width in the target buffer, the operand of the target instruction to be processed is determined.

11. The processor according to claim 9, further comprising: The execution unit is configured as follows: The operand for receiving the target instruction to be processed; as well as Perform the operation corresponding to the operand of the target instruction to be processed.

12. The processor according to claim 1, further comprising: The write-back unit is configured as follows: Based on the write-back data corresponding to the operands of the target instruction to be processed, determine M write-back sub-data; as well as In M write-back cycles, M sub-data to be written back are written back respectively, wherein the bit width of the sub-data to be written back is the second preset bit width.

13. A data processing apparatus comprising a data processor according to any one of claims 1 to 12.

14. An electronic device comprising the data processing apparatus according to claim 13.

15. A data processing method, comprising: Determine at least one operand for each of the multiple instructions to be processed; In response to determining that among the multiple instructions to be processed there is a target instruction whose operand has a bit width of a first preset bit width, the operand of the target instruction to be processed is split into M target sub-operands; as well as M target sub-operands are transmitted using M data channels, wherein the bit width of each target sub-operand is a second preset bit width, and the first preset bit width is M times the second preset bit width. Among the multiple pending instructions in the current launch cycle, there are K pending instructions with a launch priority lower than the target pending instruction, where M is an integer greater than or equal to 2 and K is an integer greater than or equal to 0.

16. The method according to claim 15, wherein, The step of transmitting M target suboperands using M data channels respectively includes: If K is greater than or equal to M-1, block M-1 operands of the subsequent pending instructions in the current transmit cycle; and Using the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to the M-1 subsequent instructions to be processed, M target suboperands are transmitted respectively in the current transmission cycle.

17. The method according to claim 16, wherein, The step of transmitting M target suboperands using M data channels respectively also includes: In the subsequent transmission cycle of the current transmission cycle, M-1 operands of the subsequent pending instructions are transmitted.

18. The method according to claim 16 or 17, wherein, K=1, M=2.

19. The method according to claim 15, wherein, The step of transmitting M target suboperands using M data channels respectively includes: When K is less than M-1, in the subsequent transmission cycle of the current transmission cycle, M target suboperands are transmitted using the target data channel corresponding to the target instruction to be processed and the M-1 data channels corresponding to the M-1 preceding instructions to be processed, respectively, wherein the transmission priority of any preceding instruction to be processed is higher than that of the target instruction to be processed.

20. The method according to claim 19, wherein, The step of transmitting M target suboperands using M data channels respectively also includes: In the current transmission cycle, the operand of the preceding pending instruction is transmitted.

21. The method according to claim 19 or 20, wherein, K=0, M=2.

22. The method according to claim 15, wherein, The first preset bit width is 64 bits, and the second preset bit width is 32 bits.

23. The method of claim 15, further comprising: The target suboperands are received using the target buffer of the reserved station; Based on the M target sub-operands, the operands of the target instruction to be processed are obtained; as well as The operands of the target instruction to be processed are transmitted using the reserved station, wherein the sum of the bit widths of the first preset bit width and the second preset bit width is consistent with the capacity of the target buffer.

24. The method according to claim 23, wherein, Determining at least one operand for each of the plurality of instructions to be processed includes: In response to the issuance of an operand with a first preset bit width in the target buffer, the operand of the target instruction to be processed is determined.

25. The method of claim 23, further comprising: The execution unit receives operands of the target instruction to be processed from the reserved station; as well as The execution unit performs the operation corresponding to the operand of the target instruction to be processed.

26. The method of claim 15, further comprising: Based on the write-back data corresponding to the operands of the target instruction to be processed, determine M write-back sub-data; as well as In M write-back cycles, M sub-data to be written back are written back respectively, wherein the bit width of the sub-data to be written back is the second preset bit width.

27. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 15 to 26.

28. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 15 to 26.

29. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 15 to 26.

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