Verification method of instruction scheduler, electronic equipment and storage medium

Abstract

The invention relates to the technical field of artificial intelligence chips, and provides an instruction scheduler verification method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a to-be-tested basic instruction sequence, inserting a delay instruction into the basic instruction sequence, and carrying out the circulation of a plurality of times through a circulation instruction, and generating a target instruction sequence; different delay parameters are configured according to delay instructions of different thread bundles, and are input to a to-be-verified instruction scheduler; in the process of processing the instruction sequence, the instruction streams of different thread bundles are staggered based on the delay parameter and the loop instruction, and a multi-emission instruction staggered combination is generated at the emission end for verification. According to the method, the parameterized delay instruction and the loop execution mechanism are introduced into the basic instruction sequence, so that instruction stream interlacing can be dynamically manufactured, a large number of multi-emission concurrency conflict test scenes can be automatically and accurately generated under the condition that code complexity is not increased, and the test efficiency is improved. The method has the advantages of high verification efficiency, comprehensive scene coverage rate and easy code maintenance.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence chip technology, and in particular to a method for verifying an instruction scheduler, an electronic device, and a storage medium. Background Technology

[0002] In AI chip architectures such as Graphics Processing Units (GPUs) and General-purpose computing on Graphics Processing Units (GPGPUs), the instruction scheduler is the core module responsible for instruction fetching, resource scheduling, and instruction dispatching. It needs to support the parallel scheduling of multiple warps. To ensure the correctness of the chip design, the instruction scheduler usually needs to be verified at the module level. This involves inputting a pre-generated test instruction sequence (also known as a kernel) into the scheduler to check its ability to make correct scheduling decisions when faced with complex combinations of concurrent instructions and resource conflicts.

[0003] Currently, the verification of instruction schedulers mainly adopts two conventional approaches: The first approach is to construct test cases using a direct kernel. This approach triggers the scheduler's scheduling between different warps and execution units by manually writing instruction sequences. However, due to the extremely large number of scenarios involving multiple instruction issuances, manually writing a direct kernel is inefficient and has poor maintainability; furthermore, the execution mode of a direct kernel is too fixed, making it difficult to achieve accurate parallelization of different warp program segments, thus failing to cover complex concurrent scheduling scenarios.

[0004] The second approach uses a Random Test Generator (RTG) to generate a random kernel. This approach achieves scheduling verification between multiple warps by randomly generating instruction sequences. However, the randomly generated instruction sequences contain a large number of redundant and repetitive test cases, making it difficult to accurately cover specific multi-launch conflict scenarios. This results in low verification accuracy, huge machine runtime consumption, and extremely slow test convergence. Summary of the Invention

[0005] This invention provides a method, electronic device, and storage medium for verifying an instruction scheduler, in order to solve the shortcomings of related instruction scheduler verification schemes, such as the low efficiency of manually constructing test cases and the difficulty in covering complex scheduling scenarios, as well as the high redundancy of randomly generated test cases and the difficulty in covering specific multi-issue collision scenarios.

[0006] This invention provides a method for verifying an instruction scheduler, comprising: Obtain the basic instruction sequence to be tested; A delay instruction is inserted into the basic instruction sequence, and a loop instruction is used to loop the sequence containing the delay instruction multiple times to generate the target instruction sequence; In the target instruction sequence, corresponding delay parameters are configured for the delayed instructions executed by different thread bundles, and the target instruction sequence with the configured parameters is input to the instruction scheduler to be verified. During the process of the instruction scheduler processing the target instruction sequence, the instruction streams of different thread bundles are interleaved based on the delay parameter and the loop instruction, so as to generate a multi-issue instruction interleaved combination at the issuing end of the instruction scheduler; The instruction scheduler is verified based on the interleaved combination of the multiple transmit instructions.

[0007] According to the present invention, a method for verifying an instruction scheduler, wherein obtaining the basic instruction sequence to be tested includes: Obtain the instruction set to be tested; The instructions in the instruction set to be tested are classified according to their characteristics to obtain the instruction classification results. The instruction characteristics include at least one of the following: instruction type, number of instruction sources, instruction source supported register type, and destination register type. Based on the instruction classification results, instructions are selected from the set of instructions to be tested and combined to construct the basic instruction sequence.

[0008] According to a verification method for an instruction scheduler provided by the present invention, the step of selecting instructions from the set of instructions to be tested and combining them to construct the basic instruction sequence based on the instruction classification result includes: Based on the instruction classification results, instructions are selected from the set of instructions to be tested and combined to obtain an initial test sequence; The synchronization barrier instruction used to achieve cross-thread bundle synchronization in the initial test sequence is replaced with a pause instruction to obtain the basic instruction sequence.

[0009] According to a verification method for an instruction scheduler provided by the present invention, the step of inserting a delayed instruction into the basic instruction sequence includes: Based on the instruction classification results, a delayed instruction is inserted into the basic instruction sequence every preset number of instructions to divide the basic instruction sequence into multiple instruction segments; The insertion position of the delayed instruction includes at least one of the following: within the same type of instruction block in the basic instruction sequence, or between different types of instruction blocks in the basic instruction sequence.

[0010] According to a verification method for an instruction scheduler provided by the present invention, configuring corresponding delay parameters for the delayed instructions executed by different thread bundles includes: Configure a first delay parameter for the delayed instruction executed by the first thread bundle, and configure a second delay parameter for the delayed instruction executed by the second thread bundle; The delay time of the delay instruction is preset to a dynamically configurable delay parameter, and the first delay parameter is different from the second delay parameter.

[0011] According to a verification method for an instruction scheduler provided by the present invention, during the process of the instruction scheduler processing the target instruction sequence, the instruction streams of different thread bundles are interleaved based on the delay parameter and the loop instruction, so as to generate a multi-issue instruction interleaving combination at the issuing end of the instruction scheduler, comprising: During each iteration of the loop instruction, the difference between the first delay parameter and the second delay parameter causes the first thread bundle and the second thread bundle to accumulate the execution delay difference. When the execution latency difference reaches the interleaving condition, the instruction scheduler will issue the first target instruction in the first thread bundle and the second target instruction in the second thread bundle within the same clock cycle, generating the multi-issue instruction interleaving combination.

[0012] According to the present invention, a verification method for an instruction scheduler is provided, wherein the instruction scheduler is a dual-issue instruction scheduler, and the verification of the instruction scheduler based on the multi-issue instruction interleaving combination includes: Using two consecutive clock cycles as a hardware execution window, the dual-issue instruction scheduler obtains the instruction combination issued within the hardware execution window, the instruction combination including at most two vector instructions and at most two scalar instructions; Resource conflict checks and data dependency checks are performed on the instructions in the instruction combination.

[0013] According to a verification method for an instruction scheduler provided by the present invention, the step of performing resource conflict checks and data dependency checks on the instructions in the instruction combination includes: Check whether there are read / write port conflicts between instructions in the same or different clock cycles within the hardware execution window; Check whether there are any unsatisfied data dependencies among the instruction sequences belonging to the same thread bundle in the instruction combination.

[0014] The present invention also provides a verification device for an instruction scheduler, comprising: The basic sequence acquisition unit is used to acquire the basic instruction sequence to be tested; The target sequence generation unit is used to insert delayed instructions into the basic instruction sequence and use loop instructions to loop the sequence containing the delayed instructions multiple times to generate a target instruction sequence. The delay parameter configuration unit is used to configure corresponding delay parameters for the delayed instructions executed by different thread bundles in the target instruction sequence, and input the target instruction sequence with configured parameters to the instruction scheduler to be verified. The instruction combination generation unit is used to, during the process of the instruction scheduler processing the target instruction sequence, interleave the instruction streams of different thread bundles based on the delay parameter and the loop instruction, so as to generate a multi-issue instruction interleaved combination at the transmitter of the instruction scheduler; The scheduler verification unit is used to verify the instruction scheduler based on the multi-issue instruction interleaving combination.

[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the verification method of the instruction scheduler as described above.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the verification method of the instruction scheduler as described above.

[0017] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the verification method of the instruction scheduler as described above.

[0018] The instruction scheduler verification method, electronic device, and storage medium provided by this invention change the single and fixed execution mode of conventional test instruction sequences by inserting delayed instructions into the basic instruction sequence under test and combining them with loop instructions for multiple iterations. Simultaneously, by configuring differentiated delay parameters for different thread bundles in the target instruction sequence, a dynamic time difference is actively introduced for each thread bundle executing in parallel. During the instruction scheduler's processing of this sequence, the loop mechanism and delay differences work together to continuously accumulate misalignments in the relative execution progress between different thread bundles, thereby breaking the fixed pace of multiple thread bundles executing in parallel. This results in complex and diverse interleaved combinations of the originally synchronous instruction stream. This mechanism can automatically and accurately generate a large number of multi-issue instruction interleaved combinations at the scheduler's issuing end, thus accurately covering various complex concurrent resource conflict test scenarios. This invention eliminates the need for manually writing a large amount of complex concurrent test instruction code and avoids the ineffective redundancy defects caused by random instruction generation schemes. Only a very small amount of basic logic code is required to quickly construct diverse real concurrent scheduling scenarios, significantly improving the completeness and accuracy of verification. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the architecture of the graphics processor provided by the present invention; Figure 2 This is a flowchart illustrating the verification method for the instruction scheduler provided by the present invention; Figure 3 This is a schematic diagram of dual-port command transmission provided by the present invention; Figure 4 This is a schematic diagram of the instruction sequence when performing dual-issue verification using the direct kernel method in related technologies. Figure 5 This is a schematic diagram of the instruction sequence for dual-issue verification after introducing delay instructions and loop instructions, provided by the present invention. Figure 6 This is a schematic diagram of the structure of the verification device for the instruction scheduler provided by the present invention; Figure 7 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] A warp is the basic unit of parallel execution in Single Instruction Multiple Threads (SIMT) architecture. For example, a SIMT32 warp refers to a single instruction that allows 32 threads to execute the same instruction set in parallel. In the architecture of AI chips (using GPUs as an example), for each warp, instruction execution is always based on the program counter (PC) and is performed sequentially. Simultaneously, the instruction execution module has multiple execution units that can execute instructions from different warps in parallel. Each warp has a unique ID identifier to distinguish it from other warps.

[0023] Figure 1 This is a schematic diagram of the architecture of the graphics processor provided by the present invention, as shown below. Figure 1 As shown, the graphics processing unit (GPU) includes at least an instruction cache 110, an instruction scheduler 120, and an instruction execution module 130. The instruction cache 110 is the source for storing GPU program instructions. In graphics and general computing tasks, the instruction sequences of each warp are pre-loaded here, awaiting retrieval by the scheduler. The instruction scheduler 120 is responsible for retrieving instructions from the instruction cache 110, performing resource scheduling, and determining instruction dispatch. In the case of multiple warps running in parallel, it must resolve instruction dependency latency issues within the same warp, as well as resource conflicts between different warps (such as read / write port conflicts, shared resource allocation, etc.). Under the premise of resolving all conflicts, the instruction scheduler 120 has the ability to issue two instructions simultaneously within the same clock cycle; therefore, it can also be called a dual-issue instruction scheduler. Here, dual-issue means that the scheduler can simultaneously issue two instructions (usually one vector instruction and one scalar instruction) to the instruction execution module 130 within the same clock cycle, thereby improving computational speed.

[0024] The Execution Unit (EU) 130 is the module that receives scheduler instructions and performs the actual computation. To enable multi-issue, the EU typically integrates different execution units. For example, in a dual-issue scenario, the EU includes a Vector Execution Unit (VEU) and a Scalar Execution Unit (SEU). The Vector Execution Unit is specifically designed to process SIMT vector data, suitable for large-scale parallel computing. It can receive two vector instructions from different warp IDs every two clock cycles for execution. Here, in digital circuits, one clock cycle refers to one clock period. The Scalar Execution Unit is specifically designed to handle single-task logic control tasks, such as loop control and address offset calculation. It can receive one scalar instruction per clock cycle, and this scalar instruction belongs to a different warp ID than the vector instructions issued in the same clock cycle. It should be understood that since the vector execution unit can receive two vector instructions every two cycles and the scalar execution unit can receive one scalar instruction every cycle (i.e., a total of two scalar instructions can be received within the two-cycle time window), when the two work in parallel at full capacity, a combination of two vector instructions and two scalar instructions can be formed. Therefore, the instruction scheduler 120 can issue four instructions every two cycles.

[0025] During the chip design phase, due to the extreme complexity of GPUs, the instruction scheduler typically needs to be extracted separately for module-level verification. In the test platform (TestBench, TB), the actual logical flow is as follows: generate test instruction stream → send to the scheduler → scheduler performs scheduling → check the scheduler's output. Since the scheduler can issue four instructions every two clock cycles, it needs to resolve the execution sequence and dependency latency issues of instructions from the same warp, as well as resource conflicts between different warps, such as read / write port conflicts for thread local registers (TLRs), warp scalar registers (WSRs), and constant scalar registers (CSRs), and the allocation and release of shared resources. When issuing instructions, the scheduler needs to ensure that there are no resource conflicts between instructions issued in the previous clock cycle and instructions issued in the same clock cycle. Therefore, the focus of instruction scheduler verification is on generating reasonable instruction sequences (i.e., kernels) to test whether the scheduler can make completely correct scheduling decisions when faced with complex instruction combinations.

[0026] Currently, the industry mainly adopts two conventional technical solutions for verifying instruction schedulers: One conventional solution is to construct test cases directly using the kernel. This solution triggers the scheduler to schedule between different warps and different Arithmetic Logic Units (ALUs) by using multiple warps in parallel, and performs correctness checks according to scheduling rules at the scheduler output interface by decoding information. The other conventional method is to use a Random Instruction Generator (RTG) to generate a random kernel. This solution also uses multiple warps in parallel to verify the scheduling between different program segments, and performs assertion checks at the output.

[0027] However, while using direct kernel to build test cases offers high targeting and accuracy, the sheer volume of scenarios involving multiple command combinations necessitates extensive manual kernel writing, resulting in extremely low verification efficiency and poor maintainability. Furthermore, the execution mode of direct kernels is too fixed; typically, the warp built first executes and exits first, making it difficult to achieve accurate parallelization of different warp segments and thus hindering coverage of complex scheduling scenarios.

[0028] While using random kernels to generate test cases is fast, the randomly generated sequences contain a large number of redundant and duplicate test cases, making it difficult to accurately cover specific dual-launch resource conflict scenarios. Therefore, this approach has low verification accuracy, consumes a significant amount of machine runtime, and has extremely slow test convergence.

[0029] To address this, the present invention provides a method for verifying an instruction scheduler. By introducing parameterized delayed instructions and a loop mechanism, it can dynamically generate a rich variety of random interleaved scenarios, thereby covering a large number of multi-launch resource conflict scenarios. Moreover, it eliminates the need to manually write a large number of complex test instructions, achieving instruction scheduling verification that balances high efficiency and high accuracy, thus overcoming the aforementioned shortcomings.

[0030] Before detailing the method provided by this invention, the execution entity of the method will first be described. The method provided by this invention is typically executed by a test platform (TB) or an electronic device with similar verification capabilities. This electronic device can be any computing device with data processing capabilities, such as a personal computer, server, or integrated circuit verification workstation. During chip module-level verification, the actual instruction scheduler, as a core component, is placed in this simulated test platform. The test platform is responsible for simulating the actual instruction fetch process, generating test instruction streams and sending them to the instruction scheduler to be verified, followed by a correctness check at the instruction scheduler's issue port. The method provided by this invention is primarily deployed and runs on such test platforms to achieve complete verification of instruction schedulers in multi-issue architectures such as GPUs.

[0031] It should be noted that all actions to acquire instruction information or data in this invention are carried out in compliance with the relevant data protection laws and policies of the country where the invention is located, and with authorization from the owner of the corresponding device.

[0032] Figure 2 This is a flowchart illustrating the verification method for the instruction scheduler provided by the present invention, as shown below. Figure 2 As shown, the method includes: Step S10: Obtain the basic instruction sequence to be tested.

[0033] Specifically, the testing platform first needs to obtain the basic instruction sequence used to trigger the verification process. This basic instruction sequence (often referred to as the native kernel) can be assembly code or machine code stream pre-written by the verification engineer, containing certain computational logic, or it can be a code stream obtained by optimizing the pre-written code by the engineer.

[0034] Understandably, in GPU architectures, instructions are typically executed in parallel based on warps. Verification of multi-issue instruction schedulers (such as dual-issue schedulers) requires triggering the scheduler's scheduling between different instruction streams by using multiple warps in parallel. The purpose of obtaining this basic instruction sequence is to provide a complete and functionally sound test base, ensuring that subsequent verification is not interfered with by logical errors in the instructions themselves.

[0035] Step S20: Insert a delay instruction into the basic instruction sequence, and use a loop instruction to loop the sequence containing the delay instruction multiple times to generate the target instruction sequence.

[0036] Specifically, after obtaining the basic instruction sequence, if multiple thread bundles are directly executed, since each thread bundle usually executes the instructions at the same pace and speed, there is no relative execution time difference between them. This highly synchronized execution state will cause the combination of instructions sent to the scheduler by different thread bundles in the same clock cycle and their corresponding relationships to always be fixed. No matter how many times it is executed repeatedly, only a very small number of certain instruction overlaps can be triggered, resulting in a very limited verification scenario.

[0037] Therefore, the testing platform modifies the basic instruction sequence. On one hand, it inserts delayed instructions into the basic instruction sequence. These delayed instructions refer to control instructions that can introduce waiting time or pause actions into the execution flow of a thread bundle, such as memory barrier instructions (fence) and wait sync channel instructions (wait sync channel).

[0038] On the other hand, a loop instruction is used to wrap the program segment that has already been interspersed with delay instructions, causing it to be executed multiple times. The sequence after the above-mentioned insertion of delays and multiple loops constitutes the final target instruction sequence sent to the scheduler.

[0039] Step S30: In the target instruction sequence, configure corresponding delay parameters for the delayed instructions executed by different thread bundles, and input the target instruction sequence with configured parameters to the instruction scheduler to be verified.

[0040] Specifically, at the test platform (TB) level, the delay time of the aforementioned inserted delay instructions is not fixed but is set as a dynamically configurable delay parameter. Here, the delay parameter refers to the specific length of time (usually expressed as several clock cycles) required for the thread bundle to wait or pause when it encounters delay instructions such as fence, wait sync channel, or pause instructions during execution. This parameter is dynamically configurable, allowing for flexible setting in an external verification environment.

[0041] Specifically, in this step, the testing platform randomly or selectively configures different delay parameters for the delayed instructions executed by different thread bundles (e.g., warp0 and warpN) running in parallel. For example, a first delay parameter is configured for warp0, and a second delay parameter is configured for warpN, and the two are not equal. By assigning different delay time values, different time differences can be actively and precisely introduced for different thread bundles. After completing the above parameter configuration, the testing platform uses the instruction fetch interface to simulate the real logical flow sequence, continuously sending the target instruction sequence carrying these dynamic delay parameters into the buffer pool corresponding to the instruction scheduler to be verified, so that the scheduler can perform resource judgment and scheduling decisions in subsequent clock cycles.

[0042] Step S40: During the process of the instruction scheduler processing the target instruction sequence, based on the delay parameter and the loop instruction, the instruction streams of different thread bundles are interleaved to generate a multi-issue instruction interleaved combination at the transmitter of the instruction scheduler.

[0043] Specifically, when the instruction scheduler to be verified receives these sequences and prepares to dispatch instructions, the relative progress of multiple thread bundles that were originally executing in unison becomes misaligned due to the different pause times (i.e., differences in delay parameters) when each thread bundle encounters a delayed instruction. This time difference is continuously amplified by the multiplier effect of multiple loops (i.e., loop instructions), causing the instruction streams of different thread bundles to interleave. Specifically, this can cause the current instruction of one thread bundle (e.g., warp0) to encounter the instruction of a different program segment of another thread bundle (e.g., warpN) within the same clock cycle (i.e., co-issue).

[0044] Because the instruction scheduler supports multi-threaded parallel scheduling, it must find opportunities to issue multiple instructions simultaneously (i.e., double-issue, such as a vector instruction and a scalar instruction) within this extremely chaotic and random instruction combination. This results in countless complex and unpredictable multi-issue instruction interleaving combinations at the instruction scheduler's issue port. Here, multi-issue instruction interleaving refers to a specific set of instructions dispatched simultaneously by the instruction scheduler to different execution units within the same clock cycle or consecutive hardware execution windows. For example, if the instruction scheduler issues four instructions—inst0, inst1, inst2, and inst3—within two clock cycles, the multi-issue instruction combination is the instruction combination {inst0, inst1, inst2, inst3}.

[0045] Understandably, the execution progress of different thread bundles is forcibly disrupted by delayed instructions and loop mechanisms, causing instruction blocks that originally had no overlap to overlap on the timeline. Therefore, this interleaved combination not only includes the scenario of sequential instruction dependencies within the same thread bundle, but also the conflict scenario of instructions from different thread bundles and of different types being co-issued at the same time, thus reproducing the cross-thread bundle port conflict and shared resource preemption scenario that is extremely difficult to artificially construct in real chip operation.

[0046] Step S50: Verify the command scheduler based on the multi-transmission command interleaving combination.

[0047] Specifically, after the scheduler generates a large number of interleaved instruction combinations, the test platform's monitor captures each instruction combination issued by the scheduler in real time. The core of the verification lies in determining whether the scheduling decisions made by the instruction scheduler in the face of these complex extreme boundary conditions (i.e., multi-issue conflict scenarios) violate the underlying hardware rules, that is, verifying whether there are conflicts in the instruction combinations issued by the scheduler.

[0048] Specifically, the test platform uses an internal assertion mechanism to check for conflicts in read / write ports of shared resources or special registers between instructions issued in the same or adjacent cycles, as well as for unresolved data dependencies. If the scheduler does not hang due to deadlock during prolonged interleaving testing, and all combinations of issued instructions conform to resource allocation and timing dependency rules, the scheduler is considered to have passed verification.

[0049] The method provided in this invention alters the conventional, single, and fixed execution mode of test instruction sequences by inserting delayed instructions into the basic instruction sequence under test and combining this with multiple loops. Simultaneously, by configuring differentiated delay parameters for different thread bundles in the target instruction sequence, a dynamic time difference is actively introduced for each thread bundle executing in parallel. During the instruction scheduler's processing of this sequence, the loop mechanism and delay differences work together to continuously accumulate misalignments in the relative execution progress between different thread bundles, thereby breaking the fixed pace of multiple thread bundles executing in parallel. This results in complex and diverse interleaved combinations of the originally synchronous instruction stream. This mechanism can automatically and accurately generate a large number of interleaved combinations of multi-issue instructions at the scheduler's issuing end, thus accurately covering various complex concurrent resource conflict test scenarios. This invention eliminates the need for manually writing a large amount of complex concurrent test instruction code and avoids the ineffective redundancy defects caused by random instruction generation schemes. Only a minimal amount of basic logic code is required to quickly construct diverse real-world concurrent scheduling scenarios, significantly improving the completeness and accuracy of verification.

[0050] Based on any of the above embodiments, step S10 specifically includes: Step S11: Obtain the instruction set to be tested.

[0051] It should be noted that because the instruction scheduler's internal processing logic for different instructions (such as decoding information, port requirements, latency periods, etc.) differs, relying solely on random or single-type instruction streams to verify the scheduler, even if the verification passes, does not prove the scheduler's completeness. Therefore, when writing test instruction sequences, it is necessary to categorize and block them to perform comprehensive multi-issue tests on the entire instruction set.

[0052] Specifically, the test platform first needs to acquire the instruction set to be tested. Here, the instruction set to be tested refers to the complete instruction library or a representative subset thereof that the instruction scheduler needs to process in real-world application scenarios (such as a GPU dual-issue architecture). To ensure the completeness of the verification, this instruction set includes standard Arithmetic Logic Unit (ALU) instructions and memory access instructions (these instructions only consider read / write resource conflicts), as well as control flow instructions (i.e., CT instructions, such as flow control-related jump instructions), and also variable-length fence instructions, wait sync channel instructions (these instructions consider timing dependencies), thereby maximizing the replication of a real and complex instruction execution environment.

[0053] Step S12: Classify the instructions in the instruction set to be tested according to the instruction characteristics to obtain the instruction classification result. The instruction characteristics include at least one of instruction type, number of instruction sources, instruction source supported register type, and destination register type.

[0054] Specifically, after obtaining the instruction set to be tested, the test platform or verification engineer will classify the instructions in the instruction set according to their characteristics, and obtain the instruction classification results. Here, instruction characteristics refer to the key attributes that determine how instructions are scheduled and executed at the hardware level, which may include, but are not limited to, instruction type, number of instruction sources, supported register types of instruction sources, and instruction destination register types.

[0055] The instruction type represents the basic operation performed by the instruction. For example, it can be divided into ALU types related to computation and logic operations, CT types related to flow control, and variable-length delayed instructions (such as fence instructions and wait syncchannel instructions). The number of instruction sources refers to the number of source operands required to execute the instruction (such as single operand, double operand, or triple operand), which determines the amount of data dependencies that need to be prepared before the instruction is issued. Instruction sources support register types and destination register types, which respectively represent the physical storage locations where the instruction reads input data and writes output results. In multi-issue GPU architectures, different register types (such as TLR, WSR, CSR, etc.) correspond to different physical read / write ports.

[0056] When classifying instructions based on the aforementioned characteristics, instructions can be categorized according to their conflicting use of specific hardware resources and ports. For example, instructions with the same instruction type and destination register type can be grouped into category A, while instructions whose source registers support special register types such as WSR and CSR, and which have a large number of source instructions, can be grouped into category B, used to trigger conflicts in the use of specific resource read / write ports. Through this multi-dimensional cross-classification of characteristics, the disorganized instruction set can be organized into multiple sets of similar instructions with clear resource preferences and potential conflict characteristics. This clarifies the specific resource pressure that various instructions may exert on the scheduler during multiple issues, providing a foundation for subsequently constructing targeted conflict scenarios.

[0057] Step S13: Based on the instruction classification results, select instructions from the set of instructions to be tested and combine them to construct the basic instruction sequence.

[0058] Specifically, after obtaining the instruction classification results, this step selects similar instructions with potential resource conflicts or read / write port conflicts from the instruction set under test for each type in the classification results and combines them. This process abandons the practice of blindly and randomly selecting instructions, instead allowing the testing platform or verification personnel to clearly and explicitly know, when generating code, what kind of computing resource or port pressure the currently combined batch of instructions is exerting on the scheduler. For example, multiple consecutive type A instructions can be combined together to form a block of similar instructions, followed by another block of similar instructions composed of multiple type B instructions, and so on. This conscious block-building method based on classification results constitutes the most original and targeted testing foundation of the verification process.

[0059] The method provided in this invention classifies and extracts the instruction set to be tested based on underlying characteristics such as instruction type, number of operands, and register read / write port occupancy before constructing the basic instruction sequence. This enables the test platform to consciously establish highly controllable resource conflict boundaries, thereby avoiding the shortcomings of traditional random instruction generators that are too blind in instruction combination and thus cannot accurately cover specific resource conflict scenarios. This lays the logical foundation for subsequent conflict scenarios such as competition for similar resources or dual-issue of cross-type execution units through delayed injection.

[0060] Based on any of the above embodiments, step S13 specifically includes: Step S131: Based on the instruction classification results, select instructions from the set of instructions to be tested and combine them to obtain an initial test sequence; Step S132: Replace the synchronization barrier instruction used to achieve cross-thread bundle synchronization in the initial test sequence with a pause instruction to obtain the basic instruction sequence.

[0061] Specifically, in actual chip module-level verification, the testing platform combines the selected instructions into a raw test code stream, i.e., the initial test sequence, based on the aforementioned instruction classification results. This initial test sequence reproduces the real business logic, which often includes complex synchronization instructions for controlling multi-threaded collaboration, i.e., synchronization barrier instructions (such as barrier instructions).

[0062] In real-world GPU applications, barrier instructions are primarily used to implement synchronization instructions across warps within a thread group, and the underlying cluster-level full synchronization logic is quite complex. However, for the specific objective of verifying the instruction scheduler's dual-issue mechanism in this invention, the focus is on ensuring that the timing and resources of each instruction issuance for each warp are conflict-free, rather than verifying the cluster-level full synchronization logic. Therefore, this embodiment of the invention performs a lightweight equivalent modeling of the original synchronization barrier instruction, simplifying and replacing it with a simple pause instruction (i.e., a stall instruction). This pause instruction's behavior is considered a simple fence instruction, its function being merely to allow the currently executing warp to wait for a delay before resuming execution. Through this replacement, a basic instruction sequence that can be directly used for subsequent injection of delays and loop operations is obtained.

[0063] The method provided in this invention replaces the native cross-thread bundle synchronization barrier instruction with a lightweight pause instruction, which not only significantly reduces the control complexity of the scheduler module-level verification environment, allowing the test platform to focus more on the core verification of instruction-level issue timing and resource conflicts, but also provides an additional means of introducing delay time for the thread bundle execution flow without changing the original code structure, which is beneficial for further disrupting the instruction issue sequence.

[0064] Based on any of the above embodiments, step S20, inserting a delay instruction into the basic instruction sequence, includes: Based on the instruction classification results, a delayed instruction is inserted into the basic instruction sequence every preset number of instructions to divide the basic instruction sequence into multiple instruction segments; The insertion position of the delayed instruction includes at least one of the following: within the same type of instruction block in the basic instruction sequence, or between different types of instruction blocks in the basic instruction sequence.

[0065] Specifically, after clarifying the classification attributes of the instructions (such as computing resources and read / write port usage), this embodiment of the invention adopts a regular slicing strategy. Specifically, when the test platform writes or generates instruction sequences, it forces the insertion of a delayed instruction (such as a fence instruction) every preset number of times (e.g., every 5 or 10 real test instructions) into the continuous code flow. This regular insertion of delayed instructions is like setting up multiple dynamic, variable delay isolation bands, dividing the originally long sequence of basic instructions into multiple instruction fragments.

[0066] Understandably, in order to fully cover various multi-issue conflict scenarios that the scheduler may encounter, the insertion position of the delay instruction mainly includes the following two cases (the two can be used alone or in combination): The first scenario involves inserting delayed instructions between different types of instruction blocks in the basic instruction sequence. This method is primarily used to create double-issue collisions across execution units (such as vector execution units and scalar execution units). By utilizing externally configured latency differences, the scheduler's ability to double-issue different types of instructions from different thread bundles to different execution units in the same clock cycle can be accurately verified.

[0067] The second scenario involves inserting delayed instructions within similar instruction blocks in the basic instruction sequence. For example, if an instruction block consists of 20 instructions that are all computation and logical operation (ALU) instructions, a delayed instruction can be inserted every 5 instructions to break up the continuous large blocks of similar instructions.

[0068] By inserting delayed instructions at the above two positions, the scheduler not only has to solve cross-type dual-issue, but also resource contention between instructions of the same type (such as register read / write port conflicts, and data dependency issues within the same thread bundle).

[0069] The method provided in this invention establishes multiple controllable resource conflict boundaries in the code stream by regularly inserting delayed instructions into the basic instruction sequence. This allows instructions with potential resource conflicts to be squeezed into the same clock cycle for testing when combined with dynamic delay and loop mechanisms. Thus, it achieves complete coverage of all extreme concurrency scenarios, such as scheduler cross-type double-issue collisions and high-pressure resource contention of the same type, with a very small amount of logic code.

[0070] Based on any of the above embodiments, in step S30, configuring corresponding delay parameters for the delay instructions executed for different thread bundles includes: Configure a first delay parameter for the delayed instruction executed by the first thread bundle, and configure a second delay parameter for the delayed instruction executed by the second thread bundle; The delay time of the delay instruction is preset to a dynamically configurable delay parameter, and the first delay parameter is different from the second delay parameter.

[0071] It should be noted that in conventional verification and testing platforms, the execution time of instructions is often fixed. Without any intervention, the combination of instructions sent to the scheduler by multiple concurrently executing warps in the same clock cycle, and their corresponding relationships, will always be fixed. To change this situation, this embodiment of the invention sets the delay time of delayed instructions to a dynamically configurable delay parameter at the testing platform level.

[0072] Specifically, before issuing instructions, the test platform will randomly or specifically assign a specific value as the first delay parameter to the delayed instructions (such as the fence instruction or wait sync channel instruction) contained in the first thread bundle (such as warp0) which is in a parallel execution state. At the same time, it will configure a second delay parameter for the same or different delayed instructions executed by the second thread bundle (such as warpN).

[0073] Understandably, the first delay parameter mentioned above differs from the second delay parameter; this is a prerequisite for achieving subsequent instruction misalignment. By setting different delay times externally for different thread bundles, it is possible to proactively introduce pauses of varying lengths into parallel thread bundles during multi-issue operations. The delay parameter here can be a number of clock cycles or a specific waiting signal, as long as it reflects a time difference.

[0074] The method provided in this invention breaks the original fixed and synchronous execution pace of multi-thread bundles by parameterizing the waiting time of delayed instructions and configuring different delay parameters for different thread bundles running in parallel. Without modifying the underlying test code (i.e., kernel logic), it provides the necessary time difference basis for creating various random instruction interleaving scenarios.

[0075] Based on any of the above embodiments, step S40 specifically includes: Step S41: In each iteration of the loop instruction, the difference between the first delay parameter and the second delay parameter is used to accumulate the execution delay difference between the first thread bundle and the second thread bundle. Step S42: When the execution delay difference reaches the interleaving condition, the instruction scheduler will issue the first target instruction in the first thread bundle and the second target instruction in the second thread bundle within the same clock cycle to generate the multi-issue instruction interleaving combination.

[0076] Specifically, the test platform uses loop instructions to nest and execute the pre-configured program segments containing delay instructions multiple times. A basic instruction sequence of finite length will have slightly different waiting times for the first thread bundle (e.g., warp0) and the second thread bundle (e.g., warpN) each time the delay instructions are executed (i.e., the difference between the first and second delay parameters). This difference may not be noticeable in a single execution. However, as the loop instructions are executed repeatedly, the execution delay difference between the first and second thread bundles accumulates. This means that as the number of loops increases, the relative misalignment in the code execution progress of the two thread bundles becomes increasingly larger.

[0077] As the aforementioned execution latency difference accumulates and amplifies, an interleaving condition will inevitably be triggered at a specific clock cycle. This interleaving condition occurs when the first thread beam happens to execute an instruction within its program segment (i.e., the first target instruction, such as the instruction that just reaches the vector execution unit), while the second thread beam, due to the accumulated latency, wakes up and executes another instruction within its program segment (i.e., the second target instruction, such as the instruction that just reaches the scalar execution unit). Faced with these two instructions from different thread beams and different program segments meeting within the same clock cycle, if the instruction scheduler determines that resources allow, it will issue them simultaneously (also known as co-issue), thus creating a multi-issue instruction interleaving combination at the issuing end composed of these instructions.

[0078] The method provided by this invention combines the outer loop mechanism with the inner variable delay parameter to generate a huge multiplier effect. This allows for the creation of a large number of complex concurrent dual-issue combination scenarios that are difficult to construct manually at a very low cost by using only a very short basic instruction sequence. This solves the problem that manually writing test cases is inefficient and difficult to cover complex scheduling scenarios.

[0079] Based on any of the above embodiments, the instruction scheduler is a dual-issue instruction scheduler, and correspondingly, step S50 specifically includes: Step S51: Using two consecutive clock cycles as a hardware execution window, obtain the instruction combination issued by the dual-issue instruction scheduler within the hardware execution window. The instruction combination includes at most two vector instructions and at most two scalar instructions. Step S52: Perform resource conflict checks and data dependency checks on the instructions in the instruction combination.

[0080] It should be noted that this embodiment of the invention further clarifies the data capture window and inspection rules during the verification process for dual-issue instruction schedulers, which are common in GPU architectures. For the verification of dual-issue instruction schedulers, it is necessary to select an observation interval that can fully expose their scheduling characteristics.

[0081] Specifically, in the GPU architecture, the vector execution unit (VLU) is responsible for processing Single Instruction Multithreaded (SIMT) data suitable for massively parallel computing. Its throughput typically involves receiving two vector instructions from different warps every two clock cycles (i.e., two clock cycles). The scalar execution unit (SLU), on the other hand, handles single-logic control tasks, typically receiving one scalar instruction per clock cycle (i.e., one clock cycle). If the test platform observes only one clock cycle, it will miss verifying resource conflicts across clock cycles and will fail to trigger the complete hardware logic of the VLU. Therefore, this embodiment of the invention selects two clock cycles (i.e., two consecutive clock cycles) as the least common multiple period to form an atomic, complete hardware execution window. Within this two-clock-cycle window, the scheduler's theoretical maximum load limit is exactly 2 vector instructions plus 2 scalar instructions (a total of 4 instructions). The test platform will capture, in real-time, instruction combinations (e.g., {inst0, inst1, inst2, inst3}) issued by the scheduler within this window.

[0082] After capturing the above-mentioned fully loaded or non-fully loaded instruction combinations, the test platform's monitor and assertion mechanism will, according to the underlying scheduling rules, adjudicate the correctness of all instructions issued within the hardware execution window, mainly checking for resource conflicts where different instructions compete for shared computing resources, and for data dependency errors in the execution order between instructions.

[0083] The method provided in this invention introduces a two-clock cycle that matches the least common multiple of the throughput of the vector execution unit and the scalar execution unit as a hardware execution window. This not only captures all instruction combinations of the dual-issue scheduler under full load limit, but also avoids the problem of missing cross-cycle resource conflicts caused by a single-cycle observation window, ensuring that the verification can fully cover the complex hardware logic boundary conditions under the dual-issue architecture.

[0084] Based on any of the above embodiments, step S52 specifically includes: Check whether there are read / write port conflicts between instructions in the same or different clock cycles within the hardware execution window; Check whether there are any unsatisfied data dependencies among the instruction sequences belonging to the same thread bundle in the instruction combination.

[0085] Specifically, when verifying the instruction combinations issued by the scheduler, the test platform mainly includes rule verification in the following two dimensions: First, conflict checking for shared resources and specific registers. In a dual-issue architecture, even instructions issued within the same clock cycle, single-instruction multithreaded (SIMT) issuance actions may occupy some register read / write ports of scalar issuance; simultaneously, the previous instruction, when issued, may preemptively occupy some register read / write ports of the subsequent instruction. Therefore, the test platform strictly checks whether, within the hardware execution window, whether two instructions within the same clock cycle or instructions in different clock cycles (i.e., two consecutive clock cycles), they attempt to simultaneously read / write the same specific register (such as TLR, WSR, CSR, etc.), leading to port conflicts.

[0086] Secondly, there's the timing conflict check for logical sequence. If the scheduler has a logical error, it might forcibly issue a second instruction within the same thread bundle before the first instruction has finished calculating, and the input of the second instruction strongly depends on the output of the first instruction, leading to an incorrect final calculation result. Therefore, the test platform's assertion mechanism rigorously checks instruction sequences belonging to the same thread bundle within instruction combinations to determine if there are any unmet data dependencies (i.e., dependency issues). If, during a long-term interleaved test, all captured instruction combinations show no port conflicts and all data dependencies have been resolved, the verification passes; if even one illegal issuance is detected, the assertion will report an error to indicate verification failure.

[0087] The method provided in this invention establishes physical read / write port conflict checking rules for the same clock cycle and across clock cycles within a specific dual-time hardware execution window, as well as strict data dependency timing checking rules within the same thread bundle. This enables the accurate identification of scheduling problems such as register contention and premature launch during multi-threaded interleaved execution, thereby improving the accuracy and reliability of chip module-level verification.

[0088] Based on any of the above embodiments, this invention provides a verification method for a GPU dual-issue instruction scheduler. The method flow of this invention will be described below with reference to specific examples. Figure 3 This is a schematic diagram of the dual-port command transmission provided by the present invention, as shown below. Figure 3 As shown, in the instruction execution module of a GPU, dual-port issuing (or multiple issuing) of instructions refers to the scheduler's ability to issue multiple instructions to different execution units simultaneously within the same clock cycle (e.g., clock cycle one). Figure 3 The example demonstrates the parallel execution of vector instruction issuance (e.g., inst0) and scalar instruction issuance (e.g., inst1).

[0089] In the operational logic of a dual-issue scheduler, instructions issued within the same clock cycle may have different register read / write ports. Vector instructions might occupy some register read / write ports of scalar instructions, and the preceding instruction might preemptively occupy some register read / write ports of the following instruction. For example, in clock cycle one, the issuance of inst1 needs to ensure no conflict with inst0. Similarly, the issuance of inst2 and inst3 in clock cycle two needs to ensure no conflict with preceding instructions and that data dependencies have been resolved. Specifically, inst2 needs to ensure no conflict with inst0 or inst1, and inst3 needs to ensure no conflict with inst0, inst1, or inst2. Therefore, for a dual-issue instruction scheduler, the main verification scenario is to induce the scheduler to generate various potentially conflicting instruction combinations (such as {inst0, inst1, inst2, inst3}) to verify whether its scheduling decisions in the face of these combinations are completely correct.

[0090] Figure 4 This is a schematic diagram of the instruction sequence used in related technologies for dual-issue verification using the direct kernel approach, such as... Figure 4 As shown, in a conventional verification scheme, if only a sequence of instructions to be tested (e.g., from alu inst0 to aluinstm+1) is provided, and then distributed to multiple thread bundles (e.g., warp0 and warpN) for parallel execution, warp0 and warpN will remain in a completely synchronized state without intervention such as variable latency. Although a dual-issue scenario is achieved, the instruction executed by warp0 (e.g., alu inst0) is always fixedly bound to the instruction executed by warpN (e.g., alu inst0), meaning that dual-issue (co-issue) occurs within the same clock cycle.

[0091] From the scheduler's perspective, the concurrent scenario in this case is completely fixed and singular. Even if this program is repeated multiple times, the combination of instructions for each simultaneous launch and the launches of the preceding and following launches is deterministic. It is impossible to spontaneously form a combination scenario where instructions from different program segments collide (for example, it is impossible to achieve interleaved dual launches of warp0's aluinst0 and warpN's aluinst2). This makes it difficult to verify the logical boundaries of the scheduler's complex resource scheduling and dependency checks, resulting in low verification accuracy and inefficiency.

[0092] Figure 5 This is a schematic diagram of the instruction sequence for dual-issue verification after introducing delay instructions and loop instructions, as provided by the present invention. Figure 5 As shown, in order to break Figure 4In contrast to the fixed emission pattern in traditional methods, this invention introduces delayed instructions and a loop mechanism into the instruction sequence. Specifically, firstly, delayed instructions (such as fence, wait sync channel, etc.) are regularly inserted into the basic test code, dividing the long code string into multiple instruction fragments; secondly, different delay time parameters are configured for these delayed instructions of different warps externally; finally, the entire sequence is wrapped with a large LABEL_LOOPN (loop instruction) and executed multiple times, for example, from the 0th loop (i.e., loop 0) to the Nth loop (i.e., loop N).

[0093] pass Figure 4 and Figure 5 The comparison shows that, Figure 4 In the middle, due to the lack of a scrambling mechanism, warp0 and warpN always maintain parallel and synchronous launch. And... Figure 5 In the initial loop (loop 0), due to delays caused by instructions such as fence, the execution progress of warp0 and warpN begins to slightly misalign. For example, warp0's alu instn instruction and warpN's alu instn-1 instruction are co-issued within the same clock cycle. As the time per cycle progresses, after multiple loops (e.g., reaching loop N), this delay difference accumulates and amplifies, causing the originally aligned sequences to become completely misaligned. At this point, warp0 might be executing its alu inst2 instruction, while warpN, due to the earlier delay, might be waking up and executing the alu instn-1 instruction. This forces the scheduler to co-issue these two completely different instructions within the same clock cycle.

[0094] The method provided in this embodiment of the invention has the following advantages: (1) The verification environment implementation logic is clear and the code complexity is low. It does not require complex control over the specific instruction issuance of the verification environment. It can perform instruction verification based on the native kernel content. It does not require configuration for each instruction. It only needs to configure the delay time of the fence and wait sync channel through parameters. All other aspects are controlled in the kernel. (2) It balances high efficiency and high scene accuracy. It is more efficient than the direct kernel and more accurate than the random kernel. By controlling the number of loops and the delay of instructions such as fence, it can increase the number of instruction issuance combination scenarios and greatly improve the efficiency of instruction concurrent verification. (3) Strong maintainability. During project development, there will inevitably be additions or deletions of instructions or changes in instruction details. Through cyclical use, the number of direct kernels can be reduced, and the burden of maintenance and updates is smaller. (4) It has strong versatility and the verification method is highly adaptable to GPUs with multi-issue instructions that have vector and scalar execution units. It is also adaptable to the verification of other similar dual-issue microarchitectures.

[0095] The verification device for the instruction scheduler provided by the present invention is described below. The verification device for the instruction scheduler described below can be referred to in correspondence with the verification method for the instruction scheduler described above.

[0096] Based on any of the above embodiments Figure 6 This is a schematic diagram of the structure of the verification device for the instruction scheduler provided by the present invention, as shown below. Figure 6 As shown, the device includes: The basic sequence acquisition unit 610 is used to acquire the basic instruction sequence to be tested; The target sequence generation unit 620 is used to insert a delay instruction into the basic instruction sequence and use a loop instruction to loop the sequence containing the delay instruction multiple times to generate a target instruction sequence; The delay parameter configuration unit 630 is used to configure corresponding delay parameters for the delayed instructions executed by different thread bundles in the target instruction sequence, and input the target instruction sequence after parameter configuration to the instruction scheduler to be verified. The instruction combination generation unit 640 is used to, during the process of the instruction scheduler processing the target instruction sequence, interleave the instruction streams of different thread bundles based on the delay parameter and the loop instruction, so as to generate a multi-issue instruction interleaved combination at the transmitter end of the instruction scheduler; The scheduler verification unit 650 is used to verify the instruction scheduler based on the multi-issue instruction interleaving combination.

[0097] The apparatus provided in this invention alters the conventional, single, and fixed execution mode of test instruction sequences by inserting delayed instructions into the basic instruction sequence under test and combining this with multiple loops. Simultaneously, by configuring differentiated delay parameters for different thread bundles in the target instruction sequence, a dynamic time difference is actively introduced for each thread bundle executing in parallel. During the instruction scheduler's processing of this sequence, the loop mechanism and delay differences work together to continuously accumulate misalignments in the relative execution progress between different thread bundles, thereby breaking the fixed pace of multiple thread bundles executing in parallel. This results in complex and diverse interleaved combinations of the originally synchronous instruction stream. This mechanism can automatically and accurately generate a large number of interleaved combinations of multi-issue instructions at the scheduler's issuing end, thus accurately covering various complex concurrent resource conflict test scenarios. This invention eliminates the need for manually writing a large amount of complex concurrent test instruction code and avoids the ineffective redundancy defects caused by random instruction generation schemes. Only a minimal amount of basic logic code is required to quickly construct diverse real concurrent scheduling scenarios, significantly improving the completeness and accuracy of verification.

[0098] Based on any of the above embodiments, the basic sequence acquisition unit is specifically used for: Obtain the instruction set to be tested; The instructions in the instruction set to be tested are classified according to their characteristics to obtain the instruction classification results. The instruction characteristics include at least one of the following: instruction type, number of instruction sources, instruction source supported register type, and destination register type. Based on the instruction classification results, instructions are selected from the set of instructions to be tested and combined to construct the basic instruction sequence.

[0099] Based on any of the above embodiments, the basic sequence acquisition unit is specifically used for: Based on the instruction classification results, instructions are selected from the set of instructions to be tested and combined to obtain an initial test sequence; The synchronization barrier instruction used to achieve cross-thread bundle synchronization in the initial test sequence is replaced with a pause instruction to obtain the basic instruction sequence.

[0100] Based on any of the above embodiments, the target sequence generation unit is specifically used for: Based on the instruction classification results, a delayed instruction is inserted into the basic instruction sequence every preset number of instructions to divide the basic instruction sequence into multiple instruction segments; The insertion position of the delayed instruction includes at least one of the following: within the same type of instruction block in the basic instruction sequence, or between different types of instruction blocks in the basic instruction sequence.

[0101] Based on any of the above embodiments, the delay parameter configuration unit is specifically used for: Configure a first delay parameter for the delayed instruction executed by the first thread bundle, and configure a second delay parameter for the delayed instruction executed by the second thread bundle; The delay time of the delay instruction is preset to a dynamically configurable delay parameter, and the first delay parameter is different from the second delay parameter.

[0102] Based on any of the above embodiments, the instruction combination generation unit is specifically used for: During each iteration of the loop instruction, the difference between the first delay parameter and the second delay parameter causes the first thread bundle and the second thread bundle to accumulate the execution delay difference. When the execution latency difference reaches the interleaving condition, the instruction scheduler will issue the first target instruction in the first thread bundle and the second target instruction in the second thread bundle within the same clock cycle, generating the multi-issue instruction interleaving combination.

[0103] Based on any of the above embodiments, the instruction scheduler is a dual-issue instruction scheduler, and correspondingly, the scheduler verification unit is specifically used for: Using two consecutive clock cycles as a hardware execution window, the dual-issue instruction scheduler obtains the instruction combination issued within the hardware execution window, the instruction combination including at most two vector instructions and at most two scalar instructions; Resource conflict checks and data dependency checks are performed on the instructions in the instruction combination.

[0104] Based on any of the above embodiments, the scheduler verification unit is specifically used for: Check whether there are read / write port conflicts between instructions in the same or different clock cycles within the hardware execution window; Check whether there are any unsatisfied data dependencies among the instruction sequences belonging to the same thread bundle in the instruction combination.

[0105] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute a verification method for an instruction scheduler. This method includes: acquiring a basic instruction sequence to be tested; inserting delayed instructions into the basic instruction sequence and using loop instructions to iterate multiple times over the sequence containing the delayed instructions to generate a target instruction sequence; configuring corresponding delay parameters for the delayed instructions executed by different thread bundles in the target instruction sequence, and inputting the target instruction sequence with configured parameters to the instruction scheduler to be verified; during the processing of the target instruction sequence by the instruction scheduler, interleaving the instruction streams of different thread bundles based on the delay parameters and the loop instructions to generate a multi-issue instruction interleaving combination at the transmitter of the instruction scheduler; and verifying the instruction scheduler based on the multi-issue instruction interleaving combination.

[0106] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the verification method of the instruction scheduler provided by the above methods. The method includes: acquiring a basic instruction sequence to be tested; inserting delayed instructions into the basic instruction sequence and using loop instructions to loop multiple times on the sequence containing the delayed instructions to generate a target instruction sequence; configuring corresponding delay parameters for the delayed instructions executed by different thread bundles in the target instruction sequence, and inputting the target instruction sequence with configured parameters to the instruction scheduler to be verified; during the process of the instruction scheduler processing the target instruction sequence, interleaving the instruction streams of different thread bundles based on the delay parameters and the loop instructions to generate a multi-issue instruction interleaving combination at the issuing end of the instruction scheduler; and verifying the instruction scheduler based on the multi-issue instruction interleaving combination.

[0108] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the verification method for the instruction scheduler provided by the above methods. The method includes: acquiring a basic instruction sequence to be tested; inserting delayed instructions into the basic instruction sequence and using loop instructions to loop multiple times on the sequence containing the delayed instructions to generate a target instruction sequence; configuring corresponding delay parameters for the delayed instructions executed by different thread bundles in the target instruction sequence, and inputting the target instruction sequence with configured parameters to the instruction scheduler to be verified; during the process of the instruction scheduler processing the target instruction sequence, interleaving the instruction streams of different thread bundles based on the delay parameters and the loop instructions to generate a multi-issue instruction interleaving combination at the issuing end of the instruction scheduler; and verifying the instruction scheduler based on the multi-issue instruction interleaving combination.

[0109] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0110] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for verifying an instruction scheduler, characterized in that, include: Obtain the basic instruction sequence to be tested; A delay instruction is inserted into the basic instruction sequence, and a loop instruction is used to loop the sequence containing the delay instruction multiple times to generate the target instruction sequence; In the target instruction sequence, corresponding delay parameters are configured for the delayed instructions executed by different thread bundles, and the target instruction sequence with the configured parameters is input to the instruction scheduler to be verified. During the process of the instruction scheduler processing the target instruction sequence, the instruction streams of different thread bundles are interleaved based on the delay parameter and the loop instruction, so as to generate a multi-issue instruction interleaved combination at the issuing end of the instruction scheduler; The instruction scheduler is verified based on the interleaved combination of the multiple transmit instructions.

2. The verification method for the instruction scheduler according to claim 1, characterized in that, The acquisition of the basic instruction sequence to be tested includes: Obtain the instruction set to be tested; The instructions in the instruction set to be tested are classified according to their characteristics to obtain the instruction classification results. The instruction characteristics include at least one of the following: instruction type, number of instruction sources, instruction source supported register type, and destination register type. Based on the instruction classification results, instructions are selected from the set of instructions to be tested and combined to construct the basic instruction sequence.

3. The verification method for the instruction scheduler according to claim 2, characterized in that, The step of selecting and combining instructions from the set of instructions to be tested based on the instruction classification results to construct the basic instruction sequence includes: Based on the instruction classification results, instructions are selected from the set of instructions to be tested and combined to obtain an initial test sequence; The synchronization barrier instruction used to achieve cross-thread bundle synchronization in the initial test sequence is replaced with a pause instruction to obtain the basic instruction sequence.

4. The verification method for the instruction scheduler according to claim 2, characterized in that, The insertion of a delayed instruction into the basic instruction sequence includes: Based on the instruction classification results, a delayed instruction is inserted into the basic instruction sequence every preset number of instructions to divide the basic instruction sequence into multiple instruction segments; The insertion position of the delayed instruction includes at least one of the following: within the same type of instruction block in the basic instruction sequence, or between different types of instruction blocks in the basic instruction sequence.

5. The verification method for the instruction scheduler according to claim 1, characterized in that, The delay instructions executed for different thread bundles are configured with corresponding delay parameters, including: Configure a first delay parameter for the delayed instruction executed by the first thread bundle, and configure a second delay parameter for the delayed instruction executed by the second thread bundle; The delay time of the delay instruction is preset to a dynamically configurable delay parameter, and the first delay parameter is different from the second delay parameter.

6. The verification method for the instruction scheduler according to claim 5, characterized in that, During the process of the instruction scheduler processing the target instruction sequence, based on the delay parameter and the loop instruction, the instruction streams of different thread bundles are interleaved to generate a multi-issue instruction interleaving combination at the issuing end of the instruction scheduler, including: During each iteration of the loop instruction, the difference between the first delay parameter and the second delay parameter causes the first thread bundle and the second thread bundle to accumulate the execution delay difference. When the execution latency difference reaches the interleaving condition, the instruction scheduler will issue the first target instruction in the first thread bundle and the second target instruction in the second thread bundle within the same clock cycle, generating the multi-issue instruction interleaving combination.

7. The verification method for the instruction scheduler according to any one of claims 1 to 6, characterized in that, The instruction scheduler is a dual-issue instruction scheduler. The verification of the instruction scheduler based on the interleaved combination of the multiple-issue instructions includes: Using two consecutive clock cycles as a hardware execution window, the dual-issue instruction scheduler obtains the instruction combination issued within the hardware execution window, the instruction combination including at most two vector instructions and at most two scalar instructions; Resource conflict checks and data dependency checks are performed on the instructions in the instruction combination.

8. The verification method for the instruction scheduler according to claim 7, characterized in that, The resource conflict check and data dependency check on the instructions in the instruction combination include: Check whether there are read / write port conflicts between instructions in the same or different clock cycles within the hardware execution window; Check whether there are any unsatisfied data dependencies among the instruction sequences belonging to the same thread bundle in the instruction combination.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the verification method of the instruction scheduler as described in any one of claims 1 to 8.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the verification method of the instruction scheduler as described in any one of claims 1 to 8.

Images