Processor, data processing method and computer equipment

Abstract

The embodiment of the invention discloses a processor, a data processing method and computer equipment, and belongs to the technical field of computers. The processor comprises a scalar processing module, a vector processing module and a matrix processing module. The scalar processing module is connected with the vector processing module and the matrix processing module. A scalar processing module in the processor not only has a function of executing a processing instruction for scalar data, but also has an instruction distribution function, so that vector processing instructions in an instruction packet can be distributed to a vector processing module, and matrix processing instructions in the instruction packet can be distributed to a matrix processing module; according to the technical scheme, a module used for distributing instructions does not need to be independently deployed in the processor, the structure of the processor is simplified, the unnecessary data interaction process caused by the fact that the instruction distribution module distributes the scalar processing instructions in the instruction packet to the scalar processing module can be avoided, the data interaction efficiency is guaranteed, and the user experience is improved. Therefore, the processor quickly responds to the received processing instruction, and the data processing efficiency of the processor is ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a processor, a data processing method, and a computer device. Background Technology

[0002] AI processors can handle various data types, including scalar, vector, and matrix data. Accordingly, AI processors include different processing engines for processing these different data types. In related technologies, an AI processor includes a task scheduler, a scalar processing engine, a vector processing engine, and a matrix processing engine, with the task scheduler connected to each engine. The task scheduler receives processing instructions for different data types and sends these instructions to the respective engines for processing. However, this processor structure is more complex, leading to lower data interaction efficiency. Summary of the Invention

[0003] This application provides a processor, a data processing method, and a computer device, which can simplify the processor structure and improve data interaction efficiency. The technical solution is as follows:

[0004] On one hand, a processor is provided, the processor including a scalar processing module, a vector processing module and a matrix processing module, the scalar processing module being connected to the vector processing module and the matrix processing module respectively;

[0005] The scalar processing module is configured to receive an instruction packet containing multiple instructions, and in response to the scalar processing instructions in the instruction packet, process the scalar data indicated by the scalar processing instructions; send the vector processing instructions in the instruction packet to the vector processing module, and send the matrix processing instructions in the instruction packet to the matrix processing module.

[0006] The vector processing module is configured to receive the vector processing instruction and, in response to the vector processing instruction, process the vector data indicated by the vector processing instruction.

[0007] The matrix processing module is used to receive the matrix processing instruction and process the matrix data indicated by the matrix processing instruction.

[0008] On the other hand, a data processing method is provided, executed by a processor as described above, the processor including a scalar processing module, a vector processing module, and a matrix processing module, the scalar processing module being connected to the vector processing module and the matrix processing module respectively; the method includes:

[0009] The scalar processing module receives an instruction packet containing multiple instructions, and in response to the scalar processing instructions in the instruction packet, processes the scalar data indicated by the scalar processing instructions, sends the vector processing instructions in the instruction packet to the vector processing module, and sends the matrix processing instructions in the instruction packet to the matrix processing module.

[0010] The vector processing module receives the vector processing instruction and, in response to the vector processing instruction, processes the vector data indicated by the vector processing instruction.

[0011] The matrix processing module receives the matrix processing instruction and processes the matrix data indicated by the matrix processing instruction.

[0012] In one possible implementation, the scalar processing module includes a decoding unit connected to the scalar processing unit; the scalar processing unit receives the instruction packet and, in response to the scalar processing instruction, processes the scalar data indicated by the scalar processing instruction, including:

[0013] The decoding unit receives the instruction packet and decodes the scalar processing instruction; upon obtaining the decoded scalar processing instruction, it sends the decoded scalar processing instruction, the vector processing instruction, and the matrix processing instruction to the scalar processing unit.

[0014] The scalar processing unit receives the decoded scalar processing instruction, the vector processing instruction, and the matrix processing instruction; in response to the decoded scalar processing instruction, it processes the scalar data indicated by the decoded scalar processing instruction; and when the processing of the scalar data indicated by the decoded scalar processing instruction is completed, it sends the vector processing instruction and the matrix processing instruction to the distribution unit.

[0015] In another possible implementation, the vector processing module includes a transport unit, a first storage unit, and a register, wherein the transport unit is connected to the first storage unit, the register, and the decoding unit, respectively; the method further includes:

[0016] If the vector processing instruction includes a vector loading instruction, the decoding unit sends the vector loading instruction to the transport unit.

[0017] The transport unit receives the vector loading instruction, and in response to the vector loading instruction, reads the vector data indicated by the vector loading instruction from the first storage unit and loads the read vector data into the register.

[0018] In another possible implementation, the vector processing module includes a register, a vector processing unit, a transport unit, and a first storage unit. The register is connected to the vector processing unit, the vector processing unit is connected to the transport unit, and the transport unit is connected to the first storage unit. The vector processing instruction includes a vector storage instruction. The vector processing module receives the vector processing instruction and, in response to the vector processing instruction, processes the vector data indicated by the vector processing instruction, including:

[0019] In response to the vector storage instruction, the vector processing unit reads the vector data indicated by the vector storage instruction from the register and sends the read vector data to the transport unit.

[0020] The transport unit receives the read vector data and sends the read vector data to the first storage unit;

[0021] The first storage unit stores the read vector data.

[0022] In another possible implementation, the matrix processing module includes a fourth storage unit, a loading unit, and a matrix processing unit, wherein the loading unit is connected to both the fourth storage unit and the matrix processing unit; the matrix processing module receives the matrix processing instruction and processes the matrix data indicated by the matrix processing instruction, including:

[0023] In response to the matrix processing instruction, the loading unit reads the matrix data indicated by the matrix processing instruction from the fourth storage unit and sends the read matrix data to the matrix processing unit.

[0024] The matrix processing unit processes the read matrix data.

[0025] In another possible implementation, the read matrix data includes feature data and weight data; the loading unit includes a feature loading subunit and a weight loading subunit, the feature loading subunit being connected to the fourth storage unit and the matrix processing unit respectively, and the weight loading subunit being connected to the fourth storage unit and the matrix processing unit respectively; the loading unit, in response to the matrix processing instruction, reads the matrix data indicated by the matrix processing instruction from the fourth storage unit and sends the read matrix data to the matrix processing unit, including:

[0026] In response to the matrix processing instruction, the feature loading subunit reads the feature data from the fourth storage unit and sends the feature data to the matrix processing unit;

[0027] In response to the matrix processing instruction, the weight loading subunit reads the weight data from the fourth storage unit and sends the weight data to the matrix processing unit.

[0028] The matrix processing unit processes the read matrix data, including:

[0029] The matrix processing unit receives the feature data and the weight data, and fuses the feature data and the weight data.

[0030] In another possible implementation, the matrix processing module includes a fifth storage unit connected to the matrix processing unit; after the matrix processing unit processes the read matrix data, the method further includes:

[0031] The matrix processing unit sends the processing result corresponding to the read matrix data to the fifth storage unit;

[0032] The fifth storage unit stores the processing results corresponding to the read matrix data.

[0033] On the other hand, a computer device is provided, the computer device including a memory and the processor described in the foregoing aspects.

[0034] In the solution provided in this application embodiment, the processor has the function of executing processing instructions for data of various data types. The scalar processing module in the processor not only has the function of executing processing instructions for scalar data, but also has the function of instruction distribution. It can distribute vector processing instructions in the instruction package to the vector processing module and matrix processing instructions in the instruction package to the matrix processing module. This couples the scalar processing module with the vector processing module and the matrix processing module, eliminating the need to deploy a separate module for instruction distribution in the processor. This simplifies the processor structure and avoids unnecessary data interaction caused by the instruction distribution module distributing scalar processing instructions in the instruction package to the scalar processing module. This ensures data interaction efficiency and enables the processor to respond quickly to the received processing instructions, thus ensuring the processor's data processing efficiency. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a processor provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of another processor structure provided in an embodiment of this application;

[0038] Figure 3 This is a schematic diagram of another processor provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of another processor provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of another processor provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of another processor provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of another processor provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of another processor provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram illustrating the interaction between different processing modules provided in an embodiment of this application;

[0045] Figure 10 This is a flowchart of a data processing method provided in an embodiment of this application;

[0046] Figure 11 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application;

[0047] Figure 12 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0049] The terms “first,” “second,” “third,” “fourth,” “fifth,” etc., used in this application may be used to describe various concepts herein, but unless otherwise specified, these concepts are not limited by these terms. These terms are used only to distinguish one concept from another. For example, without departing from the scope of this application, a first storage unit may be referred to as a second storage unit, and similarly, a second storage unit may be referred to as a first storage unit.

[0050] As used in this application, the terms "at least one," "multiple," "each," and "any" have the following meanings: at least one includes one, two, or more; multiple includes two or more; each refers to each of the corresponding multiple; and any refers to any one of the multiple. For example, multiple instructions include three instructions, where each refers to each of the three instructions, and any refers to any one of the three instructions, which could be the first instruction, the second instruction, or the third instruction.

[0051] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the instructions and data involved in this application were obtained under full authorization.

[0052] Figure 1 This is a schematic diagram of the structure of a processor provided in an embodiment of this application, such as... Figure 1 As shown, the processor includes a scalar processing module 101, a vector processing module 102, and a matrix processing module 103. The scalar processing module 101 is connected to the vector processing module 102 and the matrix processing module 103, respectively.

[0053] The processor will now be described based on the above sections.

[0054] (1) Scalar processing module 101: is used to receive an instruction packet containing multiple instructions, and in response to the scalar processing instructions in the instruction packet, process the scalar data indicated by the scalar processing instructions; send the vector processing instructions in the instruction packet to the vector processing module 102, and send the matrix processing instructions in the instruction packet to the matrix processing module 103.

[0055] In this embodiment, the processor is capable of processing data of multiple data types, including scalar, vector, and matrix types. Accordingly, the multiple data types include scalar data (i.e., scalar data), vector data (i.e., vector data), and matrix data (i.e., matrix data). The processor includes processing modules for processing multiple data types: a scalar processing module 101, a vector processing module 102, and a matrix processing module 103. The scalar processing module 101 executes processing instructions for scalar data; the vector processing module 102 executes processing instructions for vector data; and the matrix processing module 103 executes processing instructions for matrix data. The scalar processing module 101 in the processor can receive an instruction packet containing multiple instructions and execute the scalar processing instructions in the instruction packet. It can also, through connection with the vector processing module 102 and the matrix processing module 103, distribute processing instructions for other data types in the instruction packet to the vector processing module 102 or the matrix processing module 103, so that the vector processing module 102 executes the processing instructions for vector data, and the matrix processing module 103 executes the processing instructions for matrix data.

[0056] In this embodiment, the instruction package can be of any type, such as a VLIW (Very Long Instruction Word) instruction package. The multiple instructions included in the instruction package are processing instructions for at least one data type. For example, the instruction package may include multiple scalar processing instructions; or, at least one scalar processing instruction and at least one vector processing instruction; or, at least one scalar processing instruction and at least one matrix processing instruction; or, at least one scalar processing instruction, at least one vector processing instruction, and at least one matrix processing instruction.

[0057] Scalar processing instructions are for processing scalar data, meaning they indicate that the scalar data specified by the instruction should be processed. Vector processing instructions are for processing vector data, meaning they indicate that the vector data specified by the instruction should be processed. Matrix processing instructions are for processing matrix data, meaning they indicate that the matrix data specified by the instruction should be processed. Scalar, vector, and matrix processing instructions can all be processing instructions of any type, including load, store, or compute. Different types of instructions correspond to different processing methods: load type indicates data loading, store type indicates data storage, and compute type indicates data computation. In other words, scalar, vector, and matrix processing instructions all indicate that the specified data should be processed according to the indicated processing method.

[0058] For example, if the scalar processing instruction is a load-type instruction, indicating that the scalar data indicated by the scalar processing instruction is loaded into the scalar processing module 101, then the scalar processing module 101, in response to the scalar processing instruction, will load the scalar data indicated by the scalar processing instruction into the scalar processing module 101. Alternatively, if the scalar processing instruction is a calculation-type instruction, indicating that the scalar data indicated by the scalar processing instruction is calculated, then the scalar processing module 101, in response to the scalar processing instruction, will perform the calculation on the scalar data indicated by the scalar processing instruction. Or, if the scalar processing instruction is a storage-type instruction, indicating that the scalar data indicated by the scalar processing instruction is stored in a storage unit outside the processor, then the scalar processing module 101, in response to the scalar processing instruction, will send the scalar data indicated by the scalar processing instruction to the storage unit indicated by the scalar processing instruction, so that the storage unit indicates the scalar data stores the scalar data.

[0059] In this embodiment, the scalar processing module 101, the vector processing module 102, and the matrix processing module 103 can all be connected in any way, such as by electrical connection or other communication connection.

[0060] In one possible implementation, the instruction packet received by the scalar processing module 101 is sent by the first processing module. The first processing module is either a processing module in the processor other than the scalar processing module 101, the vector processing module 102, and the matrix processing module 103, or a processing module independently existing in a computer device including the processor, or a processing module in another processor in the computer device besides the processor itself.

[0061] In this embodiment of the application, during the process of processing the input data through the neural network model, the first processing module generates some processing instructions and sends the instruction packets to the scalar processing module 101 in the form of instruction packets, so that the scalar processing module 101 can receive the instruction packets.

[0062] (2) Vector processing module 102: used to receive vector processing instructions sent by scalar processing module 101, and in response to the vector processing instructions, process the vector data indicated by the vector processing instructions.

[0063] In this embodiment of the application, the vector processing module 102, through its connection with the scalar processing module 101, is able to receive vector processing instructions sent by the scalar processing module 101 and respond to the vector processing instructions so as to process the vector data indicated by the vector processing instructions according to the vector processing instructions.

[0064] For example, if the vector processing instruction is a load-type instruction, indicating that the vector data indicated by the vector processing instruction is loaded into the vector processing module 102, then the vector processing module 102, in response to the vector processing instruction, will load the vector data indicated by the vector processing instruction into the vector processing module 102. Alternatively, if the vector processing instruction is a calculation-type instruction, indicating that the vector data indicated by the vector processing instruction is calculated, then the vector processing module 102, in response to the vector processing instruction, will perform the calculation on the data indicated by the vector processing instruction. Or, if the vector processing instruction is a storage-type instruction, indicating that the vector data indicated by the vector processing instruction is stored in a storage unit outside the processor, then the vector processing module 102, in response to the vector processing instruction, will send the vector data indicated by the vector processing instruction to the storage unit indicated by the vector processing instruction, so that the storage unit indicates the vector data stores the vector data.

[0065] In one possible implementation, the scalar processing instruction instructs the processing of scalar data and sends the processing result to the vector processing module 102; the scalar processing module 101 is further configured to send the processing result corresponding to the scalar data to the vector processing module 102; the vector processing module 102 is further configured to receive the processing result corresponding to the scalar data; the vector processing module 102 is configured to process the vector data indicated by the vector processing instruction based on the processing result corresponding to the scalar data in response to the vector processing instruction.

[0066] In this embodiment, the scalar processing instruction not only instructs the scalar processing module 101 to process the scalar data indicated by the scalar processing instruction, but also instructs the processing result to be sent to the vector processing module 102. Furthermore, the vector processing instruction instructs the vector processing module 102 to process the vector data using the processing result corresponding to the scalar data. Therefore, the scalar processing module 101, in response to the scalar processing instruction, processes the scalar data indicated by the scalar processing instruction, obtains the processing result, and sends the processing result to the vector processing module 102 according to the scalar processing instruction. This enables the vector processing module 102 to process the vector data indicated by the vector processing instruction based on the processing result corresponding to the scalar data, thereby realizing a joint processing scheme between the scalar processing module 101 and the vector processing module 102. This improves the processor's data processing capability, and the scalar processing module 101 can directly send data (i.e., the processing result) to the vector processing module 102 without needing to transmit data through other storage media or other units, reducing unnecessary data interaction processes and thus ensuring data interaction efficiency.

[0067] Optionally, the process of processing the vector data indicated by the vector processing instruction based on the processing result corresponding to the scalar data includes: processing the processing result corresponding to the scalar data and the vector data indicated by the vector processing instruction.

[0068] In this embodiment of the application, the vector processing instruction indicates that the vector processing module 102 uses the processing result corresponding to the scalar data to process the vector data. Then, the vector processing module 102 processes the processing result corresponding to the scalar data and the vector data indicated by the vector processing instruction according to the vector processing instruction.

[0069] For example, the vector data indicated by the vector processing instruction is vector data 1, and the processing result corresponding to the scalar data is processing result 1. If the vector processing instruction instructs to multiply vector data 1 and processing result 1, then the vector processing module 102 will multiply vector data 1 and processing result 1 according to the vector processing instruction, and take the resulting product as the processing result corresponding to the vector processing instruction.

[0070] (3) Matrix processing module 103: used to receive matrix processing instructions sent by scalar processing module 101, and in response to the matrix processing instructions, process the matrix data indicated by the matrix processing instructions.

[0071] In this embodiment of the application, the matrix processing module 103, through its connection with the scalar processing module 101, is able to receive matrix processing instructions sent by the scalar processing module 101 and respond to the matrix processing instructions so as to process the matrix data indicated by the matrix processing instructions.

[0072] For example, if the matrix processing instruction is a load-type instruction, indicating that the matrix data indicated by the matrix processing instruction is loaded into the matrix processing module 103, then the matrix processing module 103, in response to the matrix processing instruction, will load the matrix data indicated by the matrix processing instruction into the matrix processing module 103. Alternatively, if the matrix processing instruction is a calculation-type instruction, indicating that the matrix data indicated by the matrix processing instruction is calculated, then the matrix processing module 103, in response to the matrix processing instruction, will perform the calculation on the matrix data indicated by the matrix processing instruction. Or, if the matrix processing instruction is a storage-type instruction, indicating that the matrix data indicated by the matrix processing instruction is stored in a memory unit outside the processor, then the matrix processing module 103, in response to the matrix processing instruction, will send the matrix data indicated by the matrix processing instruction to the memory unit indicated by the matrix processing instruction, so that the memory unit indicates the matrix data stores the matrix data.

[0073] In the solution provided in this application embodiment, the processor has the function of executing processing instructions for data of various data types. The scalar processing module in the processor not only has the function of executing processing instructions for scalar data, but also has the function of instruction distribution. It can distribute vector processing instructions in the instruction package to the vector processing module and matrix processing instructions in the instruction package to the matrix processing module. This couples the scalar processing module with the vector processing module and the matrix processing module, eliminating the need to deploy a separate module for instruction distribution in the processor. This simplifies the processor structure and avoids unnecessary data interaction caused by the instruction distribution module distributing scalar processing instructions in the instruction package to the scalar processing module. This ensures data interaction efficiency and enables the processor to respond quickly to the received processing instructions, thus ensuring the processor's data processing efficiency.

[0074] In the above Figure 1 Based on the illustrated embodiments, in this application embodiment, the scalar processing module 101 includes a scalar processing unit 1101 and a distribution unit 1102, such as... Figure 2 As shown, the scalar processing unit 1101 is connected to the distribution unit 1102, and the distribution unit 1102 is connected to the vector processing module 102 and the matrix processing module 103 respectively.

[0075] In this embodiment, the scalar processing unit 1101 in the scalar processing module 101 has the function of responding to scalar processing instructions, and the distribution unit 1102 has the function of distributing instructions to the vector processing module 102 and the matrix processing module 103. The scalar processing unit 1101 and the distribution unit 1102 can be connected in any way, for example, by electrical connection or other communication connection. The scalar processing unit 1101 and the distribution unit 1102 can transmit data through the connection between them.

[0076] The processor will now be described based on the above sections.

[0077] (1) Scalar processing unit 1101: is used to receive an instruction packet including multiple instructions, process the scalar data indicated by the scalar processing instruction in response to the scalar processing instruction, and send vector processing instructions and matrix processing instructions to the distribution unit 1102.

[0078] In this embodiment, the scalar processing unit 1101 can receive an instruction packet sent by the first processing module, which includes multiple instructions, and then respond to the scalar processing instructions in the instruction packet. Furthermore, the instruction packet may include vector processing instructions or matrix processing instructions. If the instruction packet includes at least one of vector processing instructions or matrix processing instructions, it can send other processing instructions in the instruction packet to the distribution unit 1102, so that the distribution unit 1102 can subsequently distribute the other processing instructions in the instruction packet to the corresponding processing modules.

[0079] The scalar processing unit 1101 can be any type of processing unit, for example, the scalar processing unit 1101 is an ALU (Arithmetic Logic Unit). The dispatch unit 1102 can be any unit with instruction dispatching function.

[0080] The first processing module is a processing module in the processor other than the scalar processing module 101, the vector processing module 102, and the matrix processing module 103, or it is a processing module that exists independently in a computer device including the processor, or it is a processing module in another processor in the computer device other than the processor.

[0081] In this embodiment of the application, during the process of processing the input data through the neural network model, the first processing module generates some processing instructions and sends the instruction packets to the scalar processing unit 1101 in the form of instruction packets, so that the scalar processing unit 1101 can receive the instruction packets.

[0082] In one possible implementation, the scalar processing instruction includes operation information and address information. The address information indicates the storage address of the scalar data indicated by the scalar processing instruction, and the operation information indicates the processing method, such as addition or subtraction.

[0083] In the embodiments of this application, the scalar processing instruction includes operation information and address information. The scalar processing instruction instructs the scalar data in the storage address indicated by the address information to be processed according to the processing method indicated by the operation information.

[0084] In one possible implementation, the scalar processing module 101 includes multiple scalar processing units 1101 connected sequentially, with the last scalar processing unit 1101 connected to the distribution unit 1102. The first scalar processing unit 1101 receives instruction packets containing multiple instructions and responds to the scalar processing instructions to complete partial scalar data processing. Then, it passes the instruction packets to the next scalar processing unit 1101 so that the next scalar processing unit 1101 can continue to respond to the scalar processing instructions, and so on. The last scalar processing unit 1101 can complete the response to the scalar processing instructions in the instruction packet and send vector processing instructions and matrix processing instructions to the distribution unit 1102.

[0085] For example, the scalar processing module 101 includes three scalar processing units 1101. The first scalar processing unit 1101 is connected to the second scalar processing unit 1101, the second scalar processing unit 1101 is connected to the third scalar processing unit 1101, and the third scalar processing unit 1101 is connected to the distribution unit 1102. For example, the scalar processing unit 1101 is an ALU, and the scalar processing module 101 includes three ALUs.

[0086] Optionally, the multiple instructions in the instruction package include multiple scalar processing instructions, and multiple scalar processing units 1101 are used to respond to these multiple scalar processing instructions, and each scalar processing unit 1101 is used to respond to at least one scalar processing instruction.

[0087] In one possible implementation, the scalar processing module 101 includes a sixth storage unit for storing the processing result corresponding to the scalar data. The sixth storage unit can be any type of memory.

[0088] In one possible implementation, the scalar processing module 101 includes a register connected to the scalar processing unit 1101, and the register is used to store data.

[0089] For example, a scalar processing instruction is a data load instruction. In response to a data load instruction, the scalar processing instruction can load the data indicated by the data load instruction into the register; or, a scalar processing instruction is a data calculation instruction. In response to a data load instruction, the scalar processing instruction reads the data indicated by the data calculation instruction from the register, performs the calculation, and writes the calculation result back into the register.

[0090] Optionally, the scalar processing module 101 includes a register file (RF), which is connected to the scalar processing unit 1101. The register file is also called a register archive. The register file includes registers, and the register file is capable of reading and writing data to the included registers. The register file is used to read and write scalar data indicated by address information in scalar processing instructions. The scalar processing unit 1101 is used to process the scalar data indicated by address information in response to operation information in scalar processing instructions.

[0091] The address information indicates the address in the registers included in the register file, and the address indicated by the address information is the storage address of the scalar data indicated by the scalar processing instruction.

[0092] For example, a scalar processing instruction is a data calculation instruction. This instruction includes operation information and address information. The register file, in response to the address information, reads the scalar data indicated by the address information from the included registers and sends the read scalar data to the scalar processing unit 1101. The scalar processing unit 1101 receives the scalar data sent from the register file and, in response to the operation information, performs calculations on the scalar data according to the processing method indicated by the operation information. Furthermore, the scalar processing unit 1101 also sends the calculation result to the register file after the scalar data calculation is completed. The register file receives the calculation result and stores it in registers.

[0093] Optionally, the register file includes multiple registers and a controller for managing data reads and writes to the multiple registers. The controller, in response to address information, reads scalar data indicated by the address information from the included registers and sends the read scalar data to the scalar processing unit 1101. The controller also receives calculation results and stores the calculation results in registers.

[0094] (2) Distribution unit 1102: used to receive vector processing instructions and matrix processing instructions sent by scalar processing unit 1101, send vector processing instructions to vector processing module 102, and send matrix processing instructions to matrix processing module 103.

[0095] In this embodiment, the distribution unit 1102 can send the received processing instructions to the corresponding processing module according to the data type targeted by the processing instructions, so that the vector processing module 102 or the matrix processing module 103 can respond to the received processing instructions. When the distribution unit 1102 receives a vector processing instruction, it can distribute the vector processing instruction to the vector processing module 102; when the distribution unit 1102 receives a matrix processing instruction, it can distribute the matrix processing instruction to the matrix processing module 103, ensuring that the distributed processing instructions can be responded to by the receiving processing module and guaranteeing the accuracy of instruction distribution.

[0096] In this embodiment, the scalar processing module includes a scalar processing unit and a distribution unit. The scalar processing unit is connected to the distribution unit, which is connected to both the vector processing module and the matrix processing module. The scalar processing unit can receive an instruction packet containing multiple instructions and respond to the scalar processing instructions in the instruction packet. Furthermore, if the instruction packet includes at least one of vector processing instructions or matrix processing instructions, it can send other processing instructions in the instruction packet to the distribution unit, so that the distribution unit can subsequently distribute the other processing instructions in the instruction packet to the corresponding processing modules. This enables the processor to not only execute processing instructions for various data types but also to distribute vector processing instructions to the vector processing module and matrix processing instructions to the matrix processing module. This ensures that the distributed processing instructions are responded to by the receiving processing modules, guarantees the accuracy of instruction distribution, simplifies the processor structure, reduces unnecessary data interaction processes, and ensures data interaction efficiency.

[0097] In the above Figure 2 Based on the illustrated embodiments, in this application embodiment, the scalar processing module 101 includes a decoding unit 1103, such as... Figure 3 As shown, the decoding unit 1103 is connected to the scalar processing unit 1101.

[0098] In this embodiment, the decoding unit 1103 and the scalar processing unit 1101 can be connected in any manner, such as by electrical connection or other communication connection. The decoding unit 1103 has the function of receiving instruction packets and decoding the scalar processing instructions in the instruction packets, and can decode the scalar processing instructions into processing instructions that the scalar processing unit 1101 can respond to.

[0099] The processor will now be described based on the above sections.

[0100] (1) Decoding unit 1103: is used to receive an instruction packet containing multiple instructions, decode the scalar processing instructions; and send the decoded scalar processing instructions, vector processing instructions and matrix processing instructions to the scalar processing unit 1101 when the decoded scalar processing instructions are obtained.

[0101] In this embodiment, the decoding unit 1103 can receive an instruction packet sent by the first processing module, which includes multiple instructions, and decode the scalar processing instructions in the instruction packet to obtain the decoded scalar processing instructions. It can also send the decoded scalar processing instructions, the vector processing instructions in the instruction packet, and the matrix processing instructions in the instruction packet to the scalar processing unit 1101 through a connection with the scalar processing unit 1101. The scalar processing unit 1101 is used to receive instructions sent by the decoding unit 1103, that is, it can receive the decoded scalar processing instructions, the vector processing instructions in the instruction packet, and the matrix processing instructions in the instruction packet. Subsequently, the scalar processing unit 1101 can respond to the decoded scalar processing instructions and can also send the vector processing instructions and matrix processing instructions to the distribution unit 1102.

[0102] The decoding unit 1103 can be any type of unit, for example, the decoding unit 1103 is a DEC (Decoder).

[0103] In this embodiment of the application, considering that the scalar processing instructions in the instruction packet may be instructions that the scalar processing unit 1101 cannot directly respond to, the decoding unit 1103 decodes the scalar processing instructions in the instruction packet after receiving the instruction packet to obtain the processing instructions that the scalar processing unit 1101 can respond to, that is, to obtain the decoded scalar processing instructions.

[0104] In one possible implementation, the processor includes an instruction packet cache unit and an instruction packet fetch unit. The instruction packet cache unit is connected to the instruction packet fetch unit, and the instruction packet fetch unit is connected to the decoding unit 1103. The instruction packet cache unit is connected to the bus in the processor and is used to receive and cache instruction packets transmitted by the first processing module via the bus. The instruction packet fetch unit is used to extract the cached instruction packets from the instruction packet cache unit and send the extracted instruction packets to the decoding unit 1103 through its connection with the decoding unit 1103. The decoding unit 1103 is used to receive the instruction packets sent by the instruction fetch unit.

[0105] Optionally, the instruction packet caching unit is a VLIW Instruction Cache (Very Long InstructionWord Instruction Cache), and the instruction packet fetching unit is a VLIW InstructionFetch Unit (Very Long Instruction Word Instruction Fetch Unit).

[0106] (2) Scalar processing unit 1101: is used to receive the decoded scalar processing instruction, vector processing instruction and matrix processing instruction sent by the decoding unit 1103, and in response to the decoded scalar processing instruction, process the scalar data indicated by the decoded scalar processing instruction; when the scalar data indicated by the decoded scalar processing instruction has been processed, it sends the vector processing instruction and matrix processing instruction to the distribution unit 1102.

[0107] In this embodiment, the scalar processing unit 1101 receives decoded scalar processing instructions, vector processing instructions, and matrix processing instructions sent by the decoding unit 1103, which is equivalent to receiving an instruction packet including multiple instructions. If the decoded scalar processing instructions are processing instructions that the scalar processing unit 1101 can respond to, then it can process the scalar data indicated by the decoded scalar processing instructions; while the vector processing instructions and matrix processing instructions are processing instructions that the scalar processing unit 1101 cannot respond to, then it sends the vector processing instructions and matrix processing instructions to the distribution unit 1102 through the connection between the two units, so that the subsequent distribution unit 1102 can distribute the vector processing instructions and matrix processing instructions to the corresponding processing modules.

[0108] In one possible implementation, the scalar processing module 101 includes a register file, and a decoding unit 1103 is connected to the register file, which in turn is connected to the scalar processing unit 1101. The decoded scalar processing instructions include operation information and address information. The decoding unit 1103 is used to send the address information to the register file and to the scalar processor, as well as to send the address information, vector processing instructions, and matrix processing instructions. The register file is used to read and write the scalar data indicated by the address information in the scalar processing instructions. The scalar processing unit 1101 is used to process the scalar data indicated by the address information in response to the operation information in the scalar processing instructions, and to send the vector processing instructions and matrix processing instructions to the dispatch unit 1102.

[0109] For example, the decoded scalar processing instructions are data calculation instructions, which include operation information and address information. The decoding unit 1103 is used to send the address information to the register file and to the scalar processor, along with vector processing instructions and matrix processing instructions. The register file, in response to the address information, reads the scalar data indicated by the address information from the included registers and sends the read scalar data to the scalar processing unit 1101. The scalar processing unit 1101 receives the scalar data sent from the register file and, in response to the operation information, performs calculations on the scalar data according to the processing method indicated by the operation information. Furthermore, the scalar processing unit 1101 also sends the calculation result to the register file after the scalar data calculation is completed; the register file receives the calculation result and stores it in registers.

[0110] In one possible implementation, the scalar processing module 101 includes multiple scalar processing units 1101 connected sequentially. The decoding unit 1103 is connected to the first scalar processing unit 1101, and the last scalar processing unit 1101 is connected to the distribution unit 1102. The first scalar processing unit 1101 receives decoded scalar processing instructions, vector processing instructions, and matrix processing instructions sent by the decoding unit 1103, and responds to the decoded scalar processing instructions to complete partial scalar data processing. Then, it passes the decoded scalar processing instructions, vector processing instructions, and matrix processing instructions to the next scalar processing unit 1101 so that the next scalar processing unit 1101 can continue to respond to the decoded scalar processing instructions, and so on. The last scalar processing unit 1101 can complete the response to the scalar processing instructions in the instruction packet and can send vector processing instructions and matrix processing instructions to the distribution unit 1102.

[0111] Optionally, the multiple instructions in the instruction packet include a scalar processing instruction. The decoding unit 1103 is used to decode the scalar processing instruction to obtain multiple sub-scalar processing instructions, and sends the multiple sub-scalar processing instructions to the first scalar processing unit 1101. The multiple scalar processing units 1101 are used to respond to the multiple sub-scalar processing instructions, and each scalar processing unit 1101 is used to respond to at least one sub-scalar processing instruction.

[0112] In this embodiment, the scalar processing module includes a decoding unit connected to the scalar processing unit. The decoding unit can receive an instruction packet containing multiple instructions. Considering that the scalar processing instructions in the instruction packet may be instructions that the scalar processing unit cannot directly respond to, the decoding unit decodes the scalar processing instructions in the instruction packet. After obtaining the decoded scalar processing instructions, the decoding unit sends the decoded scalar processing instructions, the vector processing instructions in the instruction packet, and the matrix processing instructions in the instruction packet to the scalar processing unit through the connection with the scalar processing unit. This enables the scalar processing unit to respond to the received scalar processing instructions, ensuring that the scalar processing unit can accurately respond to the scalar processing instructions, thereby ensuring the possibility and accuracy of the processor responding to the processing instructions.

[0113] Furthermore, in this processor architecture, the vector processing module and matrix processing module are placed after the scalar processing module. This processor architecture ensures that the distribution unit only distributes the vector processing instruction or matrix processing instruction to the vector processing module and matrix processing module respectively after the scalar processing unit has completed its response to the scalar processing instruction. A successful response from the scalar processing unit reflects a successful response from the vector processing module, and also reflects a successful response from the matrix processing module. This ensures that the processing instructions received by the vector processing module and matrix processing module are the required processing instructions, avoiding situations where the vector processing module or matrix processing module fails to respond to the received processing instructions, thus avoiding waste of processor resources. In addition, the scalar processing instructions in the instruction packet have a small computational load, so even if the scalar processing unit fails to respond to the scalar processing instruction, it will not cause the processor to incur excessive additional computational costs, ensuring the processor's response efficiency to the instruction packet.

[0114] It should be noted that the above Figure 3 The illustrated embodiment uses the connection between the decoding unit 1103, the scalar processing unit 1101, and the distribution unit 1102 to send the vector processing instructions and matrix processing instructions in the received instruction packet to the distribution unit 1102. In another embodiment, the decoding unit 1103 can also send the vector processing instructions and matrix processing instructions in the received instruction packet to the distribution unit 1102 in other ways.

[0115] In one possible implementation, in the scalar processing module 101, a decoding unit 1103 is connected to the scalar processing unit 1101, and a distribution unit 1102 is also connected to the scalar processing unit 1101. The decoding unit 1103 receives an instruction packet containing multiple instructions, decodes the scalar processing instructions in the instruction packet to obtain the decoded scalar processing instructions, and sends the decoded scalar processing instructions to the scalar processing unit 1101 through its connection with the scalar processing unit 1101; it also sends the vector processing instructions and matrix processing instructions from the instruction packet to the distribution unit 1102 through its connection with the distribution unit 1102. The distribution unit 1102 receives the vector processing instructions and matrix processing instructions sent by the decoding unit 1103. The scalar processing unit 1101 is configured to receive decoded scalar processing instructions, process the scalar data indicated by the scalar processing instructions in response to the scalar processing instructions in the instruction packet, and send a response completion signal to the distribution unit 1102 upon completion of processing the scalar data indicated by the scalar processing instructions. The distribution unit 1102 is further configured to send vector processing instructions to the vector processing module 102 and matrix processing instructions to the matrix processing module 103 upon receiving the response completion signal.

[0116] In this embodiment of the application, the decoding unit 1103 is capable of receiving an instruction packet sent by the first processing module, which includes multiple instructions.

[0117] It should be noted that the above description uses the example of the scalar processing unit 1101 sending a response completion signal to the distribution unit 1102 after completing the processing of the scalar data indicated by the scalar processing instruction. In another embodiment, the scalar processing unit 1101 can also use other methods to notify the distribution unit 1102 to distribute vector processing instructions or matrix processing instructions. In one possible implementation, the scalar processing module 101 includes a status register, which is connected to both the scalar processing unit 1101 and the distribution unit 1102. The status register stores flag bits, and the values ​​of the flag bits indicate whether the scalar processing unit 1101 has completed responding to the scalar processing instruction. The distribution unit 1102 is further configured to, upon receiving a vector processing instruction or matrix processing instruction sent by the decoding unit 1103, detect the flag bits in the status register in real time. If the value of the flag bits in the status register indicates that the scalar processing unit 1101 has completed responding to the scalar processing instruction, the distribution unit 1102 sends a vector processing instruction to the vector processing module 102 and a matrix processing instruction to the matrix processing module 103.

[0118] In the above Figure 3 Based on the illustrated embodiment, in this embodiment of the application, the vector processing module 102 includes a transport unit 1201, a first storage unit 1202, and a register 1203, such as... Figure 4 As shown, the transport unit 1201 is connected to the first storage unit 1202, the register 1203 and the decoding unit 1103 respectively.

[0119] In this embodiment, the data transfer unit 1201 has a data transfer function, enabling data transfer between the first storage unit 1202 and the register 1203 through its connection with the first storage unit 1202 and the register 1203. The data transfer unit 1201 is also connected to the decoding unit 1103, which can send a vector loading instruction to the data transfer unit 1201 if the vector processing instruction in the instruction packet includes a vector loading instruction. The register 1203 stores the data or calculation results required by the vector processing module 102, and the first storage unit 1202 stores vector data.

[0120] Register 1203 can be any type of register, for example, register 1203 can be a register in VRF (VectorRegisterFile). Transfer unit 1201 can be any unit with data transfer function, for example, transfer unit 1201 can be VLSU (Vector Load Store Unit).

[0121] The processor will now be described based on the above sections.

[0122] (1) Decoding unit 1103: It is also used to send a vector loading instruction to transport unit 1201 when the vector processing instruction in the instruction packet includes a vector loading instruction.

[0123] In this embodiment, when the vector processing instructions in the instruction packet include vector loading instructions, the decoding unit 1103 can directly send vector loading instructions to the transport unit 1201 through the connection between the decoding unit 1103 and the transport unit 1201, so that the transport unit 1201 can respond to the vector loading instructions in a timely manner and ensure the real-time loading of vector data.

[0124] (2) Transport unit 1201: is used to receive the vector loading instruction sent by the decoding unit 1103, and in response to the vector loading instruction, read the vector data indicated by the vector loading instruction from the first storage unit 1202 and load the read vector data into the register 1203.

[0125] In this embodiment, the transport unit 1201 is capable of responding to a vector loading instruction. The vector loading instruction indicates the data stored in the first storage unit 1202. In response to the vector loading instruction, the transport unit 1201 loads the data from the first storage unit 1202 into the register 1203, so that the subsequent vector processing module 102 can perform calculations or other processing on the data in the register 1203, thereby realizing data transport between the register 1203 and the first storage unit 1202.

[0126] In one possible implementation, the vector load instruction instructs the data to be moved from the first address to the second address, where the first address is the address in the first storage unit 1202 and the second address is the address in the register. Then, the moving unit 1201 is used to read the vector data from the first address in response to the vector load instruction and store the read vector data in the second address of the register 1203.

[0127] Optionally, the vector processing module 102 includes a vector register file connected to the transport unit 1201, and register 1203 is a register in the VRF (Vector Register File). Register 1203 is any one of multiple registers included in the vector register file. The transport unit 1201 is used to read vector data from the first storage unit 1202 at a first address in response to a vector load instruction, and send the read vector data to the vector register file. The vector register file is used to receive the vector data and store the vector data at a second address.

[0128] Optionally, the vector register file includes multiple registers and a controller, which manages data reading and writing to the multiple registers. The transfer unit 1201 is used to send the read vector data to the controller in the vector register file. The controller receives the vector data and stores it in a second address.

[0129] In this embodiment, the vector processing module includes a transport unit, a register, and a first storage unit. When the vector processing instruction in the received instruction packet includes a vector loading instruction, the decoding unit in the scalar processing module directly sends the vector loading instruction to the transport unit through the connection with the transport unit. This eliminates the need for the distribution unit to distribute the vector loading instruction to the vector processing module, enabling the transport unit to respond to the vector loading instruction in a timely manner, ensuring the real-time performance of vector loading, and thus ensuring the response efficiency of the vector loading instruction.

[0130] In the above Figure 1Based on the illustrated embodiment, in this embodiment of the application, the vector processing module 102 includes a register 1203, a vector processing unit 1204, a transport unit 1201, and a first storage unit 1202, such as... Figure 4 As shown, register 1203 is connected to vector processing unit 1204, vector processing unit 1204 is connected to transport unit 1201, and transport unit 1201 is connected to first storage unit 1202; vector processing instructions include vector storage instructions.

[0131] The processor will now be described based on the above sections.

[0132] (1) Vector processing unit 1204: Used to receive vector processing instructions sent by distribution unit 1102. If the vector processing instructions include vector storage instructions, in response to the vector storage instructions, it reads the vector data indicated by the vector storage instructions from register 1203 and sends the read vector data to transport unit 1201. (2) Transport unit 1201: Used to receive the read vector data sent by vector processing unit 1204 and send the read vector data to first storage unit 1202. (3) First storage unit 1202: Used to receive the read vector data sent by transport unit 1201 and store the read vector data.

[0133] In this embodiment, the vector processing unit 1204 is used to respond to vector processing instructions. The vector processing unit 1204 can be any type of processing unit, for example, the vector processing unit 1204 is a VALU (Vector Arithmetic Logic Unit). The first storage unit 1202 is any type of memory.

[0134] In this embodiment, the vector processing module includes a register, a vector processing unit, a transport unit, and a first storage unit. The vector processing unit can receive vector processing instructions sent by the scalar processing module. When the vector processing instruction is a vector storage instruction, the vector processing unit can respond to the vector storage instruction by reading vector data from the register and sending it to the transport unit. The transport unit then stores the read vector data in the first storage unit to realize data transport between the register and the first storage unit and to realize data storage in the first storage unit. This enables the vector processing module to respond to the vector processing instructions, ensuring the accuracy of data storage and the response efficiency of the vector storage instructions.

[0135] In one possible implementation, the vector processing module 102 includes a vector register file, which is connected to both the transport unit 1201 and the vector processing unit 1204. Register 1203 is any one of multiple registers included in the vector register file. The vector storage instruction includes operation information and address information. The address information indicates the address in register 1203, and the address indicated by the address information stores the vector data indicated by the vector storage instruction. The operation information indicates the storage method.

[0136] The register file is used to read the vector data indicated by the vector storage instruction from register 1203 in response to the address information in the vector storage instruction, and send the read vector data to the vector processing unit 1204. The vector processing unit 1204 is used to receive the read vector data sent from the register file in response to the vector storage instruction, and send the read vector data to the transfer unit 1201.

[0137] Optionally, the vector register file includes multiple registers and a controller, which manages data reading and writing of the multiple registers. The controller, in response to address information in a vector store instruction, reads the vector data indicated by the vector store instruction from register 1203 and sends the read vector data to the vector processing unit 1204.

[0138] It should be noted that the above description uses vector storage instructions as an example of vector processing instructions. In another embodiment, vector processing instructions can also be instructions of other processing types. For example, if the vector processing instruction is a vector calculation instruction, then the vector processing unit 1204 responds to the vector calculation instruction and performs calculations on the vector data indicated by the vector calculation instruction.

[0139] For example, if a vector calculation instruction instructs the calculation of data stored in register 1203 and the calculation result is stored in register 1203, then the vector processing unit 1204 responds to the vector calculation instruction by reading the vector data indicated by the vector calculation instruction from register 1203, performing calculation on the read vector data, obtaining the calculation result, and sending the calculation result to register 1203, which stores the calculation result.

[0140] For example, if a vector calculation instruction instructs the calculation of data stored in register 1203 and the calculation result to be stored in the first storage unit 1202, then the vector processing unit 1204, in response to the vector calculation instruction, reads the vector data indicated by the vector calculation instruction from register 1203, performs calculations on the read vector data, obtains the calculation result, and sends the calculation result to the transfer unit 1201. The transfer unit 1201 is used to receive the calculation result and send the calculation result to the first storage unit 1202. The first storage unit 1202 stores the calculation result.

[0141] In one possible implementation, the scalar processing module 101 includes a distribution unit 1102, and the vector processing module 102 includes a vector decoding unit 1205, such as... Figure 4 As shown, the distribution unit 1102 is connected to the vector decoding unit 1205, and the vector decoding unit 1205 is connected to the vector processing unit 1204. The vector decoding unit 1205 receives vector processing instructions sent by the distribution unit 1102, decodes the vector processing instructions to obtain decoded vector processing instructions, and sends the decoded vector processing instructions to the vector processing unit 1204. The vector processing unit 1204 processes the vector data indicated by the decoded vector processing instructions in response to the decoded vector processing instructions.

[0142] The vector processing instructions are either vector calculation instructions or vector storage instructions. The vector decoding unit 1205 decodes the received vector processing instructions to obtain processing instructions that the vector processing unit 1204 can respond to. The vector decoding unit 1205 can be any type of decoding unit; for example, the vector decoding unit is a VDEC (VectorDecoder).

[0143] In this embodiment, the vector processing unit includes a vector decoding unit connected to the vector processing unit. The vector decoding unit can receive vector processing instructions sent by the distribution unit. Considering that the vector processing instructions in the instruction packet may be instructions that the vector processing unit cannot directly respond to, the vector decoding unit decodes the vector processing instructions. After obtaining the decoded vector processing instructions, it sends the decoded vector processing instructions to the vector processing unit through the connection with the vector processing unit, so that the vector processing unit can respond to the received vector processing instructions, ensuring that the vector processing unit can accurately respond to the vector processing instructions, thereby ensuring the possibility and accuracy of the processor responding to the processing instructions.

[0144] Optionally, the vector processing module 102 includes a transmitting unit, a vector decoding unit 1205 connected to the transmitting unit, and the transmitting unit connected to the vector processing unit 1204. The vector decoding unit 1205 is used to receive vector processing instructions sent by the distribution unit 1102, decode the vector processing instructions to obtain decoded vector processing instructions, and send the decoded vector processing instructions to the transmitting unit. The transmitting unit is used to receive the decoded vector processing instructions sent by the vector decoding unit 1205, determine whether the current vector processing instructions meet the transmission conditions, and only send the vector processing instructions to the vector processing unit 1204 if the current vector processing instructions meet the transmission conditions.

[0145] The issuing unit can be of any type, such as an Issue (issuance). The issuance condition refers to the priority of the vector processing instruction and the conditions that the dependent data must meet. For example, if the vector processing instruction is the highest priority instruction among the instructions to be processed by the current vector processing unit 1204, the vector processing instruction meets the issuance condition. Another example is when the vector processing instruction depends on the processing results of other processing instructions, such as the processing result of a scalar processing instruction. That is, the vector processing instruction instructs to process the indicated vector data based on the processing result of the scalar processing instruction; if the vector processing unit has already obtained the processing result of the scalar processing instruction, indicating that the data dependent on the vector processing instruction has been obtained, then the vector processing instruction meets the issuance condition.

[0146] In this embodiment, the vector decoding unit and the vector processing unit are connected through the transmitting unit, which can ensure that the vector processing instructions received by the vector processing unit are executable instructions, avoid the situation where the instructions received by the vector processing unit cannot be executed and cause blocking, ensure the smooth execution of vector processing instructions, and ensure the performance of the processor.

[0147] In the above Figure 1 Based on the illustrated embodiments, in this application embodiment, the matrix processing module 103 includes a fourth storage unit 1301, a loading unit 1302, and a matrix processing unit 1303, with a processor such as... Figure 5 As shown, the loading unit 1302 is connected to the fourth storage unit 1301 and the matrix processing unit 1303 respectively.

[0148] In this embodiment, the fourth storage unit 1301 stores matrix data to be processed by the matrix processing unit 1303. The loading unit 1302 has a data loading function, capable of loading the matrix data in the fourth storage unit 1301 into the matrix processing unit 1303 for processing. The matrix processing unit 1303 responds to matrix processing instructions and processes the matrix data indicated by the instructions. The loading unit 1302 can be connected to both the fourth storage unit 1301 and the matrix processing unit 1303 in any manner, such as by electrical connection or other communication connection. The fourth storage unit 1301 can be any type of memory.

[0149] The processor will now be described based on the above sections.

[0150] (1) Loading unit 1302: Used to receive matrix processing instructions sent by scalar processing module 101, and in response to the matrix processing instructions, read the matrix data indicated by the matrix processing instructions from the fourth storage unit 1301, and send the read matrix data to matrix processing unit 1303. (2) Matrix processing unit 1303: Used to process the read matrix data.

[0151] The matrix processing unit 1303 can be any type of processing unit. For example, the matrix processing unit 1303 includes a Systolic Array and an accumulation unit. The Systolic Array is used to calculate the input matrix data, and the accumulation unit is used to accumulate the data output by the Systolic Array.

[0152] In this embodiment of the application, the matrix processing instruction has indicated the matrix data stored in the fourth storage unit 1301. Then, the loading unit 1302 can respond to the matrix processing instruction and load the matrix data indicated by the matrix processing instruction into the matrix processing unit 1303 so that the matrix processing unit 1303 can process the matrix data and enable the matrix processing module 103 to respond to the matrix processing instruction.

[0153] In this embodiment of the application, the matrix processing module includes a fourth storage unit, a loading unit, and a matrix processing unit. The loading unit can receive matrix processing instructions sent by the scalar processing module. In response to the matrix processing instructions, the loading unit reads the matrix data indicated by the matrix processing instructions from the fourth storage unit and loads it into the matrix processing unit so that the matrix processing unit can process the matrix data. This enables the matrix processing module to respond to the matrix processing instructions, ensuring the accuracy of matrix data processing and the efficiency of matrix processing instruction response.

[0154] In one possible implementation, the scalar processing module 101 includes a distribution unit 1102, and the matrix processing module 103 includes a matrix decoding unit and an address generation unit. The distribution unit 1102 is connected to the matrix decoding unit, the matrix decoding unit is connected to the address generation unit, and the address generation unit is connected to the loading unit 1302. The matrix decoding unit receives matrix processing instructions sent by the distribution unit 1102, decodes the matrix processing instructions to obtain decoded matrix processing instructions, and sends the decoded matrix processing instructions to the address generation unit. The address generation unit, in response to the decoded matrix processing instructions, generates an access request containing an access address and sends the access request to the loading unit 1302. The loading unit 1302, in response to the access request, accesses the fourth storage unit 1301, reads matrix data from the fourth storage unit 1301 at the access address, and sends the read matrix data to the matrix processing unit 1303.

[0155] The access address is the address in the fourth storage unit 1301, which is also the address indicated by the matrix processing instruction. The matrix processing instruction instructs the processing of the matrix data in the access address. Optionally, the matrix processing instruction is a matrix calculation instruction. The matrix decoding unit is used to decode the received matrix processing instruction to obtain the processing instruction that the address generation unit can respond to. The matrix decoding unit can be any type of decoding unit; for example, the matrix decoding unit is an MDEC (Matrix Decoder). The address generation unit (AGU) can be any type of unit.

[0156] In this embodiment, the matrix processing unit includes a matrix decoding unit and an address generation unit. Considering that the matrix processing instructions in the instruction packet may be instructions that the matrix processing unit cannot directly respond to, the matrix decoding unit decodes the matrix processing instructions. After obtaining the decoded matrix processing instructions, it sends the decoded matrix processing instructions to the address generation unit through a connection with the address generation unit, so that the address generation unit can respond to the received matrix processing instructions, thereby generating an access request and sending the access request to the loading unit. This allows the loading unit to respond to the access request, access the accurate matrix data from the fourth storage unit, and load it into the matrix processing unit. This ensures the accuracy of the matrix data in the matrix processing unit, ensures that the matrix processing unit can accurately respond to the matrix processing instructions, and thus ensures the possibility and accuracy of the processor responding to the processing instructions.

[0157] In one possible implementation, the matrix data read by the loading unit 1302 from the fourth storage unit 1301 includes feature data and weight data; the loading unit 1302 includes a feature loading subunit 1321 and a weight loading subunit 1322, such as Figure 6 As shown, the feature loading subunit 1321 is connected to the fourth storage unit 1301 and the matrix processing unit 1303, respectively, and the weight loading subunit 1322 is connected to the fourth storage unit 1301 and the matrix processing unit 1303, respectively.

[0158] In this embodiment, the feature loading subunit is used to load feature data from the fourth storage unit 1301 into the matrix processing unit 1303, and the weight loading subunit is used to load weight data from the fourth storage unit 1301 into the matrix processing unit 1303. For example, the loading subunit is an FM_Load Unit (Feature MapLoad Unit), and the weight loading subunit is a Weight Load Unit. These units can be connected in any way, for example, by electrical connection or communication connection.

[0159] The processor will now be described based on the above sections.

[0160] (1) Feature loading subunit 1321: In response to matrix processing instructions, it reads feature data from the fourth storage unit 1301 and sends the feature data to the matrix processing unit 1303. (2) Weight loading subunit 1322: In response to matrix processing instructions, it reads weight data from the fourth storage unit 1301 and sends the weight data to the matrix processing unit 1303. (3) Matrix processing unit 1303: It receives feature data and weight data and fuses the feature data and weight data.

[0161] Feature data represents a certain characteristic and can be any feature data to be processed. For example, in a network model scenario, feature data is the input data of the network model, or the input data of a certain network layer in the network model, or the data obtained in a certain step of the process of processing the input data by the network layer. Weight data represents the weight of the feature data.

[0162] In this embodiment of the application, the matrix processing instruction instructs the fusion of feature data and weight data in the fourth storage unit. The loading unit includes a feature loading subunit and a weight loading subunit. The feature loading subunit and the weight subunit respond to the matrix processing instruction respectively so as to load the feature data and weight data into the matrix processing unit, so that the matrix processing unit can fuse the feature data and weight data and ensure the accuracy of the matrix processing module's response to the matrix processing instruction.

[0163] In one possible implementation, the matrix processing module 103 includes a fifth storage unit 1304, such as... Figure 6 As shown, the fifth storage unit 1304 is connected to the matrix processing unit 1303. The matrix processing unit 1303 is also used to send the processing result corresponding to the read matrix data to the fifth storage unit; the fifth storage unit 1304 is used to receive the processing result sent by the matrix processing unit 1303 and store the processing result corresponding to the read matrix data.

[0164] The fifth storage unit 1304 in the matrix processing module 103 is used to store the processing results of the matrix processing unit 1303. The fifth storage unit 1304 can be any type of memory.

[0165] In this embodiment of the application, after the matrix processing unit in the matrix processing module processes the matrix data, it can obtain the processing result and store the processing result in the fifth storage unit to avoid the loss of the processing result and ensure data security.

[0166] In the above Figure 1 Based on the illustrated embodiments, in this application embodiment, the processor includes a DMA (Direct Memory Access) controller 104, such as... Figure 7 As shown, the scalar processing module 101 is connected to the DMA controller 104, and the DMA controller 104 is connected to the storage units in the vector processing module 102 and the matrix processing module 103, respectively.

[0167] In this embodiment, both the vector processing module 102 and the matrix processing module 103 include storage units. Optionally, the vector processing module 102 includes a first storage unit 1202, and the matrix processing module 103 includes a fourth storage unit 1301 and a fifth storage unit 1304. The first storage unit 1202 in the vector processing module 102 is connected to the DMA controller 104, and the fourth storage unit 1301 and the fifth storage unit 1304 in the matrix processing module 103 are both connected to the DMA controller 104. The DMA controller and each storage unit can be connected in any manner; for example, the DMA controller can be electrically connected to each storage unit.

[0168] The processor will now be described based on the above sections.

[0169] (1) Scalar processing module 101: also used to send a data transfer instruction in the instruction packet to DMA controller 104. The data transfer instruction indicates that the data in the second storage unit is transferred to the third storage unit. The second storage unit and the third storage unit are different storage units connected to DMA controller 104; (2) DMA controller 104: used to receive the data transfer instruction sent by scalar processing module 101, and in response to the data transfer instruction, read the data indicated by the data transfer instruction from the second storage unit and send the read data to the third storage unit; (3) Third storage unit: used to store the read data.

[0170] The second storage unit may be a storage unit in the vector processing module 102 or a storage unit in the matrix processing module 103. The third storage unit may be a storage unit in the vector processing module 102 or a storage unit in the matrix processing module 103. For example, the second storage unit may be the first storage unit 1202 in the vector processing module, and the third storage unit may be the fourth storage unit 1301 in the matrix processing module; or, the second storage unit may be the fifth storage unit 1304 in the matrix processing module, and the third storage unit may be the first storage unit 1202 in the vector processing module.

[0171] In this embodiment, the DMA controller can realize data transfer between connected memory units. The instruction packet received by the scalar processing module includes a data transfer instruction. The module can send the data transfer instruction to the DMA controller through the connection with the DMA controller, so that the DMA controller responds to the data transfer instruction and realizes data transfer between connected memory units. This eliminates the need to add a separate shared memory unit in the processor, enabling data transfer between different processing modules, simplifying the processor architecture, and eliminating the need for data interaction processes between data-interacting processing modules and shared memory units, thus improving data interaction efficiency.

[0172] It should be noted that the above-mentioned optional embodiments can be combined in any way. For example, taking the combination of the above-mentioned optional embodiments as an example, this application embodiment also provides a schematic diagram of the processor structure, such as... Figure 8 As shown.

[0173] The processor includes a bus, an instruction packet cache unit, an instruction packet fetch unit, a scalar processing module, a vector processing module, a matrix processing module, and a DMA controller.

[0174] The bus connects to the instruction packet buffer unit, which in turn connects to the instruction packet extraction unit. The bus includes an address bus, data bus, and control bus. The scalar processing module is equivalent to a Scalar Pipeline, the vector processing module to a Vector Pipeline, and the matrix processing module to a Matrix Pipeline. The scalar processing module includes a decoding unit, register file, arithmetic logic unit, sixth storage unit, and dispatch unit. The vector processing module includes a vector decoding unit, dispatch unit, vector register file, vector arithmetic logic unit, transport unit, and first storage unit. The matrix processing module includes a matrix decoding unit, address generation unit, fourth storage unit, feature loading subunit, weight loading subunit, pulse array, accumulation unit, and fifth storage unit. The connections between the bus, instruction packet buffer unit, instruction packet extraction unit, scalar processing module, vector processing module, matrix processing module, and DMA controller, as well as the connections between units within each processing module, are shown below. Figure 7 As shown.

[0175] During the processing of input data using the neural network model, the first processing module generates processing instructions and sends these instructions as instruction packets to the instruction packet buffer unit via a bus. The bus transmits these instruction packets to the buffer unit for storage. The instruction packet extraction unit reads the instruction packets from the buffer unit and, through its connection with the decoding unit in the scalar pipeline, sends the read instruction packets to the decoding unit.

[0176] In a scalar pipeline, the decoding unit parses the instruction packet to extract the processing instructions it contains, and can decode the scalar processing instructions to obtain the decoded scalar processing instructions. The decoded scalar processing instructions include operation information and address information. The address information is sent to the register file, and the operation information is sent to the arithmetic logic unit (ALU). The register file reads data from the registers according to the address information and sends the read data to the ALU. The ALU performs calculations on the read data according to the operation information and sends the calculation result to the sixth memory location. Alternatively, the calculation result can be written back to the register file through the WB (Write Back) stage unit in the scalar pipeline.

[0177] Furthermore, the decoding unit also sends vector processing instructions, matrix processing instructions, and data transfer instructions from the instruction packet to the distribution unit. The distribution unit receives the vector processing instructions and matrix processing instructions. Upon completion of the scalar processing instruction response, it sends vector processing instructions to the vector decoding unit via a connection with the vector decoding unit; it sends matrix processing instructions to the matrix decoding unit via a connection with the matrix decoding unit; and it sends data transfer instructions to the DMA controller via a connection with the DMA controller.

[0178] Furthermore, when the decoding unit parses the vector loading instruction from the instruction packet, it sends the vector loading instruction to the transport unit through the connection with the transport unit. The transport unit is used to respond to the vector loading instruction and complete the data transport between the vector register file and the first storage unit.

[0179] Furthermore, in the scalar pipeline, the sixth memory unit level handles branch instructions and exceptions. If the current instruction package has no exceptions or is on the correct branch path, it means that the current instruction package is determined to be executed. Then, other types of instructions in the instruction package are distributed to other pipelines through the dispatch unit, such as vector processing instructions or matrix processing instructions.

[0180] In a vector pipeline, the vector decoding unit receives vector processing instructions from the dispatch unit, decodes them, and obtains the decoded vector processing instructions. The decoded vector processing instructions include operation information and address information. The dispatch unit determines whether the current vector processing instruction meets the dispatch conditions. If the conditions are met, it sends the address information to the vector register file and the operation information to the vector arithmetic logic unit. The vector register file reads operands according to the address information and sends the read data to the vector arithmetic logic unit. The vector arithmetic logic unit performs vector calculations on the read data according to the operation information and writes the result back to the vector register file.

[0181] For the Vector Store instruction, the vector logic unit responds to the vector store instruction by sending the data to be stored to the transfer unit, which then stores the data to be stored in the first storage unit.

[0182] In the embodiments of this application, the lengths of different pipelines are different. For example, a vector pipeline can be calculated by only one arithmetic logic unit. However, there may be a vector processing instruction that requires multiple arithmetic logic units in the vector pipeline to be calculated. Once the instruction is calculated, the calculation result can be written back to the vector register file.

[0183] In the matrix pipeline, the matrix decoding unit decodes the matrix processing instructions sent by the distribution unit and sends the decoded matrix processing instructions to the address generation unit. Based on the decoded matrix processing instructions, the address generation unit generates an access request containing the access address and sends the access request to the feature loading subunit and the weight loading subunit. In response to the access request, the feature loading subunit reads feature data from the fourth storage unit and loads it into the pulse array. In response to the access request, the weight loading subunit reads weight data from the fourth storage unit and loads it into the pulse array according to a specific format. The pulse array fuses the feature data and weight data, outputs the calculation result, and the accumulation unit performs partial summation and accumulation. Finally, the calculation result is written into the fifth storage unit.

[0184] The DMA controller receives data transfer instructions sent by the distribution unit and completes data transfer between the first storage unit, the fourth storage unit, the fifth storage unit, and the external memory.

[0185] In this embodiment, the scalar processing module, vector processing module, and matrix processing module are coupled together. The vector processing module and matrix processing module are placed after the scalar processing module. Processing instructions for different data types are packaged together in an instruction packet. The programs of these scalar processing module, vector processing module, and matrix processing module are all concentrated in a single thread. Programmers do not need to consider multi-threaded synchronization operations, resulting in lower programming complexity. Data transfer between different processing modules is completed through the processor's internal DMA, eliminating the need for a storage medium, improving data interaction efficiency, reducing processor area, reducing unnecessary data transfer, and reducing power consumption during data transfer. Furthermore, other types of instructions (vector processing instructions, matrix processing instructions, or data transfer instructions) in the instruction packet are only distributed to the corresponding processing units after the scalar processing module has responded to the scalar processing instruction. This ensures that the processing instructions received by the vector processing module, matrix processing module, and DMA controller will definitely be executed, without considering the impact of branch prediction failures or anomalies, reducing coupling and complexity. This processor architecture facilitates data interaction between different processing modules. For example, scalar data obtained from scalar pipeline computation can be directly written to vector pipeline, matrix computation pipeline, or DMA. Data from the vector computation engine is stored in the first storage unit, while data from the matrix computation engine is stored in the fourth and fifth storage units. Data from different storage units can be directly moved between them through the DMA controller inside the processor core. All computation and data movement are controlled within a single code segment. This deep coupling greatly facilitates data interaction between different computation engines and results in high performance.

[0186] In the above Figure 8Based on the processor shown, a schematic diagram of the interaction between different processing modules is also provided, such as... Figure 9 As shown.

[0187] The scalar pipeline executes scalar processing instructions to complete the calculation of scalar data. The distribution unit then distributes the calculated scalar data and vector processing instructions from the instruction packet to the vector pipeline. Furthermore, the distribution unit distributes matrix processing instructions from the instruction packet to the matrix pipeline and data transfer instructions from the instruction packet to the DMA controller.

[0188] The vector pipeline executes vector processing instructions and writes the vector calculation results into the first memory. In the vector pipeline, the vector decoding unit receives the vector processing instructions sent by the dispatch unit, decodes the instructions, and obtains the decoded vector processing instructions. The decoded vector processing instructions include operation information and address information. The dispatch unit determines whether the current vector processing instruction meets the dispatch conditions. If the conditions are met, it sends the address information to the vector register file and the operation information to the vector arithmetic logic unit. The vector register file reads operands according to the address information and sends the read data to the vector arithmetic logic unit. The vector arithmetic logic unit performs vector calculations on the read data according to the operation information, writes the vector calculation results back to the vector register file, and the transport unit transports the results to the first memory unit for storage. Optionally, the vector arithmetic logic unit is connected to the transport unit. When the vector arithmetic logic unit obtains the vector calculation results, it can send the vector calculation results to the transport unit through the connection with the transport unit, and the transport unit transports the results to the first memory unit for storage.

[0189] The DMA controller moves the vector computation results from the first memory to the fourth memory in response to the data transfer command.

[0190] The matrix pipeline responds to matrix processing instructions by reading data from the fourth memory for matrix calculation operations. In the matrix pipeline, the matrix decoding unit decodes the matrix processing instructions sent by the distribution unit and sends the decoded instructions to the address generation unit. Based on the decoded instructions, the address generation unit generates an access request containing the access address and sends the request to the feature loading subunit and the weight loading subunit. Responding to the access request, the feature loading subunit reads feature data from the fourth memory unit and loads it into the pulse array. Responding to the access request, the weight loading subunit reads weight data from the fourth memory unit and loads it into the pulse array according to a specific format. The pulse array fuses the feature data and weight data, outputs the calculation result, and the accumulation unit performs partial summation and accumulation. Finally, the calculation result is written to the fifth memory unit.

[0191] It should be noted that the processor provided in this application embodiment can be any type of processor, for example, an AI (Artificial Intelligence) processor. Taking a neural network model scenario as an example, the computer device processes input data through a neural network model. During the processing of input data by the neural network model, instruction packets can be sent to the AI ​​processor multiple times so that the AI ​​processor can execute the processing instructions in the instruction packets to complete the processing of the input data by the neural network model. The scalar processing module is used to indicate the calculation control parameters, such as memory access addresses and matrix size parameters. The vector processing module is used to execute the activation function or pre- and post-processing functions of the neural network model. The matrix processing module is used to execute functions related to the convolutional layers or fully connected layers of the neural network model.

[0192] For example, taking a neural network model as an image recognition model, a computer device uses the image recognition model to recognize the input image. During the processing of the input image using the image recognition model, instruction packets are generated sequentially based on the network layers of the image recognition model and the input image. These instruction packets are then sent to the processor, which executes them according to the aforementioned instructions. Figure 7 The illustrated embodiment responds to the instruction packet in a manner that repeats the above process to obtain the image recognition result.

[0193] Figure 10 This application provides a data processing method, executed by the processor in the above embodiments. The processor includes a scalar processing module, a vector processing module, and a matrix processing module, with the scalar processing module connected to both the vector processing module and the matrix processing module. The method includes:

[0194] 1001. The scalar processing module receives an instruction packet containing multiple instructions, responds to the scalar processing instructions in the instruction packet, processes the scalar data indicated by the scalar processing instructions, sends the vector processing instructions in the instruction packet to the vector processing module, and sends the matrix processing instructions in the instruction packet to the matrix processing module.

[0195] 1002. The vector processing module receives vector processing instructions and, in response to the vector processing instructions, processes the vector data indicated by the vector processing instructions.

[0196] 1003. The matrix processing module receives matrix processing instructions and, in response to the matrix processing instructions, processes the matrix data indicated by the matrix processing instructions.

[0197] In one possible implementation, the scalar processing module includes a scalar processing unit and a distribution unit, the scalar processing unit being connected to the distribution unit, and the distribution unit being connected to both the vector processing module and the matrix processing module. The scalar processing module receives an instruction packet containing multiple instructions, processes the scalar data indicated by the scalar processing instructions in the instruction packet in response to the scalar processing instructions in the instruction packet, sends vector processing instructions from the instruction packet to the vector processing module, and sends matrix processing instructions from the instruction packet to the matrix processing module, including:

[0198] The scalar processing unit receives the instruction packet, responds to the scalar processing instruction, processes the scalar data indicated by the scalar processing instruction, and sends vector processing instructions and matrix processing instructions to the distribution unit.

[0199] The distribution unit receives vector processing instructions and matrix processing instructions, sends vector processing instructions to the vector processing module, and sends matrix processing instructions to the matrix processing module.

[0200] In another possible implementation, the scalar processing module includes a decoding unit connected to the scalar processing unit; the scalar processing unit receives instruction packets and, in response to scalar processing instructions, processes the scalar data indicated by the scalar processing instructions, including:

[0201] The decoding unit receives the instruction packet and decodes the scalar processing instruction; upon obtaining the decoded scalar processing instruction, it sends the decoded scalar processing instruction, vector processing instruction, and matrix processing instruction to the scalar processing unit.

[0202] The scalar processing unit receives the decoded scalar processing instructions, vector processing instructions, and matrix processing instructions. In response to the decoded scalar processing instructions, it processes the scalar data indicated by the decoded scalar processing instructions. After the scalar data indicated by the decoded scalar processing instructions has been processed, it sends the vector processing instructions and matrix processing instructions to the distribution unit.

[0203] In another possible implementation, the vector processing module includes a transport unit, a first storage unit, and a register, with the transport unit connected to the first storage unit, the register, and the decoding unit, respectively; the method further includes:

[0204] When the vector processing instructions include vector loading instructions, the decoding unit sends a vector loading instruction to the transport unit.

[0205] The transport unit receives a vector loading instruction, and in response to the vector loading instruction, reads the vector data indicated by the vector loading instruction from the first storage unit and loads the read vector data into the register.

[0206] In another possible implementation, the vector processing module includes a register, a vector processing unit, a transport unit, and a first storage unit. The register is connected to the vector processing unit, the vector processing unit is connected to the transport unit, and the transport unit is connected to the first storage unit. The vector processing instructions include vector storage instructions. The vector processing module receives vector processing instructions and, in response to the vector processing instructions, processes the vector data indicated by the vector processing instructions, including:

[0207] The vector processing unit responds to the vector storage instruction by reading the vector data indicated by the vector storage instruction from the register and sending the read vector data to the transport unit;

[0208] The transport unit receives the read vector data and sends the read vector data to the first storage unit;

[0209] The first storage unit stores the read vector data.

[0210] In another possible implementation, the processor includes a direct memory access (DMA) controller, a scalar processing module connected to the DMA controller, and the DMA controller connected to memory units in both the vector processing module and the matrix processing module; the method further includes:

[0211] The scalar processing module sends a data transfer instruction in the instruction packet to the DMA controller. The data transfer instruction instructs the data to be transferred from the second storage unit to the third storage unit. The second storage unit and the third storage unit are different storage units connected to the DMA controller.

[0212] The DMA controller receives a data transfer instruction, and in response to the data transfer instruction, reads the data indicated by the data transfer instruction from the second memory unit and sends the read data to the third memory unit;

[0213] The third storage unit stores the read data.

[0214] In another possible implementation, the scalar processing instruction instructs the processing of scalar data and the sending of the processing result to the vector processing module; after processing the scalar data indicated by the scalar processing instruction in response to the scalar processing instruction in the instruction packet, the method further includes:

[0215] The scalar processing module sends the processing result corresponding to the scalar data to the vector processing module;

[0216] The vector processing module receives the processing result corresponding to the scalar data; in response to the vector processing instruction, it processes the vector data indicated by the vector processing instruction based on the processing result corresponding to the scalar data.

[0217] In another possible implementation, the matrix processing module includes a fourth storage unit, a loading unit, and a matrix processing unit, with the loading unit connected to both the fourth storage unit and the matrix processing unit. The matrix processing module receives matrix processing instructions and processes the matrix data indicated by the instructions, including:

[0218] In response to the matrix processing instruction, the loading unit reads the matrix data indicated by the matrix processing instruction from the fourth storage unit and sends the read matrix data to the matrix processing unit.

[0219] The matrix processing unit processes the read matrix data.

[0220] In another possible implementation, the read matrix data includes feature data and weight data; the loading unit includes a feature loading subunit and a weight loading subunit, the feature loading subunit being connected to the fourth storage unit and the matrix processing unit respectively, and the weight loading subunit being connected to the fourth storage unit and the matrix processing unit respectively; the loading unit, in response to a matrix processing instruction, reads the matrix data indicated by the matrix processing instruction from the fourth storage unit and sends the read matrix data to the matrix processing unit, including:

[0221] In response to the matrix processing instruction, the feature loading subunit reads feature data from the fourth storage unit and sends the feature data to the matrix processing unit;

[0222] The weight loading subunit responds to the matrix processing instruction by reading weight data from the fourth storage unit and sending the weight data to the matrix processing unit;

[0223] The matrix processing unit processes the read matrix data, including:

[0224] The matrix processing unit receives feature data and weight data, and then fuses the feature data and weight data.

[0225] In another possible implementation, the matrix processing module includes a fifth storage unit connected to the matrix processing unit; after the matrix processing unit processes the read matrix data, the method further includes:

[0226] The matrix processing unit sends the processing result corresponding to the read matrix data to the fifth storage unit;

[0227] The fifth storage unit stores the processing results corresponding to the read matrix data.

[0228] It should be noted that the processor and data processing method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0229] This application also provides a computer device, which includes a memory and a processor as shown in the above embodiments.

[0230] Optionally, the computer device is provided as a terminal. Figure 11 This diagram illustrates a structural block diagram of a terminal 1100 provided in an exemplary embodiment of this application. The terminal 1100 can be a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, smart voice interaction device, smart home appliance, or in-vehicle terminal, etc. The terminal 1100 includes a processor 1101 and a memory 1102.

[0231] Processor 1101 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1101 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1101 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1101 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1101 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0232] The memory 1102 may include one or more computer-readable storage media, which may be non-transitory. The memory 1102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1102 are used to store at least one computer program, which is executed by the processor 1101 to implement the data processing method provided in the method embodiments of this application.

[0233] In some embodiments, the terminal 1100 may also optionally include a peripheral device interface 1103 and at least one peripheral device. The processor 1101, memory 1102, and peripheral device interface 1103 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1103 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: a radio frequency circuit 1104, a display screen 1105, a camera assembly 1106, an audio circuit 1107, and a power supply 1108.

[0234] Peripheral device interface 1103 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1101 and memory 1102. In some embodiments, processor 1101, memory 1102 and peripheral device interface 1103 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1101, memory 1102 and peripheral device interface 1103 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0235] The radio frequency (RF) circuit 1104 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1104 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1104 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1104 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 1104 can communicate with other terminals via at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1104 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0236] Display screen 1105 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1105 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1101 for processing. In this case, display screen 1105 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1105, disposed on the front panel of terminal 1100; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal 1100 or in a folded design; in still other embodiments, display screen 1105 may be a flexible display screen, disposed on a curved or folded surface of terminal 1100. Furthermore, display screen 1105 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1105 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0237] The camera assembly 1106 is used to acquire images or videos. Optionally, the camera assembly 1106 includes a front-facing camera and a rear-facing camera. The front-facing camera is disposed on the front panel of the terminal, and the rear-facing camera is disposed on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1106 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cool light flash, which can be used for light compensation at different color temperatures.

[0238] The audio circuit 1107 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1101 for processing, or input to the radio frequency circuit 1104 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal 1100. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1101 or the radio frequency circuit 1104 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1107 may also include a headphone jack.

[0239] Power supply 1108 is used to power the various components in terminal 1100. Power supply 1108 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1108 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, and a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0240] Those skilled in the art will understand that Figure 11 The structure shown does not constitute a limitation on terminal 1100 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0241] Optionally, the computer equipment is provided as a server. Figure 12 This is a schematic diagram of a server structure provided in an embodiment of this application. The server 1200 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 1201 and one or more memories 1202. The memories 1202 store at least one computer program, which is loaded and executed by the processor 1201 to implement the methods provided in the above-described method embodiments. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated upon here.

[0242] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0243] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present application should be included within the protection scope of the present application.

Claims

1. A processor, characterized in that, The processor includes a scalar processing module, a vector processing module, and a matrix processing module, wherein the scalar processing module is connected to the vector processing module and the matrix processing module, respectively. The scalar processing module is configured to receive an instruction packet containing multiple instructions, and in response to the scalar processing instructions in the instruction packet, process the scalar data indicated by the scalar processing instructions; send the vector processing instructions in the instruction packet to the vector processing module, and send the matrix processing instructions in the instruction packet to the matrix processing module. The vector processing module is configured to receive the vector processing instruction and, in response to the vector processing instruction, process the vector data indicated by the vector processing instruction. The matrix processing module is configured to receive the matrix processing instruction and, in response to the matrix processing instruction, process the matrix data indicated by the matrix processing instruction.

2. The processor according to claim 1, characterized in that, The scalar processing module includes a scalar processing unit and a distribution unit. The scalar processing unit is connected to the distribution unit, and the distribution unit is connected to both the vector processing module and the matrix processing module. The scalar processing unit is configured to receive the instruction packet, process the scalar data indicated by the scalar processing instruction in response to the scalar processing instruction, and send the vector processing instruction and the matrix processing instruction to the distribution unit. The distribution unit is configured to receive the vector processing instruction and the matrix processing instruction, send the vector processing instruction to the vector processing module, and send the matrix processing instruction to the matrix processing module.

3. The processor according to claim 2, characterized in that, The scalar processing module includes a decoding unit, which is connected to the scalar processing unit; The decoding unit is configured to receive the instruction packet, decode the scalar processing instruction, and, upon obtaining the decoded scalar processing instruction, send the decoded scalar processing instruction, the vector processing instruction, and the matrix processing instruction to the scalar processing unit. The scalar processing unit is configured to receive the decoded scalar processing instruction, the vector processing instruction, and the matrix processing instruction; in response to the decoded scalar processing instruction, process the scalar data indicated by the decoded scalar processing instruction; and, upon completion of the processing of the scalar data indicated by the decoded scalar processing instruction, send the vector processing instruction and the matrix processing instruction to the distribution unit.

4. The processor according to claim 3, characterized in that, The vector processing module includes a transport unit, a first storage unit, and a register, wherein the transport unit is connected to the first storage unit, the register, and the decoding unit, respectively. The decoding unit is further configured to send the vector loading instruction to the transport unit when the vector processing instruction includes a vector loading instruction; The transport unit is configured to receive the vector loading instruction, and in response to the vector loading instruction, read the vector data indicated by the vector loading instruction from the first storage unit and load the read vector data into the register.

5. The processor according to claim 1, characterized in that, The vector processing module includes a register, a vector processing unit, a transport unit, and a first storage unit. The register is connected to the vector processing unit, the vector processing unit is connected to the transport unit, and the transport unit is connected to the first storage unit. The vector processing instructions include vector storage instructions. The vector processing unit is configured to, in response to the vector storage instruction, read the vector data indicated by the vector storage instruction from the register and send the read vector data to the transport unit; The transport unit is used to receive the read vector data and send the read vector data to the first storage unit; The first storage unit is used to store the read vector data.

6. The processor according to claim 1, characterized in that, The processor includes a direct memory access (DMA) controller, the scalar processing module is connected to the DMA controller, and the DMA controller is connected to the memory units in the vector processing module and the matrix processing module, respectively. The scalar processing module is further configured to send a data transfer instruction in the instruction packet to the DMA controller. The data transfer instruction indicates that data in the second storage unit is transferred to the third storage unit. The second storage unit and the third storage unit are different storage units connected to the DMA controller. The DMA controller is configured to receive the data transfer instruction, and in response to the data transfer instruction, read the data indicated by the data transfer instruction from the second storage unit and send the read data to the third storage unit; The third storage unit is used to store the read data.

7. The processor according to claim 1, characterized in that, The scalar processing instruction instructs the processing of the scalar data and sends the processing result to the vector processing module; The scalar processing module is also used to send the processing result corresponding to the scalar data to the vector processing module; The vector processing module is also used to receive the processing result corresponding to the scalar data; The vector processing module is used to process the vector data indicated by the vector processing instruction in response to the vector processing instruction, based on the processing result corresponding to the scalar data.

8. The processor according to claim 1, characterized in that, The matrix processing module includes a fourth storage unit, a loading unit, and a matrix processing unit, wherein the loading unit is connected to the fourth storage unit and the matrix processing unit respectively. The loading unit is configured to, in response to the matrix processing instruction, read the matrix data indicated by the matrix processing instruction from the fourth storage unit and send the read matrix data to the matrix processing unit; The matrix processing unit is used to process the read matrix data.

9. The processor according to claim 8, characterized in that, The read matrix data includes feature data and weight data; the loading unit includes a feature loading subunit and a weight loading subunit, the feature loading subunit being connected to the fourth storage unit and the matrix processing unit respectively, and the weight loading subunit being connected to the fourth storage unit and the matrix processing unit respectively. The feature loading subunit is configured to, in response to the matrix processing instruction, read the feature data from the fourth storage unit and send the feature data to the matrix processing unit; The weight loading subunit is used to read the weight data from the fourth storage unit and send the weight data to the matrix processing unit in response to the matrix processing instruction. The matrix processing unit is used to receive the feature data and the weight data, and to fuse the feature data and the weight data.

10. The processor according to claim 8, characterized in that, The matrix processing module includes a fifth storage unit, which is connected to the matrix processing unit. The matrix processing unit is also used to send the processing result corresponding to the read matrix data to the fifth storage unit; The fifth storage unit is used to store the processing results corresponding to the read matrix data.

11. A data processing method, characterized in that, Executed by a processor as described in any one of claims 1 to 10, the processor comprising a scalar processing module, a vector processing module, and a matrix processing module, the scalar processing module being connected to the vector processing module and the matrix processing module, respectively; the method comprising: The scalar processing module receives an instruction packet containing multiple instructions, and in response to the scalar processing instructions in the instruction packet, processes the scalar data indicated by the scalar processing instructions, sends the vector processing instructions in the instruction packet to the vector processing module, and sends the matrix processing instructions in the instruction packet to the matrix processing module. The vector processing module receives the vector processing instruction and, in response to the vector processing instruction, processes the vector data indicated by the vector processing instruction. The matrix processing module receives the matrix processing instruction and, in response to the matrix processing instruction, processes the matrix data indicated by the matrix processing instruction.

12. The method according to claim 11, characterized in that, The scalar processing module includes a scalar processing unit and a distribution unit. The scalar processing unit is connected to the distribution unit, and the distribution unit is connected to both the vector processing module and the matrix processing module. The scalar processing module receives an instruction packet containing multiple instructions, and in response to the scalar processing instructions in the instruction packet, processes the scalar data indicated by the scalar processing instructions, sends the vector processing instructions in the instruction packet to the vector processing module, and sends the matrix processing instructions in the instruction packet to the matrix processing module, including: The scalar processing unit receives the instruction packet, and in response to the scalar processing instruction, processes the scalar data indicated by the scalar processing instruction; and sends the vector processing instruction and the matrix processing instruction to the distribution unit. The distribution unit receives the vector processing instruction and the matrix processing instruction, sends the vector processing instruction to the vector processing module, and sends the matrix processing instruction to the matrix processing module.

13. The method according to claim 11, characterized in that, The processor includes a direct memory access (DMA) controller, the scalar processing module is connected to the DMA controller, and the DMA controller is connected to the memory units in the vector processing module and the matrix processing module, respectively; the method further includes: The scalar processing module sends a data transfer instruction from the instruction packet to the DMA controller. The data transfer instruction instructs the data to be transferred from the second storage unit to the third storage unit. The second storage unit and the third storage unit are different storage units connected to the DMA controller. The DMA controller receives the data transfer instruction, and in response to the data transfer instruction, reads the data indicated by the data transfer instruction from the second storage unit and sends the read data to the third storage unit; The third storage unit stores the read data.

14. The method according to claim 11, characterized in that, The scalar processing instruction instructs the processing of the scalar data and sends the processing result to the vector processing module; After processing the scalar data indicated by the scalar processing instruction in the instruction packet, the method further includes: The scalar processing module sends the processing result corresponding to the scalar data to the vector processing module; The vector processing module receives the processing result corresponding to the scalar data; in response to the vector processing instruction, it processes the vector data indicated by the vector processing instruction based on the processing result corresponding to the scalar data.

15. A computer device, characterized in that, The computer device includes a memory and a processor as described in any one of claims 1 to 10.

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