Failure positioning method and device in chip simulation test and program product

Abstract

The invention provides a failure positioning method and device in a chip simulation test and a program product, and relates to the technical field of chip test. The method comprises the following steps: acquiring a failed test case when a simulation test is performed on a to-be-tested chip; extracting a data packet sequence of the test case, and extracting a target data packet sequence segment from the data packet sequence; performing a simulation test on the to-be-tested chip based on the target data packet sequence segment, and reducing the data packet sequence based on a simulation test result to obtain a reduced data packet sequence; and taking the reduced data packet sequence as a new data packet sequence, and skipping to execute the step of extracting the target data packet sequence segment from the data packet sequence until the target data packet causing the simulation test failure in the data packet sequence is determined. According to the invention, the efficiency and the accuracy can be improved when the data packets with failed simulation are screened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to a failure positioning method, device and program product in chip simulation testing. BACKGROUND

[0002] In a chip front-end development process, simulation testing of a chip to verify its performance is a crucial link. In the chip verification process, especially when chip verification fails, it is necessary to accurately locate the data packet in the test case that causes the verification failure, so as to accurately trace the problem and efficiently debug.

[0003] In related technologies, when a chip is simulated and tested, a manual execution of multiple test cases is mostly adopted. For a test case that causes simulation failure, the random constraints of the test case need to be constantly adjusted, and simulation operations are repeatedly performed until the data packet in the test case that causes simulation failure is screened out. However, the above-mentioned method of constantly adjusting the random constraints of the test case to screen the test data packet that causes simulation failure has the problems of low efficiency and low accuracy. SUMMARY

[0004] Embodiments of the present application provide a failure positioning method, device and program product in chip simulation testing, to solve the problems of low efficiency and low accuracy in screening data packets that cause simulation failure in the prior art.

[0005] In a first aspect, embodiments of the present application provide a failure positioning method in chip simulation testing, comprising: obtaining a test case that fails when simulating and testing a to-be-tested chip; extracting a data packet sequence of the test case, and extracting a target data packet sequence segment from the data packet sequence; based on the target data packet sequence segment, simulating and testing the to-be-tested chip, and based on the simulation test result, reducing the data packet sequence to obtain a reduced data packet sequence; taking the reduced data packet sequence as a new data packet sequence, jumping to execute the step of extracting the target data packet sequence segment from the data packet sequence, until a target data packet in the data packet sequence that causes simulation test failure is determined.

[0006] In a second aspect, embodiments of the present application provide a failure positioning device in chip simulation testing, comprising: an obtaining module configured to obtain a test case that fails when simulating and testing a to-be-tested chip; an extracting module configured to extract a data packet sequence of the test case, and extract a target data packet sequence segment from the data packet sequence; an updating module configured to perform simulation testing on the chip under test based on the target data packet sequence segment, and to reduce the data packet sequence based on a simulation testing result to obtain a reduced data packet sequence; a jumping module configured to jump to execute the step of extracting the target data packet sequence segment from the data packet sequence with the reduced data packet sequence as a new data packet sequence until a target data packet causing the simulation testing to fail is determined in the data packet sequence.

[0007] In a third aspect, an electronic device is provided, which includes a memory and a processor. The memory stores a computer program. The processor implements the method in the first aspect or any possible implementation manner of the first aspect when executing the computer program.

[0008] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the method in the first aspect or any possible implementation manner of the first aspect.

[0009] In a fifth aspect, a computer program product is provided, which includes a computer program. The computer program is executed by a processor to implement the method in the first aspect or any possible implementation manner of the first aspect.

[0010] Compared with the prior art, the embodiments of the present application can continuously simplify the data packet sequence of the test case according to the simulation testing result, and then gradually narrow the positioning range of the target data packet, so as to finally realize accurate locking of the target data packet causing the simulation testing to fail, and improve the positioning accuracy and positioning efficiency of the target data packet. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a structural schematic diagram of a chip simulation testing platform provided by an embodiment of the present application; Figure 2 is an implementation flowchart of a failure positioning method in chip simulation testing provided by an embodiment of the present application; Figure 3 is a schematic diagram of a target data packet sequence segment provided by an embodiment of the present application; Figure 4 is an implementation flowchart of a failure positioning method in chip simulation testing provided by another embodiment of the present application; Figure 5 is an implementation flowchart of a chip simulation testing process provided by an embodiment of the present application; Figure 6 is an implementation flowchart of a failure positioning method in chip simulation testing provided by still another embodiment of the present application; Figure 7 is an implementation flowchart of a chip simulation test flow provided by another embodiment of the present application; Figure 8 is a structural schematic diagram of a failure positioning device in a chip simulation test provided by an embodiment of the present application; Figure 9 is a schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0012] Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0013] In the related art, for a simulation failure test case, the random constraints of the test case need to be manually adjusted continuously, and simulation operations are repeatedly performed until a data packet in the test case that causes simulation failure is screened out. This approach has the problems of low efficiency and low accuracy.

[0014] To improve the positioning efficiency and positioning accuracy of the data packet that causes simulation failure, an embodiment of the present application uses part of a sequence segment (i.e., a target data packet sequence segment) in a data packet sequence of a test case to simulate the test case, so as to continuously reduce the data packet sequence according to the simulation result, limit the position range of the target data packet that causes simulation test, and finally realize accurate locking of the target data packet that causes simulation test failure, so as to improve the positioning accuracy and positioning efficiency of the target data packet.

[0015] Here, before introducing the failure positioning method in chip testing, a chip simulation test platform is introduced. An embodiment of the present application provides a chip simulation test platform for automatically simulating and testing a chip under test. Referring to Figure 1 , the platform includes a sequence generator, a driver, a monitor, a reference model, and a checking module. Here, the sequence generator is used to generate a test stimulus. The stimulus refers to a data packet sequence with a certain order generated by the sequence generator according to a test case. The driver is used to drive the stimulus generated by the sequence generator into the chip under test. The monitor is used to collect the output result of the chip under test. The reference model is used to generate a reference output according to the stimulus generated by the sequence generator. The detection module is used to compare the output result of the chip under test and the reference output, and generate a simulation test result.

[0016] Here, the chip under test uses a hardware logic processing method to process the test stimulus to generate an output result. The reference model uses a software processing method to process the test stimulus to generate a reference output. The checking module detects whether the simulation test is successful by comparing the output result and the reference output. It can be understood that when the output result and the reference output are consistent, the checking module determines that the simulation test is successful; when the output result and the reference output are inconsistent, the checking module determines that the simulation test fails.

[0017] During the chip simulation test process, the sequence generator calls the test cases in the test case library according to the automatic script, and generates the test stimulus accordingly. The driver drives the test stimulus into the chip under test, and the monitor collects the output results of the chip under test correspondingly. In addition, the sequence generator also inputs the test stimulus into the reference model, and the reference model outputs the reference output. The checking module compares the output results with the reference output to generate the simulation test results. If the simulation test is successful, the next test case is automatically executed according to the automatic script. If the simulation test fails, the failure positioning method in the chip simulation test is executed to locate the target data packet causing the simulation test failure, and after locating the target data packet in the current test case, the next test case is continued to be executed according to the automatic script, until all the test cases in the automatic script are executed, and the test cases causing the simulation test failure and the target data packet causing the simulation test failure in the test cases causing the simulation test failure are output.

[0018] The embodiment of the present application can test each test case one by one by using the automatic script, which can significantly improve the test efficiency, so as to quickly screen out the test case causing the simulation failure.

[0019] On the basis of the chip simulation test platform, the embodiment of the present application provides a failure positioning method in chip simulation test. Figure 2 The implementation flowchart of the failure positioning method in chip simulation test provided by the embodiment of the present application is shown in the following figure. Details are as follows: Step 201, obtaining the test case failing in the simulation test of the chip under test.

[0020] The embodiment of the present application can call each test case in the test case library in sequence according to the preset automatic script to perform chip simulation test. If the simulation test of the currently called test case fails, the failure positioning is performed on the data packet sequence in the test case to determine the target data packet causing the simulation test failure in the data packet sequence of the test case.

[0021] Step 202, extracting the data packet sequence of the test case, and extracting the target data packet sequence segment from the data packet sequence.

[0022] The data packet sequence of the test case is that the sequence generator generates the test stimulus according to the test case. Here, the sequence generator can randomly generate the data packet sequence with a certain order according to the preset data packet quantity and the random seed value (seed).

[0023] The embodiment of the present application can extract part of the sequence segment from the data packet sequence of the test case to obtain the target data packet sequence segment. It should be noted that, referring to the above description of the chip simulation test platform, the sequence generator can generate the test stimulus according to the test case, and the test stimulus includes the data packet sequence. Figure 3The target data packet sequence segment is a continuous data packet sequence segment extracted from the data packet sequence.

[0024] In step 203, the chip under test is simulated and tested based on the target data packet sequence segment, and the data packet sequence is reduced based on the simulation test result, to obtain a reduced data packet sequence.

[0025] In the embodiment, the chip under test is simulated and tested based on the target data packet sequence segment. If the simulation test fails, it indicates that the target data packet causing the simulation test failure is located in the target data packet sequence segment, and the target data packet sequence segment can be used as the reduced data packet sequence, thereby realizing the step-by-step reduction of the data packet sequence.

[0026] If the simulation test succeeds, it indicates that the target data packet causing the simulation test failure is located in the remaining data packet sequence segment, and the remaining data packet sequence segment can be used as the reduced data packet sequence, thereby realizing the step-by-step reduction of the data packet sequence.

[0027] In step 204, the reduced data packet sequence is used as a new data packet sequence, and the step of extracting the target data packet sequence segment from the data packet sequence is executed until the target data packet causing the simulation test failure in the data packet sequence is determined.

[0028] Here, the data packet sequence is iteratively reduced by loop, and the simulation test is continuously performed on the extracted target data packet sequence segment, so that the positioning range of the target data packet is gradually reduced, and the target data packet causing the simulation test failure is finally positioned.

[0029] In the embodiment, the chip under test is simulated and tested based on the target data packet sequence segment. If the simulation test fails, it indicates that the target data packet causing the simulation test failure is located in the target data packet sequence segment, and the target data packet sequence segment can be used as the reduced data packet sequence, thereby realizing the step-by-step reduction of the data packet sequence.

[0030] On the basis of the above embodiment, another embodiment is provided to introduce the process of reducing the data packet sequence by loop to finally determine the target data packet. Referring to Figure 4 , the implementation is as follows: In step 401, a test case failing in the simulation test of the chip under test is obtained.

[0031] In step 402, a data packet sequence of the test case is extracted.

[0032] The implementation of steps 401-402 is described above, and will not be repeated here.

[0033] In some embodiments, after step 402, the following steps can also be included: Step 403, performing simulation test on the chip under test using the first data packet in the data packet sequence.

[0034] Step 404, if the simulation test fails, determining the first data packet in the data packet sequence as the target data packet causing the simulation test to fail.

[0035] Step 405, if the simulation test succeeds, performing the step of extracting the target data packet sequence segment from the data packet sequence.

[0036] In the embodiment of the present application, after extracting the data packet sequence, the first data packet in the sequence is first subjected to simulation test, so as to determine whether the data packet is the target data packet causing the simulation test to fail. In this way, when the target data packet is the first data packet, the positioning efficiency of the target data packet can be effectively improved, and the detection of the first data packet is avoided to be missed due to the step-by-step narrowing of the positioning range, thereby affecting the overall positioning efficiency.

[0037] Here, the step of extracting the target data packet sequence segment from the data packet sequence mainly includes steps 406-407: Step 406, detecting the number of data packets in the data packet sequence.

[0038] Step 407, if the number of data packets is greater than two, determining any intermediate data packet at the middle position of the data packet sequence, and determining the data packet sequence between the first data packet in the data packet sequence and the intermediate data packet as the target data packet sequence segment.

[0039] In the case where the number of data packets in the data sequence is greater than two, the embodiment of the present application always determines the data packet sequence between the first data packet and any intermediate data packet at the middle position of the data packet sequence as the target data packet sequence segment.

[0040] Here, any intermediate data packet at the middle position of the data packet sequence refers to any data packet other than the first data packet and the last data packet. For example, the data packet at the midpoint of the data packet sequence can be determined as the intermediate data packet. The intermediate data packet can be the Mth data packet in the data packet sequence. Wherein, M=(L+H) / 2, L represents the sequence number of the first data packet in the data packet sequence, and H represents the sequence number corresponding to the last data packet in the data packet sequence. Here, the integer division down rounding method can be used to make the value of M an integer.

[0041] Step 408, performing simulation test on the chip under test based on the target data packet sequence segment.

[0042] Step 409, if the simulation test is successful, the data packet sequence between the intermediate data packet and the last data packet in the data packet sequence is determined as the reduced data packet sequence.

[0043] Step 410, if the simulation test fails, the data packet sequence between the first data packet and the intermediate data packet in the data packet sequence is determined as the reduced data packet sequence.

[0044] Step 411, the reduced data packet sequence is taken as a new data packet sequence, and step 406 is executed until the target data packet in the data packet sequence causing the simulation test to fail is determined.

[0045] It can be understood that the embodiment of the present application always determines the data packet sequence between the first data packet in the current data packet sequence and the intermediate data packet as a target data packet sequence segment. The target data packet sequence segment is used to perform simulation test on the chip to be tested. If the simulation test is successful, it is proved that the target data packet is between the intermediate data packet and the last data packet in the current data packet sequence. Therefore, the embodiment of the present application takes the data packet sequence between the intermediate data packet and the last data packet in the current data packet sequence as a new data packet sequence, so as to achieve the purpose of limiting the positioning range of the target data packet.

[0046] If the simulation test fails, it is proved that the target data packet is between the first data packet in the current data packet sequence and the intermediate data packet. Accordingly, the data packet sequence between the first data packet in the current data packet sequence and the intermediate data packet is taken as a new data packet sequence, so as to achieve the purpose of limiting the positioning range of the target data packet.

[0047] In some embodiments, after step 406, the following steps are further included: Step 412, if the number of data packets in the data packet sequence is less than or equal to two, the last data packet in the data packet sequence is determined as the target data packet causing the simulation test to fail.

[0048] The embodiment of the present application can continuously limit the data packet sequence by cyclically performing the steps of extracting the target data packet sequence segment from the data packet sequence, performing simulation test, and reducing the data packet sequence according to the simulation test result, so as to achieve the purpose of limiting the positioning range of the target data packet.

[0049] The embodiment of the present application continuously limits the number of data packets in the data packet sequence until the number of data packets in the data packet sequence is less than or equal to two, and the last data packet in the current data packet sequence is determined as the target data packet causing the simulation test to fail.

[0050] The following will be combined Figure 5 , to systematically introduce the whole chip simulation test process. Referring toFigure 5 The whole chip simulation test process is described as follows: Step 501, receiving an automatic script execution command and input parameters.

[0051] The user can input the automatic script execution command and input parameters through a command line. Here, the input parameters can include an initial data packet number H, a test case library path, and an algorithm name (for example, failure algorithm one) corresponding to the above failure positioning method. The data packet number is used for the sequence generator to generate a data packet sequence. The test case library path is used for reading a test case. The algorithm name is used to call the failure positioning method in the chip simulation test process.

[0052] Step 502, automatic script execution starts.

[0053] The embodiment of the application starts to execute the automatic script according to the above command and input parameters.

[0054] Step 503, reading the name of the ith test case in the test case library and the total number of test cases K according to the test case library path, and generating a simulation command f(i, H, S) and executing in combination with the initial data packet number H and the random seed number S.

[0055] In the embodiment of the application, after the automatic script acquires the path of the test case library, the test case name (namely, the ith test case) of the test case currently to be tested in the test case library is read in sequence, and the simulation instruction f(i, H, S) is generated according to the data packet number H and the random seed number S, and the simulation test is performed on the chip to be tested by using the simulation instruction. The simulation instruction is used to represent the data packet sequence generated by the sequence generator, namely, the data packet sequence of the ith test case.

[0056] Specifically, after the automatic script acquires the test case name, the random seed number (a random unsigned integer value), and the data packet number, it processes them into strings and splices them to form a simulation command, and the simulation command is run on the chip simulation test platform by calling the os.system function in python.

[0057] After receiving the simulation command, the chip simulation test platform randomly generates a data packet sequence according to the test case by the sequence generator. The specific process is that the data packet contents in the sequence generator are randomly valued according to the random seed number, and the number of data packets in the data packet sequence is the number of data packets in the input parameter. The randomization of the data packet contents can sufficiently verify the to-be-tested chip to ensure the security of the to-be-tested chip. Subsequently, the driver drives the above data packet sequence into the to-be-tested chip. At the same time, the sequence generator transmits the data packet sequence into the reference model. After the to-be-tested chip executes the data packet sequence and outputs the result, the monitor collects the output result of the to-be-tested chip and transmits it to the checker. The reference model outputs the reference result to the checker according to the data packet sequence. The checker performs comparison of the output results of the to-be-tested chip and the reference model and gives the checking result. Both the to-be-tested chip and the reference model process the data packet sequence, but the difference is that the to-be-tested chip often uses the logic processing mode of hardware, and the reference model uses the processing mode of software. In general, both of them generate output data packets, and if the data contents of the data packets with the same ID (ID is a component of the data packet content, and the same data packet is determined by the ID) are different, the checking module will determine that the simulation fails. Otherwise, it is successful.

[0058] Step 504, detecting whether the simulation test is successful.

[0059] If the simulation test is successful, step 514 is executed. If the simulation test fails, step 505 is executed.

[0060] Step 505, obtaining the number H of data packets of the test case used for the simulation failure, resetting the number of data packets in the simulation command to L (L = 1), and executing the simulation command f(i, L, S).

[0061] That is, the simulation test is performed on the first data packet in the data packet sequence to detect whether the first data packet is the target data packet that causes the simulation failure.

[0062] Step 506, detecting whether the simulation test is successful.

[0063] If the simulation test fails, step 511 is executed, the first data packet is determined as the data packet that causes the simulation failure, that is, P = 1. Here, P represents the order of the data packet that causes the simulation failure. And step 513 is continuously executed, and the test case name of the simulation failure and the order P of the data packet that causes the simulation failure are output.

[0064] If the simulation test is successful, step 507 is executed, and it is detected whether H-L>1 is established.

[0065] Here, H represents the number of data packets in the data packet sequence, that is, the sequence number of the last data packet in the data packet sequence. L represents the sequence number of the first data packet in the data packet sequence. The detection of whether H-L>1 is established is essentially the detection of whether there are other data packets remaining in the data packet sequence except for the first data packet and the last data packet sequence.

[0066] If not, step 512 is executed, the last data packet sequence is taken as the data packet causing the simulation failure, that is, P=H, and step 513 is jumped to be executed.

[0067] If yes, step 508 is executed, the data packet number of the simulation command is reset as M=(L+H) / 2 (integer division and rounding down), and the simulation command f(i, M, S) is executed.

[0068] That is, if there are other data packets remaining in the data packet sequence except for the first data packet and the last data packet sequence, the Mth data packet in the data packet sequence (that is, the data packet at the midpoint position) is determined, and the target data packet sequence segment between the first data packet and the Mth data packet is tested by using the simulation command.

[0069] Step 509 is executed to detect whether the simulation test is successful.

[0070] If the simulation test is successful, step 510 is executed, that is, L=M, the Mth data packet in the current data packet sequence is taken as the first data packet in the new data packet sequence.

[0071] If the simulation test fails, step 511 is executed, that is, H=M, the Mth data packet in the current data packet sequence is taken as the last data packet in the new data packet sequence.

[0072] Step 507 is jumped to be executed, so that the values of L and H are cyclically updated, so as to continuously reduce the data packets in the data packet sequence, thereby continuously narrowing the positioning range, and finally the data packet causing the simulation failure is positioned and determined, and the test case name causing the simulation failure and the sequence P of the data packet causing the simulation failure are output.

[0073] Step 514 is executed to detect whether i

[0074] If yes, step 515 is executed, that is, i=i+1, the simulation test of the next test case is performed, and step 503 is jumped to be executed.

[0075] If not, step 516 is executed, and the execution of the automation script is ended.

[0076] On the basis of the above chip test method, the embodiment of the application further provides another failure positioning method in the chip simulation test, so as to further improve the positioning efficiency of the target data packet.

[0077] In some embodiments, the target data packet sequence segment comprises: a first target data packet sequence segment and a second target data packet sequence segment.

[0078] Referring to Figure 6 The failure positioning method in the chip simulation test is described as follows: In step 601, a test case that fails in the simulation test of the to-be-tested chip is obtained.

[0079] In step 602, a data packet sequence of the test case is extracted.

[0080] In step 603, the first data packet in the data packet sequence is used to perform the simulation test on the to-be-tested chip.

[0081] In step 604, if the simulation test fails, the first data packet in the data packet sequence is determined as a target data packet that causes the simulation test to fail. In step 605, if the simulation test succeeds, the step of extracting a target data packet sequence segment from the data packet sequence is performed.

[0082] The implementation of steps 601-605 is described in the above embodiments, which will not be repeated here.

[0083] In the embodiments of the present application, the step of extracting a target data packet sequence segment from the data packet sequence mainly comprises steps 606-609: In step 606, the number of data packets in the data packet sequence is detected. In step 607, if the number of data packets is greater than four, the first data packet at a first position in the data packet sequence and the second data packet at a second position in the data packet sequence are determined.

[0084] Here, the first position and the second position are both in the middle position region of the data packet sequence, and the first position is earlier than the second position.

[0085] The middle position region is the region of the data packet sequence except the first data packet and the last data packet. For example, the first position can be at the 1 / 3 position of the data packet sequence. The second position can be at the 2 / 3 position of the data packet sequence.

[0086] In the embodiments of the present application, the M0th data packet in the data packet sequence can be determined as the first data packet. The M1th data packet in the data packet sequence can be determined as the second data packet. Wherein, M0=(L+H) / 2-(H-L) / 4, which is used to represent the data packet at the 1 / 3 position. M1=(L+H) / 2+(H-L) / 4, which is used to represent the data packet at the 2 / 3 position. Here, the integer division down rounding method can be used to make the value of M an integer.

[0087] Step 608, determining the data packet sequence between the first data packet and the second data packet in the data packet sequence as a first target data packet sequence segment.

[0088] Step 609, determining the data packet sequence between the first data packet and the second data packet in the data packet sequence as a second target data packet sequence segment.

[0089] Step 610, performing simulation test on the chip under test based on the first target data packet sequence segment and the second target data packet sequence segment respectively.

[0090] Step 611, if the simulation test corresponding to the first target data packet sequence segment fails, determining the data packet sequence between the first data packet and the first data packet in the data packet sequence as a reduced data packet sequence.

[0091] If the simulation test of the first target data packet sequence segment fails, it proves that the target data packet is in the first target data packet sequence segment, and the first target data packet sequence segment is determined as the reduced data packet sequence.

[0092] Step 612, if the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment succeeds, determining the data packet sequence between the second data packet and the last data packet in the data packet sequence as a reduced data packet sequence.

[0093] If the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment succeeds, it proves that the target data packet is after the second data packet, and thus the data packet sequence between the second data packet and the last data packet is determined as the reduced data packet sequence to reduce the positioning range of the target data packet.

[0094] Step 613, if the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment fails, determining the data packet sequence between the first data packet and the second data packet as a reduced data packet sequence.

[0095] If the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment fails, it proves that the target data packet is between the first data packet and the second data packet. Therefore, the data packet sequence between the first data packet and the second data packet is determined as the reduced data packet sequence.

[0096] Here, the embodiment of the present application uses two data packet sequence segments to perform simulation test respectively, which can effectively expand the reduction range of the data packet sequence, thereby improving the positioning efficiency of the target data packet.

[0097] Step 614, taking the reduced data packet sequence as a new data packet sequence, and jumping to execute step 606 until the target data packet in the data packet sequence causing the simulation test to fail is determined.

[0098] Embodiments of the present application continuously reduce the data packet sequence, thereby continuously narrowing the positioning range of the target data packet sequence, and finally determining the target data packet in the data packet sequence causing the simulation test to fail.

[0099] In some embodiments, after step 606, the following steps are further included: Step 615, if the number of data packets in the data packet sequence is less than or equal to four, detecting whether the number of data packets in the data packet sequence is greater than two.

[0100] When the number of data packets in the data packet sequence is less than or equal to four, in the determination of the first data packet and the second data packet by M0=(L+H) / 2-(H-L) / 4 and M1=(L+H) / 2+(H-L) / 4, since the integer division is used, it is very likely that M0=M1 occurs, and further causes the first target data packet sequence segment and the second target data packet sequence segment to be unable to be extracted from the data packet sequence to further narrow the positioning range of the target data packet. At this time, it is detected whether the number of data packets is greater than two, so as to continue to use the method of selecting any intermediate data packet in the above embodiment to extract the data packet sequence segment, so as to further narrow the data packet sequence.

[0101] Step 616, if the number of data packets in the data packet sequence is greater than two, determining any intermediate data packet at the middle position of the data packet sequence, and determining the data packet sequence between the first data packet in the data packet sequence and the intermediate data packet as a third target data packet sequence segment.

[0102] Step 617, performing simulation test on the chip under test based on the third target data packet sequence segment, and reducing the data packet sequence based on the simulation test result to obtain a reduced data packet sequence. Step 618, taking the reduced data packet sequence as a new data packet sequence, and jumping to execute the step of detecting whether the number of data packets in the data packet sequence is greater than two, until the number of data packets in the data packet sequence is less than or equal to two, and the last data packet in the data packet sequence is determined as the target data packet causing the simulation test to fail.

[0103] The specific implementation of steps 615-617 is described above Figure 4 Corresponding embodiments are not described here.

[0104] The embodiment of the present application uses two target data packet sequence segments to respectively perform simulation tests in the early stage of limiting the data packet sequence, so as to expand the limiting range of the data packet sequence, and improve the positioning speed of the target data packet. When the two target data packet sequence segments cannot be extracted in the later stage, one target data packet sequence segment is extracted to further limit the positioning range of the target data packet, until the target data packet causing the simulation test failure is determined.

[0105] The whole chip simulation test process is introduced systematically below. Figure 7 The whole chip simulation test process is introduced systematically below. Figure 7 The whole chip simulation test process is introduced systematically below. Step 701, receiving an automatic script execution command and input parameters.

[0106] The user can input the automatic script execution command and the input parameters through a command line. Here, the input parameters can include an initial data packet number H, a test case library path, and an algorithm name (for example, failure algorithm two) corresponding to the above failure positioning method.

[0107] Step 702, automatic script execution starts.

[0108] Step 703, reading the name of the ith test case in the test case library and the total number of test cases K according to the test case library path, generating a simulation command f(i, H, S) in combination with the initial data packet number H and a random seed number S, and executing the simulation command.

[0109] Step 704, detecting whether the simulation test is successful.

[0110] If the simulation test is successful, step 720 is executed. If the simulation test fails, step 705 is executed.

[0111] Step 705, obtaining the data packet number H of the test case used for the simulation failure, resetting the data packet number in the simulation command to L (L=1), and executing the simulation command f(i, L, S).

[0112] Step 706, detecting whether the simulation test is successful.

[0113] If the simulation test fails, step 718 is executed, the first data packet is determined as the data packet causing the simulation failure, that is, P=1. And step 719 is continuously executed, the name of the test case causing the simulation failure and the order P of the data packet causing the simulation failure are output.

[0114] The specific implementation of the above steps 701 to 706 is described in the above corresponding embodiment, which will not be described here again. Figure 5 The specific implementation of the above steps 701 to 706 is described in the above corresponding embodiment, which will not be described here again.

[0115] If the simulation test is successful, step 707 is executed, and it is detected whether H-L>3 is established.

[0116] Here, H represents the number of packets in the packet sequence, that is, the sequence number of the last packet in the packet sequence. L represents the sequence number of the first packet in the packet sequence. Testing whether HL > 3 essentially tests whether the first target packet sequence segment and the second target packet sequence segment can still be extracted from the packet sequence.

[0117] If not, execute step 713. If true, execute steps 708 and 709.

[0118] Step 708 : Reset the number of data packets of the simulation command to M0 = (L+H) / 2-(HL) / 4 (round down when divided by integer) and execute the simulation command f(i, M0, S).

[0119] Step 709 : Reset the number of data packets of the simulation command to M1=(L+H) / 2+(HL) / 4 (round down when divided by integer) and execute the simulation command f(i, M1, S).

[0120] Here, if HL>3 holds, it proves that the first data packet and the second data packet can be extracted from the data packet sequence. At this time, continue to execute steps 708 and 709 to extract the first data packet and the second data packet, thereby constructing the first target data packet sequence segment and the second target data packet sequence segment for simulation testing.

[0121] Step 710, detect the simulation command f(i, M0, S) (i.e. Figure 7 A0) shows whether the simulation is successful; Step 711, detect the simulation command f(i,M1,S) (i.e. Figure 7 A1) Whether the simulation is successful; Step 712: If A0 fails to simulate, execute H=M0. If A0 succeeds but A1 fails, execute H=M1 and L=M0. If A0 succeeds and A1 succeeds, execute L=M1.

[0122] Jump to step 707 to cyclically update the values ​​of L and H to continuously reduce the data packets in the data packet sequence, thereby continuously narrowing the positioning range, until HL>3 is no longer true, and then jump to step 713.

[0123] Here, when HL>3 is not established, it proves that the first data packet and the second data packet cannot be extracted and determined in the current data packet sequence. In order to further narrow the positioning range of the target data packet and accurately locate the target data packet, the following is used. Figure 5 The failure location method in the corresponding embodiment is used to accurately locate the target data packet.

[0124] Step 713, detecting whether H-L>1 is true.

[0125] If not, then executing step 717; If true, then executing step 714, resetting the data packet number of the simulation command to M=(L+H) / 2 (integer division down) and executing the simulation command f(i, M, S).

[0126] Step 715, detecting whether the simulation test is successful.

[0127] Step 716, if the simulation test is successful, then executing L=M, i.e. taking the Mth data packet in the current data packet sequence as the first data packet in the new data packet sequence.

[0128] If the simulation test fails, then executing H=M, i.e. taking the Mth data packet in the current data packet sequence as the last data packet in the new data packet sequence.

[0129] Jumping to execute step 713, so as to cyclically update the values of L and H, so as to constantly reduce the data packets in the data packet sequence, thereby constantly narrowing the positioning range, until H-L>1 is not true, and step 717 is executed.

[0130] Step 717, determining the last data packet in the data packet sequence as the target data packet causing the simulation failure, i.e. P=H. And continuing to execute step 719.

[0131] Step 719, outputting the test case name of the simulation failure and the data packet order P causing the simulation failure.

[0132] Step 720, detecting whether i

[0133] If true, then executing step 721, i=i+1, and jumping to execute step 703.

[0134] If not, then executing step 722, and the automatic script execution ends.

[0135] The specific implementation mode of the above steps 713 to 722 is described in detail in Figure 5 The corresponding embodiments, which will not be described here.

[0136] In essence, the principle of the above failure positioning method is that when the simulation environment executes simulation instructions of the same random seed number (i.e., seed value, used to randomize the packet sequence of the test case), the packet sequence input into the chip under test is always input in the same order, and the contents of the packets in the same order are the same, at this time, the number of input packets in the simulation instructions is constantly changed (i.e., the packet sequence is reduced), and the position of the target packet can be judged according to the simulation result. When the number of packets in the simulation command is less than the order of the target packet, the simulation is not executed to the target packet at this time, and therefore the simulation is successful. On the contrary, when the number of packets in the simulation command is greater than or equal to the order of the target packet, the simulation will execute to the target packet at this time, and therefore the simulation fails.

[0137] The above failure positioning methods can be used to locate the target failure packet that causes the simulation test to fail, but the difference between the two is the speed of locating the target packet. The first failure positioning method will only execute one simulation at a time under the condition of "H-L>1", and after the simulation is completed, it is judged according to the simulation result whether to continue adjusting the number of packets to continue executing the next simulation. The second failure positioning method executes two simulations in parallel under the condition of "H-L>3", and judges according to the simulation results of the two times whether to adjust the number of packets to continue executing the next two simulations. Therefore, compared with the first failure positioning method, the automatic script can quickly filter the position of the failure packet, but it will also consume more cpu resources.

[0138] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0139] The following is a device embodiment of the present application. For details not described in detail, please refer to the corresponding method embodiments described above.

[0140] Figure 8 The structure of the failure positioning device in chip simulation test provided by the embodiment of the present application is shown. For the convenience of description, only the part related to the embodiment of the present application is shown, and the details are as follows: As Figure 8 shown, the failure positioning device 8 in chip simulation test includes an acquisition module 81, an extraction module 82, an update module 83 and a jump module 84.

[0141] The acquisition module 81 is used to acquire the test case that fails in the simulation test of the chip under test; The extraction module 82 is used to extract the packet sequence of the test case, and extract the target packet sequence segment from the packet sequence; The updating module 83 is configured to perform simulation testing on the chip under test based on the target data packet sequence segment, and reduce the data packet sequence based on a simulation testing result to obtain a reduced data packet sequence. The jumping module 84 is configured to jump to execute the step of extracting the target data packet sequence segment from the data packet sequence with the reduced data packet sequence as a new data packet sequence until a target data packet causing the simulation testing to fail in the data packet sequence is determined.

[0142] Optionally, the extracting module 82 is specifically configured to: detect a number of data packets in the data packet sequence; if the number of data packets is greater than two, determine any intermediate data packet at an intermediate position of the data packet sequence, and determine a data packet sequence between a first data packet in the data packet sequence and the intermediate data packet as the target data packet sequence segment.

[0143] Optionally, the extracting module 82 is further configured to: if the number of data packets in the data packet sequence is less than or equal to two, determine a last data packet in the data packet sequence as the target data packet causing the simulation testing to fail.

[0144] Optionally, the updating module 83 is specifically configured to: if the simulation testing succeeds, determine a data packet sequence between the intermediate data packet and a last data packet in the data packet sequence as the reduced data packet sequence; if the simulation testing fails, determine a data packet sequence between a first data packet in the data packet sequence and the intermediate data packet as the reduced data packet sequence.

[0145] Optionally, the target data packet sequence segment includes a first target data packet sequence segment and a second target data packet sequence segment. The extracting module 82 is specifically configured to: detect a number of data packets in the data packet sequence; if the number of data packets is greater than four, determine a first data packet at a first position in the data packet sequence and a second data packet at a second position in the data packet sequence; the first position and the second position are both at an intermediate position region of the data packet sequence, and the first position is earlier than the second position; determine a data packet sequence between the first data packet in the data packet sequence and the first data packet as the first target data packet sequence segment; determine a data packet sequence between the first data packet in the data packet sequence and the second data packet as the second target data packet sequence segment.

[0146] Optionally, the updating module 83 is specifically configured to: simulate the to-be-tested chip based on the first target data packet sequence segment and the second target data packet sequence segment respectively; If the simulation test corresponding to the first target data packet sequence segment fails, the data packet sequence between the first data packet and the second data packet in the data packet sequence is determined as the reduced data packet sequence. If the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment succeeds, the data packet sequence between the second data packet and the last data packet in the data packet sequence is determined as the reduced data packet sequence. If the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment fails, the data packet sequence between the first data packet and the second data packet is determined as the reduced data packet sequence.

[0147] Optionally, the extraction module 82 is further configured to: If the number of data packets in the data packet sequence is less than or equal to four, it is detected whether the number of data packets in the data packet sequence is greater than two. If the number of data packets in the data packet sequence is greater than two, any intermediate data packet at the intermediate position in the data packet sequence is determined, and the data packet sequence between the first data packet and the intermediate data packet in the data packet sequence is determined as the third target data packet sequence segment. The to-be-tested chip is simulated based on the third target data packet sequence segment, and the data packet sequence is reduced based on the simulation test result to obtain a reduced data packet sequence. The reduced data packet sequence is taken as a new data packet sequence, and the step of detecting whether the number of data packets in the data packet sequence is greater than two is executed, until the number of data packets in the data packet sequence is less than or equal to two, and the last data packet in the data packet sequence is determined as the target data packet causing the simulation test to fail.

[0148] Optionally, the extraction module 82 is further configured to: The to-be-tested chip is simulated based on the first data packet in the data packet sequence. If the simulation test fails, the first data packet in the data packet sequence is determined as the target data packet causing the simulation test to fail. If the simulation test succeeds, the step of extracting the target data packet sequence segment from the data packet sequence is executed.

[0149] The apparatus embodiment can implement the above method embodiments, and has the same technical principles and implementation effects as the above method embodiments, which will not be described herein again.

[0150] Figure 9 is a schematic diagram of an electronic device provided by an embodiment of the present application. As shown inFigure 9 As shown, the electronic device 9 of this embodiment includes a processor 90 and a memory 91. The memory 91 stores a computer program 92. The processor 90 implements the steps in the above method embodiments when executing the computer program 92. Alternatively, the processor 90 implements the functions of the modules / units in the above apparatus embodiments when executing the computer program 92.

[0151] For example, the computer program 92 can be divided into one or more modules / units, which are stored in the memory 91 and executed by the processor 90 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program 92 in the electronic device 9.

[0152] The electronic device 9 can include, but is not limited to, the processor 90 and the memory 91. Those skilled in the art can understand that the electronic device 9 can include more or less components, or combine certain components, or different components, for example, the electronic device 9 can also include an input / output device, a network access device, a bus, etc. Figure 9 The electronic device 9 is only an example and does not constitute a limitation on the electronic device 9, which can include more or less components than those shown, or combine certain components, or different components, for example, the electronic device 9 can also include an input / output device, a network access device, a bus, etc.

[0153] The processor 90 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0154] The memory 91 can be an internal storage unit of the electronic device 9, such as a hard disk or a memory of the electronic device 9. The memory 91 can also be an external storage device of the electronic device 9, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device 9. Further, the memory 91 can include both the internal storage unit and the external storage device of the electronic device 9. The memory 91 is used to store the computer program 92 and other programs and data required by the electronic device 9. The memory 91 can also be used to temporarily store data that has been output or will be output.

[0155] For the convenience and brevity of description, only the above-mentioned division of functional modules / units is exemplified, and in actual application, the above-mentioned functions can be completed by different functional modules / units according to needs. The above-mentioned modules / units can be realized in the form of hardware, software or a combination of hardware and software.

[0156] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method in each method embodiment described above is implemented.

[0157] The embodiment of the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the method in each method embodiment described above is implemented.

[0158] The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium can include any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, Read-Only Memory (ROM), Random Access Memory (RAM), electric carrier wave signal, telecommunication signal and software distribution medium, etc.

[0159] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments. If there is no special description and no logical conflict, the terms and / or descriptions of different embodiments are consistent and can be mutually referenced. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0160] The above-described embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for locating failures in chip simulation testing, characterized in that: include: Obtain test cases that failed during simulation testing of the chip under test; Extracting a data packet sequence of the test case, and extracting a target data packet sequence segment from the data packet sequence; Performing a simulation test on the chip under test based on the target data packet sequence segment, and reducing the data packet sequence based on the simulation test result to obtain a reduced data packet sequence; The reduced data packet sequence is used as a new data packet sequence, and the step of extracting the target data packet sequence segment from the data packet sequence is skipped and executed until the target data packet causing the simulation test failure is determined in the data packet sequence.

2. The failure location method in chip simulation test according to claim 1, characterized in that: The step of extracting a target data packet sequence segment from the data packet sequence comprises: Detect the number of packets in a packet sequence; If the number of the data packets is greater than two, any intermediate data packet in the middle position of the data packet sequence is determined, and the data packet sequence between the first data packet in the data packet sequence and the intermediate data packet is determined as the target data packet sequence segment.

3. The failure location method in chip simulation test according to claim 2, characterized in that: After detecting the number of data packets in the data packet sequence, the method further includes: If the number of data packets in the data packet sequence is less than or equal to two, the last data packet in the data packet sequence is determined as the target data packet that causes the simulation test to fail.

4. The failure location method in chip simulation test according to claim 2 or 3, characterized in that: The reducing the data packet sequence based on the simulation test result to obtain the reduced data packet sequence includes: If the simulation test is successful, the data packet sequence between the intermediate data packet and the last data packet in the data packet sequence is determined as the reduced data packet sequence; If the simulation test fails, the data packet sequence between the first data packet and the intermediate data packet in the data packet sequence is determined as the reduced data packet sequence.

5. The failure location method in chip simulation test according to claim 1, characterized in that: The target data packet sequence segment includes: a first target data packet sequence segment and a second target data packet sequence segment; The step of extracting a target data packet sequence segment from the data packet sequence comprises: Detect the number of packets in a packet sequence; If the number of the data packets is greater than four, determining a first data packet at a first position in the data packet sequence and a second data packet at a second position in the data packet sequence; the first position and the second position are both in the middle position region of the data packet sequence, and the first position is earlier than the second position; Determine a data packet sequence between the first data packet in the data packet sequence and the first data packet as the first target data packet sequence segment; The data packet sequence between the first data packet and the second data packet in the data packet sequence is determined as the second target data packet sequence segment.

6. The method for locating failures in chip simulation testing according to claim 5, characterized in that: Performing a simulation test on the chip to be tested based on the target data packet sequence segment, and reducing the data packet sequence based on the simulation test result to obtain a reduced data packet sequence, including: Performing simulation tests on the chip under test based on the first target data packet sequence segment and the second target data packet sequence segment respectively; If the simulation test corresponding to the first target data packet sequence segment fails, determining the data packet sequence between the first data packet in the data packet sequence and the first data packet as the reduced data packet sequence; If the simulation test corresponding to the first target data packet sequence segment succeeds, and the simulation test corresponding to the second target data packet sequence segment succeeds, then determining the data packet sequence between the second data packet and the last data packet in the data packet sequence as the reduced data packet sequence; If the simulation test corresponding to the first target data packet sequence segment succeeds and the simulation test corresponding to the second target data packet sequence segment fails, the data packet sequence between the first data packet and the second data packet is determined as the reduced data packet sequence.

7. The failure location method in chip simulation test according to claim 5 or 6, characterized in that: After detecting the number of packets in the packet sequence, it also includes: If the number of packets in the packet sequence is less than or equal to four, then checking whether the number of packets in the packet sequence is greater than two; If the number of data packets in the data packet sequence is greater than two, determining any intermediate data packet at a middle position of the data packet sequence, and determining a data packet sequence between the first data packet in the data packet sequence and the intermediate data packet as a third target data packet sequence segment; Performing a simulation test on the chip under test based on the third target data packet sequence segment, and reducing the data packet sequence based on the simulation test result to obtain a reduced data packet sequence; The reduced data packet sequence is used as a new data packet sequence, and the step of detecting whether the number of data packets in the data packet sequence is greater than two is jumped to execute until the number of data packets in the data packet sequence is less than or equal to two, and the last data packet in the data packet sequence is determined as the target data packet that causes the simulation test to fail.

8. The method for locating failures in chip simulation testing according to any one of claims 1 to 3, characterized in that: After extracting the data packet sequence of the test case, the method further includes: Performing a simulation test on the chip to be tested using the first data packet in the data packet sequence; If the simulation test fails, the first data packet in the data packet sequence is determined as the target data packet causing the simulation test failure; If the simulation test is successful, the step of extracting the target data packet sequence segment from the data packet sequence is executed.

9. A failure location device in chip simulation testing, characterized in that: include: An acquisition module is used to acquire test cases that fail during simulation testing of the chip under test; An extraction module, configured to extract a data packet sequence of the test case and extract a target data packet sequence segment from the data packet sequence; An updating module, configured to perform a simulation test on the chip to be tested based on the target data packet sequence segment, and reduce the data packet sequence based on the simulation test result to obtain a reduced data packet sequence; The jump module is used to use the reduced data packet sequence as a new data packet sequence and jump to execute the step of extracting the target data packet sequence segment from the data packet sequence until the target data packet causing the simulation test failure is determined in the data packet sequence.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 8 when being executed by a processor.

Images