Driving device, display device and driving method thereof

Abstract

The invention discloses a driving device, a display device and a driving method thereof. The display device may include: a display panel including a plurality of pixels; a timing control unit that generates image data to be displayed in each of the pixels on the basis of input image data; a data driving unit that determines first data voltages corresponding to data lines connected to the pixels on the basis of the image data, and supplies second data voltages to the data lines, the second data voltages being generated by adding compensation voltages to the determined first data voltages; and a crosstalk compensation unit that calculates the compensation voltage by comparing the first data voltages corresponding to the pixels disposed on three or more horizontal lines adjacent to each other among the pixels with each other in units of adjacent horizontal lines.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202110037342.0 filed on January 12, 2021, and invention name “Display device and driving method thereof”. Technical Field

[0002] The present invention relates to a display device, and more particularly to a display device and a driving method thereof. Background Art

[0003] With the advancement of information technology, the importance of display devices as a medium connecting users and information has become increasingly prominent. In response, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), and plasma display devices (PDPs) is increasing.

[0004] Each pixel of the display device can emit light at a brightness corresponding to a data voltage supplied through the data line, and the display device can display an image frame by combining the light emission of each pixel.

[0005] At this time, depending on the pattern of the image frame, line crosstalk or horizontal crosstalk may occur, which may reduce the display quality. If line crosstalk occurs, unexpected bright lines or dark lines will be displayed, and the user may perceive the display as an error. Summary of the Invention

[0006] An object of the present invention is to provide a display device that adds a compensation voltage for eliminating horizontal crosstalk to a data voltage to be supplied to each pixel and supplies the resulting voltage to each pixel in order to eliminate horizontal crosstalk that may occur between pixels arranged in units of horizontal lines.

[0007] Another object of the present invention is to provide a driving method of the display device.

[0008] However, the purpose of the present invention is not limited to the above-mentioned purpose, and various extensions can be made without departing from the scope of the idea and field of the present invention.

[0009] One aspect of the present invention to achieve the above-mentioned objective provides a display device.

[0010] The display device includes a display panel including a plurality of pixels, a timing control section that generates image data to be displayed in each of the pixels based on input image data, a data drive section that determines each first data voltage corresponding to each data line connected to each of the pixels based on the image data, and supplies each second data voltage to each of the data lines, each of the second data voltages being generated by adding a compensation voltage to each determined first data voltage, and a crosstalk compensation section that compares each of the first data voltages corresponding to each of the pixels arranged on three or more horizontal lines adjacent to each other among the pixels with each other in units of adjacent horizontal lines, and thereby calculates the compensation voltage.

[0011] The crosstalk compensation section can include a first data compensation section that compares each of the first data voltages corresponding to each of the pixels arranged on an i-th (i is a natural number of three or more) horizontal line with each of the first data voltages corresponding to each of the pixels arranged on an (i-1)-th horizontal line, and thereby outputs a first compensation voltage, and a second data compensation section that compares each of the first data voltages corresponding to each of the pixels arranged on the (i-1)-th horizontal line to an i-k-th (k is a natural number greater than 1 and smaller than i) horizontal line in units of adjacent horizontal lines, and thereby outputs a second compensation voltage.

[0012] The crosstalk compensation section can further include a first addition section that linearly combines the first compensation voltage and the second compensation voltage to calculate the compensation voltage.

[0013] The first data compensation section can include an average voltage calculation section that outputs a first average value of each of the first data voltages corresponding to each of the pixels arranged on the i-th horizontal line, a first delay section that delays an output of the average voltage calculation section by a predetermined time, and thereby outputs a second average value of each of the first data voltages corresponding to each of the pixels arranged on the (i-1)-th horizontal line, a difference calculation section that outputs a first difference voltage by differentiating the first average value and the second average value from each other, and a first compensation gain application section that applies a first compensation gain to the first difference voltage, and thereby outputs the first compensation voltage.

[0014] The first compensation gain can be predetermined such that horizontal crosstalk between each of the pixels arranged on the i-th horizontal line and each of the pixels arranged on the (i-1)-th horizontal line is cancelled out.

[0015] The predetermined time can be one horizontal period.

[0016] The second data compensation section can include a second delay section that delays the output of the difference calculation section by a predetermined time to output at least one differential voltage corresponding to each of the pixels arranged on the (i-1)th horizontal line to the (i-k)th horizontal line, a second compensation gain application section that applies a second compensation gain independently to the at least one differential voltage, and a second addition section that adds each output value of the second compensation gain application section to output the second compensation voltage.

[0017] The second compensation gain can be predetermined such that horizontal crosstalk between each of the pixels arranged on the (i-1)th horizontal line to the (i-k)th horizontal line is cancelled out.

[0018] The at least one differential voltage can include a second differential voltage that is a voltage between an average of each of the first data voltages corresponding to each of the pixels arranged on the (i-1)th horizontal line and an average of each of the first data voltages corresponding to each of the pixels arranged on the (i-2)th horizontal line, and a third differential voltage that is a voltage between an average of each of the first data voltages corresponding to each of the pixels arranged on the (i-2)th horizontal line and an average of each of the first data voltages corresponding to each of the pixels arranged on the (i-3)th horizontal line.

[0019] The second data compensation section can include a second addition section that adds the first differential voltage and the output of the second compensation gain application section to each other to output, a second delay section that delays the output of the second addition section by a predetermined time to output the second compensation voltage, and the second compensation gain application section that applies a second compensation gain to the output of the second delay section to feedback to the second addition section.

[0020] The display device can further include a memory that stores each of the first data voltages in units of horizontal lines.

[0021] The data driving section can read each of the first data voltages corresponding to each of the pixels arranged on the ith horizontal line from the memory and add the compensation voltage to each of the read first data voltages to generate the second data voltage.

[0022] Other aspects of the present application for achieving the object provide a driving method of a display device.

[0023] The driving method of the display device can include the steps of determining first data voltages corresponding to data lines connected to pixels based on image data; comparing the first data voltages corresponding to the pixels arranged on three or more horizontal lines adjacent to each other among the pixels in units of adjacent horizontal lines to calculate a compensation voltage; generating second data voltages by adding the compensation voltage to the first data voltages; and supplying the second data voltages to the data lines.

[0024] The step of calculating the compensation voltage can include the steps of comparing the first data voltages corresponding to the pixels arranged on an i-th (i is a natural number of three or more) horizontal line and the first data voltages corresponding to the pixels arranged on an i-1-th horizontal line to calculate a first compensation voltage; and comparing the first data voltages corresponding to the pixels arranged on the i-1-th horizontal line to an i-k-th (k is a natural number greater than 1 and less than i) horizontal line in units of adjacent horizontal lines to calculate a second compensation voltage.

[0025] The step of calculating the compensation voltage can include the step of calculating the compensation voltage by linearly combining the first compensation voltage and the second compensation voltage.

[0026] The step of calculating the first compensation voltage can include the steps of calculating a first differential voltage by differentiating a first average of the first data voltages corresponding to the pixels arranged on the i-th horizontal line and a second average of the first data voltages corresponding to the pixels arranged on the i-1-th horizontal line from each other; and calculating the first compensation voltage by applying a first compensation gain to the first differential voltage.

[0027] The first compensation gain can be determined in advance so that horizontal crosstalk between the pixels arranged on the i-th horizontal line and the pixels arranged on the i-1-th horizontal line is canceled out.

[0028] The step of calculating the second compensation voltage can include the steps of calculating an average value in units of horizontal line for the first data voltages corresponding to the pixels arranged on the i-1-th horizontal line to the i-k-th horizontal line; calculating at least one differential voltage by differentiating each of the average values corresponding to adjacent horizontal lines from each other; applying a second compensation gain to the at least one differential voltage; and calculating the second compensation voltage by adding the at least one differential voltage to which the second compensation gain is applied.

[0029] It can be that the second compensation gain is applied to the at least one differential voltage at a certain attenuation ratio, respectively.

[0030] It can be that the step of generating the second data voltage is a step of adding the compensation voltage to the first data voltage corresponding to the pixel arranged on the i-th horizontal line to generate the second data voltage.

[0031] (Inventive Effects)

[0032] The display device and the driving method thereof according to the present application can prevent horizontal crosstalk or line crosstalk that can occur on two or more horizontal lines in addition to horizontal crosstalk or line crosstalk that can occur on two adjacent horizontal lines. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a view for explaining a display device according to an embodiment of the present application.

[0034] Figure 2 is a circuit diagram exemplarily showing a pixel according to an embodiment of the present application.

[0035] Figure 3 is a conceptual view for explaining horizontal crosstalk that a display device according to an embodiment of the present application intends to improve.

[0036] Figure 4 is a block diagram showing Figure 1 is an exemplary view showing a configuration of a crosstalk compensation section according to an embodiment of the present application.

[0037] Figure 5 is a block diagram showing a first embodiment of a crosstalk compensation section according to an embodiment of the present application.

[0038] Figure 6 is a block diagram showing a second embodiment of a crosstalk compensation section according to an embodiment of the present application.

[0039] Figure 7 is a flowchart showing a driving method of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] Hereinafter, each embodiment of the present application will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present application. The present application can be realized by various means, and is not limited to the embodiments described herein.

[0041] In order to clearly explain the present application, portions unrelated to the explanation are omitted, and the same or similar constituent elements are assigned the same reference numerals throughout the specification. Thus, the symbols previously explained can be used in other drawings.

[0042] Further, the size and the thickness of each of the illustrated components are arbitrarily shown for the purpose of explanation, and the present application is not necessarily limited to the illustrated cases. In the drawings, the thicknesses are exaggerated for the purpose of clear illustration of each layer and region.

[0043] Figure 1 FIG. 1 is a diagram for explaining a display device to which an embodiment of the present application relates.

[0044] Referring to Figure 1 , the display device DD can include a display panel 100, a timing control section 200, a scan driving section 300, a light emitting driving section 400, a data driving section 500, a crosstalk compensation section 510, a memory 520, and a power management section 600.

[0045] The display panel 100 can include a plurality of pixels PX[i,j]. The plurality of pixels PX[i,j] can be constituted by p rows (p is a natural number) and q columns (q is a natural number). Each pixel PX[i,j] arranged in the same row (hereinafter, it is possible to mix a horizontal line to refer to) can be connected to the same scan line and the same light emitting line. In addition, each pixel PX[i,j] arranged in the same column (hereinafter, it is possible to mix a vertical line to refer to) can be connected to the same data line. For example, the pixel PX[i,j] arranged in the i-th (i is a natural number below p) row and the j-th (j is a natural number below q) column can be connected to the i-th scan line SL[i] and the i-th light emitting line EL[i], and to the j-th data line DL[j].

[0046] The timing control section 200 can generate a scan driving control signal SCS, a data driving control signal DCS, and a light emitting control signal ECS in correspondence with a synchronization signal supplied from the outside. The scan driving control signal SCS can be supplied to the scan driving section 300, the data driving control signal DCS can be supplied to the data driving section 500, and the light emitting control signal ECS can be supplied to the light emitting driving section 400. In addition, the timing control section 200 can generate image data RGB based on input image data (not illustrated) supplied from the outside, and supply the generated image data RGB to the data driving section 500. For example, the timing control section 200 can decide a digital voltage corresponding to a gradation value constituting the input image data (not illustrated), and generate the image data RGB indicating the decided digital voltage.

[0047] The scan driving control signal SCS can include a scan start signal and a clock signal. The scan start signal can be a signal for controlling a first timing of a scan signal. The clock signal can be used in order to shift the scan start signal.

[0048] The light emission control signal ECS can include a light emission start signal and a clock signal. The light emission start signal can control a first timing of the light emission signal. The clock signal can be used for shifting the light emission start signal.

[0049] The data drive control signal DCS can include a source start pulse and a clock signal. The source start pulse can control a sampling start time point of the data. The clock signal can be used for controlling the sampling operation.

[0050] The scan driving section 300 can receive the scan drive control signal SCS from the timing control section 200, and supply the scan signal to each scan line SL[1], SL[2],..., SL[p] in turn based on the scan drive control signal SCS. If the scan signal is supplied in turn, each pixel PX[i,j] is selected in a horizontal line unit (or a pixel row unit), and the data signal can be supplied to the selected pixel PX[i,j].

[0051] The scan driving section 300 can include scan driving stages configured in a shift register form. The scan driving section 300 can generate the scan signal in a manner that the scan start signal in the form of a pulse with a turn-on level is sequentially transferred to the next scan driving stage according to the control of the clock signal.

[0052] The light emission driving section 400 can receive the light emission control signal ECS from the timing control section 200, and supply the light emission signal to each light emission control line EL[1], EL[2],..., EL[p] in turn based on the light emission control signal ECS. The light emission signal can be used for controlling the light emission time of each pixel PX[i,j]. For this purpose, the light emission signal can be set with a width wider than the scan signal.

[0053] The data driving section 500 can receive the data drive control signal DCS and the image data RGB from the timing control section 200. The data driving section 500 can determine each first data voltage to be supplied to each data line DL[1], DL[2],..., DL[q] based on the image data RGB, and supply each second data voltage to each data line DL[1], DL[2],..., DL[q], wherein each second data voltage is generated by adding a compensation voltage for compensating horizontal crosstalk to each determined first data voltage.

[0054] The data driving part 500 can supply each second data voltage to each data line DL[1], DL[2],..., DL[q] in correspondence with the data driving control signal DCS. Each second data voltage can be supplied to each pixel PX[i,j] disposed on a horizontal line selected according to a scan signal. To this end, the data driving part 500 can supply each second data voltage to each data line DL[1], DL[2],..., DL[q] in synchronization with the scan signal.

[0055] For example, the data driving part 500 can determine each first data voltage DV[1], DV[2],..., DV[q] (hereinafter referred to as LDV[i]) that should be supplied to each pixel PX[i,j] disposed on the i-th horizontal line selected according to a scan signal, and store the determined each first data voltage LDV[i] in the memory 520 in units of horizontal lines (or every other horizontal period).

[0056] In addition, the data driving part 500 can deliver each first data voltage DV[1], DV[2],..., DV[q] (hereinafter can be collectively referred to as LDV[i]) that should be supplied to each pixel PX[i,j] disposed on the i-th horizontal line to the crosstalk compensation part 510, and can receive a compensation voltage CDV[i] for compensating for each first data voltage DV[1], DV[2],..., DV[q] from the crosstalk compensation part 510. The data driving part 500 can add the received compensation voltage CDV[i] to each first data voltage DV[1], DV[2],..., DV[q] read from the memory 520, thereby generating each second data voltage.

[0057] The crosstalk compensation section 510 can compare each first data voltage corresponding to each pixel arranged on three or more horizontal lines (for example, the i-2, i-1, and i horizontal lines) adjacent to each other among the pixels PX[i, j] with each other, and calculate a compensation voltage CDV[i] based on the comparison. The crosstalk compensation section 510 can supply the calculated compensation voltage CDV[i] to the data drive section 500. Specifically, for example, the crosstalk compensation section 510 can compare each first data voltage LDV[i] corresponding to each pixel arranged on the i horizontal line with each first data voltage LDV[i-1] corresponding to each pixel arranged on the i-1 horizontal line. The crosstalk compensation section 510 can compare each first data voltage LDV[i-1] corresponding to each pixel arranged on the i-1 horizontal line with each first data voltage LDV[i-2] corresponding to each pixel arranged on the i-2 horizontal line. The crosstalk compensation section 510 can compare each first data voltage LDV[i-2] corresponding to each pixel arranged on the i-2 horizontal line with each first data voltage LDV[i-3] corresponding to each pixel arranged on the i-3 horizontal line. Here, the calculated compensation voltage CDV[i] can be added to each first data voltage LDV[i] corresponding to each pixel arranged on the i horizontal line.

[0058] That is, the crosstalk compensation section 510 according to an embodiment of the present disclosure can compensate for each first data voltage LDV[i] corresponding to each pixel arranged on the i horizontal line by considering each first data voltage LDV[i-1] corresponding to each pixel arranged on the i-1 horizontal line, each first data voltage LDV[i-2] corresponding to each pixel arranged on the i-2 horizontal line, and each first data voltage LDV[i-3] corresponding to each pixel arranged on the i-3 horizontal line. Accordingly, the crosstalk compensation section 510 according to an embodiment of the present disclosure can compensate for horizontal crosstalk generated through two or more horizontal lines.

[0059] The power management section 600 can supply a voltage of a first power source VDD, a voltage of a second power source VSS, and a voltage of an initialization power source Vint to the display panel 100. The first power source VDD and the second power source VSS can generate a voltage for driving the light emitting element included in each pixel PX[i, j] of the display panel 100. In an embodiment, the voltage of the second power source VSS can be lower than the voltage of the first power source VDD. For example, the voltage of the first power source VDD can be a positive voltage, and the voltage of the second power source VSS can be a negative voltage. The voltage of the initialization power source Vint can initialize the driving transistor and / or the light emitting element included in each pixel PX[i, j].

[0060] In Figure 1The crosstalk compensation section 510 and the storage 520 are shown separately from the data driver 500, but are not necessarily limited thereto, and can be integrated with the data driver 500.

[0061] Figure 2 FIG. 1 is a circuit diagram illustrating a pixel according to an embodiment of the present application.

[0062] In Figure 2 In the drawings, a pixel PX[i, j] arranged in the ith row (or horizontal line) and the jth column is shown for convenience of explanation, but the same circuit can be applied to other pixels.

[0063] Referring to Figure 2 The pixel PX[i, j] can include a light emitting element EL, first to seventh transistors T1 to T7, and an energy storage capacitor Cst.

[0064] The light emitting element EL can include a first electrode electrically connected to a second electrode (e.g., a drain electrode) of the first transistor T1 and a second electrode connected to the second power supply VSS. Specifically, the first electrode of the light emitting element EL can be electrically connected to the second electrode of the first transistor T1 through the sixth transistor T6.

[0065] The light emitting element EL can generate light of a predetermined brightness in correspondence with an amount of current (a drive current) supplied from the first transistor T1. In an embodiment, the light emitting element EL can be an organic light emitting diode including an organic light emitting layer. In this case, the first electrode of the light emitting element EL can be an anode, and the second electrode can be a cathode. Conversely, the first electrode of the light emitting element EL can be a cathode, and the second electrode can be an anode.

[0066] In other embodiments, the light emitting element EL can be an inorganic light emitting element formed of an inorganic substance. Alternatively, the light emitting element EL can have a plurality of inorganic light emitting elements connected in parallel and / or in series between the second power supply VSS and the second electrode of the first transistor T1.

[0067] The first transistor T1 can include a first electrode electrically connected to the first power supply VDD, a second electrode electrically connected to the first electrode of the light emitting element EL, and a gate electrode connected to the first node N1. Specifically, the first electrode of the first transistor T1 can be connected to the first power supply VDD through the fifth transistor T5. The second electrode of the first transistor T1 can be connected to the light emitting element EL through the sixth transistor T6. The first transistor T1 can supply a drive current to the light emitting element EL. The first transistor T1 can be referred to as a drive transistor. That is, the first transistor T1 can control an amount of current flowing from the first power supply VDD to the second power supply VSS via the light emitting element EL in correspondence with a voltage applied to the first node N1.

[0068] The storage capacitor Cst can be connected between the first power source VDD and the first node N1. For example, the storage capacitor Cst can include a first electrode connected to the first power source VDD and a second electrode connected to the first node N1. The storage capacitor Cst can be charged by a differential voltage between the first power source VDD and the first node N1.

[0069] The second transistor T2 can be connected between the data line DL[j] and the third node N3. The second transistor T2 can include a gate electrode connected to the i-th scan line SL[i]. The second transistor T2 can be turned on when a scan signal (which can be a low level) is supplied to the i-th scan line SL[i], so that the data line DL[j] and the third node N3 can be electrically connected. Accordingly, a data voltage (or a data signal) supplied to the data line DL[j] can be transferred to the third node N3.

[0070] Further, if the second transistor T2 is turned on in correspondence with the scan signal supplied to the i-th scan line SL[i], a data voltage supplied through the data line DL[j] can be charged to the storage capacitor Cst. For example, the storage capacitor Cst can be charged by a differential voltage between the voltage of the first power source VDD and the data voltage.

[0071] The third transistor T3 can be connected between the first node N1 and the second node N2. The third transistor T3 can include a gate electrode connected to the i-th scan line SL[i]. The third transistor T3 can be turned on when a scan signal (which can be a low level) is supplied to the i-th scan line SL[i], so that the first node N1 and the second node N2 can be electrically connected. If the first node N1 and the second node N2 are electrically connected to each other, the first transistor T1 can become a form equivalent to a diode. In the case where the first transistor T1 has a form equivalent to a diode, a threshold voltage of the first transistor T1 can be compensated by a charge charged to the first electrode of the first transistor T1.

[0072] The fourth transistor T4 can be connected between the first node N1 and the initialization power source Vint, and can include a gate electrode connected to a previous scan line (or an i-1-th scan line SL[i-1]). The fourth transistor T4 can be turned on when a previous scan signal is supplied through the previous scan line, so that the gate electrode of the first transistor T1 and the second electrode of the storage capacitor Cst are initialized with a voltage of the initialization power source Vint.

[0073] The fifth transistor T5 can be connected between the first power supply VDD and the third node N3. The fifth transistor T5 can include a gate electrode connected to the i-th light emitting control line EL[i]. The fifth transistor T5 can be turned on by a light emitting control signal supplied through the i-th light emitting control line EL[i], thereby electrically connecting the first electrode of the first transistor T1 and the first power supply VDD to each other.

[0074] The sixth transistor T6 can be connected between the second node N2 and the first electrode of the light emitting element EL. The sixth transistor T6 can include a gate electrode connected to the i-th light emitting control line EL[i]. For example, the sixth transistor T6 can be turned on by a light emitting control signal supplied through the i-th light emitting control line EL[i], thereby electrically connecting the second node N2 and the first electrode of the light emitting element EL.

[0075] The seventh transistor T7 can be connected between the first electrode of the light emitting element EL and the initialization power supply Vint. The seventh transistor T7 can include a gate electrode connected to the i-th scan line SL[i]. Accordingly, the seventh transistor T7 can be turned on by a scan signal supplied to the i-th scan line SL[i], thereby initializing the voltage of the first electrode of the light emitting element EL with the voltage of the initialization power supply Vint.

[0076] In an embodiment, Figure 2 Each of the transistors T1, T2, T3, T4, T5, T6, and T7 illustrated can be a p-type transistor (PMOS). For example, Figure 2 Each of the transistors T1, T2, T3, T4, T5, T6, and T7 illustrated can be an LTPS (Low-Temperature Poly-Silicon) thin film transistor. However, it is not necessarily limited thereto, and each of the transistors T1, T2, T3, T4, T5, T6, and T7 can be an n-type transistor (NMOS).

[0077] An embodiment of the present application relates to a display device DD, which is not limited to Figure 2 The explanation of the pixel described above can also be applied to various forms of pixels applicable to those skilled in the art.

[0078] On the other hand, in Figure 2In the pixel PX[i,j] shown, a capacitive coupling Cde can occur between the wiring to which the first power supply VDD is applied and the data line DL[j]. In addition, a capacitive coupling Cdi can occur between the data line DL[j] and the wiring to which the initialization power supply Vint is applied. In addition, a capacitive coupling Cgi can occur between the wiring to which the initialization power supply Vint is applied and the gate electrode of the first transistor Tl. Such capacitive couplings Cde, Cdi, Cgi (which can also be referred to as parasitic capacitances) can cause the initialization to be performed at a voltage different from the initialization power supply Vint when the initialization based on the initialization power supply Vint is performed, and can also affect the voltage stored in the storage capacitor Cst. In addition, when the first power supply VDD is supplied, impulse noise can also be included, which can be a factor of the reaction speed of the voltage supplied to the initialization power supply Vint becoming slow. In particular, horizontal crosstalk in which a residual image occurs between adjacent horizontal lines can occur due to such capacitive couplings. The horizontal crosstalk can be referred to in combination with line crosstalk.

[0079] Figure 3 FIG. 1 is a conceptual view for explaining horizontal crosstalk which a display device according to an embodiment of the present application is intended to improve.

[0080] Referring to FIG. 1, Figure 3 The scan lines SL[1],..., SL[r-l], SL[r], SL[r+l], SL[r+2], SL[r+3], SL[r+4],..., SL[s-l], SL[s], SL[s+l], SL[s+2], SL[s+3], SL[s+4],..., SL[p] can be alternately arranged along the first direction DRl at one side of the display panel 100, and each of the horizontal lines in which pixels are arranged can be connected to one scan line.

[0081] The data lines DL[1],..., DL[u], DL[u+l],..., DL[v], DL[v+l],..., DL[q] can be alternately arranged along the second direction DR2 at one side of the display panel 100, and each of the vertical lines in which pixels are arranged can be connected to one data line.

[0082] Referring to FIG. 1, Figure 3The pixels connected to the first to (r-1)th (r is a natural number larger than 0 and smaller than p) scan lines SL[r-1] can receive a data voltage corresponding to 128 gray. During the next scan, some of the pixels connected to the rth to (r+4)th scan lines SL[r+4] and the pixels connected to the (s-1)th scan line SL[s-1] can receive a data voltage corresponding to 128 gray, and the rest can receive a data voltage corresponding to 0 gray. In addition, the pixels connected to the sth to last scan lines SL[p] (not shown) can receive a data voltage corresponding to 128 gray.

[0083] Ideally, the pixel PX[r, u] connected to the rth scan line SL[r] and the (u)th data line DL[u] and the pixel PX[r, u+1] connected to the rth scan line SL[r] and the (u+1)th data line DL[u+1] can emit light at 128 gray.

[0084] However, due to the capacitive coupling explained in Figure 2 , the pixel PX[r, u] connected to the rth scan line SL[r] and the (u)th data line DL[u] and the pixel PX[r, u+1] connected to the rth scan line SL[r] and the (u+1)th data line DL[u+1] can emit light at a gray higher than 128 gray. Thus, a bright line can occur in which the pixels connected to the rth scan line SL[r] appear brighter than the pixels connected to the (r-1)th scan line SL[r-1].

[0085] Ideally, the pixel PX[s, u] connected to the sth scan line SL[s] and the (u)th data line DL[u] and the pixel PX[s, u+1] connected to the sth scan line SL[s] and the (u+1)th data line DL[u+1] can emit light at 128 gray.

[0086] However, due to the capacitive coupling explained in Figure 2 , the pixel PX[s, u] connected to the sth scan line SL[s] and the (u)th data line DL[u] and the pixel PX[s, u+1] connected to the sth scan line SL[s] and the (u+1)th data line DL[u+1] can emit light at a gray lower than 128 gray. Thus, a dark line can occur in which the pixels connected to the sth scan line SL[s] appear darker than the pixels connected to the (s-1)th scan line SL[s-1].

[0087] The bright line or the dark line as described above does not necessarily occur only between the horizontal lines in which the data voltage sharply changes. For example, Figure 2 The voltage involved in the initialization power supply can possibly decrease in response speed until the horizontal line, so that the bright line or the dark line can possibly occur on the horizontal line in stages.

[0088] For example, the pixels connected to the (r+1)th scan line SL[r+1] can emit light in a gray level higher than 128 gray levels, although they are darker than the pixels connected to the rth scan line SL[r]. The pixels connected to the (r+2)th scan line SL[r+2] can emit light in a gray level higher than 128 gray levels, although they are darker than the pixels connected to the (r+1)th scan line SL[r+1].

[0089] Similarly, the pixels connected to the (s+1)th scan line SL[s+1] can emit light in a gray level lower than 128 gray levels, although they are brighter than the pixels connected to the sth scan line SL[s]. The pixels connected to the (s+2)th scan line SL[s+2] can emit light in a gray level lower than 128 gray levels, although they are brighter than the pixels connected to the (s+1)th scan line SL[s+1].

[0090] As described above, the horizontal crosstalk in which the bright line or the dark line occurs can occur via the horizontal lines, so that the data voltage input to one horizontal line needs to be compensated based on the data voltage input to the horizontal lines.

[0091] Hereinafter, the configuration and the operation of the crosstalk compensation section 510 for improving the horizontal crosstalk will be described in detail with reference to the pixels arranged on the ith (i is a natural number of 3 or more) horizontal line as a reference (i.e., with reference to the pixels arranged on at least three horizontal lines).

[0092] Figure 4 is a graph showing Figure 1 An example of the configuration of the crosstalk compensation section.

[0093] Referring to Figure 4 The crosstalk compensation section 510 can include a first data compensation section 511, a second data compensation section 512, and a first addition section 513.

[0094] The first data compensation unit 511 may sequentially receive inputs of the first data voltages supplied to the pixels arranged on a horizontal line from the data driving unit 500. For example, the first data compensation unit 511 may sequentially receive inputs of the first data voltages DV[1], DV[2], ..., DV[q], or LDV[i] corresponding to the pixels arranged on the i-th horizontal line. Furthermore, the first data compensation unit 511 may compare the first data voltages LDV[i] corresponding to the pixels arranged on the i-th horizontal line (i is a natural number greater than or equal to 3) with the first data voltages LDV[i-1] corresponding to the pixels arranged on the i-1-th horizontal line, thereby outputting a first compensation voltage XT1.

[0095] The second data compensating unit 512 can compare the first data voltages LDV[i-2], LDV[i-3], ..., LDV[ik] corresponding to the pixels arranged on the i-1th horizontal line to the ikth horizontal line (k is a natural number greater than 1 and less than i) in units of adjacent horizontal lines, thereby outputting the second compensation voltage XT2. To this end, the second data compensating unit 512 can receive the first differential voltage dSV[i] (refer to Figures 5 to 6 ), but is not necessarily limited thereto. For example, the second data compensation unit 512 may also be implemented as follows: similarly to the first data compensation unit 511, the second data compensation unit 512 may directly and sequentially receive inputs of the first data voltages DV[1], DV[2], ..., DV[q], or LDV[i] supplied to the pixels arranged on the ikth horizontal line from the data driving unit 500, and output the second compensation voltage XT2.

[0096] The first adding unit 513 may linearly combine the first compensation voltage XT1 and the second compensation voltage XT2 to calculate the compensation voltage CDV[i]. For example, the first adding unit 513 may add the first compensation voltage XT1 and the second compensation voltage XT2 to calculate the compensation voltage CDV[i]. The calculated compensation voltage CDV[i] may be added to each first data voltage LDV[i] corresponding to each pixel arranged on the i-th horizontal line by the data driving unit 500.

[0097] Figure 5 This is a block diagram showing a first embodiment of a crosstalk compensation unit according to an embodiment of the present invention.

[0098] Reference Figure 5 The first data compensation part 511 may include an average voltage calculation part AVGR, a first delay part DR1, a difference calculation part DFC, and a first compensation gain application part GXT1.

[0099] The average voltage calculation section AVGR can output a first average value AVG[i] of the first data voltages LDV[i] corresponding to the pixels arranged on the i-th horizontal line. For example, the average voltage calculation section AVGR can add the first data voltages LDV[i] corresponding to the pixels arranged on the i-th horizontal line to calculate a first average value of the added first data voltages.

[0100] The first delay section DR1 can delay the output of the average voltage calculation section AVGR by a predetermined time to output a second average value AVG[i-1] of the first data voltages corresponding to the pixels arranged on the i-1-th horizontal line. Here, the predetermined time can be one horizontal period. That is, the first delay section DR1 delays and outputs the output of the average voltage calculation section AVGR by one horizontal period, so that at the point in time when the average voltage calculation section AVGR outputs the first average value AVG[i] of the first data voltages LDV[i] corresponding to the pixels arranged on the i-th horizontal line, the first delay section DR1 outputs the second average value AVG[i-1] of the first data voltages LDV[i-1] corresponding to the pixels arranged on the i-1-th horizontal line. The first delay section DR1 can be implemented by a delay register.

[0101] The difference calculation section DFC can output a first difference voltage dSV[i] by differencing the first average value AVG[i] and the second average value AVG[i-1] from each other. Here, the first difference voltage dSV[i] can correspond to an average data voltage difference between the pixels arranged on the i-th horizontal line and the pixels arranged on the i-1-th horizontal line.

[0102] The first compensation gain application section GXT1 can apply a first compensation gain to the first difference voltage dSV[i] to output a first compensation voltage XT1 to the first addition section 513. For example, the first compensation gain application section GXT1 can be implemented by an amplification circuit having various forms of gain.

[0103] The first compensation gain can be predetermined such that the horizontal crosstalk between the pixels arranged on the i-th horizontal line and the pixels arranged on the i-1-th horizontal line is cancelled out. For example, as shown in FIG. 6, input image data in which the data voltages supplied to the pixels are sharply changed on a certain horizontal line can be input to the display device DD, and the first compensation gain to remove bright lines or dark lines appearing in the pixels arranged on the i-th horizontal line and the i-1-th horizontal line adjacent to each other can be experimentally determined. Figure 3

[0104] The second data compensation section 512a can include a second delay section DR2, a second compensation gain application section GXT2, and a second addition section ADR2.​

[0105] The second delay section DR2 can delay the output of the difference calculation section DFC by a predetermined time, and output at least one difference voltage corresponding to each pixel arranged on the i-1th horizontal line to the i-kth horizontal line (k is a natural number larger than 1 and smaller than i). For example, the second delay section DR2 can delay the output of the difference calculation section DFC by one horizontal period to output the second difference voltage dSV[i-1], delay the output of the difference calculation section DFC by two horizontal periods to output the third difference voltage dSV[i-2], delay the output of the difference calculation section DFC by three horizontal periods to output the fourth difference voltage dSV[i-3], and delay the output of the difference calculation section DFC by four horizontal periods to output the fifth difference voltage dSV[i-4].

[0106] The second difference voltage dSV[i-1] can be a difference voltage between an average value of each first data voltage corresponding to each pixel arranged on the i-1th horizontal line and an average value of each first data voltage corresponding to each pixel arranged on the i-2th horizontal line. The third difference voltage dSV[i-2] can be a difference voltage between an average value of each first data voltage corresponding to each pixel arranged on the i-2th horizontal line and an average value of each first data voltage corresponding to each pixel arranged on the i-3th horizontal line. The fourth difference voltage dSV[i-3] can be a difference voltage between an average value of each first data voltage corresponding to each pixel arranged on the i-3th horizontal line and an average value of each first data voltage corresponding to each pixel arranged on the i-4th horizontal line. The fifth difference voltage dSV[i-4] can be a difference voltage between an average value of each first data voltage corresponding to each pixel arranged on the i-4th horizontal line and an average value of each first data voltage corresponding to each pixel arranged on the i-5th horizontal line.

[0107] In Figure 5 The case in which four delay registers DR are connected in series to output the second difference voltage dSV[i-1] to the fifth difference voltage dSV[i-4] is shown in FIG. 10, but this is an example, and the number of delay registers DR and the number of difference voltages output by the second delay section DR2 can be variously modified.

[0108] The second compensation gain application section GXT2 can apply the second compensation gains f1, f2, f3, f4, which are independent respectively, to at least one of the differential voltages output from the second delay section DR2. For example, the second compensation gain f1 can be applied to the second differential voltage dSV[i-1], the second compensation gain f2 can be applied to the third differential voltage dSV[i-2], the second compensation gain f3 can be applied to the fourth differential voltage dSV[i-3], and the second compensation gain f4 can be applied to the fifth differential voltage dSV[i-4] (f1, f2, f3, f4 are arbitrary constants). The second compensation gain application section GXT2 can be implemented by a plurality of amplification circuits GC that receive outputs of the respective delay registers DR included in the second delay section DR2.

[0109] The second compensation gains f1, f2, f3, f4 can be determined in advance so that the horizontal crosstalk between the respective pixels arranged on the i-k (k is a natural number larger than 2) horizontal line is canceled out. For example, the second compensation gain f1 can be determined experimentally so that the horizontal crosstalk between the respective pixels arranged on the i-1 horizontal line and the respective pixels arranged on the i-2 horizontal line is canceled out. The second compensation gain f2 can be determined experimentally so that the horizontal crosstalk between the respective pixels arranged on the i-2 horizontal line and the respective pixels arranged on the i-3 horizontal line is canceled out. The second compensation gain f3 can be determined experimentally so that the horizontal crosstalk between the respective pixels arranged on the i-3 horizontal line and the respective pixels arranged on the i-4 horizontal line is canceled out. The second compensation gain f4 can be determined in advance so that the horizontal crosstalk between the respective pixels arranged on the i-4 horizontal line and the respective pixels arranged on the i-5 horizontal line is canceled out.

[0110] The second addition section ADR2 can add the respective output values of the second compensation gain application section GXT2 to output a second compensation voltage XT2 to the first addition section 513. The first addition section 513 can add the first compensation voltage XT1 and the second compensation voltage XT2 to calculate a compensation voltage CDV[i].

[0111] Figure 6 is a block diagram showing a second embodiment of a crosstalk compensation section according to an embodiment of the present application.

[0112] Figure 6 is a block diagram showing a second embodiment of a crosstalk compensation section according to an embodiment of the present application. Figure 5 An embodiment of the second data compensation section 512a will be described below. Figure 5 An embodiment of the second data compensation section 512b will be described below.

[0113] As shown in FIG. 6, the second data compensation section 512a can be implemented by a plurality of amplification circuits GC that receive outputs of the respective delay registers DR included in the second delay section DR2. Figure 5 As shown in FIG. 6, the second data compensation section 512a can be implemented by a plurality of amplification circuits GC that receive outputs of the respective delay registers DR included in the second delay section DR2. As shown in FIG. 6, the second data compensation section 512a can be implemented by a plurality of amplification circuits GC that receive outputs of the respective delay registers DR included in the second delay section DR2.

[0114] The horizontal crosstalk has a tendency to gradually attenuate at a certain ratio between adjacent horizontal lines in many cases, and thus the second data compensation section 512b can be implemented in the form of a loop filter.

[0115] For example, the second data compensation section 512b can include a second addition section ADR2 that adds the first differential voltage dSV[i] and the output of a second compensation gain application section GXT2 to each other and outputs the result, a second delay section DR2 that delays the output of the second addition section ADR2 by a predetermined time and outputs a second compensation voltage XT2, and the second compensation gain application section GXT2 that applies a second compensation gain to the output of the second delay section DR2 and feeds back the result to the second addition section ADR2.

[0116] In the case where the second data compensation section 512b is in the form of a loop filter, the second compensation voltage XT2 can be expressed as XT2 = dSV[i-1] + f1 x dSV[i-2] + f1 x dSV[i-3] +... in Equation 1. Figure 6 2 In this case, the second differential voltage dSV[i-1] can not be applied with a compensation gain. To solve this problem, the second data compensation section 512b can further include a third compensation gain application section that applies a third compensation gain to the second compensation voltage XT2 in Equation 2. Figure 6

[0117] As shown in Equation 3, in the case where the second data compensation section 512b is implemented in the form of a loop filter, the second compensation gain application section GXT2 and the second delay section DR2 can be implemented by a single amplification circuit and a delay register, respectively, and thus the circuit area can be reduced. Figure 6

[0118] Figure 7 is a flowchart illustrating a driving method of a display device according to an embodiment of the present application.

[0119] Referring to Figure 7 , the driving method of the display device can include the steps of determining first data voltages to be supplied to data lines connected to pixels based on image data (S100), comparing the first data voltages corresponding to the pixels disposed on three or more horizontal lines adjacent to each other among the pixels with each other in units of the adjacent horizontal lines to thereby calculate a compensation voltage for compensating for horizontal crosstalk (S110), adding the compensation voltage to the first data voltages to thereby generate second data voltages (S120), and supplying the second data voltages to the data lines (S130).

[0120] ​​​The step S110 of calculating the compensation voltage can include a step of comparing the first data voltages corresponding to the pixels arranged on the i-th (i is a natural number of 3 or more) horizontal line with the first data voltages corresponding to the pixels arranged on the (i-1)-th horizontal line to calculate a first compensation voltage, and a step of comparing the first data voltages corresponding to the pixels arranged on the (i-1)-th to (i-k)-th (k is a natural number of more than 1 and less than i) horizontal lines in units of adjacent horizontal lines to calculate a second compensation voltage.

[0121] The step S110 of calculating the compensation voltage can include a step of linearly combining the first compensation voltage and the second compensation voltage to calculate the compensation voltage.

[0122] The step of calculating the first compensation voltage can include a step of differentiating a first average of the first data voltages corresponding to the pixels arranged on the i-th horizontal line from a second average of the first data voltages corresponding to the pixels arranged on the (i-1)-th horizontal line to calculate a first differential voltage, and a step of applying a first compensation gain to the first differential voltage to calculate the first compensation voltage.

[0123] The first compensation gain can be determined in advance so that horizontal crosstalk between the pixels arranged on the i-th horizontal line and the pixels arranged on the (i-1)-th horizontal line is cancelled out.

[0124] The step of calculating the second compensation voltage can include a step of calculating an average value of the first data voltages corresponding to the pixels arranged on the (i-1)-th to (i-k)-th horizontal lines in units of horizontal lines, a step of differentiating the average values corresponding to adjacent horizontal lines from each other to calculate at least one differential voltage, a step of applying a second compensation gain to the at least one differential voltage, and a step of adding the at least one differential voltage to which the second compensation gain is applied to calculate the second compensation voltage.

[0125] The second compensation gain can be applied to the at least one differential voltage at a certain attenuation rate, respectively.

[0126] The step S120 of generating the second data voltages can add the compensation voltage to each of the first data voltages corresponding to the pixels arranged on the i-th horizontal line to generate the second data voltages.

[0127] The display device DD described in Figures 1 to 6 can perform the driving method of the display device. Therefore, it should be interpreted that the operation method of the display device DD described in Figures 1 to 6 can be applied in addition to the above-described steps.

[0128] The foregoing description of the drawings and described embodiments of the application are only examples of the application and are not intended to limit the meaning, practices or scope of the application as set forth in the claims. Therefore, various modifications and other embodiments of the application can be made by those skilled in the art without departing from the true spirit and scope of the application. The true spirit and scope of the application should be determined by a fair reading of the appended claims.

Claims

1. A driving device configured to supply a data voltage to each pixel via each data line. The driving device comprises: a data driving unit that determines first data voltages corresponding to the pixels, generates second data voltages using compensation voltages for the determined first data voltages, and supplies the generated second data voltages to the pixels through the data lines; as well as a crosstalk compensation unit that calculates the compensation voltage by comparing the first data voltages corresponding to the pixels arranged on at least three or more adjacent horizontal lines among the pixels; The crosstalk compensation part outputs a compensation voltage by comparing first data voltages of pixels arranged on a horizontal line with first data voltages of pixels arranged on a horizontal line adjacent to the horizontal line. 2 . The driving device according to claim 1 , further comprising a timing control unit configured to generate image data to be displayed in each pixel based on input image data. 3 . The driving device according to claim 2 , further comprising a memory storing each of the first data voltages in units of horizontal lines. 4 . The driving device according to claim 3 , wherein the data driving section, the crosstalk compensation section, the timing control section, and the memory are included in one chip. 5 . The driving device of claim 1 , wherein each of the second data voltages is generated by adding the compensation voltage to each of the first data voltages.

6. A display device comprising: a display panel comprising a plurality of pixels connected to respective data lines; a data driving unit that determines first data voltages corresponding to the pixels, generates second data voltages using compensation voltages for the determined first data voltages, and supplies the generated second data voltages to the pixels through the data lines; a crosstalk compensation unit that calculates the compensation voltage by comparing the first data voltages corresponding to the pixels arranged on at least three or more adjacent horizontal lines among the pixels; The crosstalk compensation unit includes: a first data compensation unit that outputs a first compensation voltage by comparing the first data voltages corresponding to the pixels arranged on an i-th horizontal line with the first data voltages corresponding to the pixels arranged on an i-1-th horizontal line, where i is a natural number greater than or equal to 3; as well as The second data compensation unit outputs a second compensation voltage by comparing the first data voltages corresponding to the pixels arranged on the i-1th to ikth horizontal lines in units of adjacent horizontal lines, where k is a natural number greater than 1 and less than i. 7 . The display device of claim 6 , the crosstalk compensation section further comprising a first adding section that calculates the compensation voltage by linearly combining the first compensation voltage and the second compensation voltage.

8. The display device according to claim 6, wherein the first data compensating unit comprises: an average voltage calculation unit configured to output a first average value of the first data voltages corresponding to the pixels arranged on the i-th horizontal line; a first delay unit configured to delay the output of the average voltage calculation unit by a predetermined time to output a second average value of the first data voltages corresponding to the pixels arranged on the (i-1)th horizontal line; a difference calculation section that outputs a first differential voltage by differentiating the first average value and the second average value from each other; as well as A first compensation gain application section applies a first compensation gain to the first differential voltage to output the first compensation voltage. 9 . The display device according to claim 8 , wherein the first compensation gain is predetermined so that horizontal crosstalk between the pixels arranged on the i-th horizontal line and the pixels arranged on the (i-1)-th horizontal line is canceled out. 10 . The display device according to claim 8 , wherein the predetermined time is a horizontal period.

11. The display device according to claim 8, wherein the second data compensating unit comprises: a second delay unit that delays the output of the difference calculation unit by a predetermined time to output at least one differential voltage corresponding to each of the pixels arranged on the (i-1)th horizontal line to the (ik)th horizontal line; a second compensation gain applying unit configured to apply a second compensation gain independently of the other second compensation gain to the at least one differential voltage; as well as A second adding section outputs the second compensation voltage by adding the output value of the second compensation gain applying section. 12 . The display device according to claim 11 , wherein the second compensation gain is predetermined so that horizontal crosstalk between the pixels arranged on the (i-1)th horizontal line to the (ik)th horizontal line is canceled out.

13. The display device according to claim 11, wherein the at least one differential voltage comprises: a second differential voltage, wherein the second differential voltage is a voltage between an average value of the first data voltages corresponding to the pixels arranged on the (i-1)th horizontal line and an average value of the first data voltages corresponding to the pixels arranged on the (i-2)th horizontal line; as well as a third differential voltage, wherein the third differential voltage is a voltage between an average value of the first data voltages corresponding to the pixels arranged on the (i-2)th horizontal line and an average value of the first data voltages corresponding to the pixels arranged on the (i-3)th horizontal line.

14. The display device according to claim 8, wherein the second data compensating unit comprises: a second adding section configured to add the first differential voltage and an output of the second compensation gain applying section to output the voltage; a second delay unit configured to output the second compensation voltage by delaying the output of the second adder by a predetermined time; and The second compensation gain application section applies a second compensation gain to the output of the second delay section and feeds the resultant output back to the second addition section. 15 . The display device according to claim 6 , further comprising a timing control section configured to generate image data to be displayed in each pixel based on input image data. 16 . The display device of claim 15 , further comprising a memory configured to store each of the first data voltages in units of horizontal lines. 17 . The display device according to claim 16 , wherein the data driving part, the crosstalk compensation part, the timing control part, and the memory are included in one chip.

18. The display device according to claim 17, wherein the data driving unit reads the first data voltages corresponding to the pixels arranged on the i-th horizontal line from the memory, and adds the compensation voltage to each of the read first data voltages to generate the second data voltages.

19. The display device of claim 6, wherein each of the second data voltages is generated by adding the compensation voltage to each of the first data voltages.

20. A driving method for a driving device, comprising: determining first data voltages corresponding to data lines connected to pixels based on image data; a step of calculating a compensation voltage by comparing the first data voltages corresponding to the pixels arranged on three or more adjacent horizontal lines in units of adjacent horizontal lines; adding the compensation voltage to each of the first data voltages to generate each of the second data voltages; as well as supplying each of the second data voltages to each of the data lines, The step of calculating the compensation voltage is to output the compensation voltage by comparing the first data voltages of the pixels arranged on a horizontal line with the first data voltages of the pixels arranged on a horizontal line adjacent to the horizontal line.

21. The driving method of the driving device according to claim 20, wherein the step of calculating the compensation voltage comprises: a step of calculating a first compensation voltage by comparing the first data voltages corresponding to the pixels arranged on the i-th horizontal line with the first data voltages corresponding to the pixels arranged on the (i-1)-th horizontal line, wherein i is a natural number greater than or equal to 3; and The step of comparing the first data voltages corresponding to the pixels arranged on the (i-1)th to (ik)th horizontal lines in units of adjacent horizontal lines to output a second compensation voltage, wherein k is a natural number greater than 1 and less than i. 22 . The driving method of the driving device according to claim 21 , wherein the step of calculating the compensation voltage comprises the step of calculating the compensation voltage by linearly combining the first compensation voltage and the second compensation voltage.

23. The driving method of the driving device according to claim 21, wherein the step of calculating the first compensation voltage comprises: calculating a first differential voltage by differentiating a first average value of the first data voltages corresponding to the pixels arranged on the i-th horizontal line and a second average value of the first data voltages corresponding to the pixels arranged on the (i-1)th horizontal line; as well as The step of applying a first compensation gain to the first differential voltage to calculate the first compensation voltage. 24 . The driving method of claim 23 , wherein the first compensation gain is predetermined so that horizontal crosstalk between the pixels arranged on the i-th horizontal line and the pixels arranged on the (i-1)-th horizontal line is offset.

25. The driving method of the driving device according to claim 21, wherein the step of calculating the second compensation voltage comprises: a step of calculating an average value of each of the first data voltages corresponding to each of the pixels arranged on the (i-1)th horizontal line to the (ik)th horizontal line, using a horizontal line as a unit; a step of calculating at least one differential voltage by differentiating the average values ​​corresponding to adjacent horizontal lines from each other; the step of applying a second compensation gain to the at least one differential voltage; as well as The step of calculating the second compensation voltage by adding the at least one differential voltage to which the second compensation gain is applied. 26 . The driving method of the driving device according to claim 25 , wherein the second compensation gain is applied to the at least one differential voltage at a certain attenuation ratio.

27. The driving method of claim 21, wherein the step of generating the second data voltages is to add the compensation voltage to each of the first data voltages corresponding to the pixels arranged on the i-th horizontal line to generate the second data voltages.

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