Liquid crystal display driving circuit control method based on multi-channel synchronization

Abstract

This invention relates to the field of liquid crystal display driving technology and discloses a control method for a liquid crystal display driving circuit based on multi-channel synchronization. This method collects historical data of multi-channel display signals, extracts channel synchronization features to generate a multi-channel signal synchronization matrix, filters channel offset features and converts them into display driving timing coordination values. After activating the backlight adjustment unit, it collects display signal and backlight brightness data, determines the backlight interference intensity based on their interactive response, and constructs timing stability evaluation parameters by combining the display driving timing coordination values. These parameters are used to predict multi-channel signal distortion, generating display timing fluctuation deviations. When the fluctuation deviation exceeds a preset threshold, the refresh frequency parameters of the display driving circuit are adjusted. This method, by deeply mining historical data features and comprehensively evaluating the relationship between backlight interference and timing coordination, achieves precise control over the multi-channel signal transmission state, effectively optimizing the display driving effect of the liquid crystal display.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display driving technology, specifically to a control method for a liquid crystal display driving circuit based on multi-channel synchronization. Background Technology

[0002] With the continuous development of display technology, LCD monitors, with their thinness, lightness, and low power consumption, have been widely used in various electronic devices. To meet the demands for high resolution and high refresh rates, multi-channel display driving technology has gradually become mainstream. By transmitting display signals in parallel through multiple channels, data processing efficiency and display response speed can be effectively improved. However, under the multi-channel driving architecture, issues such as the synchronization of signals between channels, timing stability, and adaptability to external interference remain key factors restricting display quality.

[0003] In existing control methods for multi-channel display driver circuits, the synchronization processing of multi-channel signals largely relies on real-time signal acquisition and simple logic judgments, lacking in-depth mining of historical data. This makes it difficult to capture potential synchronization characteristics between channels when constructing channel synchronization relationships, and the generated synchronization matrix often deviates from the actual signal transmission state, thus affecting the accuracy of subsequent channel offset feature screening. Furthermore, traditional methods often use fixed compensation coefficients when processing channel offsets, failing to convert them into adaptive display driver timing coordination values ​​based on the dynamic changes in offset characteristics, resulting in a lack of targeted timing adjustments.

[0004] Backlight adjustment, as a crucial factor affecting display performance, involves a complex interactive response with the display signal. Current technologies often limit backlight interference assessments to single parameters (such as brightness fluctuation amplitude), failing to integrate the transmission status of the display signal for comprehensive analysis. This results in an inability to accurately quantify backlight interference intensity. This limitation leads to a lack of comprehensiveness in the construction of timing stability assessment parameters, making it difficult to accurately reflect the operating state of the drive circuit and consequently affecting the ability to predict signal distortion.

[0005] When multi-channel signals become distorted, existing control methods typically adjust the refresh rate only after the distortion has become apparent, lagging behind the actual signal changes. This passive adjustment not only fails to suppress timing fluctuations in a timely manner but may also cause flickering and stuttering in the display due to frequent adjustments, thus degrading the user's viewing experience. In summary, existing control methods for multi-channel LCD display drive circuits still have significant shortcomings in terms of synchronization accuracy, interference adaptability, and timeliness of timing adjustments, necessitating a more sophisticated control strategy. Summary of the Invention

[0006] The purpose of this invention is to provide a control method for a liquid crystal display driving circuit based on multi-channel synchronization, so as to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides a control method for a liquid crystal display display driving circuit based on multi-channel synchronization, the method comprising:

[0008] Historical data of multi-channel display signals are acquired through the display driver circuit;

[0009] Channel synchronization features are extracted from the historical data of the multi-channel display signals, and a multi-channel signal synchronization matrix is ​​generated based on the channel synchronization features. Channel offset features are then filtered according to the gradient distribution of the multi-channel signal synchronization matrix, and the channel offset features are converted into display drive timing coordination values.

[0010] The backlight adjustment unit is activated and display signals and backlight brightness data are collected. The backlight interference intensity is determined based on the interaction response between the display signals and backlight brightness data. Timing stability evaluation parameters are constructed by combining the backlight interference intensity with the display driver timing coordination value.

[0011] The timing stability evaluation parameters are used to predict the multi-channel signal distortion and generate a display timing fluctuation deviation. When the display timing fluctuation deviation is greater than a preset fluctuation threshold, the refresh frequency parameters of the display driving circuit are adjusted.

[0012] Preferably, the step of extracting channel synchronization features from the historical data of the multi-channel display signal includes: dividing the signal sampling segments within a fixed time window; calculating the spectral energy distribution of each signal sampling segment; determining the channel signal synchronization strength based on the spectral energy distribution; and extracting the channel synchronization feature vector based on the channel signal synchronization strength.

[0013] Preferably, generating a multi-channel signal synchronization matrix based on the channel synchronization characteristics includes: setting a timing tolerance interval for the display driving circuit; constructing a multi-channel signal synchronization matrix using the channel synchronization characteristics and the timing tolerance interval; and adjusting the dimensional distribution of the multi-channel signal synchronization matrix according to the phase difference between adjacent channels.

[0014] Preferably, determining the backlight interference intensity based on the interaction response between the display signal and the backlight brightness data includes: identifying the correspondence between the rising edge of the display signal and the change in backlight brightness; calculating the time delay between the display signal transition and the backlight response; quantizing the backlight interference intensity matrix according to the time delay; and coupling the backlight interference intensity matrix with channel offset features for analysis.

[0015] Preferably, the step of constructing timing stability evaluation parameters by means of the backlight interference intensity and the display driver timing coordination value includes: establishing a correlation model between backlight fluctuation and channel timing offset; calculating the channel synchronization attenuation coefficient based on the backlight interference intensity and the display driver timing coordination value; and generating a timing stability evaluation value by means of the channel synchronization attenuation coefficient.

[0016] Preferably, the step of predicting multi-channel signal distortion using the timing stability evaluation parameter includes: loading a standard waveform template of the display signal; comparing the timing stability evaluation parameter with a waveform matching threshold; calculating a predicted value of multi-channel signal distortion when the timing stability evaluation parameter is lower than the waveform matching threshold; and mapping the predicted value of multi-channel signal distortion to a display timing fluctuation deviation.

[0017] Preferably, adjusting the refresh frequency parameters of the display driver circuit includes: obtaining the phase compensation parameters of the current display channel; calculating the refresh frequency adjustment amount based on the display timing fluctuation deviation; calibrating the refresh frequency adjustment amount using the phase compensation parameters; and writing the calibrated refresh frequency adjustment amount into the display driver register.

[0018] Preferably, the method further includes: maintaining the current refresh frequency parameter of the display driving circuit when the display timing fluctuation deviation is equal to a preset fluctuation threshold; increasing the refresh frequency parameter of the display driving circuit when the display timing fluctuation deviation is less than the preset fluctuation threshold; the increase in the refresh frequency parameter of the display driving circuit needs to refer to the changing trend of the backlight interference intensity.

[0019] Preferably, the historical data of the multi-channel display signal includes signal amplitude, signal frequency and signal phase data of at least three display channels within a complete refresh cycle, and the storage format of the historical data is a set of waveform segments marked with timestamps.

[0020] Preferably, the process of acquiring historical data for the multi-channel display signal includes:

[0021] Set a synchronous clock trigger mechanism to control the sampling start time of all channels;

[0022] The original waveform data of each channel is time-domain aligned and calibrated by interpolation resampling based on the channel with the highest sampling frequency.

[0023] The resampled channel data is stored as a set of labeled waveform data blocks according to the timestamp. The set of waveform data blocks includes the channel number, timestamp sequence and normalized amplitude value.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] This control method for liquid crystal display display driving circuits based on multi-channel synchronization starts with the synchronization processing of multi-channel signals. By collecting historical data and extracting channel synchronization features, it provides richer reference data for the generation of the synchronization matrix. Historical data contains the transmission patterns of each channel signal under different operating conditions. The synchronization features extracted based on this data can more comprehensively reflect the inherent correlation between channels, making the generated multi-channel signal synchronization matrix more closely match the actual signal transmission state. This feature extraction method based on historical data avoids misjudgment of synchronization features caused by signal fluctuations at a single moment, making the subsequent selection of channel offset features more targeted, thus ensuring that the converted display driving timing coordination values ​​better match the actual driving requirements.

[0026] In handling backlight interference, this method does not evaluate backlight brightness or display signals in isolation, but determines the intensity of backlight interference by collecting the interaction between the two. The operation of the backlight adjustment unit has a multi-dimensional impact on the transmission of display signals. This impact is not a simple linear relationship, but rather manifests as a dynamic interactive response. By capturing this interaction, the degree of influence of backlight interference on display driving timing can be quantified more accurately, providing crucial support for the construction of timing stability evaluation parameters. Simultaneously, combining the backlight interference intensity with the display driving timing coordination value allows the evaluation parameters to comprehensively reflect the superposition effect of synchronization state and external interference, thereby more realistically characterizing the timing stability of the driving circuit.

[0027] For the prediction and handling of multi-channel signal distortion, this method predicts the signal distortion degree through timing stability evaluation parameters, generates display timing fluctuation deviations, and forms a proactive adjustment mechanism. This mechanism can detect abnormal operation of the drive circuit in advance by monitoring fluctuation deviations before signal distortion becomes obvious. When the fluctuation deviation exceeds a preset threshold, the refresh rate parameters are adjusted in time, optimizing the operation of the drive circuit without affecting normal display. This proactive intervention reduces the degradation of image quality caused by the accumulation of signal distortion, enabling the LCD to maintain a relatively stable display effect under different operating conditions.

[0028] This method organically combines multi-channel synchronous processing, backlight interference assessment, and timing adjustment to form a closed-loop control system. Information transmission and feedback between each stage make the entire control process more coherent and adaptable. Whether it's dynamic changes in channel signals or fluctuations in the backlight environment, this method can make corresponding adjustments through the coordinated action of each stage, thereby improving the adaptability of the display driver circuit to complex operating conditions and making the display performance of the LCD more aligned with practical application needs. Attached Figure Description

[0029] Figure 1This is a schematic diagram illustrating the working principle of the liquid crystal display driving circuit control method based on multi-channel synchronization described in this invention.

[0030] Figure 2 A flowchart for extracting channel synchronization features;

[0031] Figure 3 A flowchart for determining the backlight interference intensity;

[0032] Figure 4 This is a flowchart for acquiring historical data of multi-channel display signals. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Please see Figure 1 This invention provides a control method for a liquid crystal display display driving circuit based on multi-channel synchronization, the method comprising:

[0035] Historical data of multi-channel display signals are acquired through the display driver circuit. The display driver circuit integrates a multi-channel signal acquisition module, capable of simultaneously receiving raw signals transmitted from at least three display channels, with the acquisition process covering the complete display refresh cycle. The acquired signal data includes the signal amplitude, frequency, and phase information of each channel, and each data point is accompanied by a corresponding timestamp, ultimately forming a set of waveform segments for storage.

[0036] Channel synchronization features are extracted from historical data of the multi-channel display signals, and a multi-channel signal synchronization matrix is ​​generated based on these features. Channel offset features are then filtered according to the gradient distribution of the multi-channel signal synchronization matrix and converted into display drive timing coordination values. Historical data is segmented, and feature parameters are determined by analyzing the synchronization of each segment. A matrix is ​​then constructed based on these feature parameters, and offset features are filtered out through matrix analysis to complete the conversion to coordination values.

[0037] The backlight adjustment unit is activated and displays the signal and backlight brightness data are collected. The backlight interference intensity is determined based on the interaction response between the display signal and the backlight brightness data. Timing stability evaluation parameters are constructed using the backlight interference intensity and the display driver timing coordination value. After the backlight adjustment unit is activated, dynamic data on changes in the display signal and backlight brightness are collected in real time. The interference intensity is calculated by analyzing the response relationship between the two, and then combined with the timing coordination value to construct parameters for evaluating stability.

[0038] The timing stability evaluation parameters are used to predict the distortion of multi-channel signals, generating a display timing fluctuation deviation. When the display timing fluctuation deviation exceeds a preset fluctuation threshold, the refresh frequency parameters of the display driver circuit are adjusted. By comparing the timing stability evaluation parameters with a preset standard, the degree of signal distortion is predicted, thus obtaining the timing fluctuation deviation. When this deviation exceeds a set threshold, the refresh frequency parameters of the display driver circuit are adjusted to maintain display stability.

[0039] Example 1: See Figure 2 When extracting channel synchronization features from historical data of multi-channel display signals, the first step is to divide the signal sampling segments into fixed time windows. The setting of the time window needs to be combined with the actual operating frequency of the display driver circuit. For example, the length of the time window can be adjusted accordingly at different refresh rates to ensure that each window can completely capture the signal changes within that time period. Each time window is evenly divided into several signal sampling segments, and the number of sampling points contained in each sampling segment is determined according to the signal sampling frequency, so that each sampling segment can reflect local signal characteristics without losing details due to excessive length.

[0040] When calculating the spectral energy distribution of each signal sampling segment, a signal processing algorithm is used to transform the signal in each sampling segment, converting the time-domain signal into a frequency-domain signal, thereby obtaining the energy distribution of that sampling segment at different frequency components. In this way, the energy strength of the signal at each frequency point can be clearly displayed, and the energy proportion of different frequency components can intuitively reflect the frequency characteristics of the signal.

[0041] Determining channel signal synchronization strength based on spectral energy distribution is achieved by comparing the consistency of energy distribution across different channels at the same frequency component. When the energy values ​​of multiple channels at the same frequency component are close and their trends are consistent, it indicates strong synchronization at that frequency; conversely, if the energy values ​​differ significantly and their trends are chaotic, the synchronization is weak. By comprehensively analyzing the synchronization of multiple frequency components, a synchronization strength index between channels is obtained.

[0042] When extracting channel synchronization feature vectors based on channel signal synchronization strength, information such as synchronization strength of different frequency bands, synchronization stability indicators within each time window, and synchronization differences between channels are integrated according to preset dimensions. This information is arranged in an orderly manner to form a vector that can comprehensively reflect the channel synchronization characteristics. This vector contains parameters of multiple dimensions, each parameter corresponding to a specific synchronization feature.

[0043] When generating a multi-channel signal synchronization matrix based on channel synchronization characteristics, the timing tolerance range of the display driving circuit is first set. The size of the timing tolerance range is determined according to the hardware characteristics of the LCD. For example, different models of LCDs have different tolerance ranges for timing deviations due to differences in panel materials and driving methods. The timing tolerance range needs to cover the timing fluctuation range that may occur under normal operating conditions.

[0044] When constructing a multi-channel signal synchronization matrix using channel synchronization characteristics and timing tolerance intervals, the rows and columns of the matrix correspond to different display channels, and each element value in the matrix represents the degree of synchronization between the corresponding two channels within the timing tolerance interval. When calculating the element values, parameters such as synchronization strength and synchronization stability in the channel synchronization characteristics are comprehensively considered, as well as the overlap between the signals of the two channels within the timing tolerance interval. The magnitude of the element value directly reflects the level of synchronization between the two channels.

[0045] When adjusting the dimensionality distribution of a multi-channel signal synchronization matrix based on the phase difference between adjacent channels, the phase difference between adjacent channels is first calculated. When the phase difference is large, exceeding a certain range, it indicates a significant difference in phase between the signals of adjacent channels. In this case, the matrix dimension needs to be increased to more finely divide the synchronization state, thus more accurately reflecting the synchronization relationship between channels. When the phase difference between adjacent channels is small and they are in a close state, the matrix dimension can be appropriately reduced. This reduces data processing volume and improves computational efficiency while ensuring accuracy in reflecting the synchronization state. In this way, the multi-channel signal synchronization matrix can dynamically adapt to changes in channel phase difference, more accurately reflecting the synchronization status of multi-channel signals.

[0046] Example 2: See Figure 3 When determining the backlight interference intensity based on the interaction response between the display signal and backlight brightness data, the first step is to identify the correspondence between the rising edge of the display signal and changes in backlight brightness. The display signal is monitored in real time by a signal processing module, and edge detection technology is used to capture the rising edge of the display signal, i.e., the moment the signal transitions from a low level to a high level. Simultaneously, backlight brightness data is collected in real time by a brightness sensor, recording the brightness value at each moment. The moment of the display signal's rising edge is compared with the backlight brightness data on the same time axis, marking backlight brightness values ​​that change significantly before and after the rising edge of the display signal. This establishes a temporal correspondence between the two, clarifying whether a change in the display signal will trigger a change in backlight brightness and the specific moment of that change.

[0047] When calculating the time delay between display signal transitions and backlight response, the exact moment of each display signal transition, whether it's a rising or falling edge, is recorded. Simultaneously, backlight brightness data is continuously monitored to determine the point at which a significant change in backlight brightness begins. The difference between these two points is the time delay. To reduce the influence of random factors, multiple measurements are taken for the same type of signal transition, obtaining multiple time delay values. These data are then processed using statistical methods to obtain a representative time delay value, reflecting the lag in the backlight system's response to changes in the display signal.

[0048] When quantifying the backlight interference intensity matrix based on the time delay, the time delay is converted into a corresponding interference intensity value. Generally, a larger time delay indicates a more delayed response of the backlight system to changes in the display signal, resulting in stronger interference and a higher interference intensity value; conversely, a smaller time delay results in a lower interference intensity value. Subsequently, the interference intensity values ​​corresponding to each display channel are arranged in a matrix format. The rows and columns of the matrix correspond to different display channels and different signal transition types, respectively. Each element in the matrix represents the backlight interference intensity of that channel under the corresponding signal transition, forming the backlight interference intensity matrix.

[0049] When coupling the backlight interference intensity matrix with channel offset features, key parameters such as offset and offset frequency in the channel offset features are extracted and correlated with the element values ​​in the backlight interference intensity matrix. By analyzing the numerical relationship between the two, it is determined which channels have a strong correlation with the backlight interference intensity and which channels are less affected by backlight interference, thus clarifying the specific effect of backlight interference on the offset of different channels.

[0050] When constructing timing stability evaluation parameters based on backlight interference intensity and display driver timing coordination values, a correlation model between backlight fluctuations and channel timing offsets is first established. This model collects a large amount of backlight fluctuation data and corresponding channel timing offset data, analyzing the inherent relationship between the two in terms of their changing trends and amplitudes, forming a model structure that describes how backlight fluctuations affect channel timing offsets. The model includes the correspondence between parameters such as backlight fluctuation amplitude, fluctuation frequency, and channel timing offset amount and offset speed, and can predict possible channel timing offsets based on the input backlight fluctuation parameters.

[0051] When calculating the channel synchronization attenuation coefficient based on backlight interference intensity and display driver timing coordination value, the backlight interference intensity value and the display driver timing coordination value are substituted into a preset calculation process. The display driver timing coordination value reflects the degree of timing coordination between channels; a higher value indicates a better coordination effect. During the calculation, the destructive effect of backlight interference intensity on timing coordination and the magnitude of the display driver timing coordination value itself are comprehensively considered to obtain the synchronization attenuation coefficient for each channel. This coefficient reflects the degree of attenuation of channel synchronization performance under the influence of backlight interference.

[0052] When generating timing stability assessment values ​​using channel synchronization attenuation coefficients, the synchronization attenuation coefficients of each channel are integrated. Based on the weight of each channel's role in the display system, the corresponding synchronization attenuation coefficients are weighted. The weight allocation is determined by the importance of the channel; the more important the channel, the greater the weight its synchronization attenuation coefficient carries in the integration process.

[0053] Example 3: When predicting multi-channel signal distortion using timing stability evaluation parameters, a standard waveform template for the display signal is first loaded. This standard waveform template is stored in the storage unit of the display driver circuit and covers ideal signal waveforms at different resolutions and refresh rates, including information such as signal amplitude variation curves, phase variation patterns, and frequency characteristics. These templates are obtained through prior signal acquisition and analysis of similar LCD displays under ideal operating conditions and can reflect the waveform characteristics that a signal should have during normal display. During loading, based on the current display's operating mode, such as resolution settings and color depth, the corresponding standard waveform template is retrieved from the storage unit as a benchmark for subsequent signal comparisons.

[0054] When comparing timing stability evaluation parameters with waveform matching thresholds, the waveform matching threshold is determined based on the characteristics of the standard waveform template; different standard waveform templates correspond to different thresholds. The threshold setting comprehensively considers factors such as the hardware performance of the LCD display and normal signal transmission losses, representing the maximum acceptable deviation range of the signal without affecting the display effect. Comparing the timing stability evaluation parameters with this threshold, if the evaluation parameter is higher than the threshold, it indicates a high degree of matching between the current signal and the standard waveform; if the evaluation parameter is lower than the threshold, it indicates that the signal may have significant distortion.

[0055] When the timing stability assessment parameter is lower than the waveform matching threshold, the predicted value of multi-channel signal distortion is calculated. By analyzing the difference between the assessment parameter and the threshold, and combining the allowable fluctuation range of parameters such as signal amplitude and phase in the standard waveform template, the calculation method of distortion is determined. The calculation of the distortion prediction value needs to cover multiple dimensions, including the deviation ratio of signal amplitude, the phase offset, and the frequency fluctuation range. The deviations of these dimensions are comprehensively quantified to obtain a value that can reflect the overall degree of signal distortion, namely the predicted value of multi-channel signal distortion.

[0056] When mapping multi-channel signal distortion prediction values ​​to display timing fluctuation deviations, a correspondence table is established between the distortion prediction values ​​and timing fluctuation deviations. This correspondence is obtained through analysis of a large amount of historical data, clarifying the timing fluctuation deviation ranges corresponding to different ranges of distortion prediction values. During the mapping process, based on the calculated multi-channel signal distortion prediction values, the corresponding timing fluctuation deviation value is looked up in the correspondence table. This value, expressed in units of time, intuitively reflects the degree of deviation between the actual display timing and the ideal timing.

[0057] When adjusting the refresh rate parameters of the display driver circuit, the phase compensation parameters of the current display channel are obtained. These phase compensation parameters are stored in a dedicated register of the display driver circuit and are used to compensate for phase deviations caused by factors such as hardware differences and varying transmission path lengths between different display channels. By reading the data from the register, the current phase compensation value for each display channel is obtained. These values ​​include forward compensation and reverse compensation, corresponding to phase lead and phase lag compensation, respectively.

[0058] When calculating the refresh rate adjustment based on the display timing fluctuation deviation, the relationship between the refresh rate adjustment and the display timing fluctuation deviation is determined by considering the operating characteristics of the display driver circuit. A positive display timing fluctuation deviation indicates that the actual timing lags behind the ideal timing, requiring an increase in the refresh rate to shorten the signal transmission cycle; a negative deviation indicates that the actual timing leads the ideal timing, requiring a decrease in the refresh rate to extend the signal transmission cycle. The specific calculation process uses the following formula:

[0059]

[0060] Where Δf represents the refresh rate adjustment amount, k represents the adjustment coefficient, the value of which is determined according to the model and working mode of the LCD monitor, and is usually between 0.5 and 1.5; Δt represents the display timing fluctuation deviation; T0 represents the current refresh cycle, which is the reciprocal of the current refresh rate; and f0 represents the current refresh rate.

[0061] When calibrating the refresh frequency adjustment using phase compensation parameters, the obtained phase compensation parameters are substituted into the calibration process. For each display channel, the initially calculated refresh frequency adjustment is corrected based on the magnitude and direction of its phase compensation value. If the phase compensation value of a certain channel is large, it indicates that the phase deviation of that channel is significant, and the adjustment amount needs to be appropriately increased to offset the effect of the phase deviation when adjusting the refresh frequency; if the phase compensation value is small, the adjustment amount can be appropriately reduced to avoid over-adjustment leading to new timing deviations.

[0062] When writing the calibrated refresh rate adjustment to the display driver register, a write command is sent through the control interface of the display driver circuit. The control interface interacts with the register according to a preset communication protocol, first verifying the validity of the write command to ensure its reliable source and correct format. After successful verification, the calibrated refresh rate adjustment is converted into a binary data format recognizable by the register and written to the corresponding register address. After writing, the data in the register is read for verification to confirm that the written data matches the calibrated refresh rate adjustment, ensuring the accuracy of the refresh rate parameter adjustment. The adjusted refresh rate parameter takes effect immediately, and the display driver circuit drives the signal according to the new frequency, thereby improving display timing fluctuations.

[0063] Example 4: See Figure 4 When the timing fluctuation deviation equals the preset fluctuation threshold, the display driver circuit maintains the current refresh rate parameters. At this point, the display system is in a critical stable state, and the synchronization and timing coordination of the signals in each channel are just within an acceptable range. The control module of the display driver circuit continuously monitors the signal transmission status of each channel, including the rising and falling edge times of the signal, as well as the amplitude changes of the signal during transmission. The current refresh rate parameters, including frequency value and period duration, are recorded in the storage unit. The control module does not modify these parameters again, ensuring that the signal refreshes and displays according to the original rhythm. Each display channel sends signals according to the predetermined timing, and the backlight adjustment unit also maintains the current brightness output mode, avoiding any instantaneous fluctuations that may be caused by parameter adjustments.

[0064] When the timing fluctuation deviation is less than the preset fluctuation threshold, the display driver circuit begins to increase the refresh rate parameter. At this time, the signal synchronization and stability are good, and increasing the refresh rate can speed up the image update and make dynamic display content smoother. During the process of increasing the refresh rate, the control module will gradually adjust the parameters, and the adjustment range is determined according to the current system load to avoid sudden changes in the circuit's operating state caused by a large adjustment at once. For example, if the current refresh rate is 60Hz, it can be adjusted to 70Hz first. After running stably for a period of time, if the fluctuation deviation is still at a low level, it can then be adjusted to 80Hz.

[0065] Increasing the refresh rate parameter of the display driver circuit requires consideration of the changing trend of backlight interference intensity. By analyzing historical data on backlight interference intensity, it can be determined whether it is rising, falling, or remaining stable. If the backlight interference intensity continues to rise, even if the display timing fluctuation is small, the increment of each refresh rate increase will be reduced, for example, from 10Hz increments to 5Hz increments, to reduce mutual interference between high-frequency signals and the backlight system. If the backlight interference intensity gradually decreases, the normal adjustment range can be maintained, or even the adjustment range can be appropriately increased when the system load is low, to improve display performance more quickly.

[0066] Historical data for multi-channel display signals includes signal amplitude, frequency, and phase data for at least three display channels within a complete refresh cycle. This data covers a complete cycle in the display process, comprehensively reflecting the signal characteristics of each channel under normal operating conditions. Signal amplitude data records the voltage variation range of the signal within the cycle, from the minimum to the maximum value; signal frequency data reflects the number of cycle changes of the signal per unit time, which is related to the refresh frequency of the display driver circuit; signal phase data reflects the time difference between signals from different channels, such as the difference between the peak signal occurrence time of channel A and the peak signal occurrence time of channel B.

[0067] Historical data is stored as a collection of timestamped waveform segments. Each waveform segment corresponds to a continuous signal change process, with timestamps accurate to the microsecond level, accurately marking the acquisition time of each signal data point. For example, within a complete refresh cycle, signal data is acquired every 10 microseconds. These data are arranged in chronological order to form a waveform segment, which contains the signal amplitude, frequency, and phase information for that time period.

[0068] The following is a sample table for storing historical data of multi-channel display signals:

[0069] Channel number Timestamp (μs) Signal amplitude (V) Signal frequency (Hz) Signal phase (°) 1 0 0.3 60 0 1 10 0.5 60 10 1 20 0.8 60 20 2 0 0.4 60 5 2 10 0.6 60 15 2 20 0.9 60 25 3 0 0.35 60 3 3 10 0.55 60 13 3 20 0.85 60 23

[0070] In the table, the signal data for each channel is recorded sequentially by timestamp. By comparing the signal phase of different channels at the same timestamp, the synchronization between channels can be analyzed. Observing the change in signal amplitude over time allows us to understand the fluctuation characteristics of the signal within its period. This data is stored in binary format in the circuit's storage module, facilitating rapid subsequent reading and analysis, and providing raw data for steps such as extracting channel synchronization characteristics and generating a synchronization matrix.

[0071] Example 5: The historical data acquisition process for multi-channel display signals includes setting a synchronous clock trigger mechanism to control the sampling start time of all channels. A high-precision clock generator is integrated within the display driver circuit. The synchronous clock signal generated by this generator is simultaneously transmitted to the sampling units of each display channel. The synchronous clock trigger mechanism includes a trigger signal generation module and a signal distribution network. The trigger signal generation module generates a start trigger pulse at a preset time interval, with the pulse width and amplitude meeting the input requirements of each sampling unit. The signal distribution network adopts a star topology to ensure that the synchronous trigger signal reaches the sampling unit of each display channel simultaneously, avoiding trigger delays caused by different transmission path lengths. After receiving the trigger pulse, the sampling unit immediately starts the signal acquisition process, ensuring that all channels begin sampling the display signal at the same time, eliminating systematic deviations caused by different sampling start times among the channels.

[0072] The raw waveform data for each channel undergoes time-domain alignment calibration using interpolation resampling with the highest sampling frequency channel as the reference. First, the highest sampling frequency channel among all display channels is identified, as it has the shortest sampling interval, acquires the most signal data points per unit time, and has the highest temporal resolution of the raw waveform data. The time axis of this channel is used as the reference time axis, and the timestamp of each sampling point is recorded. For other channels with lower sampling frequencies, their raw waveform data is processed using an interpolation algorithm, inserting new data points between adjacent raw sampling points to ensure that the number of sampling points for these channels matches that of the highest sampling frequency channel. During interpolation, the signal value at the insertion point is calculated based on the signal amplitude and phase change trends of the raw sampling points to ensure that the resampled waveform accurately reflects the changing characteristics of the original signal.

[0073] The resampled channel data is stored as a set of labeled waveform data blocks, each containing a channel number, a timestamp sequence, and a normalized amplitude value. The channel number assigns a unique identifier to each display channel to distinguish different channel data; the identifier can be numbers, letters, or a combination of both, such as "CH01" or "CH02". The timestamp sequence consists of a series of consecutive time points, each accurate to the nanosecond level, corresponding to the resampled reference timeline and recording the acquisition time of each signal data point. The normalized amplitude value converts the amplitude of the original signal to a value within the 0-1 range. During the conversion, the maximum amplitude value of the original waveform data for that channel is used as a reference; the amplitude value of each sample point is divided by the maximum amplitude value to obtain the corresponding normalized result. This processing method eliminates amplitude differences between different channels caused by hardware gain variations, facilitating direct comparison of signal amplitudes between different channels. The waveform data block set is stored in segments, with each data block corresponding to a fixed time segment, such as 1 second of signal data. The size of the data blocks is optimized based on the read / write performance of the storage medium to improve data storage and retrieval efficiency. The storage medium is a high-speed non-volatile memory, which ensures that data will not be lost in the event of power failure. It also supports fast data writing and reading operations to meet the data access speed requirements of the real-time display driver circuit.

[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0075] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A control method for a liquid crystal display display driving circuit based on multi-channel synchronization, characterized in that, include: Historical data of multi-channel display signals are acquired through the display driver circuit; Channel synchronization features are extracted from the historical data of the multi-channel display signals, and a multi-channel signal synchronization matrix is ​​generated based on the channel synchronization features. Channel offset features are then filtered according to the gradient distribution of the multi-channel signal synchronization matrix, and the channel offset features are converted into display drive timing coordination values. The backlight adjustment unit is activated and the display signal and backlight brightness data are collected. The backlight interference intensity is determined based on the interaction response between the display signal and the backlight brightness data. Timing stability evaluation parameters are constructed by combining the backlight interference intensity with the display driver timing coordination value. The timing stability evaluation parameters are used to predict the distortion of multi-channel signals and generate and display timing fluctuation deviations. When the display timing fluctuation deviation is greater than the preset fluctuation threshold, the refresh frequency parameter of the display driving circuit is adjusted. When the display timing fluctuation deviation is equal to the preset fluctuation threshold, the current refresh frequency parameter of the display driving circuit is maintained; When the display timing fluctuation deviation is less than a preset fluctuation threshold, the refresh frequency parameter of the display driving circuit is increased; the increase of the refresh frequency parameter of the display driving circuit needs to refer to the changing trend of the backlight interference intensity.

2. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The step of extracting channel synchronization features from the historical data of the multi-channel display signal includes: dividing the signal sampling segments within a fixed time window; calculating the spectral energy distribution of each signal sampling segment; determining the channel signal synchronization strength based on the spectral energy distribution; and extracting the channel synchronization feature vector based on the channel signal synchronization strength.

3. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The step of generating a multi-channel signal synchronization matrix based on the channel synchronization characteristics includes: setting a timing tolerance range for the display driving circuit; constructing a multi-channel signal synchronization matrix using the channel synchronization characteristics and the timing tolerance range; and adjusting the dimensional distribution of the multi-channel signal synchronization matrix according to the phase difference between adjacent channels.

4. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The determination of backlight interference intensity based on the interaction response between the display signal and the backlight brightness data includes: identifying the correspondence between the rising edge of the display signal and the change in backlight brightness; calculating the time delay between the display signal transition and the backlight response; quantizing the backlight interference intensity matrix according to the time delay; and coupling the backlight interference intensity matrix with channel offset features for analysis.

5. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The step of constructing timing stability evaluation parameters by means of the backlight interference intensity and the display driver timing coordination value includes: establishing a correlation model between backlight fluctuation and channel timing offset; calculating the channel synchronization attenuation coefficient based on the backlight interference intensity and the display driver timing coordination value; and generating timing stability evaluation value through the channel synchronization attenuation coefficient.

6. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The method of predicting multi-channel signal distortion using the timing stability evaluation parameters includes: loading a standard waveform template of the display signal; comparing the timing stability evaluation parameters with a waveform matching threshold; calculating the predicted value of multi-channel signal distortion when the timing stability evaluation parameters are lower than the waveform matching threshold; and mapping the predicted value of multi-channel signal distortion to the display timing fluctuation deviation.

7. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The adjustment of the refresh frequency parameters of the display driver circuit includes: obtaining the phase compensation parameters of the current display channel; calculating the refresh frequency adjustment amount based on the display timing fluctuation deviation; calibrating the refresh frequency adjustment amount using the phase compensation parameters; and writing the calibrated refresh frequency adjustment amount into the display driver register.

8. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The historical data of the multi-channel display signal includes signal amplitude, signal frequency and signal phase data of at least three display channels within a complete refresh cycle. The storage format of the historical data is a set of waveform segments marked with timestamps.

9. The liquid crystal display display driving circuit control method based on multi-channel synchronization as described in claim 1, characterized in that, The process of acquiring historical data for the multi-channel display signal includes: Set a synchronous clock trigger mechanism to control the sampling start time of all channels; The original waveform data of each channel is time-domain aligned and calibrated by interpolation resampling based on the channel with the highest sampling frequency. The resampled channel data is stored as a set of labeled waveform data blocks according to the timestamp. The set of waveform data blocks includes the channel number, timestamp sequence and normalized amplitude value.

Images