Method for measuring offset of epitaxial pattern

Abstract

The invention discloses a method for measuring the offset of an epitaxial pattern. The method comprises the following steps: forming a first groove filled with a first material on a substrate as a first alignment mark of a deep layer; forming a second alignment mark on the surface of the substrate by taking the first alignment mark as a reference, and measuring an initial first deviation value between the first alignment mark and the second alignment mark; performing epitaxial growth on the substrate to form an epitaxial layer; thinning the back surface of the substrate to expose the first alignment mark; simultaneously aligning the second alignment mark covered by the epitaxial layer on the front surface of the substrate and the first alignment mark exposed out of the back surface of the substrate by adopting double-sided alignment photoetching equipment to respectively obtain a second deviation value and a third deviation value relative to the equipment reference; based on the measured first, second and third deviation values, the exact pattern offset caused by epitaxial growth is calculated. According to the method, the wafer does not need to be damaged, the measurement precision is high, the speed is high, and the process monitoring level and the product yield are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for measuring the shift of epitaxial patterns. BACKGROUND

[0002] In semiconductor integrated circuit manufacturing process, epitaxial process plays a key role. This process refers to the growth of one or more layers of single crystal material film on the surface of a carefully treated single crystal substrate (such as a silicon wafer), which has the same or a specific lattice arrangement relationship with the substrate, i.e. epitaxial layer. These epitaxial layers, due to their high purity, low defect density, and precisely controllable doping concentration and thickness, etc. excellent characteristics, become the basis for manufacturing high-performance integrated circuit devices.

[0003] However, the epitaxial growth process itself, especially when growing thicker epitaxial layers, can cause a thorny problem - pattern shift. Specifically, the pattern structure pre-made on the surface of the substrate before epitaxial growth, such as patterned alignment marks or active area boundaries of devices, etc., after epitaxial growth, their actual position on the wafer surface may drift horizontally or geometrically distorted compared to the original design position. In severe cases, these patterns may even become blurred or completely disappear.

[0004] The physical mechanism causing epitaxial pattern shift is multifaceted. One of the main factors is the lattice mismatch between the epitaxial layer and the substrate; if there is a difference in the lattice constants of the two, a strain will be generated at the interface, and when the thickness of the epitaxial layer accumulates beyond a certain critical value, the stored strain energy may be released through the formation of dislocations, lattice tilting, etc., thus causing the overlying pattern to shift relatively. The difference in thermal expansion coefficient is also an important reason; epitaxial growth is usually carried out at high temperature (such as more than 1000 degrees Celsius), and if the epitaxial layer and the substrate material shrink differently during cooling to room temperature, the resulting thermal stress may cause the wafer to warp or local structure to deform, thus causing pattern shift. In addition, the anisotropy of epitaxial growth means that the growth rate of the crystal may be different in different directions, which will cause non-uniformity in the epitaxial layer when covering the edges of patterns in different directions, causing direction-dependent pattern shift or distortion. At the same time, the non-uniformity of atomic diffusion and nucleation on the surface cannot be ignored; the steps, defects or contaminants on the edges of the pattern will affect the migration and attachment of local atoms, causing uneven growth rate, and causing the epitaxial layer to shift when covering the pattern. Finally, when the accumulated stress (whether it is lattice mismatch stress or thermal stress) reaches a certain threshold, it may be relieved through stress release mechanisms such as dislocation slip, micro-crack generation, etc., which are often accompanied by macroscopic pattern displacement.

[0005] For multi-layer photolithography processes that rely on precise alignment, the above-mentioned pattern shift problem is extremely detrimental. For example, if the mark pattern used for photolithography alignment is significantly shifted or distorted, it will directly lead to a severe decrease in overlay accuracy between the subsequent photolithography layer and the previous layer. Such alignment errors can cause device structure defects, which in turn can lead to substandard electrical performance or even complete failure, ultimately lowering product yield. This problem is particularly prominent in thick epitaxial (e.g., thickness greater than 10 microns) applications, because generally the thicker the epitaxial layer, the greater the cumulative shift can be.

[0006] Currently, the conventional method in the industry for checking and measuring epitaxial wafer pattern shift is to make a slice of the epitaxial wafer and perform cross-sectional observation. The general operation process includes: cutting the epitaxial wafer containing the pattern to be measured into small samples, carefully preparing and protecting the cross section, then making different doped regions or material interfaces more clearly visible through chemical staining (such as junction staining) techniques, and finally observing the cross-sectional morphology using high-magnification microscopes such as scanning electron microscopes (SEM) or transmission electron microscopes (TEM), thereby measuring the relative position change of the pattern before and after epitaxial growth.

[0007] However, this traditional method based on slice observation has several obvious limitations. First, it is destructive, requiring the cutting and destruction of a complete wafer, so it cannot be used for in-situ, non-destructive measurement of product wafers on the production line, and is generally only suitable for analysis during the process development stage or small-batch sampling detection. Second, this method is quite time-consuming; preparing a high-quality cross-sectional sample itself is a complex process involving multiple steps such as cutting, grinding, polishing, cleaning, and staining, and subsequent microscope observation and data analysis also require a large amount of time. Its precision is also relatively limited; the slice preparation process itself can introduce additional damage or deformation, and the effectiveness of the staining can affect the clarity of the interface boundary, plus the inherent errors of microscope observation and measurement, limiting the measurement accuracy. Moreover, this method can only obtain shift information at a limited number of points on the sample, making it difficult to fully reflect the shift distribution throughout the wafer area.

[0008] Therefore, the epitaxial pattern shift measurement means in the prior art has deficiencies in terms of destructiveness, efficiency, and precision, and cannot fully meet the urgent needs of modern semiconductor manufacturing for high efficiency, high precision, and non-destructive process monitoring. The industry urgently needs an innovative method that can quickly, accurately, and non-destructively measure the shift of epitaxial patterns, so as to more effectively monitor, control, and compensate for the pattern displacement introduced by the epitaxial process, thereby improving the overall manufacturing precision and yield of integrated circuits. SUMMARY

[0009] The present application aims to solve the problems in the prior art. The commonly used method, such as making an epitaxial wafer slice and observing the cross section by an electron microscope, is a destructive detection method, which needs to break the silicon wafer and cannot be used for online monitoring or non-destructive evaluation of finished wafers. At the same time, the method is complex, involving slice preparation, sample processing, microscope observation and other links, which is time-consuming and low in efficiency. In addition, the slice preparation process may introduce additional errors, and the precision of microscope observation is limited, which is difficult to meet the demand of modern semiconductor manufacturing for high-precision measurement, especially in the application scenarios of thick epitaxial growth (such as more than 10 microns) and other pattern offset problems, the limitations of the existing method are more prominent.

[0010] Therefore, the technical problem to be solved by the present application is to provide a non-destructive, high-efficiency and high-precision method for measuring the epitaxial pattern offset, so as to overcome the shortcomings of the prior art.

[0011] To achieve the above object and other related objects, the present application provides a method for measuring epitaxial pattern offset, comprising:

[0012] Step one, forming a first trench on a substrate, and filling a first material in the first trench to form a first alignment mark;

[0013] Step two, taking the first alignment mark as a reference, forming a second alignment mark on the substrate, and measuring a first deviation between the first alignment mark and the second alignment mark;

[0014] Step three, epitaxial growth on the substrate to form an epitaxial layer;

[0015] Step four, thinning the back surface of the substrate to expose the back surface of the first alignment mark;

[0016] Step five, using a double-sided alignment lithography device to align the front and back surfaces of the substrate at the same time to obtain a front second deviation of the second alignment mark covered by the epitaxial layer and a back third deviation of the first alignment mark;

[0017] Step six, calculating the pattern offset of the epitaxial layer based on the first deviation, the second deviation and the third deviation.

[0018] Preferably, in step one, the forming of the first trench comprises: coating photoresist on the substrate; forming a pattern corresponding to the first trench on the photoresist by exposure and development; forming the first trench by deep silicon etching of the substrate with the photoresist pattern as a mask; and removing the photoresist.

[0019] Preferably, in step one, the deep silicon etching is performed in a photoresist hard mask mode.

[0020] Preferably, in step one, the deep silicon etching has a depth greater than 80 microns.

[0021] Preferably, in step one, the first material is polysilicon.

[0022] Preferably, in step two, the method of forming the second alignment mark comprises: using the first alignment mark as a reference, forming the second alignment mark on the silicon material of the substrate by photolithography and etching.

[0023] Preferably, in step two, the measuring the first deviation amount comprises: forming a corresponding first overlay mark and a second overlay mark respectively while forming the first alignment mark and the second alignment mark; measuring an overlay deviation between the first overlay mark and the second overlay mark using an overlay measurement device to obtain the first deviation amount, denoted as (ΔX_AB, ΔY_AB).

[0024] Preferably, in step three, the epitaxial growth is single crystal silicon epitaxial growth.

[0025] Preferably, in step three, the thickness of the epitaxial layer is less than 6 microns or greater than 10 microns.

[0026] Preferably, in step five, the alignment accuracy of the double-side alignment photolithography device is better than 200 nanometers.

[0027] Preferably, in step six, the front second deviation amount is denoted as (ΔX_front-B, ΔY_front-B), the back third deviation amount is denoted as (ΔX_back-A, ΔY_back-A), and the calculation formula of the pattern offset amount (ΔX, ΔY) of the epitaxial layer is: ΔX = ΔX_front-B - ΔX_back-A - ΔX_AB; ΔY = ΔY_front-B - ΔY_back-A - ΔY_AB.

[0028] As described above, the method of measuring epitaxial pattern offset amount of the present application has the following beneficial effects:

[0029] The method of the present application realizes nondestructive detection, and the whole measurement process does not need destructive treatment on the silicon wafer, so that the silicon wafer after measurement can continue to be used for subsequent process flow or other tests, thereby effectively saving the sample cost. Meanwhile, the measurement precision is high, mainly depending on the performance of high-precision overlay measurement equipment and double-side alignment photolithography equipment, and can reach nanometer level, which is much higher than the precision of traditional methods, and by deducting the initial inherent deviation, the system error is further eliminated, thereby ensuring the accuracy of the measurement result. In addition, since the automatic equipment is used for measurement and calculation, the processes of slice preparation, dyeing and microscopic observation are omitted, so that the measurement efficiency is high, the time consumption is short, and the process feedback cycle can be greatly shortened. The method is also easy to realize full-wafer multi-point offset data acquisition, can generate an intuitive offset distribution map of the whole wafer, and effectively reflects the uniformity characteristics of the epitaxial process, which is information that cannot be comprehensively obtained by traditional cross-section observation. Especially in the process of handling the more serious pattern offset problem such as thick epitaxy, the method shows strong applicability, provides fast and accurate data support for optimizing epitaxial process parameters, evaluating stress control effect and performing reliable online process monitoring, and has important practical significance for improving the overall process stability, improving device performance and improving the yield of final products. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A schematic diagram of a method for measuring epitaxial pattern offset according to the present application is shown.

[0031] Figure 2 A schematic diagram of accurately defining the initial position and shape of the first alignment mark by using photolithography technology according to the present application is shown.

[0032] Figure 3 A schematic diagram of forming a first groove and removing photoresist according to the present application is shown.

[0033] Figure 4 A schematic diagram of forming a polysilicon photolithography alignment mark A according to the present application is shown.

[0034] Figure 5 A schematic diagram of forming a pattern corresponding to a second groove according to the present application is shown.

[0035] Figure 6 A schematic diagram of forming a second groove and removing photoresist according to the present application is shown.

[0036] Figure 7 A schematic diagram of forming an epitaxial layer according to the present application is shown.

[0037] Figure 8 A schematic diagram of thinning the back surface of the substrate to expose the back surface of the first alignment mark according to the present application is shown.

[0038] Figure 9Figure 1 shows a schematic diagram of a dual-side alignment lithography apparatus of the present application, which simultaneously aligns the front and back sides of a substrate. DETAILED DESCRIPTION

[0039] Other advantages and novel features of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. The present application may, however, be embodied in various different forms and should not be considered limited to the embodiments set forth in the description below. Rather, the various embodiments of the present application are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0040] An embodiment of the present application provides a method for measuring the offset of an epitaxial pattern, the method comprising the following steps:

[0041] Step 1: Form a first trench on the substrate and fill the first trench with a first material to form a first alignment mark. This step is used to create a deep reference mark inside the substrate that can be exposed by subsequent backside thinning.

[0042] In some embodiments, in step 1, forming the first trench comprises: coating a photoresist on the substrate, the photoresist layer is used for subsequent patterning; forming a pattern corresponding to the first trench on the photoresist by exposure and development; using photolithography technology to accurately define the initial position and shape of the first alignment mark, forming a structure as shown in Figure 2 ; using the photoresist pattern as a mask, performing deep silicon etching on the substrate to form the first trench; and removing the photoresist to form a structure as shown in Figure 3 .

[0043] In some embodiments, in step 1, the deep silicon etching is performed using a photoresist hard mask mode. Using a hard mask mode helps to achieve the desired deep trench etching, as hard masks generally have higher selectivity and etching resistance, and can withstand long deep silicon etching processes.

[0044] In some embodiments, in step 1, the depth of the deep silicon etching is greater than 80 microns. The etching is deep enough to ensure that the bottom of the first alignment mark can be reliably exposed after the subsequent step of backside thinning of the substrate, so as to facilitate alignment measurement from the back side.

[0045] In some embodiments, in step 1, the first material is polysilicon. Polysilicon is chosen as the filling material because it is easy to fill the deep trench by standard processes such as chemical vapor deposition, and its material properties are different from the single crystal silicon substrate and the subsequently grown epitaxial layer, which facilitates subsequent differentiation and detection. In addition, polysilicon filling can form a relatively stable mark structure. In this way, a polysilicon lithography alignment mark A is formed, and a structure as shown in Figure 4 is formed.

[0046] Step two, forming a second alignment mark on the substrate with the first alignment mark as a reference, and measuring a first deviation between the first alignment mark and the second alignment mark. This step establishes the initial relative position relationship between the second alignment mark (to be covered by the epitaxial layer in the future) and the deep first alignment mark before epitaxial growth.

[0047] In some embodiments, in step two, forming the second alignment mark includes: forming the second alignment mark (alignment mark B) on the silicon material of the substrate by lithography and etching with the first alignment mark (i.e. the alignment mark A formed by poly filling) as a reference. The alignment mark B is etched on the single crystal silicon region of the substrate, which is characterized by that the subsequent epitaxial growth is controllable and can better reflect the influence of epitaxial growth on the silicon-based pattern. While the first alignment mark A is poly filled, the epitaxial growth morphology thereon is uncontrollable. Specifically, forming the second trench includes: coating a photoresist on the substrate, which is used for subsequent patterning; forming a pattern corresponding to the second trench on the photoresist by exposure and development, forming a structure as shown in Figure 5 ; etching the substrate by deep silicon etching with the photoresist pattern as a mask, forming a structure as shown in Figure 6 ; and removing the photoresist, forming a structure as shown in

[0048] In some embodiments, in step two, measuring the first deviation includes: forming a first set of alignment marks (alignment mark A) and a second set of alignment marks (alignment mark B) respectively by using the same lithography step or the immediately adjacent lithography step while forming the first alignment mark A and the second alignment mark B, and the two sets of alignment marks have a preset overlay relationship; and measuring the overlay deviation between the first set of alignment marks and the second set of alignment marks by using an overlay measurement device, such as an optical overlay measurement machine, to obtain the first deviation, denoted as (ΔX_AB, ΔY_AB). By measuring the deviation between the specially designed overlay marks, the actual relative position deviation of the alignment marks A and B after completion of the fabrication can be accurately obtained. This deviation includes the inherent error that may be introduced by the lithography, etching and other process steps, which is measured and recorded, and is crucial for subsequent accurate calculation of epitaxial pattern deviation, avoiding misjudgment of the deviation introduced by the process itself as epitaxial-induced deviation.

[0049] Step three, performing epitaxial growth on the substrate to form an epitaxial layer, forming a structure as shown in Figure 7 . This is a key step to generate pattern deviation.

[0050] In some embodiments, in step three, the epitaxial growth is single crystal silicon epitaxial growth. The epitaxial growth is usually performed at high temperature, with the purpose of growing a high-quality single crystal silicon layer on the substrate.

[0051] In some embodiments, in step 3, the thickness of the epitaxial layer is not limited and can be relatively thin, for example, less than 6 microns, or relatively thick, for example, greater than 10 microns. This method is particularly suitable for thick epitaxial processes because thick epitaxial processes are more likely to cause significant pattern shift, making accurate measurement even more important. During the epitaxial growth process, due to factors such as lattice mismatch, thermal stress, and growth anisotropy, the epitaxial layer overlying the second alignment mark B may experience relative displacement, i.e., pattern shift.

[0052] As mentioned above, at the first alignment mark A (Poly filling area), the epitaxial growth morphology is uncontrollable due to its non-single-crystal silicon nature; while at the second alignment mark B (silicon-based area), the epitaxial growth is relatively controllable.

[0053] Step 4: Thin the back side of the substrate to expose the back side of the first alignment mark, forming Figure 8 The structure shown in Figure 1 is thinned by chemical mechanical polishing (CMP) or back grinding until the polysilicon filling the first trench is exposed from the backside of the substrate. This step allows the first alignment mark A, originally buried deep within the substrate, to be detected from the backside, serving as a stable reference that is not directly affected by the epitaxial growth on the front side.

[0054] Step 5: Use double-sided alignment lithography equipment to align the front and back of the substrate simultaneously (such as Figure 9 As shown), the second deviation of the front side of the second alignment mark covered by the epitaxial layer and the third deviation of the back side of the first alignment mark are obtained. The double-sided alignment lithography equipment has the ability to align the front and back patterns of the wafer simultaneously or in the same coordinate system. The optical system of the equipment detects the second alignment mark B on the front side that has been covered by the epitaxial layer and the first alignment mark A on the back side that has been exposed, respectively. The lithography machine can perform alignment operations according to the alignment marks and output the coordinate information or offset of the marks relative to the reference coordinate system of the equipment after the alignment is completed. Specifically, the alignment offset (ΔX_front-B, ΔY_front-B) of the second alignment mark B after the front side is aligned with the epitaxial coverage, and the alignment offset (ΔX_back-A, ΔY_back-A) of the first alignment mark A exposed after the back side is aligned are obtained. This step utilizes the high-precision alignment capability of the double-sided alignment lithography machine to associate the position of the front mark B that has shifted after the epitaxial growth with the position of the unaffected back mark A under the same measurement reference.

[0055] In some embodiments, in step 5, the alignment accuracy of the double-sided alignment lithography equipment is better than 200 nanometers. Using high-precision double-sided alignment equipment is key to ensuring the accuracy of the final calculated pattern offset. The alignment accuracy of the equipment must be high enough to distinguish tiny pattern offsets.

[0056] Step six, calculate the pattern shift of the epitaxial layer based on the first deviation, the second deviation and the third deviation. The data of the three deviations are integrated to get the actual pattern shift caused by the epitaxial growth.

[0057] In some embodiments, in step six, the front second deviation is denoted as (ΔX_front-B, ΔY_front-B), the back third deviation is denoted as (ΔX_back-A, ΔY_back-A), and the formula for calculating the pattern shift (ΔX, ΔY) of the epitaxial layer is: ΔX = ΔX_front-B - ΔX_back-A - ΔX_AB; ΔY = ΔY_front-B - ΔY_back-A - ΔY_AB. Wherein, (ΔX_front-B, ΔY_front-B) represents the measurement position of the front mark B after epitaxy (relative to the equipment reference); (ΔX_back-A, ΔY_back-A) represents the measurement position of the back mark A (relative to the equipment reference); (ΔX_AB, ΔY_AB) represents the initial inherent deviation between the mark A and the mark B before epitaxy. Through this calculation, (ΔX_front-B - ΔX_back-A) essentially gives the relative position deviation of the front mark B after epitaxy relative to the back mark A. Subtracting the initial inherent deviation (ΔX_AB, ΔY_AB) can accurately separate the pattern shift (ΔX, ΔY) caused purely by the epitaxial growth process.

[0058] Compared with the traditional method of making a slice from a wafer and observing the cross section using an electron microscope, the measurement method provided by the embodiment has significant advantages. The method realizes non-destructive testing, and the wafer does not need to be destructively processed during the entire measurement process. After measurement, the wafer can continue to be used for subsequent process flow or other tests, effectively saving sample cost. At the same time, the measurement accuracy is high, mainly depending on the performance of high-precision overlay measurement equipment and double-side alignment photolithography equipment, and can reach the nanometer level, which is much higher than the accuracy of the traditional method. By deducting the initial inherent deviation, the system error is further eliminated, and the accuracy of the measurement result is ensured. In addition, since the measurement and calculation are performed by using automatic equipment, the processes of slice preparation, staining and microscopic observation are omitted, the measurement efficiency is high, the time consumption is short, and the process feedback cycle can be greatly shortened. The method is also easy to realize full-wafer multi-point offset data acquisition, can generate an intuitive offset distribution map, and effectively reflects the uniformity characteristics of the epitaxial process. This is information that the traditional cross-section observation cannot fully obtain. Especially when dealing with processes such as thick epitaxy, the method shows strong applicability in solving the more serious pattern offset problem, and provides fast and accurate data support for optimizing epitaxial process parameters, evaluating stress control effect and performing reliable online process monitoring. It has important practical significance for improving the overall process stability, improving device performance and improving the yield of final products.

[0059] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the application in a schematic manner, and only show the components related to the application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in shape, number and proportion, and the layout pattern of the components may be more complex.

[0060] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the application should be covered by the claims of the application.

Claims

1. A method for measuring the offset of an epitaxial pattern, characterized in that: At least: Step 1: forming a first trench on a substrate and filling the first trench with a first material to form a first alignment mark; Step 2: forming a second alignment mark on the substrate with the first alignment mark as a reference, and measuring a first deviation between the first alignment mark and the second alignment mark; Step 3: performing epitaxial growth on the substrate to form an epitaxial layer; Step 4: thinning the back surface of the substrate to expose the back surface of the first alignment mark; Step 5: Using a double-sided alignment photolithography device, align the front and back surfaces of the substrate simultaneously to obtain a second deviation of the front surface of the second alignment mark covered by the epitaxial layer and a third deviation of the back surface of the first alignment mark; Step six: Calculate the pattern offset of the epitaxial layer based on the first deviation, the second deviation, and the third deviation.

2. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step one, forming the first groove includes: coating a photoresist on the substrate; forming a pattern corresponding to the first groove on the photoresist through exposure and development; performing deep silicon etching on the substrate using the photoresist pattern as a mask to form the first groove; and removing the photoresist.

3. The method for measuring the offset of an epitaxial pattern according to claim 2, wherein: In step one, the deep silicon etching is performed using a photoresist hard mask mode.

4. The method for measuring the offset of an epitaxial pattern according to claim 2 or 3, wherein: In step 1, the depth of the deep silicon etching is greater than 80 microns.

5. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step 1, the first material is polysilicon.

6. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step 2, the method for forming the second alignment mark includes: using the first alignment mark as a reference, forming the second alignment mark on the silicon material of the substrate by photolithography and etching.

7. The method for measuring the offset of an epitaxial pattern according to claim 1 or 6, wherein: In step 2, measuring the first deviation includes: forming corresponding first overlay marks and second overlay marks respectively while forming the first alignment mark and the second alignment mark; using an overlay measurement device to measure the overlay deviation between the first overlay mark and the second overlay mark to obtain the first deviation, which is recorded as (ΔX_AB, ΔY_AB).

8. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step three, the epitaxial growth is single crystal silicon epitaxial growth.

9. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step three, the thickness of the epitaxial layer is less than 6 microns or greater than 10 microns.

10. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step five, the alignment accuracy of the double-sided alignment lithography equipment is better than 200 nanometers.

11. The method for measuring the offset of an epitaxial pattern according to claim 1, wherein: In step six, the second deviation on the front side is recorded as (ΔX_front-B, ΔY_front-B), and the third deviation on the back side is recorded as (ΔX_back-A, ΔY_back-A). The calculation formula for the graphic offset (ΔX, ΔY) of the epitaxial layer is: ΔX = ΔX_front-B - ΔX_back-A - ΔX_AB; ΔY = ΔY_front-B - ΔY_back-A - ΔY_AB.

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