Inverter topology with low common-mode voltage and phase current THD

Abstract

The invention discloses an inverter topology with low common-mode voltage and phase current THD. The inverter topology comprises a direct-current power supply Vu, a direct-current power supply V1, a power switch S1, a power switch S2, a power switch Sa1, a power switch Sa2, a power switch Sb1, a power switch Sb2, a power switch Sc1, a power switch Sc2, a power switch Sd1 and a power switch Sd2. The direct-current power supply Vu and the direct-current power supply V1 are connected in series, and the power switch S1 and the power switch S2 form a half-bridge structure; the power switch Sa1 and the power switch Sa2 are connected in series to form an A bridge arm; the power switch Sb1 and the power switch Sb2 are connected in series to form a bridge arm B; the power switch Sc1 and the power switch Sc2 are connected in series to form a C bridge arm; and the power switch Sd1 and the power switch Sd2 are connected in series to form a D bridge arm. According to the invention, a path can be effectively provided for the zero-sequence current generated by the unbalanced load, and the symmetry of the three-phase output voltage can be maintained under the condition of the unbalanced load.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inverters, and particularly relates to an inverter topology with low common-mode voltage and phase current THD. BACKGROUND

[0002] At present, with the rapid development of renewable energy such as solar energy and wind energy, the demand for efficient and reliable inverters is increasing, and H6 (six-switch) inverters have been widely used in these fields due to their excellent performance. However, there is a common-mode voltage (CMV) in the traditional 3-φ H6 inverter. The common-mode voltage has several adverse effects on the double-level inverter-fed motor drive system, including ground leakage current, insulation failure, motor bearing failure, and electromagnetic interference (EMI). In order to suppress CMV, active or passive filters can be used. However, this not only increases the loss, but also increases the cost, weight and size of the system. Therefore, researchers try to use pulse width modulation (PWM) strategies to reduce CMV, such as active zero state pulse width modulation (AZSPWM) or near state pulse width modulation (NSPWM). Using these methods can reduce the CMV by 66.6%. However, the PWM-based method can cause the total harmonic distortion (THD) of the phase current to rise, which in turn causes additional losses in the inverter and motor. One way to improve the phase current THD is to increase the switching frequency, but this increases the switching loss and may reduce the efficiency. In addition, higher switching frequency increases the number of high-frequency conversions in CMV, which is one of the problems that needs to be solved, because it often leads to current leakage and electromagnetic interference.

[0003] To solve the above problems, researchers have developed new 3-φ three-level inverter topologies based on the concept of DC and AC bypass. These topologies reduce CMV and leakage current by isolating or clamping the 3-φ load during zero state. These topologies can be divided into two types: single zero vector bypass (SZVB) or double zero vector bypass (DZVB). In SZVB type topology, the inverter configuration can only use one of the two achievable zero vectors generated by the inverter. For example, the H7 type DC and AC bypass topology is SZVB type, which uses 7 controllable power semiconductor switches to reduce CMV. This is basically achieved by connecting an additional controlled switch in series with the H6 inverter or 3-φ diode bridge. Although the THD of phase current in SZVB type topology is improved compared with AZSPWM or NSPWM, it is still not as good as the traditional space vector modulation (CSVM). This problem is solved in DZVB type topology, which can use two zero vectors to eliminate CMV. For example, the H8 type DC and AC bypass inverter topology can use both zero vectors at the same time. Therefore, in DZVB topology, CSVM can be used as PWM scheme, which presents lower phase current THD. However, DZVB type topology usually uses two additional series switches and H6 inverter, which increases the conduction loss compared with SZVB type topology.

[0004] To solve the problem of increased loss, researchers have proposed an improved two-level inverter that does not require additional switches in series with the H6 inverter. The additional switches are connected in another way, i.e. a topology with one three-level phase branch and two two-level phase branches. In this case, the peak-to-peak value of CMV and dv / dt are reduced. However, compared with the CSVM scheme, the THD is improved.

[0005] At the same time, under unbalanced load conditions, it is difficult for the inverter to maintain the symmetry of the three-phase output voltage. Since the inverter does not have a fourth bridge arm, it cannot provide a path for the zero sequence current generated by the unbalanced load, resulting in ineffective control of the neutral current, asymmetric and distorted output voltage, and high harmonic content of output voltage and current, affecting power quality and normal operation of load equipment. To this end, we propose an inverter topology with low common-mode voltage and phase current THD. SUMMARY

[0006] The purpose of the present application is to provide an inverter topology with low common-mode voltage and phase current THD to solve the problems in the prior art.

[0007] To achieve the above purpose, the present application provides the following technical scheme: an inverter topology with low common-mode voltage and phase current THD, comprising a DC power supply V u , a DC power supply V l, power switch S1, power switch S2, power switch S a1 , power switch S a2 , power switch S b1 , power switch S b2 , power switch S c1 , power switch S c2 , power switch S d1 , and power switch S d2 ; the direct current power supply V u and direct current power supply V l are connected in series, and the power switch S1 and the power switch S2 form a half-bridge structure;

[0008] The power switch S a1 , power switch S a2 are connected in series to form an A bridge arm; the power switch S b1 , power switch S b2 are connected in series to form a B bridge arm; the power switch S c1 , power switch S c2 are connected in series to form a C bridge arm; the power switch S d1 , power switch S d2 are connected in series to form a D bridge arm.

[0009] Preferably, the direct current power supply V u positive terminal connects a node P, and the direct current power supply V u negative terminal connects a node N; the direct current power supply V l positive terminal connects a node N, and the direct current power supply V l negative terminal connects a node O; the direct current power supply V u , direct current power supply V l form a series power supply group with a direct current side voltage of Vdc.

[0010] Preferably, one end of the power switch S1 connects a direct current power supply V u positive terminal P, and the other end of the power switch S1 connects a common node M; one end of the power switch S2 connects a direct current power supply V u negative terminal N, and the other end of the power switch S2 also connects the node M, that is, the power switch S1 and the power switch S2 are connected in parallel between P-M and N-M, forming a half-bridge structure, and M is a half-bridge output terminal.

[0011] Preferably, one end of the power switch S a1 connects the node M, and the other end of the power switch S a1 is connected to one end of the power switch S a2 , and the other end of the power switch S a2 connects the node O, and the power switch S a1 , power switch S a2 connects a point as an A phase output terminal, and an output current i A ;

[0012] Power switch S b1 One end connects M point, power switch S b1 The other end connects power switch S b2 One end connects, power switch S b2 The other end connects O point, power switch S b1 , power switch S b2 The connection point is B phase output end, and the output current is i B .

[0013] Power switch S c1 One end connects M point, power switch S c1 The other end connects power switch S c2 One end connects, power switch S c2 The other end connects O point, power switch S c1 , power switch S c2 The connection point is C phase output end, and the output current is i C .

[0014] Power switch S d1 One end connects M point, power switch S d1 The other end connects power switch S d2 One end connects, power switch S d2 The other end connects O point, power switch S d1 , power switch S d2 The connection point is neutral line related output end, and the output current is i n .

[0015] Preferably, the three-phase output end is connected to the load after being filtered by an inductor.

[0016] Compared with the prior art, the application has the beneficial effects that:

[0017] 1. Compared with the traditional H6 type 3-φ inverter, the application can reduce the CMVp-p value by 66.6%, effectively weaken the adverse effects of CMV, and further improve the stability.

[0018] 2. Compared with the improved double-level inverter, the application can effectively solve the CMV problem while still maintaining superior THD performance and output better voltage and current waveforms.

[0019] 3. Compared with the traditional three-phase three-bridge arm inverter, the application can effectively provide a path for the zero sequence current generated by the unbalanced load and maintain the symmetry of the three-phase output voltage under the condition of unbalanced load. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and are meant to explain the application without limiting the scope thereof. In the drawings:

[0021] Figure 1 is the circuit schematic of the present application;

[0022] Figure 2 is the SV diagram of the topology proposed by the present application;

[0023] Figure 3 is the (a) SV hexagon diagram, (b) region 1 sector diagram, (c) region 2 sector diagram, (d) region 3 sector diagram of the present application;

[0024] Figure 4 is the reference vector and SV coordinate diagram of the present application;

[0025] Figure 5 is the fourth bridge arm control block diagram of the present application;

[0026] Figure 6 is the current THD comparison diagram of the topology of the present application and the conventional topology;

[0027] Figure 7 is the output voltage waveform diagram of the three-phase three-bridge inverter of the present application;

[0028] Figure 8 is the inverter output voltage waveform diagram of the present application;

[0029] Figure 9 is the load diagram of the neutral current (upper) and three-phase load current (lower) of the present application. DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application.

[0031] Please refer to Figure 1 In the embodiments of the present application, an inverter topology with low common-mode voltage and phase current THD includes a DC power supply V u , a DC power supply V l , a power supply switch S1, a power supply switch S2, a power supply switch Sa1 , power switch S a2 , power switch S b1 , power switch S b2 , power switch S c1 , power switch S c2 , power switch S d1 , and power switch S d2 ; the direct current power supply V u and direct current power supply V l are connected in series, and the power switch S1 and the power switch S2 form a half-bridge structure;

[0032] The power switch S a1 , power switch S a2 are connected in series to form an A bridge arm; the power switch S b1 , power switch S b2 are connected in series to form a B bridge arm; the power switch S c1 , power switch S c2 are connected in series to form a C bridge arm; and the power switch S d1 , power switch S d2 are connected in series to form a D bridge arm.

[0033] Preferably, the direct current power supply V u positive terminal is connected to a node P, and the direct current power supply V u negative terminal is connected to a node N; the direct current power supply V l positive terminal is connected to the node N, and the direct current power supply V l negative terminal is connected to a node O; the direct current power supply V u , the direct current power supply V l form a series power supply group with a direct current side voltage of Vdc.

[0034] Preferably, one end of the power switch S1 is connected to the direct current power supply V u positive terminal P, and the other end of the power switch S1 is connected to a common node M; one end of the power switch S2 is connected to the direct current power supply V u negative terminal N, and the other end of the power switch S2 is also connected to the node M, that is, the power switch S1 and the power switch S2 are connected in parallel between P-M and N-M, forming a half-bridge structure, and M is a half-bridge output terminal.

[0035] Preferably, one end of the power switch S a1 is connected to the node M, and the other end of the power switch S a1 is connected to one end of the power switch S a2 , and the other end of the power switch S a2 is connected to the node O; one end of the power switch S a1 , and one end of the power switch S a2 are connected to an A-phase output terminal, and an output current i A flows through the A-phase output terminal;

[0036] Power switch S b1 One end is connected to point M, power switch S b1 The other end is connected to power switch S b2 One end is connected, power switch S b2 The other end is connected to point O, power switch S b1 , power switch S b2 The connection point is the B-phase output end, and the output current is i B ;

[0037] Power switch S c1 One end is connected to point M, power switch S c1 The other end is connected to power switch S c2 One end is connected, power switch S c2 The other end is connected to point O, power switch S c1 , power switch S c2 The connection point is the C-phase output end, and the output current is i C ;

[0038] Power switch S d1 One end is connected to point M, power switch S d1 The other end is connected to power switch S d2 One end is connected, power switch S d2 The other end is connected to point O, power switch S d1 , power switch S d2 The connection point is the neutral line related output end, and the output current is i n .

[0039] Preferably, the three-phase output end is connected to the load after being filtered by an inductor.

[0040] A standard three-phase four-leg inverter (consisting of S a1 , S a2 , S b1 , S b2 , S c1 , S c2 , S d1 , S d2 , and the rated voltage is Vdc) is connected across two terminals M (half-bridge output end) and O (negative terminal of DC power source Vl). The voltage across M can also be explained as the DC link voltage (VMO) of the inverter, which has two possible voltage levels of Vdc and Vdc / 2. The control of the three-phase four-leg inverter can be divided into two independent parts: the control of the first three legs and the control of the fourth leg.

[0041] For the first three legs, there are more SVs in the proposed topology compared to the conventional solution (H6 inverter with six switches) because of the two possible levels of the DC-link voltage of this structure. The H6 structure results in 8 switching states, while the half-bridge structure can have 2 switching states. Therefore, the proposed topology has a total of 2 x 8 = 16 switching states because it is a cascaded configuration of half-bridge and H6 structures. Table 1 gives the opening switches of all SVs in the proposed topology.

[0042] SV TOS SV TOS SV TOS

[222] [S1, S a1 , S b1 , S c1 ]]

[111] [S2, S a1 , S b1 , S c1 ]]>

[002] [S1, S a2 , S b2 , S c1 ]]>

[220] [S1, S a1 , S b1 , S c2 ]]

[110] [CDATA[S2, S a1 , S b1 , S c2 ]]

[000] [S1, S a2 , S b2 , S c2 ]]

[202] [S1, S a1 , S b2 , S c1 ]]>

[101] [S2, S a1 , S b2 , S c1 ]]>

[001] [S2, S a1 , S b1 , S c1 ]]>

[200] [S1, S a1 , S b2 , S c2 ]]>

[100] [S2, S a1 , S b2 , S c2 ]]>

[000] [S2, S a2 , S b2 , S c2 ]]>

[022] [S1, S a2 , S b1 , S c1 ]]>

[011] [S2, S a2 , S b1 , S c1 ]]>

[020] [S1, S a2 , S b1 , S c2 ]]>

[010] [S2, S a2 , S b1 , S c2 ]]>

[0043] Zero vectors

[000] can be implemented using two different switching states S1, S a2 , S b2 , S c2 and S2, S a2 , S b2 , S c2 , while the other vectors have only one switching state each. For this reason, although there are 16 switching states, the proposed topology has only 15 SVs. Out of the 15 SVs, 3 are zero vectors, so the total number of different SV coordinates (positions) is 13. The proposed topology SVs are shown in Figure 2 , indicating that there are 13 SV coordinates (positions) and 15 SVs, with 3 zero SVs concentrated in the center of the hexagon.

[0044] In the case of the proposed topology, the CMV can be expressed in terms of the average of the three-phase voltages as follows:

[0045]

[0046] In terms of the average of the three-phase voltages as follows:

[0047]

[0048] The SV hexagon of the inverter topology is divided into three regions, as shown in Figure 3 (a), each of which is further divided into 6 sectors (S1 to S6), as shown in Figure 3 (b)-(d):

[0049] Figure 3 (b) shows the sector configuration of region 1. The position of each SV is represented by a small square or circle, and the number inside the circle is the SV number. Next to each SV, the corresponding k value is also given. Each sector consists of three SVs, and these SVs are chosen in such a way that the maximum CMV P-P in that sector is Vdc / 3. Take sector S1 of region 1 as an example Figure 3(b)], whose constituent SVs are

[202] (CMV = 2Vdc / 3),

[200] (CMV = Vdc / 3), and

[101] (CMV = Vdc / 3). It can be seen that the maximum difference between the CMV values ​​produced by these three SVs is Vdc / 3. Therefore, for any selected SV sequence, CMVP-P is always equal to Vdc / 3 for a given sector. The same is true for all other sectors.

[0050] The general structure of any given sector is as follows Figure 4 As shown: a sector generally includes three SVs: SV1, SV m ; and SV n Since each region contains 7 SVs, the variables l, m, and n can take any integer value between 1 and 7. l SV m and SV n The coordinates of are (xl, yl), (xm, ym) and (xn, yn). The reference vector is located in the sector with coordinates (x, y), SV l SV m and SV n The residence time of each vector is recorded as Tl, Tm and Tn respectively, and the switching period is recorded as Ts. The calculation formula of the residence time of each vector is as follows:

[0051]

[0052] In order to achieve the best performance of CMV and phase current THD, the three SV sequences are determined as shown in Table 2:

[0053] Sector SV Sequence-1 SV Sequence-2 SV Sequence-3 S1 1-2-3-2-1 2-1-3-1-3-1-2 2-3-1-3-1-3-2 S2 1-2-4-2-1 2-1-4-1-4-1-2 2-4-1-4-1-4-2 S3 1-4-5-4-1 4-1-5-1-5-1-4 4-5-1-5-1-5-4 S4 1-6-5-6-1 6-1-5-1-5-1-6 6-5-1-5-1-5-6 S5 7-4-5-4-7 7-4-5-7-5-4-7 7-4-5-7-5-4-7 S6 7-4-2-4-7 7-4-2-7-2-4-7 7-4-2-7-2-4-7

[0054] These sequences are explained below:

[0055] SV Sequence-1: This is a five-pulse sequence designed to minimize the number of CMV transitions in one switching cycle. This SV sequence is designed to provide the best CMV performance.

[0056] SV Sequence-2: This is a seven-pulse sequence designed to achieve better THD performance while minimizing CMV. Although THD performance is improved, the number of switching transitions is higher in this case, which may result in higher switching losses.

[0057] SV Sequence-3: This is also a seven-pulse sequence designed to minimize switching transitions and achieve better THD. In this case, the number of switching transitions is less than in SV Sequence-2. The CMV performance is not as good as the previous SV sequence.

[0058] Considering that all these schemes can reduce CMVP-P by 66.6%, the subsequent simulations will adopt the SV sequence-3 scheme.

[0059] The control of the fourth bridge arm actually controls the action of the upper and lower switches of the fourth bridge arm so that the neutral current in tracks the three-phase load current. The average current control method with high control accuracy, fixed switching frequency and strong anti-interference performance is adopted, such as Figure 5 As shown in the figure: the three-phase load current is first summed and negative, then subtracted from the neutral current and the output regulation value is compared with the triangle wave through a simple PI controller to generate a PWM signal to drive the corresponding switch tube action.

[0060] This inverter topology not only has superior phase current THD performance, but also demonstrates its advantages in CMV by comparison with existing solutions. In addition, this topology can effectively solve the problem of unbalanced load.

[0061] To compare the proposed topology with existing topologies, a V / F controlled induction motor load is considered. The phase current THD values ​​at different input frequencies are as follows: Figure 6 As shown. Figure 6 The analysis shows that while the proposed topology reduces CMVP-P by 66.6%, it still exhibits superior phase current THD performance. It can be observed that the proposed topology always has better THD performance compared to the existing topology.

[0062] Figure 7 and Figure 8 The output voltage waveforms of a three-phase, three-leg inverter and the proposed inverter under unbalanced load conditions are shown in Figure 2. As can be seen, the three-phase voltages of the traditional three-phase, three-leg inverter are severely asymmetric when powered. However, the new inverter topology has a strong capability to handle unbalanced or nonlinear loads.

[0063] Figure 9 The sum of the negative three-phase load current and the neutral current i is given n , it can be seen that by independently controlling the zero-sequence voltage of the fourth bridge arm, the neutral current i n The reference command current is tracked very well.

[0064] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. An inverter topology with low common-mode voltage and phase current THD, characterized by: Including DC power supply V u , DC power supply V l , power switch S1, power switch S2, power switch S a1 , power switch S a2 , power switch S b1 , power switch S b2 , power switch S c1 , power switch S c2 , power switch S d1 And the power switch S d2 The DC power supply V u and DC power supply V l Connected in series, the power switch S1 and the power switch S2 form a half-bridge structure; The power switch S a1 , power switch S a2 are connected in series to form the A bridge arm; the power switch S b1 , power switch S b2 are connected in series to form the B bridge arm; the power switch S c1 , power switch S c2 are connected in series to form a C bridge arm; the power switch S d1 , power switch S d2 They are connected in series to form a D bridge arm.

2. The inverter topology with low common mode voltage and phase current THD according to claim 1, characterized in that: The DC power supply V u The positive terminal is connected to the node P, the DC power supply V u The negative terminal is connected to node N; the DC power supply V l The positive terminal is connected to N, the DC power supply is V l The negative terminal is connected to node O, the DC power supply V u , DC power supply V l A series power supply group with a DC side voltage of Vdc is formed.

3. The inverter topology with low common mode voltage and phase current THD according to claim 1, characterized in that: One end of the power switch S1 is connected to a DC power supply V u The positive terminal is point P, the other end of the power switch S1 is connected to the common node M; one end of the power switch S2 is connected to the DC power supply V u The negative terminal is point N, and the other end of the power switch S2 is also connected to point M. That is, the power switches S1 and S2 are connected in parallel between PM and NM to form a half-bridge structure, and M is the output end of the half-bridge.

4. The inverter topology with low common mode voltage and phase current THD according to claim 1, characterized in that: The power switch S a1 One end is connected to point M, the power switch S a1 The other end is connected to the power switch S a2 One end is connected to the power switch S a2 The other end is connected to point O, the power switch S a1 , power switch S a2 The connection point is the A phase output terminal, and the output current i A ; Power switch S b1 One end is connected to point M, the power switch S b1 The other end is connected to the power switch S b2 One end is connected to the power switch S b2 The other end is connected to point O, the power switch S b1 , power switch S b2 The connection point is the B phase output terminal, and the output current i B ; Power switch S c1 One end is connected to point M, the power switch S c1 The other end is connected to the power switch S c2 One end is connected to the power switch S c2 The other end is connected to point O, the power switch S c1 , power switch S c2 The connection point is the C phase output terminal, and the output current i C ; Power switch S d1 One end is connected to point M, the power switch S d1 The other end is connected to the power switch S d2 One end is connected to the power switch S d2 The other end is connected to point O, the power switch S d1 , power switch S d2 The connection point is the neutral line related output terminal, the output current i n .

5. The inverter topology with low common mode voltage and phase current THD according to claim 1, characterized in that: The three-phase output is connected to the load after filtering inductance.

Images