Reconfigurable digital beamforming method based on api functions

Abstract

The application particularly relates to a reconfigurable digital beam forming method based on API functions, adopting a CPU+multi-block DSP+FPGA architecture, and parameters are quickly sent to the multi-block DSP+FPGA by the CPU in the mode of API functions, so that the reconfiguration of the arbitrary array size and the beam function can be realized. The parameters such as the reconfigurable number of the radar array, the number of array elements, the number of beams, the data rate and the like are configured by software, the multi-block DSP+FPGA board card realizes the reconfiguration of the arbitrary array size and the beam function according to the parameters, has the characteristics of quickly adjusting the strategy according to the form and dynamically deploying the function, and greatly improves the adaptability and the survival performance of the radar system.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a reconfigurable digital beamforming method based on API functions. Background Technology

[0002] In related technologies, to improve the adaptability and survivability of radar systems, the operating modes and functions of radar systems are becoming increasingly complex, and the requirements for the number, size, and functions of radar arrays are also increasing. Therefore, realizing dynamic reconfigurable radar array technology is particularly important. Traditional array element processing platforms, which are built using modular architectures, usually have strong software and hardware coupling. When parameters change, they require maintenance and upgrades, resulting in long debugging cycles and poor flexibility.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This invention provides a reconfigurable digital beamforming method based on API functions, a computer program product, and a storage medium, thereby overcoming, to some extent, the deficiencies existing in the prior art.

[0005] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0006] According to a first aspect of the present invention, a reconfigurable digital beamforming method based on API functions is provided, the method comprising:

[0007] The CPU receives the reconstructed unit manifold data sent by the host computer, parses the reconstructed unit manifold data, rearranges the data using the data parsing results, obtains J array surface information, and sends the J array surface information to the corresponding DSP boards respectively.

[0008] The reconstructed unit manifold data includes: the total number of antenna array elements P, the number of antenna array channels processed by a single FPGA n, and the number of array elements within a single array channel processed by a single FPGA m, as well as address information; the array information includes: radar parameter information, array element coordinate information, and beam angle information.

[0009] Each DSP board generates array manifold data based on the array surface information and sends the array manifold data to the FPGA processing platform. The array manifold data contains complex weighting coefficients of m*n array elements of L beams, and its data stream is arranged based on the complex weighting coefficients of a single channel of L*m beams.

[0010] Each FPGA processing platform rearranges the complex weighting coefficients according to the configured number of channels and the number of array elements in the subarray. The array data and weighting coefficients in each channel are processed through a cascaded architecture of ternary multipliers to obtain the single-channel beamforming result. Then, all single-channel beamforming results are aligned and summed to obtain the beamforming data of a single FPGA reconstruction module. The beamforming data is then sent to the FPGA integration platform.

[0011] The FPGA integration platform aligns the beamforming data from each FPGA processing platform, and then accumulates the aligned beamforming data to obtain the integrated beamforming result.

[0012] In some exemplary embodiments, before sending the J array information to the corresponding DSP boards, the method further includes:

[0013] During system initialization, the CPU enumerates the DSP board and writes the DSP board information into the system.

[0014] When the device ID of the DSP board matches the PCI driver ID, the CPU loads the driver and configures the device node name for each different DSP board.

[0015] In some exemplary embodiments, the method further includes:

[0016] During system initialization, the CPU receives the array element coordinate information sent by the host computer.

[0017] In some exemplary embodiments, the central processing unit (CPU) receives reconstruction data sent by the host computer, including:

[0018] The CPU pre-binds to the host computer's IP address and port number using the API functions corresponding to the User Datagram Protocol (UDP) and creates a data receiving queue.

[0019] Upon receiving the current UDP packet, write it into the data receive queue;

[0020] Perform frame header verification on the current UDP packet;

[0021] When verification fails, the UDP API function is called to report the verification error information to the host computer.

[0022] If the verification is successful, the reconstructed data is parsed.

[0023] In some exemplary embodiments, the DSP board generates array manifold data based on the array surface information, including:

[0024] The DSP board determines the complex weighting coefficients based on the number of array elements and the number of beams; the data stream of the complex weighting coefficients is read and written using ping-pong operations.

[0025] In some exemplary embodiments, the DSP board sends array manifold data to the FPGA processing platform, including:

[0026] The DSP boards send the array manifold data to their respective FPGA processing platforms via the SRIO interface; the complex weighted coefficients generated by each DSP board are arranged in the same way and do not require rearrangement.

[0027] In some exemplary embodiments, the FPGA integration platform includes at least one FPGA integration platform;

[0028] The method further includes:

[0029] When the receiving bandwidth of a single FPGA integration platform is less than the sum of the transmitting bandwidths of J FPGA processing platforms, multiple FPGA integration platforms are invoked and cascaded to ensure that the receiving bandwidth of the cascaded multiple FPGA integration platforms is greater than the sum of the transmitting bandwidths of J FPGA processing platforms.

[0030] In some exemplary embodiments, the method further includes:

[0031] The CPU obtains the reconfiguration array information from the host computer. The reconfiguration array information includes at least one of the following: number of reconfigurations, number of channels, number of array elements, number of beams, and data rate.

[0032] The CPU calls the PCIe API function to send the reconstructed array information to the DSP board and FPGA processing platform.

[0033] In some exemplary embodiments, the method further includes:

[0034] The FPGA processing platform receives beamforming data sent by the DSP board via the SRIO interface; and

[0035] The FPGA processing platform receives AD echo data through the GT interface and writes it into the buffer modules of each channel.

[0036] According to a second aspect of the present invention, a computer program product is provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the above-described reconfigurable digital beamforming method based on API functions.

[0037] According to a third aspect of the present invention, a storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described API function-based reconfigurable digital beamforming method.

[0038] According to a fourth aspect of the present invention, an electronic device is provided, comprising:

[0039] Processor; and

[0040] Memory for storing the executable instructions of the processor;

[0041] The processor is configured to implement the above-described API function-based reconfigurable digital beamforming method by executing the executable instructions.

[0042] The reconfigurable digital beamforming method based on API functions provided in the embodiments of this invention, by configuring parameters such as the number of reconfigurable radar arrays, the number of array elements, the number of beams, and the data rate, allows multiple DSP boards and FPGA platforms to reconfigure arbitrary array sizes and beam functions according to these parameters. It features rapid strategy adjustment based on the situation and dynamic deployment of functions, greatly improving the adaptability and survivability of the radar system. Data transmission and control between the CPU and the host computer, between the CPU and the DSP boards, and between the DSP boards and the FPGA platform are performed through specified API functions, enabling adaptation to different functions and modes, different array sizes, and different numbers of beams; achieving decoupling of hardware and software and improving development efficiency.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0045] Figure 1 The illustration shows a schematic diagram of a reconfigurable digital beamforming method based on API functions, an exemplary embodiment of the present invention.

[0046] Figure 2 The illustration shows a schematic diagram of a reconfigurable digital beamforming method based on API functions, an exemplary embodiment of the present invention.

[0047] Figure 3 This diagram illustrates an exemplary embodiment of the present invention: an array manifold coefficient rearrangement process.

[0048] Figure 4 This diagram illustrates an exemplary embodiment of the present invention, showing a process for inputting array data.

[0049] Figure 5 The diagram illustrates a read control timing diagram according to an exemplary embodiment of the present invention.

[0050] Figure 6 This schematic diagram illustrates a single-channel beamforming process according to an exemplary embodiment of the present invention.

[0051] Figure 7 This schematic diagram illustrates an embodiment of the present invention for generating an alignment pulse.

[0052] Figure 8 The diagram illustrates the composition of an electronic device according to an exemplary embodiment of the present invention. Detailed Implementation

[0053] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0055] In related technologies, an open software architecture using API functions can achieve different modes and functions through software parameterization configuration, thus decoupling software and hardware. Due to the large number of input and output channels and complex beam functions of array antennas, a single DSP+FPGA architecture is usually used. However, the single DSP+FPGA array element processing limit is low, making it unsuitable for complex scenarios with large arrays and multiple elements.

[0056] To address the shortcomings and deficiencies of existing technologies, this example implementation provides a reconfigurable digital beamforming method based on API functions. Through flexible custom parameter configuration on the host computer, beamforming processing for beamforms of arbitrary array sizes can be completed quickly.

[0057] In this example implementation, refer to Figure 1As shown, the reconfigurable digital beamforming method based on API functions may specifically include the following steps:

[0058] Step S11: The CPU receives the reconstructed unit manifold data sent by the host computer, parses the reconstructed unit manifold data, rearranges the data using the data parsing results, obtains J array information, and sends the J array information to the corresponding DSP boards respectively.

[0059] The reconstructed unit manifold data includes: the total number of antenna array elements P, the number of antenna array channels processed by a single FPGA n, and the number of array elements within a single array channel processed by a single FPGA m, as well as address information; the array information includes: radar parameter information, array element coordinate information, and beam angle information.

[0060] Step S12: Each DSP board generates array manifold data based on the array surface information and sends the array manifold data to the FPGA processing platform. The array manifold data contains complex weighting coefficients of m*n array elements of L beams, and its data stream is arranged based on the complex weighting coefficients of a single channel of L*m beams.

[0061] Step S13: Each FPGA processing platform rearranges the complex weighting coefficients according to the configured number of channels and the number of array elements in the subarray. The array data and weighting coefficients in each channel are processed through a cascaded architecture of ternary multipliers to obtain the single-channel beamforming result. Then, all single-channel beamforming results are aligned and summed to obtain the beamforming data of a single FPGA reconstruction module. The beamforming data is then sent to the FPGA integration platform.

[0062] In step S14, the FPGA integration platform aligns the beamforming data from each FPGA processing platform, and then accumulates the aligned beamforming data to obtain the integrated beamforming result.

[0063] The method provided by this invention is implemented based on a CPU+DSP+FPGA processing platform. The CPU has powerful single-instruction functionality, high speed, and simple control, making it easy to parse and issue configuration parameters; the DSP has strong computing power and high precision, which is beneficial for the generation of complex weighting coefficients in digital beamforming; the FPGA has high parallelism and is suitable for high-speed data rate transmission, which is beneficial for the parallel processing of complex weighting coefficients and array data with multi-channel high-speed sampling rates.

[0064] The following will describe in more detail each step of the API function-based reconfigurable digital beamforming method in this exemplary embodiment, with reference to the accompanying drawings and embodiments.

[0065] For example, assume the total number of antenna array elements is P, the number of reconfigurable array elements is J, the maximum number of channels for a single FPGA processing antenna array is N, the maximum number of array elements within a single channel of a single FPGA processing array is M, the data rate of a single array element is T, the number of data transmitted by a single array element is K, and the number of beams to be formed by the processing platform is L. The number of reconfigurable array elements J ≥ P / (N*M), where J ∈ positive integers, and the input data rate of a single input channel is T*M. The FPGA operating clock frequency F of the processing platform only needs to satisfy: F > T*L.

[0066] In step S11, the CPU receives the reconstructed unit manifold data sent by the host computer, parses the reconstructed unit manifold data, rearranges the data using the data parsing results, and obtains J array information; and sends the J array information to the corresponding DSP boards respectively.

[0067] For example, the central processing unit (CPU) receives reconstruction data sent by the host computer, including:

[0068] Step S21: The CPU pre-binds the IP address and port number of the host computer through the API function corresponding to the User Datagram Protocol (UDP) and creates a data receiving queue.

[0069] Step S22: After receiving the current UDP packet, write it into the data receive queue;

[0070] Step S23: Perform frame header verification on the current UDP packet;

[0071] Step S24: If the verification fails, call the UDP API function to report the verification error information to the host computer;

[0072] Step S25: If the verification is successful, parse the reconstructed data.

[0073] For example, the method further includes: during system initialization processing, the CPU receives array element coordinate information sent by the host computer.

[0074] Specifically, for the CPU, the CPU processing platform binds the IP address and port number of the front-end host computer software through UDP-related API functions, creates a data receiving queue, and enables the timer interrupt function to wait for data arrival. When a UDP data packet is received, frame header verification is performed. If the verification fails, the CPU sends a verification error message back to the host computer through the UDP API function; if the verification succeeds, J array information is reconstructed based on the total number of antenna array elements P, the number of antenna array channels processed by a single FPGA n, and the number of array elements within a single array channel processed by a single FPGA, according to the parameter information. Each array information contains radar parameter information, array element coordinate information, and beam angle information. The array element coordinate information is sent by the host computer only once during each power-on initialization, while the beam angle information can be changed according to the repetition frequency timing in the radar parameters, but the beam angle information must correspond one-to-one with each array information.

[0075] For example, before sending the J array information to the corresponding DSP boards, the method further includes:

[0076] In step S31, during system initialization, the CPU enumerates the DSP board and writes the DSP board into the system.

[0077] In step S32, when the device ID of the DSP board matches the PCI driver ID, the CPU loads the driver and configures the device node name for each different DSP board.

[0078] Specifically, before sending the rearranged J array information to the J DSP boards, the CPU processing platform calls PCIe-related API functions to enumerate PCI devices (i.e., DSP boards) during system initialization. After the system has enumerated all devices, the PCI devices are added to the system. When the enumerated PCI device ID matches the PCI driver ID, the CPU processing platform loads the driver. To distinguish between multiple device nodes, different device node names can be set, and they can be differentiated using major and minor device numbers. At the application layer, the corresponding device node is opened, and then the READ or WRITE function is called to perform the transfer operation using PCIe.

[0079] In step S12, each DSP board generates array manifold data based on the array surface information and sends the array manifold data to the FPGA processing platform. The array manifold data contains complex weighting coefficients of m*n array elements of L beams, and its data stream is arranged based on the complex weighting coefficients of a single channel of L*m beams.

[0080] For example, the DSP board generates array manifold data based on the array surface information, including: the DSP board determines complex weighting coefficients based on the number of array elements and the number of beams; wherein the data stream of the complex weighting coefficients is read and written using ping-pong operation.

[0081] For example, the DSP board sends array manifold data to the FPGA processing platform, including: the DSP board sends the array manifold data to its corresponding FPGA processing platform through the SRIO interface; wherein the complex weighted coefficients generated by each DSP board are arranged in the same way and do not need to be rearranged.

[0082] Specifically, the DSP processing platform generates array manifold data based on radar parameters, antenna array dimensions, and beam pointing parameters sent from the CPU processing platform. This array manifold data contains complex weighting coefficients for m*n elements of L beams, and its data stream is arranged according to the weighting coefficients of individual channels of L*m beams, such as... Figure 3 As shown, this represents the 1 to L*m complex weighting coefficients for channel 1, the 1 to L*m complex weighting coefficients for channel 2, ..., the 1 to L*m complex weighting coefficients for channel n, with each channel having L*m complex weighting coefficients. A one-to-one correspondence is established between beams 1 to L*m and array elements 1 to m. The 1 to L data points from each channel in the array's flow data are used as the complex weighting coefficients for array element 1, the L+1 to L*2 data points from each channel are used as the complex weighting coefficients for array element 2, and so on, resulting in L complex weighting coefficients for each array element. The complex weighting coefficients generated by each DSP processing platform have the same arrangement and do not require rearrangement; they can be directly sent to their respective FPGA processing platforms via the SRIO interface.

[0083] In step S13, each FPGA processing platform rearranges the complex weighting coefficients according to the configured number of channels and the number of array elements in the subarray. The array data and weighting coefficients in each channel are processed through a cascaded architecture of ternary multipliers to obtain the single-channel beamforming result. Then, all single-channel beamforming results are aligned and summed to obtain the beamforming data of a single FPGA reconstruction module. The beamforming data is then sent to the FPGA integration platform.

[0084] For example, the method further includes: the FPGA processing platform receiving beamforming data sent by the DSP board through the SRIO interface; and the FPGA processing platform receiving AD echo data through the GT interface and writing it into each channel buffer module respectively.

[0085] Specifically, the FPGA processing platform receives the complex weighted coefficient data stream sent by the DSP via SRIO, and receives the AD echo data via GT, such as... Figure 4As shown. For the complex weighted coefficient data stream, ping-pong operation is used for read and write processing. The coefficients of each channel are written to the respective channel ping-pong buffer module through a selector. The write addresses of the n channels are consistent. The ping-pong buffer module corresponding to each channel is implemented by configuring M dual-port RAMs. The first dual-port RAM buffers the complex weighted coefficients of beams 1 to L of array element 1, the second dual-port RAM buffers the complex weighted coefficients of beams 1 to L of array element 2, ..., the m-th dual-port RAM buffers the complex weighted coefficients of beams 1 to L of array element M, ensuring that the complex weighted coefficients of all beams of each array element are arranged sequentially in the dual-port RAMs, and the write addresses of the M dual-port RAMs are exactly the same. For AD echo data, the data of each channel is also written to the respective channel buffer module, and then, under the control of the read control module, as shown... Figure 5 As shown, on one hand, the array data is read from the cache module until K data points are read from each array element. On the other hand, the complex weighting coefficients of the L beams corresponding to the M array elements in the M dual-port RAMs are read out cyclically. To ensure that the weighting coefficients and data corresponding to each array element in each channel are aligned, the read addresses of each RAM are consistent, and the read enable of each RAM differs by one clock cycle. Figure 6 As shown, to conserve multiplier resources, the beamforming processing unit employs a classic 3-multiplier architecture. One data point from a single array element is expanded to L multipliers, corresponding to the complex weighting coefficients of L beams. This process is pipelined sequentially until the output of the final stage serves as the beamforming result for a single channel. The beamforming results from each channel are processed using the same readout control module, ensuring consistency. The final digital beamforming result is obtained by summing the outputs from all channels. Each FPGA board follows the same processing method.

[0086] In step S14, the FPGA integration platform aligns the beamforming data from each FPGA processing platform, and then accumulates the aligned beamforming data to obtain the integrated beamforming result.

[0087] For example, an FPGA integration platform includes at least one FPGA integration platform.

[0088] The method further includes: when the receiving bandwidth of a single FPGA integration platform is less than the sum of the transmitting bandwidths of J FPGA processing platforms, calling multiple FPGA integration platforms and cascading them, so that the receiving bandwidth of the cascaded multiple FPGA integration platforms is greater than the sum of the transmitting bandwidths of J FPGA processing platforms.

[0089] Specifically, the receiving bandwidth of the FPGA integration platform needs to be greater than the sum of the transmitting bandwidths of J FPGA processing platforms. When the receiving bandwidth of one FPGA integration platform cannot meet the requirements, multiple FPGA integration platforms can be cascaded for processing, ultimately outputting a single beam to form the integrated result. For example... Figure 7As shown, the transmission delays between the beamforming results of each array are not consistent. Therefore, it is necessary to align the output results of each array in the FPGA integration platform before performing inter-array summation. The data from each array is buffered, and an alignment read pulse is generated based on the number of valid data outputs from each array. The data from each array is read from the buffer, and the final integrated digital beamforming result is obtained by summing the output results of all arrays.

[0090] For example, the method further includes: the CPU obtaining the reconfiguration array information from the host computer, the reconfiguration array information including at least one of the following: number of reconfigurations, number of channels, number of array elements, number of beams, and data rate; the CPU calling the PCIE API function to send the reconfiguration array information to the DSP board and FPGA processing platform.

[0091] Specifically, when the array is expanded and reconstructed—that is, when parameters such as the number of array elements, the number of channels, the number of wavenumbers, the array data rate, and the number of array data elements change—users can customize the configuration through the host computer and generate manifold data, which is then sent to the CPU processing platform. The CPU reconstructs the array based on the array parameters and sends the reconstructed array information to multiple DSP+FPGA processing platforms via PCIe-related API functions. The FPGA integration module then accumulates the digital beamforming results of each array to complete the beamforming of the new array. When selecting certain subarrays from the current array as the new array, the software configuration unit only needs to set the weighting coefficients in the array manifolds corresponding to the unused subarrays to zero. When adding subarrays to expand the array, adding multiple DSP+FPGA processing platforms is sufficient to meet the requirements.

[0092] The method provided in the embodiments of the present invention is referred to Figure 2As shown, the CPU receives the reconstructed unit manifold data sent by the host computer software configuration module via UDP API functions. It rearranges the reconstructed unit manifold data according to the number of reconstructions and sends the reconstructed data packets to the corresponding DSP board via PCIE API functions based on the address information contained in each reconstructed data packet. Each DSP board generates weighting coefficients based on the number of array elements and beams, and sends them to the FPGA processing platform for beamforming algorithm implementation. Simultaneously, each DSP board can perform transmit and receive calibration on the beamforming results. Each FPGA processing platform rearranges the weighting coefficients according to the configured number of channels and the number of array elements in the subarray. The array data in each channel and the weighting coefficients are processed through a cascaded architecture of three multipliers to obtain the single-channel beamforming result. After aligning all single-channel data, they are summed to obtain the beamforming result of a single FPGA processing platform. The operating frequency of the FPGA processing platform must be greater than the product of the number of beams and the single-array data rate. Beamforming data from each FPGA processing platform is sent to the FPGA integration platform for effective judgment and alignment pulses are generated. The aligned FPGA reconfiguration modules are then summed to obtain the final integrated beamforming result. Repeating the above process completes the beamforming processing of the reconfigurable extended array.

[0093] The method provided by this invention addresses the issue that existing technologies, when constructing scalable arrays in a modular fashion, require constant maintenance and debugging of the array element processing platform when parameters such as array size, number of array elements, number of beams, and data rate change. This results in low development efficiency and poor software-hardware coupling. In contrast, this invention configures parameters such as the data flow, number of beams, and data rate of the reconfigurable array on a host computer. The CPU then rapidly distributes these data parameters via API functions, and multiple DSP+FPGA boards complete the digital beamforming of any reconfigurable array.

[0094] Compared with the prior art, the present invention has the following advantages:

[0095] 1) Data and parameters are distributed through software configuration via API functions, resulting in high development efficiency.

[0096] 2) The system architecture of CPU + multiple DSP + FPGA board can realize arbitrary array size and beam function according to parameters, and has strong reconfigurability.

[0097] 3) Each FPGA hardware internally achieves loose coupling between data rate and number of beams, while externally and in software, it achieves decoupling, resulting in strong versatility and applicability.

[0098] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0099] It should be noted that although several modules or units of the device for performing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0100] Figure 8 A schematic diagram of an electronic device suitable for implementing embodiments of the method of the present invention is shown.

[0101] It should be noted that, Figure 8 The electronic device 1000 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0102] like Figure 8 As shown, the electronic device 1000 includes a Central Processing Unit (CPU) 1001, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 1002 or programs loaded from Storage Unit 1008 into Random Access Memory (RAM) 1003. The RAM 1003 also stores various programs and data required for system operation. The CPU 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An Input / Output (I / O) interface 1005 is also connected to the bus 1004.

[0103] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage section 1008 as needed.

[0104] In particular, according to embodiments of the present invention, the processes described below with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a storage medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1009, and / or installed from removable medium 1011. When the computer program is executed by central processing unit (CPU) 1001, it performs various functions defined in the system of this application.

[0105] It should be noted that the storage medium shown in the embodiments of the present invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, wherein computer-readable program code is carried. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0107] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0108] It should be noted that, as another aspect, this application also provides a storage medium, which may be included in an electronic device or may exist independently without being assembled into the electronic device. The aforementioned storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the methods described in the following embodiments. For example, the electronic device may perform... Figure 1 The steps of the method shown.

[0109] In one embodiment, this application provides a computer program product including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0110] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0111] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0112] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A reconfigurable digital beamforming method based on API functions, characterized in that, The method includes: The CPU receives the reconstructed unit manifold data sent by the host computer and parses it. This includes: the CPU pre-binding with the host computer's IP address and port number using the API function corresponding to the User Datagram Protocol (UDP) and creating a data receiving queue; upon receiving the current UDP packet, writing it into the data receiving queue; performing frame header verification on the current UDP packet; if verification fails, calling the UDP API function to report the verification error to the host computer; if verification succeeds, parsing the reconstructed data; using the data parsing results to rearrange the data and obtain J array information; and sending the J array information to the corresponding DSP boards. The reconstructed unit manifold data includes: the total number of antenna array elements P, the number of antenna array channels processed by a single FPGA n, and the number of array elements within a single array channel processed by a single FPGA m, as well as address information; the array information includes: radar parameter information, array element coordinate information, and beam angle information. Each DSP board generates array manifold data based on the array surface information and sends the array manifold data to the FPGA processing platform. The array manifold data contains complex weighting coefficients of m*n array elements of L beams, and its data stream is arranged based on the complex weighting coefficients of a single channel of L*m beams. Each FPGA processing platform rearranges the complex weighting coefficients according to the configured number of channels and the number of array elements in the subarray. The array data and weighting coefficients in each channel are processed through a cascaded architecture of ternary multipliers to obtain the single-channel beamforming result. Then, all single-channel beamforming results are aligned and summed to obtain the beamforming data of a single FPGA reconstruction module. The beamforming data is then sent to the FPGA integration platform. The FPGA integration platform aligns the beamforming data from each FPGA processing platform, and then accumulates the aligned beamforming data to obtain the integrated beamforming result. The CPU obtains the reconfiguration array information from the host computer. The reconfiguration array information includes at least one of the following: number of reconfigurations, number of channels, number of array elements, number of beams, and data rate. The CPU calls the PCIE API function to send the reconfiguration array information to the DSP board and FPGA processing platform.

2. The method according to claim 1, characterized in that, Before sending the J array information to the corresponding DSP boards, the method further includes: During system initialization, the CPU enumerates the DSP board and writes the DSP board information into the system. When the device ID of the DSP board matches the PCI driver ID, the CPU loads the driver and configures the device node name for each different DSP board.

3. The method according to claim 1, characterized in that, The method further includes: During system initialization, the CPU receives the array element coordinate information sent by the host computer.

4. The method according to claim 1, characterized in that, The DSP board generates array manifold data based on the array surface information, including: The DSP board determines the complex weighting coefficients based on the number of array elements and the number of beams; the data stream of the complex weighting coefficients is read and written using ping-pong operations.

5. The method according to claim 1, characterized in that, The DSP board sends array manifold data to the FPGA processing platform, including: The DSP boards send the array manifold data to their respective FPGA processing platforms via the SRIO interface; the complex weighted coefficients generated by each DSP board are arranged in the same way and do not require rearrangement.

6. The method according to claim 1, characterized in that, The method further includes: When the receiving bandwidth of a single FPGA integration platform is less than the sum of the transmitting bandwidths of J FPGA processing platforms, multiple FPGA integration platforms are invoked and cascaded to ensure that the receiving bandwidth of the cascaded multiple FPGA integration platforms is greater than the sum of the transmitting bandwidths of J FPGA processing platforms.

7. The method according to claim 1, characterized in that, The method further includes: The FPGA processing platform receives beamforming data sent by the DSP board via the SRIO interface; and The FPGA processing platform receives AD echo data through the GT interface and writes it into the buffer modules of each channel.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the reconfigurable digital beamforming method based on API functions as described in any one of claims 1 to 7.

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