A high-speed ADC test efficiency optimization method based on ATE external SoC

Abstract

The application provides a high-speed ADC test efficiency optimization method based on an ATE external SoC, and has the characteristics that it comprises the following steps: step 1, starting a test system, and issuing basic parameters by an ATE; step 2, a signal source applies a preset excitation signal to a to-be-tested ADC, and the ADC outputs a high-speed digital sampling data stream; step 3, the ADC transmits the sampling data stream to a PL end of a ZYNQ SoC; step 4, the PL end completes system clock domain conversion; step 5, a PS end completes ADC static and dynamic parameter calculation based on cached data; and step 9, after the test is completed, an ATE issues a test termination instruction to complete the ADC parameter test. The application solves the core contradiction between high-speed collection and low-speed calculation of the ATE external FPGA architecture from the architecture level, greatly improves the adaptive flexibility and reusability of the test scheme, and creates a reliability guarantee system integrating self-diagnosis and full-process automatic control.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a method for optimizing the testing efficiency of high-speed ADC based on an ATE external SoC. Background Technology

[0002] In high-end electronics fields such as communications, radar, and aerospace, high-speed analog-to-digital converters (ADCs) are core components for converting analog signals to digital signals. The accuracy and efficiency of their performance parameter testing directly impact product mass production yield and delivery cycle. The industry's demand for comprehensive, timely mass production testing of high-speed ADCs is increasingly urgent. To address this demand, the ATE (Automatic Test Equipment) external FPGA testing method has emerged. This method involves attaching an FPGA to the ADC test interface board, working in conjunction with the ATE host to complete the testing tasks. It leverages the FPGA's high-speed data stream processing capabilities to compensate for the shortcomings of traditional ATEs in high-speed signal reception, achieving comprehensive parameter testing coverage.

[0003] However, in the practical application of the ATE external FPGA full-parameter testing architecture, the existing parameter calculation scheme still has certain bottlenecks. Although the FPGA can complete the reception and preliminary preprocessing of high-speed sampling data, the existing scheme still relies on the ATE host to undertake all parameter calculation tasks. Limited by the ATE serial data processing architecture, it has two major drawbacks when facing the massive preprocessed data transmitted by the FPGA: First, the computational efficiency is low. The ATE needs to complete the serial calculation of static and dynamic parameters one by one. In particular, the FFT frequency domain analysis and complex harmonic extraction of dynamic parameters are time-consuming, resulting in excessively long calculation time for the full parameters of a single ADC, which is difficult to match the high efficiency requirements of mass production testing. Second, the data transmission and calculation are not well connected. The low-speed data receiving interface of the ATE is not compatible with the high-speed data output capability of the FPGA, which is prone to data congestion. Moreover, in the serial calculation mode, it is necessary to wait for the previous parameter calculation to be completed before the next parameter processing can start, which further aggravates the overall test delay. If FPGA is used to calculate static and dynamic parameters, although FPGA has high-speed parallel processing capabilities and can complete the reception and preliminary preprocessing of high-speed sampled data, FPGA is based on hardware logic programming and lacks the software scheduling capabilities of general-purpose processors. It does not support the flexible development, debugging and iteration of complex algorithms, and it is also difficult to realize intelligent monitoring of system status and automated handling of anomalies.

[0004] In summary, existing technologies have not yet proposed a parameter calculation scheme that can adapt to ATE (Automatic Test Equipment) and balance high-speed hardware processing with flexible software computing. There is an urgent need to build a heterogeneous collaborative computing architecture that can reasonably decompose the parameter calculation task from ATE, rely on dedicated processing chips to complete high-speed data processing and efficient parameter calculation, and at the same time realize high-speed data interaction and full-process control with ATE. This architecture can solve the efficiency problem of high-speed ADC full parameter testing from the architectural level and ensure the dual requirements of accuracy and timeliness for mass production testing. Summary of the Invention

[0005] To address the issues of low data transmission efficiency and insufficient computational architecture flexibility in traditional ADC parameter testing systems, this invention proposes a high-speed ADC testing efficiency optimization method based on an external ATE SoC, characterized by the following steps: Step 1: Start the test system and have the ATE issue basic parameters; Step 2: The signal source applies a preset excitation signal to the ADC under test, and the ADC outputs a high-speed digital sampling data stream; Step 3: The ADC transmits the sampled data stream to the PL terminal of the ZYNQ SoC via the JESD204B protocol. The PL terminal performs preprocessing operations on the received data. Step 4: The PL terminal completes the conversion from the ADC sampling clock domain to the ZYNQ SoC system clock domain; Step 5: The data processed across clock domains is transmitted to the PS end via the AXI bus, where the DDR cache module performs high-speed data caching; the ARM core on the PS end runs a Linux system and calculates the static and dynamic parameters of the ADC based on the cached data. Step 6: After the PS terminal completes the full-process status monitoring of the test, it retrieves the calculation results from the parameter calculation module and automatically compares and verifies them with the standard parameters in the ADC datasheet. If the result deviation exceeds the normal threshold, the system automatically triggers a retest process and returns to Step 2 to perform a new round of sampling and calculation. If the result deviation is within the normal threshold range, the valid calculation result is directly output. Step 7: The PS side of the ZYNQ SoC transmits the effective calculation results to the ATE via Gigabit Ethernet; Step 8: The ATE receives Ethernet data, completes CRC verification, frame header parsing, and extracts ADC model information, parameter type, and test results. At the same time, it displays the parsed test results comprehensively for testers to interpret. Step 9: After the test is completed, ATE issues a test termination command to complete this ADC parameter test.

[0006] The core innovations of this invention are mainly reflected in three aspects: First, it constructs a new integrated ADC parameter calculation architecture based on the ZYNQ SoC's PL+PS heterogeneous architecture. This architecture solves the core contradiction of high-speed acquisition and low-speed calculation in ATE external FPGA architecture, as well as the technical pain points of low efficiency in serial calculation and poor data transmission and instruction interaction. Second, relying on the hardware-software co-development characteristics of ZYNQ SoC, it significantly improves the adaptability and reusability of the test scheme. For the hardware adaptation requirements of different ADC models, the hardware logic of the PL side can be quickly reconstructed through the IP core, while the software calculation program can be flexibly modified based on the PS side ARM core. The hardware and software adjustments are independent of each other and easy to operate, without the need for overall system reconstruction, which greatly reduces development costs and shortens the product adaptation cycle. At the same time, this architecture is not limited to ADC parameter testing. Furthermore, by adapting hardware interface modules to different testing scenarios and optimizing software algorithms, its application can be expanded to specialized testing areas for other types of chips such as DACs, sensors, and RF chips. Thirdly, it has created a reliability assurance system that integrates self-diagnosis and full-process automated management and control. The self-diagnosis module is integrated at the PS end to achieve dual protection of full monitoring of system operation status and automatic verification of calculation results. At the same time, the ATE completes the fully automated management and visualization of the test from command issuance, parameter calculation to result archiving, making test data traceable and fundamentally improving the automation level and fault tolerance of the test process. Attached Figure Description

[0007] Figure 1 This is a hardware structure diagram of the data transmission link; Figure 2 This is a flowchart of the data transmission processing. Detailed Implementation

[0008] The present invention will be further described below with reference to the accompanying drawings and embodiments: This invention presents a high-speed ADC parameter calculation architecture based on the ZYNQ series SoC. This architecture leverages the ZYNQ SoC's combination of hardware programmability and flexible software development, resulting in enhanced development environment adaptability, higher efficiency in algorithm debugging and iteration, and strong reusability. The architecture includes a PL-side hardware preprocessing and cross-clock domain processing module, a PS-side DDR cache and parameter calculation module, and a self-diagnostic module. Efficient interaction between the PL and PS sides is achieved via the AXI4 bus, and a data transmission and visualization closed loop is constructed using ATE (Automatic Equipment). This leverages the high-speed processing advantages of the PL-side hardware while utilizing the PS-side development environment for rapid algorithm debugging, iteration, and deployment, ultimately achieving high-speed processing, accurate calculation of ADC parameters, and real-time monitoring of system status.

[0009] The high-speed ADC testing efficiency optimization method based on ATE external SoC of the present invention adopts the following architecture: with ZYNQ SoC as the core, the PL end receives ADC sampling data through JESD204B protocol and completes preprocessing and cross-clock domain conversion, and then transmits the data to the PS end through AXI bus; the PS end is equipped with Linux system, and completes data caching and parameter calculation through DDR cache module and parameter calculation module, and realizes system operation monitoring and calculation result verification in combination with self-diagnosis module. Finally, the PS end transmits the calculation result to ATE through Gigabit Ethernet, and the ATE completes data result processing and visualization display.

[0010] The ADC is the object under test, which is directly connected to the ZYNQ SoC through the JESD204B high-speed serial interface. It converts the externally input analog excitation signal into a high-speed digital sampling data stream and outputs the data stream to the PL terminal, providing the original data basis for subsequent parameter calculations.

[0011] The ATE serves as the control center, data interaction core, and result visualization management unit for the entire high-speed ADC testing process within the architecture. It includes a data processing module and a visualization module, establishing a bidirectional communication link with the ZYNQ SoC via Gigabit Ethernet. This allows it to send test configuration, start / stop, and reset commands via Ethernet and receive execution status and anomaly feedback from the ZYNQ SoC. It also performs test data parsing, multi-dimensional result display, and full-data archiving. Furthermore, the ATE is developed based on a dedicated development environment, using a visualization module to visualize data results. It can visualize ADC static and dynamic parameters through numerical lists and supports convenient human-computer interaction, helping testers intuitively and efficiently interpret the status of various parameters.

[0012] The ZYNQ SoC is the core processing unit of this method, including the PL end and the PS end. It leverages the heterogeneous synergy between the high-speed hardware processing of the PL end and the flexible software scheduling of the PS end to build an integrated hardware platform for ADC data reception, processing, calculation and transmission.

[0013] The ZYNQ SoC includes a JESD204B interface module, a data acquisition preprocessing module, a cross-clock domain processing module, a DDR cache module, a parameter calculation module, and a self-diagnostic module. The JESD204B interface module is the communication interface unit between the ZYNQ SoC and the ADC. Its function is to interface with the high-speed serial data stream output by the ADC, perform serial-to-parallel conversion, frame synchronization calibration, and data bit width matching, ensuring that the data output by the ADC can be stably input into the internal modules of the ZYNQ SoC.

[0014] The data acquisition preprocessing module is deployed at the PL end of the ZYNQ SoC to perform hardware framing of the ADC sampling data, providing a structured and reliable data stream for subsequent cross-clock domain transmission.

[0015] The cross-clock domain processing module is deployed on the PL terminal of the ZYNQ SoC to realize the conversion between the ADC sampling clock domain and the ZYNQ SoC system clock domain, eliminate the metastability risk caused by clock asynchrony, and ensure the integrity and stability of cross-domain data transmission.

[0016] The DDR cache module is deployed on the PS side of the ZYNQ SoC to cache ADC sampling data, providing continuous and stable data support for the parameter calculation module, and realizing temporary data storage and scheduling.

[0017] The parameter calculation module is deployed in the ARM core of the PS side of the ZYNQ SoC. Relying on the flexible software scheduling advantage of the heterogeneous architecture of the ZYNQ SoC, it completes the distributed parallel calculation of ADC static and dynamic parameters based on cached data. It is the core functional module of the system to realize accurate and efficient calculation of all ADC parameters, and forms a heterogeneous collaboration with the high-speed hardware processing of the PL side.

[0018] The self-diagnostic module is deployed on the PS side of the ZYNQ SoC, which can realize system operation status monitoring and automatic verification of calculation results. It can monitor the operation status of each module of the system and the integrity of the data transmission link in real time, and at the same time verify the validity of the parameter calculation process, promptly report various system anomalies, and improve the reliability and maintainability of the overall architecture.

[0019] The Gigabit Ethernet is the communication interface between the ZYNQ SoC and the ATE. It encapsulates the parameter calculation results output by the ZYNQ SoC into standard Ethernet frames, transmits the result data to the ATE through the Ethernet link, and simultaneously receives test configuration commands issued by the ATE.

[0020] In one embodiment of the high-speed ADC testing efficiency optimization method based on ATE external SoC of the present invention, the implementation process is as follows: Step 1: Start the test system and complete the initial configuration of ZYNQ SoC, ATE, signal source and ADC. The ATE will issue test parameters and calculate basic parameters such as thresholds to ensure that each module is in a ready state.

[0021] Step 2: The signal source applies a preset excitation signal to the ADC under test according to the initialization configuration; after receiving the excitation signal, the ADC completes the conversion from analog signal to digital signal and outputs a high-speed digital sampling data stream.

[0022] Step 3: The ADC transmits the sampled data stream to the PL terminal of the ZYNQ SoC via the JESD204B protocol. The data preprocessing module at the PL terminal performs preprocessing operations such as data rearrangement on the received data.

[0023] Step 4: The PL-side cross-clock domain processing module, i.e., the asynchronous FIFO, receives the pre-processed frame data stream and completes the conversion from the ADC sampling clock domain to the ZYNQ SoC system clock domain, eliminating metastability risks and ensuring stable data transmission.

[0024] Step 5: The data processed across clock domains is transmitted to the PS end via the AXI bus, and the DDR cache module completes high-speed caching of the data; the ARM core on the PS end runs a Linux system, calls the parameter calculation module program, and completes the calculation of the static and dynamic parameters of the ADC based on the cached data.

[0025] Step 6: The PS-side self-diagnostic module monitors the operating status of each module in the system, the integrity of the data transmission link, and the validity of the calculation process in real time. After completing the status monitoring of the entire test process, it retrieves the calculation results of the parameter calculation module and automatically compares and verifies them with the standard parameters in the ADC datasheet. If the result deviation exceeds the normal threshold, the system automatically triggers the retest process and returns to Step 2 to perform a new round of sampling and calculation. If the result deviation is within the normal threshold range, the valid calculation result is directly output.

[0026] Step 7: The PS (Power Supply) of the ZYNQ SoC encapsulates the valid calculation result into a standard Ethernet frame and performs CRC verification. The result data is then transmitted to the ATE (Automatic Equipment) via Gigabit Ethernet. If the verification results in Step 6 are all abnormal for three consecutive times, the PS encapsulates the abnormal data, device identifier, and system status information and transmits it to the ATE via Gigabit Ethernet. The ATE then issues an alarm and records and archives the abnormal information.

[0027] Step 8: The ATE data processing module receives Ethernet data, completes CRC verification, frame header parsing, and extracts ADC model information, parameter type, and test results. At the same time, the visualization module comprehensively displays the parsed test results for testers to interpret.

[0028] Step 9: After the test is completed, the ATE console module issues a test termination command, all modules stop working, and the ATE archives and stores the test data, calculation results, and system running status information in a standardized format, thus completing this ADC parameter test.

[0029] It should be noted that the above description is merely illustrative and explanatory of the present invention. Those skilled in the art should understand that any modifications and substitutions to the present invention fall within the scope of protection of the present invention.

Claims

1. A method for optimizing the testing efficiency of a high-speed ADC based on an ATE external SoC, characterized in that, It includes the following steps: Step 1: Start the test system and have the ATE issue basic parameters; Step 2: The signal source applies a preset excitation signal to the ADC under test, and the ADC outputs a high-speed digital sampling data stream; Step 3: The ADC transmits the sampled data stream to the PL terminal of the ZYNQ SoC via the JESD204B protocol. The PL terminal performs preprocessing operations on the received data. Step 4: The PL terminal completes the conversion from the ADC sampling clock domain to the ZYNQ SoC system clock domain; Step 5: The data processed across clock domains is transmitted to the PS terminal via the AXI bus, and the DDR cache module completes the high-speed caching of the data. The PS-side ARM core is equipped with a Linux system, which calculates the static and dynamic parameters of the ADC based on cached data; Step 6: After the PS terminal completes the full-process status monitoring of the test, it retrieves the calculation results from the parameter calculation module and automatically compares and verifies them with the standard parameters in the ADC datasheet. If the result deviation exceeds the normal threshold, the system automatically triggers a retest process and returns to Step 2 to perform a new round of sampling and calculation. If the result deviation is within the normal threshold range, the valid calculation result is directly output. Step 7: The PS side of the ZYNQ SoC transmits the effective calculation results to the ATE via Gigabit Ethernet; Step 8: The ATE receives Ethernet data, completes CRC verification, frame header parsing, and extracts ADC model information, parameter type, and test results. At the same time, it displays the parsed test results comprehensively for testers to interpret. Step 9: After the test is completed, ATE issues a test termination command to complete this ADC parameter test.

2. The method for optimizing high-speed ADC testing efficiency based on an ATE external SoC according to claim 1, characterized in that, The ADC is the object under test, which is directly connected to the ZYNQ SoC through the JESD204B high-speed serial interface. It converts the externally input analog excitation signal into a high-speed digital sampling data stream and outputs the data stream to the PL terminal, providing the original data basis for subsequent parameter calculations.

3. The method for optimizing high-speed ADC testing efficiency based on an external ATE SoC according to claim 1, characterized in that, The ATE includes a data processing module and a visualization module. It sends commands via gigabit Ethernet and receives the execution status and anomaly feedback from the ZYNQ SoC, completing the parsing of test data, multi-dimensional display of results, and archiving and storing of all information. At the same time, the ATE is developed based on a dedicated development environment and realizes the visualization of data results through the visualization module, completing the visualization display of ADC static and dynamic parameters, while supporting convenient human-computer interaction.

4. The method for optimizing high-speed ADC testing efficiency based on an external ATE SoC according to claim 1, characterized in that, The ZYNQ SoC is the core processing unit, including a PL end and a PS end. It leverages the heterogeneous synergy between the high-speed hardware processing of the PL end and the flexible software scheduling of the PS end to build an integrated hardware platform for ADC data reception, processing, calculation and transmission.

5. The method for optimizing high-speed ADC testing efficiency based on an external ATE SoC according to claim 1, characterized in that, The ZYNQ SoC includes a JESD204B interface module, a data acquisition preprocessing module, a cross-clock domain processing module, a DDR cache module, a parameter calculation module, and a self-diagnostic module.

6. The method for optimizing high-speed ADC testing efficiency based on an ATE external SoC according to claim 5, characterized in that, The JESD204B interface module is the communication interface unit between the ZYNQ SoC and the ADC. Its function is to interface with the high-speed serial data stream output by the ADC, complete serial-to-parallel conversion, frame synchronization calibration and data bit width matching, and ensure that the data output by the ADC can be stably input into the internal modules of the ZYNQ SoC.

7. The method for optimizing high-speed ADC testing efficiency based on an external ATE SoC according to claim 5, characterized in that, The data acquisition preprocessing module is deployed at the PL end of the ZYNQ SoC to perform hardware framing of the ADC sampling data, providing a structured and reliable data stream for subsequent cross-clock domain transmission; the cross-clock domain processing module is deployed at the PL end of the ZYNQ SoC to realize the conversion between the ADC sampling clock domain and the ZYNQ SoC system clock domain.

8. The method for optimizing high-speed ADC testing efficiency based on an ATE external SoC according to claim 5, characterized in that, The DDR cache module is deployed on the PS side of the ZYNQ SoC to cache ADC sampling data and realize temporary data storage and scheduling. The parameter calculation module is deployed in the ARM core of the PS side of the ZYNQ SoC. It completes the distributed parallel calculation of ADC static and dynamic parameters based on cached data, forming a heterogeneous collaboration with the high-speed hardware processing of the PL side.

9. The method for optimizing high-speed ADC testing efficiency based on an external ATE SoC according to claim 5, characterized in that, The self-diagnostic module is deployed on the PS side of the ZYNQ SoC to realize system operation status monitoring and automatic verification of calculation results. It monitors the operation status of each module of the system and the integrity of the data transmission link in real time, and verifies the validity of the parameter calculation process. It also promptly reports various system anomalies, thereby improving the reliability and maintainability of the overall architecture.

10. The method for optimizing high-speed ADC testing efficiency based on an ATE external SoC according to claim 1, characterized in that, The Gigabit Ethernet is the communication interface between the ZYNQ SoC and the ATE. It encapsulates the parameter calculation results output by the ZYNQ SoC into standard Ethernet frames, transmits the result data to the ATE through the Ethernet link, and simultaneously receives test configuration commands issued by the ATE.

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