High-performance parallel robot controller based on arm + fpga architecture

Abstract

The invention belongs to the technical field of parallel robot controllers, and discloses a high-performance parallel robot controller based on an arm + fpga architecture, through deep heterogeneous fusion of an ARM and an FPGA, the control period is shortened to be within 10 microseconds, the trajectory tracking error is controlled to be 0.1 mm or below, and the performance bottleneck of a traditional architecture in a high-speed scene is solved; the multi-core ARM undertakes complex tasks such as global trajectory planning and dynamics solution, and realizes parallel processing by means of an NEON instruction set; the FPGA fully releases the hardware parallel characteristic of the FPGA, real-time tasks such as multi-axis motion control and sensor data fusion are synchronously completed through a distributed logic unit, and a complex decision-real-time execution assembly line cooperation mode is formed. Inertial parameters and load changes of the mechanical arm are estimated in real time through an LSTM neural network, and feedforward compensation is carried out on interference such as mechanical vibration and load abrupt change in combination with an extended state observer achieved through FPGA hardware; the innovatively designed double closed-loop control architecture supports seamless switching between a force control mode and a position control mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of parallel robot controllers, and in particular relates to a high-performance parallel robot controller based on an ARM+FPGA architecture. Background Art

[0002] Parallel robots place stringent demands on the controller's real-time performance, computing efficiency, and environmental adaptability during high-speed and precise operations. However, the architectural design of traditional controllers has the following technical problems.

[0003] In the existing control architecture, the collaborative mode between processors and dedicated logic units is rigidified, and deep heterogeneous integration has not been achieved. In most solutions, general-purpose processors (such as ARM) are responsible for complex tasks such as dynamic solution and trajectory planning, while parallel computing units such as FPGA are only used as auxiliary interface extensions. Their hardware parallel characteristics are not fully activated, resulting in waste of computing resources and contradictions with real-time performance. When the movement speed of the robotic arm exceeds 1m / s, the serial calculation of a single processor can hardly support the microsecond control cycle, and the trajectory tracking delay increases significantly.

[0004] At the same time, the coordination between control and perception is insufficient, lacking a closed-loop optimization mechanism for dynamic response. Traditional solutions often involve serial processes for sensor data processing, control algorithm execution, and actuator driving, failing to leverage parallel computing to achieve a pipelined "perception-decision-control" approach. This results in delayed control parameter adjustments and significant degradation of trajectory accuracy under dynamic disturbances such as sudden load changes and mechanical vibration. Furthermore, the integration of energy efficiency and safety monitoring is low, relying heavily on single-dimensional state detection, making it difficult to adapt to complex operating conditions. Summary of the Invention

[0005] The purpose of the present invention is to provide a high-performance parallel robot controller based on ARM+FPGA architecture to solve the problems raised in the above background technology.

[0006] In order to achieve the above objectives, the present invention provides the following technical solution: a high-performance parallel robot controller based on ARM+FPGA architecture, the controller comprising: Multi-core ARM heterogeneous computing module: Using the Cortex-A72+M7 architecture, the A72 core runs the ROS system for scheduling and interaction, while the M7 core accelerates dynamic inverse solution through the NEON instruction set. It introduces DVFS technology to dynamically adjust power consumption and provide computing power support for the FPGA parallel control module, achieving basic computing power allocation for software and hardware collaboration. FPGA parallel control module: To match the Cortex-A72+M7 architecture, the FPGA parallel control module adopts a distributed design. The motion control submodule implements multi-channel control, and the sensor fusion submodule processes multi-source data in parallel. The reconfigurable logic unit supports online algorithm upgrades, inherits ARM computing power output, and improves the response speed of the underlying control. High-speed communication interface module: Based on the multi-core ARM heterogeneous computing module and the FPGA parallel control module, the high-speed communication interface module realizes high-speed data transmission between ARM and FPGA through the PCIe4.0 bare core. TSN Ethernet ensures the synchronization of multiple controllers, and the hardware firewall enhances security, establishing an efficient and secure channel for data exchange between modules. Dynamic trajectory planning module: Based on a stable communication environment, the dynamic trajectory planning module uses ARM to implement global path optimization, FPGA to complete interpolation through hardware pipeline, geometric constraint pre-calculation unit to avoid singular points, and connects data interaction with high-speed communication interface modules to improve the real-time and reliability of trajectory planning; Adaptive control algorithm module: Based on the planned trajectory, the adaptive control algorithm module uses an LSTM network to estimate inertial parameters and implements ESO vibration compensation through FPGA. The dual closed-loop architecture supports force control or position control switching, inherits the trajectory planning results, and optimizes control accuracy and adaptability. Multimodal safety monitoring module: To ensure the safety of the control process, the multimodal safety monitoring module adopts a three-level redundancy design, achieving rapid response at the hardware level, priority processing at the software level, and fault prediction at the cloud level, building a full-process safety protection system; Reconfigurable power management module: Based on the energy consumption requirements of each module, the reconfigurable power management module dynamically allocates power, recovers energy during braking, and coordinates all the aforementioned modules to improve system energy efficiency and stability through intelligent power supply regulation.

[0007] Preferably, the multi-core ARM heterogeneous computing module includes: (1) Architecture composition and core functions: With the Cortex-A72+M7 architecture as the core, the A72 core is equipped with the ROS real-time operating system, responsible for global task scheduling, human-computer interaction and cloud data interaction, and supports multi-language mixed programming to adapt to complex scenario requirements. The M7 core uses the NEON instruction set to parallelize the dynamic inverse solution calculation process, significantly improving computing efficiency; The inverse solution formula of dynamics: , Where: is the joint output torque (N·m); is the moment of inertia of the robotic arm (kg·m 2) ; is the joint angular acceleration (rad / s2) ; m is the equivalent mass of the robotic arm (kg); is the acceleration due to gravity (9.8m / s 2) ; is the distance from the center of mass to the joint (m); is the joint angle (rad); This formula is derived based on the Newton-Euler equation and accurately calculates the joint driving torque by decomposing the coupling relationship between the inertial force and gravity in the motion of the manipulator. The term describes the effect of inertial load on the torque, The term reflects the effect of gravity load. In the multi-core ARM heterogeneous computing module, the M7 core uses the NEON instruction set to parallelize the formula to meet the efficient computing requirements of the inverse dynamics solution. (2) Dynamic power consumption regulation and computing power support: Dynamic voltage and frequency adjustment technology is introduced to automatically adjust power consumption according to load changes, achieving energy efficiency optimization while ensuring computing power output. The output computing power resources provide solid support for subsequent FPGA parallel control modules, building a basic computing power framework for system software and hardware collaboration.

[0008] Preferably, the FPGA parallel control module includes: (1) Distributed control and data processing: To match the computing power output of multi-core ARM, a distributed computing architecture is adopted. The motion control submodule uses Verilog language to implement multi-channel PWM generation, encoder frequency multiplication and hardware-level PID control to ensure the precise response of the underlying actuator. The sensor fusion submodule integrates multiple interfaces and processes multi-source sensor data such as force, torque or laser ranging in parallel; Hardware-level PID control formula: , Where: For the Output of a control cycle; is the proportionality coefficient; is the integration coefficient; is the differential coefficient; for The position error of the cycle; is the control period (μs); This formula originates from the PID control algorithm in classical control theory and is adapted to digital control systems through discretization. In the formula, the proportional term ( ) fast response error, integral term ( ) to eliminate the steady-state deviation, the differential term ( ) To suppress overshoot, in the FPGA parallel control module, this formula is solidified into hardware logic using the Verilog language, and combined with pipeline technology to achieve real-time control, ensuring the precise response of the underlying actuator; (2) Reconfigurable design and control enhancement: Design a reconfigurable logic unit to support online upgrades of control algorithms without shutting down for burning, effectively improving system adaptability, taking over the computing power output of the ARM module, and converting upper-level instructions into low-level control signals, thereby enhancing the system's real-time control capabilities.

[0009] Preferably, the high-speed communication interface module includes: (1) High-speed data transmission and synchronization guarantee: Based on the collaborative requirements of the aforementioned computing and control modules, a high-speed data channel between ARM and FPGA is built through the PCIe4.0 bare core to achieve low-latency transmission of large amounts of data. At the same time, TSN Ethernet technology is used to ensure nanosecond-level synchronization between multiple controllers according to the IEEE802.1AS standard to meet the requirements of multi-axis collaborative control; (2) Security protection and data interaction center: integrated hardware firewall, real-time interception of abnormal data in the industrial network, improving the security of system communication, and building an efficient and stable channel for computing power allocation, control command transmission and sensor data feedback.

[0010] Preferably, the dynamic trajectory planning module includes: (1) Collaborative planning and global optimization: Based on the stable data interaction environment provided by the high-speed communication module, the ARM and FPGA collaborative working mode is adopted. The ARM side performs global path optimization based on the Chomp algorithm, which can realize dynamic obstacle avoidance and task priority scheduling according to real-time working conditions, ensuring the global optimality of path planning; (2) Hardware acceleration and singularity avoidance: The FPGA side performs quintic polynomial interpolation through hardware pipeline technology to improve trajectory smoothness. The geometric constraint pre-calculation unit verifies the kinematic feasibility in advance in the FPGA, effectively avoiding the risk of singularities in real-time calculations. The planning results are transmitted through the communication module to provide an accurate trajectory benchmark for the adaptive control algorithm module. Quintic polynomial interpolation formula: , Where: is the joint angle trajectory (rad); are the polynomial coefficients; is the time variable (s); Coefficient solution conditions: , This formula, based on polynomial interpolation theory, solves for coefficients by setting six boundary conditions (start and end point position, velocity, and acceleration), ensuring the continuity of the trajectory and its derivatives, thereby achieving smooth motion. In the dynamic trajectory planning module, the FPGA performs the interpolation calculations of this formula through hardware pipelining technology, and in conjunction with the global path optimization results on the ARM side, provides continuous and stable motion instructions for the robotic arm.

[0011] Preferably, the adaptive control algorithm module includes: (1) Parameter identification and data support: Based on the trajectory benchmark output by the dynamic trajectory planning module, the online identification submodule integrates machine learning and traditional control theory. The LSTM neural network is used to estimate the inertia parameters and load changes of the manipulator in real time, providing data support for control strategy adjustment. (2) Interference compensation and mode switching: The interference compensation submodule implements an extended state observer through FPGA hardware to perform feedforward compensation for periodic interference such as mechanical vibration. The dual closed-loop control architecture supports seamless switching between force control and position control modes. The control method can be flexibly adjusted according to task requirements, taking over trajectory planning results and further improving control accuracy.

[0012] Preferably, the multimodal security monitoring module includes: (1) Three-level redundancy design and hardware protection: To ensure the stable operation of the adaptive control process, a three-level redundancy design is adopted. The hardware level uses an independent FPGA to monitor overcurrent, overtemperature and other abnormalities in real time, with a response time of microseconds. The output can be directly cut off to avoid equipment damage. The software level is based on the ROS state machine and prioritizes abnormal events through a real-time queue. (2) Cloud-based early warning and full-process monitoring: The cloud-level analyzes the vibration spectrum through edge computing nodes, uses the SVM algorithm to predict faults, monitors the control process in all time periods and multiple dimensions, and builds a full-process security protection system from hardware to the cloud.

[0013] Preferably, the reconfigurable power management module includes: (1) Dynamic power allocation and power supply guarantee: In view of the energy consumption characteristics of all the above modules, a bidirectional DC-DC converter and a supercapacitor energy storage unit are integrated. The dynamic power allocation function can adjust the power supply priority according to the real-time load of each module, ensuring stable power supply to key modules during peak computing power periods; (2) Energy recovery and system closed-loop optimization: During braking, FPGA controls IGBT to achieve energy recovery and store it in supercapacitors, improving system energy efficiency. It coordinates the operating status of all modules and optimizes overall energy consumption and stability through intelligent power supply regulation.

[0014] The beneficial effects of the present invention are as follows: 1. The present invention shortens the control cycle to less than 10μs and controls the trajectory tracking error below 0.1mm through the deep heterogeneous fusion of ARM and FPGA, solving the performance bottleneck of traditional architecture in high-speed scenarios. By reconstructing the deep heterogeneous fusion architecture of ARM and FPGA, the problem of unbalanced computing resource allocation in traditional controllers is completely solved. Multi-core ARM undertakes complex tasks such as global trajectory planning and dynamics solution, and uses the NEON instruction set to achieve parallel processing; FPGA fully unleashes its hardware parallel characteristics and synchronously completes real-time tasks such as multi-axis motion control and sensor data fusion through distributed logic units, forming a "complex decision-making-real-time execution" pipeline collaboration mode. This architecture breaks the shackles of traditional serial computing, avoids the problem of lengthened control cycle due to excessive load on a single processor, ensures immediate response to control instructions in high-speed motion scenarios, and significantly improves the real-time processing efficiency of the system.

[0015] 2. This invention builds a closed-loop adaptive "perception-decision-compensation" system. Using an LSTM neural network to estimate the manipulator's inertia parameters and load changes in real time, combined with an extended state observer implemented in FPGA hardware, it provides feedforward compensation for disturbances such as mechanical vibration and sudden load changes. The innovative dual-closed-loop control architecture supports seamless switching between force and position control modes, dynamically adjusting the control strategy based on the operating conditions. This mechanism overcomes the limitations of traditional fixed-parameter control, ensuring stable trajectory accuracy even under complex operating conditions and effectively improving the system's adaptability to dynamic environments.

[0016] 3. The present invention solves the problems of insufficient reliability and low energy efficiency of traditional controllers through multi-dimensional optimization. The multimodal safety monitoring module adopts a three-level redundancy design with hardware-level rapid response, software-level priority processing, and cloud-level fault prediction, covering the entire process of safety protection from bottom-level execution to global monitoring; the reconfigurable power management module uses dynamic power distribution and braking energy recovery mechanisms to adjust the power supply strategy in real time according to the load of each module to reduce energy waste. This design not only improves the system's risk resistance under extreme working conditions, but also extends the continuous working time through energy efficiency optimization, enabling it to stably adapt to various high-end application scenarios such as precision manufacturing and flexible assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a flow chart of the high-performance parallel robot controller based on the ARM+FPGA architecture of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, an embodiment of the present invention provides a high-performance parallel robot controller based on an ARM+FPGA architecture, the controller comprising: Multi-core ARM heterogeneous computing module: Using the Cortex-A72+M7 architecture, the A72 core runs the ROS system for scheduling and interaction, while the M7 core accelerates dynamic inverse solution through the NEON instruction set. It introduces DVFS technology to dynamically adjust power consumption and provide computing power support for the FPGA parallel control module, achieving basic computing power allocation for software and hardware collaboration. FPGA parallel control module: To match the Cortex-A72+M7 architecture, the FPGA parallel control module adopts a distributed design. The motion control submodule implements multi-channel control, and the sensor fusion submodule processes multi-source data in parallel. The reconfigurable logic unit supports online algorithm upgrades, inherits ARM computing power output, and improves the response speed of the underlying control. High-speed communication interface module: Based on the multi-core ARM heterogeneous computing module and the FPGA parallel control module, the high-speed communication interface module realizes high-speed data transmission between ARM and FPGA through the PCIe4.0 bare core. TSN Ethernet ensures the synchronization of multiple controllers, and the hardware firewall enhances security, establishing an efficient and secure channel for data exchange between modules. Dynamic trajectory planning module: Based on a stable communication environment, the dynamic trajectory planning module uses ARM to implement global path optimization, FPGA to complete interpolation through hardware pipeline, geometric constraint pre-calculation unit to avoid singular points, and connects data interaction with high-speed communication interface modules to improve the real-time and reliability of trajectory planning; Adaptive control algorithm module: Based on the planned trajectory, the adaptive control algorithm module uses an LSTM network to estimate inertial parameters and implements ESO vibration compensation through FPGA. The dual closed-loop architecture supports force control or position control switching, inherits the trajectory planning results, and optimizes control accuracy and adaptability. Multimodal safety monitoring module: To ensure the safety of the control process, the multimodal safety monitoring module adopts a three-level redundancy design, achieving rapid response at the hardware level, priority processing at the software level, and fault prediction at the cloud level, building a full-process safety protection system; Reconfigurable power management module: Based on the energy consumption requirements of each module, the reconfigurable power management module dynamically allocates power, recovers energy during braking, and coordinates all the aforementioned modules to improve system energy efficiency and stability through intelligent power supply regulation.

[0020] Among them, the multi-core ARM heterogeneous computing module includes: (1) Architecture composition and core functions: With the Cortex-A72+M7 architecture as the core, the A72 core is equipped with the ROS real-time operating system, responsible for global task scheduling, human-computer interaction and cloud data interaction, and supports multi-language mixed programming to adapt to complex scenario requirements. The M7 core uses the NEON instruction set to parallelize the dynamic inverse solution calculation process, significantly improving computing efficiency; The inverse solution formula of dynamics: , Where: is the joint output torque (N·m); is the moment of inertia of the robotic arm (kg·m 2) ; is the joint angular acceleration (rad / s 2) ; m is the equivalent mass of the robotic arm (kg); is the acceleration due to gravity (9.8m / s 2) ; is the distance from the center of mass to the joint (m); is the joint angle (rad); This formula is derived based on the Newton-Euler equation and accurately calculates the joint driving torque by decomposing the coupling relationship between the inertial force and gravity in the motion of the manipulator. The term describes the effect of inertial load on the torque, The term reflects the effect of gravity load. In the multi-core ARM heterogeneous computing module, the M7 core uses the NEON instruction set to parallelize the formula to meet the efficient computing requirements of the inverse dynamics solution. (2) Dynamic power consumption adjustment and computing power support: Dynamic voltage and frequency adjustment technology is introduced to automatically adjust power consumption according to load changes, achieving energy efficiency optimization while ensuring computing power output. The output computing power resources provide solid support for subsequent FPGA parallel control modules, building a basic computing power framework for system software and hardware collaboration; The A72 core and the M7 core exchange data through internal shared memory (512KB capacity), and the interaction cycle is consistent with the FPGA control cycle (10μs / time). When the M7 core completes the dynamic inverse solution calculation, it notifies the A72 core through an interrupt signal (GPIO pin PA0). The A72 core packages the results and transmits them to the FPGA parallel control module via PCIe4.0 to ensure that the computing power output matches the timing of the underlying control.

[0021] Real-time kernel configuration: Use the Linux kernel with the RT_PREEMPT 5.4.0-rt1 real-time patch. When compiling the kernel, enable the CONFIG_PREEMPT_RT_FULL option, and configure the interrupt response priority as "FPGA control instruction interrupt > sensor data interrupt > cloud interaction interrupt"; Communication mechanism between ROS and the real-time kernel: The A72 core runs ROS Noetic and interacts with the real-time kernel through the SharedMemoryTransport (shared memory transport) plugin of roscpp. The configuration parameters are "shared memory block size 1MB, data frame format is sensor_msgs / JointState + custom control instruction frame, communication frequency 100kHz"; Device tree configuration fragment: Supplement the key peripheral device tree nodes of the ARM chip (such as NXP i.MX8QM). The example is as follows: / *Device tree fragment: PCIe4.0 interface configuration between ARM and FPGA* / &pcie0{ status="okay"; pcie@0,0{ reg=<0x00000000 0x0 0x0 0x0 0x0>; device_type="pci"; max-link-speed=<4>; / *PCIe4.0* / [[ID=%20]]ranges=<0x81000000 0x0 0x10000000 0x0 0x10000000 0x0 0x<1000000>; %20 }; }; / *GPIO interrupt configuration (PA0 pin is used for M7 - A72 synchronization)* / &gpio1{ gpio-line-names="M7_A72_INT",...; interrupts=<0 IRQ_TYPE_EDGE_RISING>; / *PA0 rising edge interrupt* / }; Measured data of end-to-end delay, bandwidth, and jitter: Test environment: The hardware platform is "NXP i.MX8QM + Xilinx XC7K325T", and the test tools are lttng (delay analysis) and iperf3 (bandwidth test):

[0022] Among them, the FPGA parallel control module includes: (1) Distributed control and data processing: To match the computing power output of multi-core ARM, a distributed computing architecture is adopted. The motion control submodule uses Verilog language to implement multi-channel PWM generation, encoder frequency multiplication and hardware-level PID control to ensure the precise response of the underlying actuator. The sensor fusion submodule integrates multiple interfaces and processes multi-source sensor data such as force, torque or laser ranging in parallel; Hardware-level PID control formula: , Where: For the Output of a control cycle; is the proportionality coefficient; is the integration coefficient; is the differential coefficient; For the Position error of one cycle; is the control period (μs);

[0023] This formula originates from the PID control algorithm in classical control theory and is adapted to digital control systems through discretization. In the formula, the proportional term ( ) fast response error, integral term ( ) to eliminate the steady-state deviation, the differential term ( ) To suppress overshoot, in the FPGA parallel control module, this formula is solidified into hardware logic using the Verilog language, and combined with pipeline technology to achieve real-time control, ensuring the precise response of the underlying actuator; (2) Reconfigurable design and control enhancement: A reconfigurable logic unit is designed to support online upgrades of control algorithms without shutting down for burning, effectively improving system adaptability. The reconfigurable logic unit adopts the partial reconfiguration (PR) technology of Xilinx7 series FPGA and is divided into a static area (accounting for 60%, including basic control logic) and a dynamic area (accounting for 40%, including upgradeable algorithms). The upgrade bit stream is received through the AXI4-Lite interface, and CRC32 check is used to ensure data integrity. During the upgrade process, the static area remains running, with a switching time of ≤50ms. It takes over the computing power output of the ARM module and converts upper-level instructions into underlying control signals, thereby enhancing the real-time control capability of the system. The static logic includes an 8-channel PWM generation module (1MHz frequency), a 4-channel encoder interface module (supporting 16-bit frequency multiplication), and a PCIe 4.0 communication interface module. The dynamic logic includes a hardware PID controller (configurable parameters) and a sensor data fusion unit (supporting weighted fusion of force, torque, and laser data). The timing for loading the reconfiguration bitstream via the AXI4-Lite interface is: address line stability time ≥ 10ns, data line setup time ≥ 5ns, and the check completion signal valid within 20ns after data transmission.

[0024] Key function measured data:

[0025] Among them, the high-speed communication interface module includes: (1) High-speed data transmission and synchronization guarantee: Based on the collaborative requirements of the aforementioned computing and control modules, a high-speed data channel between ARM and FPGA is built through the PCIe4.0 bare core to achieve low-latency transmission of large amounts of data. At the same time, TSN Ethernet technology is used to ensure nanosecond-level synchronization between multiple controllers according to the IEEE802.1AS standard to meet the requirements of multi-axis collaborative control; TSN Ethernet uses the IEEE1588PTP protocol for clock synchronization, with a timestamp accuracy of ±10ns. The interpolation trigger of the dynamic trajectory planning module and the compensation calibration of the adaptive control module are both bound to the rising edge of the TSN signal, with a trigger delay of ≤2ns. When the synchronization deviation for three consecutive cycles is greater than 50ns, ARM restarts the TSN clock source (model DP83640) via the I2C bus, with a restart time of ≤1ms. (2) Security protection and data interaction center: integrated hardware firewall, real-time interception of abnormal data in the industrial network, improving the security of system communication; the firewall is based on FPGA implementation, with a built-in industrial protocol feature library (supporting Modbus / TCP, EtherCAT frame format verification), and uses deep packet inspection (DPI) to identify abnormal traffic (such as burst message frequency > 1000 frames / ms, illegal IP address access), with an interception response time of ≤1μs, and supports dynamic update of the whitelist (configured through the ROS interface), building an efficient and stable channel for computing power allocation, control command transmission and sensor data feedback.

[0026] Test report: Test equipment list: TSN synchronization test tool (Keysight N4391A), PCIe performance tester (LeCroyPCIe Summit T3), industrial Ethernet switch (Hirschmann RS20); Core test results: TSN synchronization accuracy: According to the IEEE802.1AS standard, a three-controller network test showed a measured synchronization deviation of ±8ns (≤10ns design value), with no synchronization loss during the 12-hour test. PCIe 4.0 latency: The latency for a single data transfer (128 bytes) is 120ns, and the average latency for a bulk transfer (1MB) is 80ns. Hardware firewall performance: The response time for intercepting abnormal Modbus / TCP messages (illegal IP addresses) was 0.8μs (≤1μs design value), and there was no packet loss in the throughput test (1Gbps traffic).

[0027] Among them, the dynamic trajectory planning module includes: (1) Collaborative planning and global optimization: Based on the stable data interaction environment provided by the high-speed communication module, the ARM and FPGA collaborative working mode is adopted. The ARM side performs global path optimization based on the Chomp algorithm. The iteration step of the Chomp algorithm is set to 0.02s, and the gradient descent coefficient is 0.5. The obstacle handling adopts a 5mm safety distance threshold. When the distance between the path and the obstacle is less than the threshold, the offset calculation is triggered (the offset direction is along the obstacle normal vector); when the obstacle movement is detected (speed > 0.1m / s), the algorithm trigger frequency is increased from 10Hz to 50Hz to adapt to dynamic scenarios; dynamic obstacle avoidance and task priority scheduling can be achieved according to real-time working conditions to ensure the global optimality of path planning; ARM and FPGA are synchronized via TSN Ethernet, with an interaction frequency of 10μs / time. After the FPGA completes interpolation, it feedbacks the execution status via a PCIe4.0 interrupt signal (active high). When the FPGA interpolation deviation exceeds 5%, the ARM immediately restarts the Chomp algorithm for path replanning, with a restart delay of ≤2 control cycles. (2) Hardware acceleration and singularity avoidance: The FPGA side performs quintic polynomial interpolation through hardware pipeline technology to improve trajectory smoothness. The geometric constraint pre-calculation unit verifies the kinematic feasibility in advance in the FPGA, effectively avoiding the risk of singularities in real-time calculations. The planning results are transmitted through the communication module to provide an accurate trajectory benchmark for the adaptive control algorithm module. Quintic polynomial interpolation formula: , Where: is the joint angle trajectory (rad); are the polynomial coefficients; is the time variable (s); Coefficient solution conditions: , This formula, based on polynomial interpolation theory, solves for coefficients by setting six boundary conditions (start and end point position, velocity, and acceleration), ensuring the continuity of the trajectory and its derivatives, thereby achieving smooth motion. In the dynamic trajectory planning module, the FPGA performs the interpolation calculations of this formula through hardware pipelining technology, and in conjunction with the global path optimization results on the ARM side, provides continuous and stable motion instructions for the robotic arm.

[0028] Among them, the adaptive control algorithm module includes: (1) Parameter identification and data support: Based on the trajectory benchmark output by the dynamic trajectory planning module, the online identification submodule integrates machine learning and traditional control theory, and uses an LSTM neural network to estimate the inertia parameters and load changes of the robot arm in real time, providing data support for the adjustment of the control strategy; the LSTM network structure is a 3-layer hidden layer (64 neurons per layer), and the input is the joint angle (θ), angular velocity ( ), angular acceleration ( ) and end load feedback (F), a total of 6-dimensional features, the output is the moment of inertia (I) and equivalent mass (m); the training data comes from 1000 sets of measured dynamic data under different loads (0-5kg), using the Adam optimizer (learning rate 0.001, 500 iterations), and the loss function is the mean square error (MSE); The training data was collected under the following conditions: the load increased from 0 to 5 kg in steps of 0.5 kg. Under each load condition, the robot arm operated at three speeds: 0.5 m / s, 1 m / s, and 1.5 m / s. The sensor sampling frequency was 1 kHz. Each set of data contained 1000 consecutive sampling points of joint angle, angular velocity, and output torque. (2) Interference compensation and mode switching: The interference compensation submodule implements the extended state observer (ESO) through FPGA hardware to perform feedforward compensation for periodic interference such as mechanical vibration; the ESO is a second-order discretization structure, and the state equation is: , Where: is the position estimate; For speed estimation; is the expansion state (vibration interference amount); is the position error; To control the cycle; is the observer gain. The gain parameter is selected based on the pole placement method to ensure that the absolute value of the real part of the observer closed-loop pole is ≥10 6 , ensuring that the vibration disturbance observation error converges to less than 5% within two control cycles; the compensation delay is solidified into hardware logic in Verilog language to ≤ 2 control cycles; the dual closed-loop control architecture supports seamless switching between force control and position control modes; The control method can be flexibly adjusted according to mission requirements, taking over trajectory planning results and further improving control accuracy.

[0029] Dual closed-loop switching triggers the following conditions: A force error greater than 5N in force control mode or a position error greater than 0.1mm in position control mode triggers mode switching. The switching process uses a 0.5s linear transition (parameters smoothly transition from the old mode to the new mode proportionally over time). The force / position control logic unit in the FPGA switches via the AXI4 bus control register (address 0x0001). Writing '0x01' for position control and '0x02' for force control, with a switching delay of ≤10μs.

[0030] Among them, the multimodal security monitoring module includes: (1) Three-level redundancy design and hardware protection: To ensure the stable operation of the adaptive control process, a three-level redundancy design is adopted. The hardware level uses an independent FPGA to monitor overcurrent, overtemperature and other abnormalities in real time, with a response time of microseconds. The output can be directly cut off to avoid equipment damage. The software level is based on the ROS state machine and prioritizes abnormal events through a real-time queue. The hardware level sends an 8-bit binary exception code to the software level (bit 0 = overcurrent, bit 1 = overtemperature, bit 2 = communication abnormality); the software level priority list is: overcurrent (1) > overtemperature (2) > communication delay (3) > load abnormality (4), the smaller the priority value, the higher the priority; the hardware level reserves 100μs for the software level to confirm before cutting off the output, and if there is no response after the timeout, the software level is forced to execute; The mapping relationship between exception codes and software priorities is as follows: bit 0 (overcurrent) → priority 1, bit 1 (overtemperature) → priority 2, bit 2 (communication abnormality) → priority 3, bit 3 (load abnormality) → priority 4, and bits 4-7 are reserved. The spectral characteristics of the 10 fault types in the SVM model training samples are: bearing wear (128 Hz ± 5 Hz), joint looseness (256 Hz ± 8 Hz), motor abnormal noise (312 Hz ± 10 Hz), etc. The sampling frequency of the wavelet packet decomposition during feature extraction is 10 kHz. (2) Cloud-based early warning and full-process monitoring: The cloud-level analyzes the vibration spectrum through edge computing nodes, uses the SVM algorithm to predict faults, monitors the control process in all time periods and multiple dimensions, and builds a full-process security protection system from hardware to cloud. Vibration spectrum feature extraction uses a five-layer wavelet packet decomposition to divide the 10-500 Hz frequency band into eight equal parts, and the energy value of each sub-band is extracted as a 128-dimensional feature. The SVM algorithm uses a penalty coefficient C = 10, the RBF kernel function (γ = 0.1), and 5-fold cross-validation. The training termination condition is 1000 iterations or an error ≤ 1e-5. The fault feature library contains the spectral features of 10 typical fault types, such as bearing wear (128 Hz characteristic peak) and joint looseness (256 Hz characteristic peak).

[0031] Among them, the reconfigurable power management module includes: (1) Dynamic power distribution and power supply guarantee: In view of the energy consumption characteristics of all the above modules, a bidirectional DC-DC converter and a supercapacitor energy storage unit are integrated. The bidirectional DC-DC converter adopts the STM32G431 control chip, and the peripheral circuit includes a 200μH inductor and a 10μF filter capacitor, supporting a 12V-48V input voltage range; the supercapacitor adopts a 3-series and 2-parallel connection method (single-cell model MaxwellBCAP3000) to form a 7.5V / 6000F energy storage unit; the FPGA controls the IGBT's turn-on delay to ≤100ns and the turn-off delay to ≤80ns, and energy recovery is started within 10μs after the braking signal is triggered; the dynamic power distribution function can adjust the power supply priority according to the real-time load of each module, ensuring stable power supply to key modules during peak computing power periods; (2) Energy recovery and system closed-loop optimization: During braking, FPGA controls IGBT to achieve energy recovery and store it in supercapacitors, improving system energy efficiency. It coordinates the operating status of all modules and optimizes overall energy consumption and stability through intelligent power supply regulation.

[0032] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0033] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. High-performance parallel robot controller based on ARM+FPGA architecture, characterized by: The controller includes: Multi-core ARM heterogeneous computing module: Adopting the Cortex-A72+M7 architecture, the A72 core runs the ROS system for scheduling and interaction, while the M7 core accelerates dynamic inverse solution through the NEON instruction set and introduces DVFS technology to dynamically adjust power consumption; FPGA parallel control module: The FPGA parallel control module adopts a distributed design, the motion control submodule realizes multi-channel control, and the sensor fusion submodule processes multi-source data in parallel; High-speed communication interface module: PCIe4.0 bare core enables high-speed data transmission between ARM and FPGA, TSN Ethernet ensures multi-controller synchronization, and hardware firewall enhances security; Dynamic trajectory planning module: Based on a stable communication environment, ARM implements global path optimization, FPGA performs interpolation through hardware pipeline, and the geometric constraint pre-calculation unit avoids singular points; Adaptive control algorithm module: Based on the planned trajectory, it uses an LSTM network to estimate inertia parameters, implements ESO compensation vibration through FPGA, and a dual closed-loop architecture supports force control or position control switching; Multimodal security monitoring module: adopts a three-level redundancy design, achieving rapid response at the hardware level, priority processing at the software level, and fault prediction at the cloud level; Reconfigurable power management module: Based on the energy consumption requirements of each module, the reconfigurable power management module dynamically allocates power, recovers energy during braking, and improves system energy efficiency and stability through intelligent power supply regulation.

2. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The multi-core ARM heterogeneous computing module includes: (1) Architecture composition and core functions: The Cortex-A72+M7 architecture is the core. The A72 core is equipped with the ROS real-time operating system, which is responsible for global task scheduling, human-computer interaction, and cloud data interaction. It supports multi-language mixed programming. The M7 core uses the NEON instruction set to parallelize the dynamic inverse solution calculation process. (2) Dynamic power consumption regulation and computing power support: Dynamic voltage and frequency adjustment technology is introduced to automatically adjust power consumption according to load changes, achieving energy efficiency optimization while ensuring computing power output.

3. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The FPGA parallel control module includes: (1) Distributed control and data processing: Using a distributed computing architecture, the motion control submodule implements multi-channel PWM generation, encoder frequency multiplication, and hardware-level PID control using the Verilog language. The sensor fusion submodule integrates multiple interfaces and processes multi-source sensor data such as force, torque, or laser ranging in parallel. (2) Reconfigurable design and control enhancement: Design a reconfigurable logic unit to support online upgrades of control algorithms without shutting down for burning, take over the computing power output of the ARM module, and convert upper-level instructions into low-level control signals.

4. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The high-speed communication interface module includes: (1) High-speed data transmission and synchronization guarantee: A high-speed data channel between ARM and FPGA is built through the PCIe4.0 bare core to achieve low-latency transmission of large amounts of data. TSN Ethernet technology is used to ensure nanosecond-level synchronization between multiple controllers according to the IEEE802.1AS standard; (2) Security protection and data interaction center: integrated hardware firewall to intercept abnormal data in the industrial network in real time.

5. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The dynamic trajectory planning module includes: (1) Collaborative planning and global optimization: Based on the stable data interaction environment provided by the high-speed communication module, the ARM and FPGA collaborative working mode is adopted. The ARM side performs global path optimization based on the Chomp algorithm, which can realize dynamic obstacle avoidance and task priority scheduling according to real-time working conditions; (2) Hardware acceleration and singularity avoidance: The FPGA side performs quintic polynomial interpolation through hardware pipeline technology, and the geometric constraint pre-calculation unit verifies the kinematic feasibility in advance in the FPGA.

6. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The adaptive control algorithm module includes: (1) Parameter identification and data support: By integrating machine learning with traditional control theory, the online identification submodule uses an LSTM neural network to estimate the inertia parameters and load changes of the robotic arm in real time; (2) Interference compensation and mode switching: The extended state observer is implemented through FPGA hardware to perform feedforward compensation for periodic interference of mechanical vibration. The dual closed-loop control architecture supports seamless switching between force control and position control modes, and the control method can be flexibly adjusted according to task requirements.

7. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The multimodal security monitoring module includes: (1) Three-level redundancy design and hardware protection: A three-level redundancy design is adopted. The hardware level uses an independent FPGA to monitor overcurrent and overtemperature anomalies in real time, with a response time of microseconds, and directly cuts off the output to avoid equipment damage. The software level is based on the ROS state machine and prioritizes abnormal events through a real-time queue; (2) Cloud-based early warning and full-process monitoring: The cloud-level edge computing nodes analyze the vibration spectrum and use the SVM algorithm to predict faults.

8. The high-performance parallel robot controller based on ARM+FPGA architecture according to claim 1 is characterized in that: The reconfigurable power management module includes: (1) Dynamic power allocation and power supply guarantee: Based on the energy consumption characteristics of each module, a bidirectional DC-DC converter and a supercapacitor energy storage unit are integrated. The dynamic power allocation function adjusts the power supply priority according to the real-time load of each module; (2) Energy recovery and system closed-loop optimization: During braking, FPGA controls IGBT to achieve energy recovery and store it in supercapacitors, and intelligent power supply regulation is used to optimize overall energy consumption and stability.

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