Method and system for synchronously correcting and outputting current and voltage signals

Abstract

The invention discloses a current and voltage signal synchronous correction and output method and system, and relates to the technical field of power system analysis and control. Compared with a previous current and voltage signal correction method, the method solves the problems that traditional multi-channel signal acquisition depends on conventional clock control, and synchronization precision is insufficient; a conventional sampling circuit is weak in anti-interference capability. The problem that an existing scheme lacks efficient error prediction and dynamic optimization capability is solved. Through a multi-channel FPGA clock synchronization and double-differential sampling technology, complete acquisition of high-frequency transient characteristics of voltage and current signals is ensured; a dynamic calibration algorithm and multi-stage composite filtering are combined, so that common-mode interference and non-linear errors are effectively suppressed; and finally, through optical fiber isolation output and intelligent feedback control, signal full-link synchronous correction is realized, the electric energy metering error can be reduced, the fault positioning precision is improved, the characteristics of high precision, strong anti-interference and low energy consumption are realized, and a reliable data reference is provided for intelligent power grid and new energy grid connection.

Description

Technical Field

[0001] The present invention relates to the technical field of power system analysis and control, and in particular to a method and system for synchronously correcting and outputting current and voltage signals. Background Art

[0002] In power system monitoring, industrial automation control and other application scenarios, accurate processing of current and voltage signals is the core link to ensure stable operation of equipment and improve measurement accuracy. However, traditional technologies have significant limitations:

[0003] Traditional multi-channel signal acquisition relies on conventional clock control, which lacks synchronization precision and makes it difficult to accurately capture transient high-frequency signals (such as the high-frequency components of power grid faults). For example, during a power grid fault, the rapid changes in high-frequency signals can be distorted due to asynchronous sampling, hindering fault analysis and location. Furthermore, the lack of effective multi-band conversion technology during signal transmission prevents the full preservation of high-frequency signal characteristics, limiting the accuracy of subsequent processing.

[0004] Conventional sampling circuits have weak anti-interference capabilities, and common-mode noise can easily cause signal baseline drift, resulting in severe signal distortion, especially in industrial scenarios with complex electromagnetic environments. Furthermore, temperature changes can cause device parameter drift (such as shifting transformer characteristics). Traditional calibration methods lag behind and cannot dynamically compensate for temperature data in real time, leading to accumulated errors that affect signal accuracy.

[0005] Existing solutions lack efficient error prediction and dynamic optimization capabilities. When signal offset exceeds a threshold, the sampling frequency or compensation parameters cannot be adjusted in real time, making it difficult to meet high-precision output requirements. For example, in electricity metering, uncorrected signal offsets can lead to energy calculation errors, affecting transaction fairness.

[0006] To address the above pain points, this technical solution systematically solves problems such as insufficient synchronization accuracy, difficulty in capturing high-frequency signals, noise interference, temperature drift, and error compensation lag through innovative links such as FPGA synchronous pulse control acquisition, multi-band conversion of transmission circuits, double differential sampling noise reduction, temperature dynamic calibration compensation, filtering denoising, error model prediction and superposition output, and FPGA real-time monitoring and adaptive adjustment, providing a better solution for the precise processing and output of current and voltage signals.

[0007] In order to solve the above problems, the present invention proposes a method and system for synchronously correcting and outputting current and voltage signals. Summary of the Invention

[0008] The purpose of the present invention is to provide a method and system for synchronously correcting and outputting current and voltage signals to solve the problems raised in the background technology:

[0009] Traditional multi-channel signal acquisition relies on conventional clock control, which has insufficient synchronization accuracy; conventional sampling circuits have weak anti-interference capabilities; and existing solutions lack efficient error prediction and dynamic optimization capabilities.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] The current and voltage signal synchronous correction and output method includes:

[0012] The synchronous pulse signal is output through the FPGA synchronization channel to control the acquisition equipment to collect the original voltage signal and current signal, which are then input into the transmission circuit to obtain multi-band current and voltage signals. The current and voltage signals with preliminary noise reduction are output through the double differential sampling circuit.

[0013] Collect temperature data, and dynamically calibrate and adaptively compensate the current and voltage signals that have undergone preliminary noise reduction based on the temperature data to obtain calibrated current and voltage signals;

[0014] Performing filtering and denoising on the calibrated current and voltage signals to obtain denoised current and voltage signals;

[0015] The denoised current and voltage signals, timestamp reference, and temperature data are used as inputs to the error evaluation model to obtain the prediction error, which is then superimposed on the DAC for output.

[0016] The offset of the current and voltage signals is monitored in real time through FPGA. If it exceeds the preset offset threshold, the sampling frequency or compensation parameters are dynamically adjusted and fed back to the acquisition device.

[0017] Preferably, the method for outputting a synchronization pulse signal through an FPGA synchronization channel includes:

[0018] Based on FPGA, the external reference clock is multiplied / divided through a phase-locked loop or digital clock manager to generate a global master clock. The global master clock is divided through the global clock network to generate a synchronous pulse signal, which is then distributed to each sampling channel.

[0019] Preferably, the transmission circuit includes an input stage, a linear transmission stage, a differential processing stage, a frequency compensation stage, and an isolated output stage; the input stage filters out DC components by capacitive coupling in series with a magnetic core, and suppresses high-frequency oscillations by a parallel RC buffer circuit;

[0020] The linear transmission stage constructs a segmented linearization circuit, including a low-frequency band and a high-frequency band. The low-frequency band uses an RC integrator circuit to improve gain stability, and the high-frequency band adds a negative feedback capacitor to compensate for phase delay. The linear transmission stage also outputs a PWM signal based on the FPGA to control the resistance value of the digital potentiometer.

[0021] The positive and negative input terminals of the differential processing stage are symmetrically connected to the signal, and the common mode voltage is eliminated by matching resistors; high frequency common mode interference is suppressed by adding common mode chokes; and compensation current is injected through DAC;

[0022] The frequency compensation stage uses analog switches to switch between different RC delay networks; the switch state is controlled by an FPGA; and the output signal phase is compared with the reference clock to dynamically adjust the delay parameters;

[0023] The isolated output stage converts the voltage signal into an optical signal through the LED driving circuit; and uses a transimpedance amplifier to restore the optical signal into a voltage signal.

[0024] Preferably, the method for obtaining the calibrated current and voltage signals includes:

[0025] At the signal zero point, the acquisition device collects the signal mean within a short-time window and calculates the static offset voltage. This static offset voltage is used as the input of the LSTM model to obtain the predicted compensation current. The corresponding compensation current is generated based on the DAC and injected into the reverse end of the signal chain that outputs the original voltage and current signals through a transconductance amplifier.

[0026] Perform a Clarke transform on the three-phase voltage signal in the signal chain to extract the positive-sequence voltage component. Calculate the fundamental frequency of the positive-sequence voltage component based on FFT. Subtract the fundamental frequency of the positive-sequence voltage component from the rated frequency to obtain the frequency offset. This frequency offset is input into the frequency division controller to dynamically adjust the acquisition clock of the acquisition device.

[0027] The sensor data is fused through Kalman filtering to obtain the temperature rise gradient of the component. The temperature rise gradient of the component is used as the input of the neural network model to obtain the temperature compensation parameter, which is then superimposed on the DAC for output.

[0028] A dynamic error window is set in the FPGA to calculate the signal deviation in real time. When the signal deviation exceeds the preset signal threshold, a calibration event is triggered. A gradient descent algorithm is used to establish a loss function with the goal of minimizing the signal deviation, and the temperature compensation parameters are iteratively adjusted.

[0029] Preferably, the method for obtaining the denoised current and voltage signals includes:

[0030] filtering abnormal values ​​exceeding a preset limiting threshold value in the calibrated current and voltage signals;

[0031] Dynamically adjust the filter coefficient based on the signal standard deviation of the current and voltage signals after filtering outliers based on the sliding window statistics;

[0032] Separating the high-frequency noise and effective transient signal of the current and voltage signals after dynamically adjusting the filter coefficients to obtain the filtered current and voltage signals;

[0033] The synchronous clock is encoded into an optical signal and transmitted to the signal receiving device through optical fiber. The signal receiving device uses the transmitted optical signal as a timestamp reference to perform signal alignment to obtain the denoised current and voltage signals.

[0034] The current and voltage signal synchronous correction and output system implements the current and voltage signal synchronous correction and output, including:

[0035] Acquisition and processing module: Outputs synchronous pulse signals through the FPGA synchronization channel, controls the acquisition equipment to collect original voltage and current signals, and then inputs them into the transmission circuit to obtain multi-band current and voltage signals. The double differential sampling circuit outputs the current and voltage signals with preliminary noise reduction.

[0036] Signal calibration module: collects temperature data, and dynamically calibrates and adaptively compensates the current and voltage signals that have undergone preliminary noise reduction based on the temperature data to obtain calibrated current and voltage signals;

[0037] Signal denoising module: Filters and denoises the calibrated current and voltage signals to obtain denoised current and voltage signals;

[0038] Error denoising module: This module uses the denoised current and voltage signals, timestamp reference, and temperature data as inputs to the error estimation model to obtain the prediction error, which is then superimposed on the DAC output.

[0039] Signal correction module: The FPGA is used to monitor the offset of the current and voltage signals in real time. If the offset exceeds the preset threshold, the sampling frequency or compensation parameters are dynamically adjusted and fed back to the acquisition device.

[0040] Compared with the prior art, the present invention provides a method and system for synchronously correcting and outputting current and voltage signals, which has the following beneficial effects:

[0041] The present invention uses multi-channel FPGA clock synchronization and dual differential sampling technology to ensure the complete acquisition of high-frequency transient characteristics of voltage and current signals; combines dynamic calibration algorithm with multi-stage composite filtering to effectively suppress common-mode interference and nonlinear errors; and finally realizes full-link synchronous correction of signals through optical fiber isolation output and intelligent feedback control, which can reduce electricity metering errors and improve fault location accuracy. It has the characteristics of high precision, strong anti-interference and low energy consumption, and provides a reliable data benchmark for the integration of smart grids and new energy. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a flow chart of the method mentioned in Example 1 of the present invention;

[0043] Figure 2 This is a block diagram of the transmission circuit structure mentioned in Example 1 of the present invention;

[0044] Figure 3 This is a system block diagram mentioned in Example 2 of the present invention;

[0045] Figure 4 This is a schematic diagram of the system interface mentioned in Example 2 of the present invention. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0047] This invention uses multi-channel FPGA clock synchronization and dual differential sampling technology to ensure the complete acquisition of high-frequency transient characteristics of voltage and current signals. It also combines a dynamic calibration algorithm with multi-stage composite filtering to effectively suppress common-mode interference and nonlinear errors. Finally, through optical fiber isolation output and intelligent feedback control, it achieves full-link synchronous correction of signals, which can reduce energy metering errors and improve fault location accuracy. It combines high precision, strong anti-interference and low energy consumption, providing a reliable data benchmark for smart grids and new energy grid integration. Specifically, it includes the following content.

[0048] Example 1:

[0049] See also Figure 1-2 The current and voltage signal synchronous correction and output method of the present invention includes:

[0050] The synchronous pulse signal is output through the FPGA synchronization channel to control the acquisition equipment to collect the original voltage signal and current signal, which are then input into the transmission circuit to obtain multi-band current and voltage signals. The current and voltage signals with preliminary noise reduction are output through the double differential sampling circuit.

[0051] Methods for outputting synchronization pulse signals through FPGA synchronization channels include:

[0052] Based on FPGA, the external reference clock is multiplied / divided through a phase-locked loop (PLL) or digital clock manager (DCM) to generate a highly stable global master clock. The global master clock is divided through the global clock network to generate a synchronous pulse signal, which is then distributed to each sampling channel.

[0053] Reference Figure 2 The transmission circuit includes an input stage, a linear transmission stage, a differential processing stage, a frequency compensation stage, and an isolated output stage. The input stage filters out the DC component by capacitive coupling in series with the magnetic core, and suppresses high-frequency oscillations through a parallel RC buffer circuit. The input stage uses a pre-saturation design in the nonlinear region of the magnetic core to avoid magnetic saturation distortion under large currents.

[0054] The linear transmission stage constructs a segmented linearization circuit, including a low-frequency band (0-10kHz) and a high-frequency band (10-1MHz). An RC integration circuit is used to improve gain stability in the low-frequency band, and a negative feedback capacitor is added to the high-frequency band to compensate for phase delay. Segmented frequency response compensation technology can reduce the flatness error of the amplitude-frequency characteristic across the entire frequency band. The linear transmission stage outputs a PWM signal based on the FPGA to control the resistance value of the digital potentiometer to achieve self-gain adjustment.

[0055] The differential processing stage connects signals symmetrically to the positive and negative inputs, eliminating common-mode voltages through matched resistors. Common-mode chokes are also added to suppress high-frequency common-mode interference. Compensation currents are injected through the DAC to offset DC offsets at the inputs. The differential processing stage effectively suppresses common-mode noise through its symmetrical layout and dynamic baseline correction.

[0056] The frequency compensation stage uses analog switches to switch between different RC delay networks. The FPGA controls the switch states to adjust the delay. The output signal phase is compared with the reference clock to dynamically adjust the delay parameters. This digitally controlled analog delay technology effectively minimizes phase error.

[0057] The isolated output stage converts the voltage signal into an optical signal through the LED driver circuit; a transimpedance amplifier is used to restore the optical signal to a voltage signal; the isolated output stage combines optical coupling with optical fiber transmission to achieve complete electrical isolation and effectively improve anti-interference capabilities.

[0058] Collect temperature data, and dynamically calibrate and adaptively compensate the current and voltage signals that have undergone preliminary noise reduction based on the temperature data to obtain calibrated current and voltage signals;

[0059] The method of obtaining the calibrated current and voltage signals includes:

[0060] Near the signal zero point, the signal mean within a short time window is collected through an acquisition device (such as an ADC) to calculate the static offset voltage. The static offset voltage is used as the input of the LSTM model to obtain the predicted compensation current. The corresponding compensation current is generated based on the DAC, and the corresponding compensation current is injected into the reverse end of the signal chain that outputs the original voltage signal and current signal through a transconductance amplifier. High-precision detection is only enabled when the signal crosses zero, which can reduce power consumption. By learning historical offset data through the LSTM model, the compensation amount can be predicted in advance, reducing real-time calculation delays.

[0061] Perform a Clarke transform on the three-phase voltage signal in the signal chain to extract the positive-sequence voltage component. Calculate the fundamental frequency of the positive-sequence voltage component based on FFT. Subtract the fundamental frequency of the positive-sequence voltage component from the rated frequency to obtain the frequency offset. This frequency offset is input into the frequency division controller to dynamically adjust the acquisition clock of the acquisition device.

[0062] The sensor data is fused through Kalman filtering to obtain the temperature rise gradient of the component; the temperature rise gradient of the component is used as the input of the neural network model to obtain the temperature compensation parameter, which is then superimposed on the DAC for output.

[0063] Based on the temperature rise prediction model, temperature compensation parameters can be injected in advance to offset the lag caused by thermal inertia.

[0064] A dynamic error window is set in the FPGA to calculate the signal deviation in real time. When the signal deviation exceeds the preset signal threshold, a calibration event is triggered. A gradient descent algorithm is used to establish a loss function with the goal of minimizing the signal deviation, and the temperature compensation parameters are iteratively adjusted.

[0065] Performing filtering and denoising on the calibrated current and voltage signals to obtain denoised current and voltage signals;

[0066] Methods for obtaining denoised current and voltage signals include:

[0067] filtering abnormal values ​​exceeding a preset limiting threshold value in the calibrated current and voltage signals;

[0068] Dynamically adjust the filter coefficient based on the signal standard deviation of the current and voltage signals after filtering outliers based on the sliding window statistics;

[0069] Separating the high-frequency noise and effective transient signal of the current and voltage signals after dynamically adjusting the filter coefficients to obtain the filtered current and voltage signals;

[0070] The synchronous clock is encoded into an optical signal and transmitted to the signal receiving device through optical fiber. The signal receiving device uses the transmitted optical signal as a timestamp reference to perform signal alignment to obtain the denoised current and voltage signals.

[0071] The denoised current and voltage signals, timestamp reference, and temperature data are used as inputs to the error evaluation model to obtain the prediction error, which is then superimposed on the DAC for output.

[0072] The offset of the current and voltage signals is monitored in real time through FPGA. If it exceeds the preset offset threshold, the sampling frequency or compensation parameters are dynamically adjusted and fed back to the acquisition device.

[0073] When the offset of the current or voltage signal exceeds a preset offset threshold, the sampling frequency is adjusted according to pre-set rules. This can be achieved by changing the clock division factor within the FPGA. For example, when the current or voltage signal fluctuates significantly, the sampling frequency is increased to obtain more detailed signal information; when the current or voltage signal is relatively stable, the sampling frequency is appropriately reduced to reduce the amount of data processing. In addition to adjusting the sampling frequency, compensation parameters can also be dynamically adjusted. Compensation parameters can be used to modify the amplitude and phase of the current or voltage signal to reduce signal offset. Appropriate compensation parameters can be determined using a lookup table or algorithmic calculation and applied to the collected current or voltage signal.

[0074] Example 2:

[0075] See also Figure 3-4 The current and voltage signal synchronous correction and output system of the present invention comprises:

[0076] Acquisition and processing module: Outputs synchronous pulse signals through the FPGA synchronization channel, controls the acquisition equipment to collect original voltage and current signals, and then inputs them into the transmission circuit to obtain multi-band current and voltage signals. The double differential sampling circuit outputs the current and voltage signals with preliminary noise reduction.

[0077] Signal calibration module: collects temperature data, and dynamically calibrates and adaptively compensates the current and voltage signals that have undergone preliminary noise reduction based on the temperature data to obtain calibrated current and voltage signals;

[0078] Signal denoising module: Filters and denoises the calibrated current and voltage signals to obtain denoised current and voltage signals;

[0079] Error denoising module: This module uses the denoised current and voltage signals, timestamp reference, and temperature data as inputs to the error estimation model to obtain the prediction error, which is then superimposed on the DAC output.

[0080] Signal correction module: The FPGA is used to monitor the offset of the current and voltage signals in real time. If the offset exceeds the preset threshold, the sampling frequency or compensation parameters are dynamically adjusted and fed back to the acquisition device.

[0081] Reference Figure 4The system's interface displays real-time signal fluctuations on a line graph, with the horizontal axis representing sampling points (1-80) and the vertical axis representing signal amplitude (-1.2 to 1.2), providing a visual representation of signal dynamics. Data cards display key parameters, including FPGA operating status (normal), sampling frequency (1000Hz), system temperature (45.2°C), and signal error (±0.02%), providing real-time feedback on system health. The system supports interactive adjustments, using a slider to adjust the sampling frequency and input boxes to set the compensation parameter (currently 0.5) and offset threshold (0.1). Clicking "Execute Calibration" triggers parameter optimization, enabling dynamic system control. Alarm levels, such as "Overtemperature Warning" and "Signal Offset Alarm," are color-coded to quickly indicate system anomalies (such as temperature exceeding the specified limit or voltage signal offset exceeding the threshold), facilitating fault location. The system compares historical trends of voltage, current, and temperature using a line graph, with the horizontal axis representing time / sampling points (0-2200) and the vertical axis representing the physical quantity. This effectively assists in analyzing historical operating patterns and abnormal fluctuations.

[0082] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for synchronously correcting and outputting current and voltage signals, characterized in that: The steps include: The synchronous pulse signal is output through the FPGA synchronization channel to control the acquisition equipment to collect the original voltage signal and current signal, which are then input into the transmission circuit to obtain multi-band current and voltage signals. The current and voltage signals with preliminary noise reduction are output through the double differential sampling circuit. Collect temperature data, and dynamically calibrate and adaptively compensate the current and voltage signals that have undergone preliminary noise reduction based on the temperature data to obtain calibrated current and voltage signals; Performing filtering and denoising on the calibrated current and voltage signals to obtain denoised current and voltage signals; The denoised current and voltage signals, timestamp reference, and temperature data are used as inputs to the error evaluation model to obtain the prediction error, which is then superimposed on the DAC for output. The offset of the current and voltage signals is monitored in real time through FPGA. If it exceeds the preset offset threshold, the sampling frequency or compensation parameters are dynamically adjusted and fed back to the acquisition device.

2. The method for synchronous correction and output of current and voltage signals according to claim 1, characterized in that: Methods for outputting synchronization pulse signals through FPGA synchronization channels include: Based on FPGA, the external reference clock is multiplied / divided through a phase-locked loop or digital clock manager to generate a global master clock. The global master clock is divided through the global clock network to generate a synchronous pulse signal, which is then distributed to each sampling channel.

3. The method for synchronous correction and output of current and voltage signals according to claim 1, characterized in that: The transmission circuit includes an input stage, a linear transmission stage, a differential processing stage, a frequency compensation stage, and an isolated output stage; the input stage filters out DC components by capacitive coupling in series with a magnetic core, and suppresses high-frequency oscillations by a parallel RC buffer circuit; The linear transmission stage constructs a segmented linearization circuit, including a low-frequency band and a high-frequency band. The low-frequency band uses an RC integrator circuit to improve gain stability, and the high-frequency band adds a negative feedback capacitor to compensate for phase delay. The linear transmission stage also outputs a PWM signal based on the FPGA to control the resistance value of the digital potentiometer. The positive and negative input terminals of the differential processing stage are symmetrically connected to the signal, and the common mode voltage is eliminated by matching resistors; high frequency common mode interference is suppressed by adding common mode chokes; and compensation current is injected through DAC; The frequency compensation stage uses analog switches to switch between different RC delay networks; the switch state is controlled by an FPGA; and the output signal phase is compared with the reference clock to dynamically adjust the delay parameters; The isolated output stage converts the voltage signal into an optical signal through the LED driving circuit; and uses a transimpedance amplifier to restore the optical signal into a voltage signal.

4. The method for synchronous correction and output of current and voltage signals according to claim 1, characterized in that: The method of obtaining the calibrated current and voltage signals includes: At the signal zero point, the acquisition device collects the signal mean within a short-time window and calculates the static offset voltage. This static offset voltage is used as the input of the LSTM model to obtain the predicted compensation current. The corresponding compensation current is generated based on the DAC and injected into the reverse end of the signal chain that outputs the original voltage and current signals through a transconductance amplifier. Perform a Clarke transform on the three-phase voltage signal in the signal chain to extract the positive-sequence voltage component. Calculate the fundamental frequency of the positive-sequence voltage component based on FFT. Subtract the fundamental frequency of the positive-sequence voltage component from the rated frequency to obtain the frequency offset. This frequency offset is input into the frequency division controller to dynamically adjust the acquisition clock of the acquisition device. The sensor data is fused through Kalman filtering to obtain the temperature rise gradient of the component. The temperature rise gradient of the component is used as the input of the neural network model to obtain the temperature compensation parameter, which is then superimposed on the DAC for output. A dynamic error window is set in the FPGA to calculate the signal deviation in real time. When the signal deviation exceeds the preset signal threshold, a calibration event is triggered. A gradient descent algorithm is used to establish a loss function with the goal of minimizing the signal deviation, and the temperature compensation parameters are iteratively adjusted.

5. The method for synchronous correction and output of current and voltage signals according to claim 1, characterized in that: Methods for obtaining denoised current and voltage signals include: filtering abnormal values ​​exceeding a preset limiting threshold value in the calibrated current and voltage signals; Dynamically adjust the filter coefficient based on the signal standard deviation of the current and voltage signals after filtering outliers based on the sliding window statistics; Separating the high-frequency noise and effective transient signal of the current and voltage signals after dynamically adjusting the filter coefficients to obtain the filtered current and voltage signals; The synchronous clock is encoded into an optical signal and transmitted to the signal receiving device through optical fiber. The signal receiving device uses the transmitted optical signal as a timestamp reference to perform signal alignment to obtain the denoised current and voltage signals.

6. A current and voltage signal synchronous correction and output system, which implements the current and voltage signal synchronous correction and output according to any one of claims 1 to 7, characterized in that: include: Acquisition and processing module: Outputs synchronous pulse signals through the FPGA synchronization channel, controls the acquisition equipment to collect original voltage and current signals, and then inputs them into the transmission circuit to obtain multi-band current and voltage signals. The double differential sampling circuit outputs the current and voltage signals with preliminary noise reduction. Signal calibration module: collects temperature data, and dynamically calibrates and adaptively compensates the current and voltage signals that have undergone preliminary noise reduction based on the temperature data to obtain calibrated current and voltage signals; Signal denoising module: Filters and denoises the calibrated current and voltage signals to obtain denoised current and voltage signals; Error denoising module: This module uses the denoised current and voltage signals, timestamp reference, and temperature data as inputs to the error estimation model to obtain the prediction error, which is then superimposed on the DAC output. Signal correction module: The FPGA is used to monitor the offset of the current and voltage signals in real time. If the offset exceeds the preset threshold, the sampling frequency or compensation parameters are dynamically adjusted and fed back to the acquisition device.

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