Display driving system and display device

Abstract

The invention belongs to the technical field of display, and particularly relates to a display driving system and a display device, and the display driving system comprises a clock input module which is configured to receive at least two clock signals with different frequencies; the partition control module is configured to generate a partition configuration signal, the partition configuration signal is used for configuring at least two refresh areas, and each refresh area has an independent boundary position and a refresh rate; the signal distribution module is connected with the clock input module and the partition control module, and the signal distribution module is configured to distribute clock signals with different frequencies to scanning lines of corresponding areas according to partition configuration signals; or the signal distribution module is configured to respond to the global control signal and output a turn-off voltage signal to the designated area so as to inhibit the refreshing operation; and the refresh execution module comprises a gate driving circuit, and the gate driving circuit comprises a driving transistor and is used for driving the scanning lines according to the output of the signal distribution module. The refresh rate is dynamically adjusted, and power consumption is reduced.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a display driving system and a display device. Background Art

[0002] In modern display technology, a monitor's refresh rate is a crucial parameter. It determines the number of times the screen refreshes per second, directly impacting both display quality and power consumption. Generally speaking, a higher refresh rate improves the display quality, but also results in higher power consumption. To reduce power consumption, some monitors dynamically adjust their refresh rate based on the content being displayed, ensuring both display quality and power efficiency.

[0003] However, existing dynamic adjustment of the display refresh rate can often only adjust the refresh rate of a fixed area of ​​the display that is set in advance, and cannot be adjusted separately for any area of ​​the display. In some cases, this may result in poor display effects or excessive power consumption. Summary of the Invention

[0004] The purpose of this application is to solve the technical problem in the prior art that the dynamic adjustment of the display refresh rate can only adjust the refresh rate of a fixed area and cannot be adjusted separately for any area of ​​the display, resulting in poor display effect or excessive power consumption.

[0005] In a first aspect, the present application provides a display driving system for performing partitioned refresh on a display panel, the display driving system comprising: a clock input module configured to receive at least two clock signals of different frequencies; a partition control module configured to generate a partition configuration signal, wherein the partition configuration signal is used to configure at least two refresh areas, each of which has an independent boundary position and refresh rate; a signal distribution module connecting the clock input module and the partition control module, wherein the signal distribution module is configured to distribute clock signals of different frequencies to scan lines of corresponding areas according to the partition configuration signal; or the signal distribution module is configured to output a shutdown voltage signal to a designated area in response to a global control signal to suppress a refresh operation; a refresh execution module comprising a gate drive circuit, wherein the gate drive circuit comprises a drive transistor for driving the scan lines according to the output of the signal distribution module.

[0006] In an exemplary embodiment of the present application, the partition control module includes: a touch unit, which can capture the vertical coordinate of the touch operation; and a signal conversion unit, which is configured to convert the vertical coordinate into a step waveform signal with a level jump point.

[0007] In an exemplary embodiment of the present application, the signal distribution module includes a plurality of circuit units, and the plurality of circuit units are arranged between adjacent clock signal lines; each of the circuit units includes a switching transistor, the gate of the switching transistor receives the partition configuration signal, the first electrode of the switching transistor is connected to the clock signal, and the second electrode of the switching transistor is connected to the scan line driving circuit of the corresponding area.

[0008] In an exemplary embodiment of the present application, the signal distribution module inputs a turn-off voltage to the gate node of the driving transistor in response to a global control signal; the driving capability of the global control signal is greater than the turn-on threshold of the driving transistor.

[0009] In an exemplary embodiment of the present application, the gate drive circuit outputs a clock pulse matching the partition refresh rate when the signal distribution module is configured to output a clock pulse matching the partition refresh rate according to the partition configuration signal; and the gate drive circuit maintains a low potential at the gate node of the driving transistor when the signal distribution unit is configured to respond to a global control signal.

[0010] In an exemplary embodiment of the present application, the signal wiring of the touch control unit is arranged in a different layer from the scan lines and data lines of the display panel.

[0011] In an exemplary embodiment of the present application, the display driving system further includes a picture detection module, which is configured to output a high-level global control signal when identifying that the graphic data of the display panel area has not changed for N consecutive frames, where N≥2.

[0012] In an exemplary embodiment of the present application, the clock input module includes at least two frequency values, and the highest frequency value and the lowest frequency value satisfy: the highest frequency value ≥ 2 times the lowest frequency value.

[0013] In an exemplary embodiment of the present application, the partition control module includes multiple groups of partition configuration signals, the wavelength of each group of the partition configuration signals matches the corresponding clock signal frequency, and the duty cycle of the partition configuration signals is set according to the ratio of the number of rows in the refresh area.

[0014] The second aspect of the present application provides a display device, comprising: a timing controller, which outputs at least two clock signals of different frequencies; a display panel, which includes at least two refresh areas with different refresh rates; and a display driving system as described in any of the above items, wherein the clock input module receives at least two clock signals of different frequencies output by the timing controller, and the refresh execution module connects the scan lines of different refresh areas of the display panel.

[0015] The display drive system and display device of the present application have at least the following beneficial effects:

[0016] The display driving system of the present application solution can refresh the display panel in different zones. The display driving system includes a clock input module, a zone control module, a signal distribution module and a refresh execution module. The clock input module can receive at least two clock signals of different frequencies. The zone control module can be configured to generate a zone configuration signal. The zone configuration signal is used to configure at least two refresh areas on the display panel. Each refresh area has an independent boundary position and a corresponding refresh rate. The signal distribution module connects the clock input module and the zone control module. The signal distribution module is configured to distribute clock signals of different frequencies to scan lines of corresponding areas according to the zone configuration signal. Alternatively, the signal distribution module is configured to output a shutoff voltage signal to a designated area in response to a global control signal to suppress the refresh operation. The refresh execution module includes a gate drive circuit. The gate drive circuit includes a drive transistor for driving the scan line according to the output of the signal distribution module. In this way, by realizing dynamic zone refresh control of the display panel, different areas are allowed to independently set refresh rates or completely shut down refresh, achieving high refresh and smoothness in dynamic areas and zero refresh in static areas, significantly reducing the power consumption of the display device.

[0017] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 The figure shows a structural block diagram of the display driving system provided in the first embodiment of the present application.

[0021] Figure 2 The diagram shows the level structure of the partition configuration signal provided in the first embodiment of the present application.

[0022] Figure 3 The circuit structure diagram of the refresh execution module provided in the first embodiment of the present application is shown.

[0023] Figure 4 A structural schematic diagram of the connection between the metal signal wiring and the partition control module provided in Example 1 or Example 2 of the present application is shown.

[0024] Figure 5 A coordinate diagram of signals and wavelengths at different frequencies of the display panel provided by the first or second embodiment of the present application is shown.

[0025] Figure 6 A schematic diagram of the connection structure between the high-frequency group, the low-frequency group and the refresh execution module provided in the third embodiment of the present application is shown.

[0026] Figure 7 A schematic diagram of the structure of the partition configuration signal and each clock signal provided in the third embodiment of the present application is shown.

[0027] Figure 8 The diagram shows the level structure of each signal provided in the third embodiment of the present application.

[0028] Figure 9 A structural schematic diagram of the global control signal and the third transistor provided in the fourth embodiment of the present application is shown.

[0029] Figure 10 The diagram shows the level structure of each signal provided in the fourth embodiment of the present application.

[0030] Figure 11 A schematic diagram of the connection structure of the display panel, timing controller and display driving system provided in Example 5 of the present application is shown.

[0031] Description of reference numerals:

[0032] 100. Display drive system; 110. Clock input module; 120. Partition control module; 120a. First partition configuration signal; 120b. Second partition configuration signal; 120c. Third partition configuration signal; AP1. Fourth partition configuration signal; AP2. Fifth partition configuration signal; AP. Global control signal; 121. Metal signal routing; 130. Signal distribution module; T1. First switching transistor; T2. Second switching transistor; T3. Third switching transistor; T4. First transistor; T5. Second transistor; T6. Third transistor; 140. Refresh execution module; CLK1. First clock signal; CLK2. Second clock signal; CLK3. Third clock signal; 200. Timing controller; 300. Display panel; 310. Scan line; 320. Data line. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0034] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0035] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0036] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0037] Example 1

[0038] The first embodiment of the present application provides a display driving system 100, which can refresh the display panel 300 in partitions, and the screen refresh rate in each partition is different.

[0039] Figure 1 Shows the structural block diagram of the display driving system.

[0040] In the examples of this application, see Figure 1 As shown, the display driving system 100 includes a clock input module 110 , a partition control module 120 , a signal distribution module 130 and a refresh execution module 140 .

[0041] The clock input module 110 is configured to receive at least two clock signals of different frequencies. The clock signal can be generated by an oscillator inside the timing controller 200, and the target frequency is generated by a frequency division circuit, and finally converted and output by a level converter. The clock signal with the highest frequency value and the clock signal with the lowest frequency value meet the following conditions: the highest frequency value ≥ 2 times the lowest frequency value. By having different refresh rates in the high-frequency and low-frequency regions, a perceptible energy saving effect is ensured.

[0042] The partition control module 120 is configured to generate a partition configuration signal, which is used to configure at least two refresh zones so that the refresh zones are refreshed at their respective refresh rates under the influence of the partition configuration signal. It is worth noting that each refresh zone has an independent boundary position and refresh rate, so that different partition configuration signals are matched to different refresh zones, thereby enabling different zones to refresh at different refresh rates.

[0043] See also Figure 1 As shown, the signal distribution module 130 can be connected to the clock input module 110 and the partition control module 120. The signal distribution module 130 is configured to distribute clock signals of different frequencies to the scan lines 310 of the corresponding refresh areas according to the partition configuration signal, so that different refresh areas are refreshed at different refresh rates, thereby improving the display effect and reducing the power consumption required for display refresh.

[0044] The refresh execution module 140 includes a gate driving circuit (not shown). The gate driving circuit includes a driving transistor, which can drive the scan line 310 in the display panel 300 according to the output of the signal distribution module 130 .

[0045] In this embodiment, the partition control module 120 includes multiple sets of partition configuration signals. The wavelength of each partition configuration signal matches the frequency of the corresponding clock signal, and the duty cycle of the partition configuration signal is set according to the ratio of the number of rows in the refresh area. Wavelength matching achieves precise timing synchronization to eliminate signal misalignment, and combining the duty cycle with the row ratio achieves spatial pixel-level alignment, ensuring zero edge flicker and zero redundant refresh at any partition ratio.

[0046] In the embodiment of the present application, the signal distribution module 130 includes a plurality of circuit units (not shown in the figure), and the plurality of circuit units are arranged between adjacent clock signal lines. Each circuit unit includes a switching transistor, that is, a switching transistor is provided on each clock signal line. The gate of each switching transistor is connected to its corresponding partition control module 120 for receiving the partition configuration signal; the first electrode of the switching transistor is connected to the clock input module 110 for receiving the clock signal; the second electrode is connected to the scan line 310 driving circuit of the corresponding refresh area to allocate clock signals of different frequencies to the corresponding refresh area.

[0047] In this way, the partition configuration signal is used to control the opening or closing of the switching transistor, so that the corresponding clock signal enters or blocks the clock signal from entering the scan line 310 driving circuit, so that different refresh areas are refreshed according to different refresh rates or the corresponding refresh areas are suppressed from refreshing, so that different areas of the display panel 300 use different refresh rates for display refresh, thereby improving the display effect and reducing power consumption.

[0048] For example, the clock input module 110 is configured to receive three clock signals of different frequencies, such as 240 Hz, 120 Hz, and 60 Hz; the partition control module 120 is configured to generate three sets of partition configuration signals; and the signal distribution module 130 includes three circuit units, each of which is provided with the aforementioned switching transistors. The gates of the switching transistors in the three circuit units correspond to the three sets of partition configuration signals. When the display panel 300 selects the partitioning conditions for each refresh frequency according to the user, the partition control module 120 inputs the three sets of partition configuration signals according to the different partitioning conditions. The frequency, wavelength, and duty cycle of each set of partition configuration signals will differ according to the corresponding clock signal frequency. That is, the frequency, wavelength, and duty cycle of the three sets of partition configuration signals are different. The three sets of partition configuration signals respectively control different switching transistors to input clock signals of different frequencies.

[0049] In the embodiment of the present application, the switch transistor in the circuit unit can be an NMOS (N-type channel metal oxide semiconductor field effect transistor). Of course, in other embodiments, the switch transistor in the circuit unit can also be a PMOS (P-type channel metal oxide semiconductor field effect transistor), and the corresponding on and off levels are low and high, respectively.

[0050] For example, the display panel 300 has 90 scan lines 310. The refresh rate of the first 30 lines (1 to 30) is 120 Hz, the refresh rate of the middle 30 lines (31 to 60) is 240 Hz, and the refresh rate of the last 30 lines (61 to 90) is 60 Hz. That is, the display panel 300 can be divided into three refresh areas, and each refresh area has a different refresh rate, namely 120 Hz, 240 Hz, and 60 Hz. Figure 1 As shown, the clock input module 110 receives a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3, which correspond to the 240 Hz, 120 Hz, and 60 Hz refresh zones, respectively. The partition control module 120 includes a first partition configuration signal 120 a, a second partition configuration signal 120 b, and a third partition configuration signal 120 c. The signal distribution module 130 includes a first switch transistor T1, a second switch transistor T2, and a third switch transistor T3, which correspond to the first partition configuration signal 120 a, the second partition configuration signal 120 b, and the third partition configuration signal 120 c, respectively. That is, the first partition configuration signal 120 a controls the opening and closing of the first switch transistor T1, the second partition configuration signal 120 b controls the opening and closing of the second switch transistor T2, and the third partition configuration signal 120 c controls the opening and closing of the third switch transistor T3.

[0051] Figure 2 The level structure diagram of the partition configuration signal is shown. Figure 3 Shows the circuit structure diagram of the refresh execution module.

[0052] See also Figure 1 、 Figure 2 and Figure 3 As shown, the first partition configuration signal 120a, the second partition configuration signal 120b, and the third partition configuration signal 120c have different high-level maintenance times. The second partition configuration signal 120b can be input at a high level in the first 1 / 3 time period, while the first partition configuration signal 120a and the third partition configuration signal 120c are at a low level. The second switch transistor T2 is turned on, and the first switch transistor T1 and the third switch transistor T3 are turned off, so that the second clock signal CLK2 (120 Hz) is input to the gate drive circuit of the refresh execution module 140. The gate drive circuit of the refresh execution module 140 controls the 1st to 30th row scan lines 310 to perform row-by-row scanning, so that the 120 Hz refresh area of ​​the display panel 300 is refreshed in the first 1 / 3 time period, while the 240 Hz and 60 Hz refresh areas are not refreshed in the first 1 / 3 time period.

[0053] See also Figure 1 、 Figure 2 and Figure 3 As shown, the first partition configuration signal 120a can be input at a high level in the middle 1 / 3 time period, the second partition configuration signal 120b and the third partition configuration signal 120c are at a low level, the first switch transistor T1 is turned on, and the second switch transistor T2 and the third switch transistor T3 are turned off, so that the first clock signal CLK1 (240HZ) is input into the gate drive circuit of the refresh execution module 140, and the gate drive circuit of the refresh execution module 140 controls the 31st to 60th row scan lines 310 to scan row by row, so that the 240HZ refresh area of ​​the display panel 300 is refreshed in the middle 1 / 3 time period, while the 120HZ and 60HZ refresh areas are not refreshed in the middle 1 / 3 time period.

[0054] See also Figure 1 、 Figure 2 and Figure 3 As shown, the third partition configuration signal 120c can be input at a high level in the last 1 / 3 time period, the first partition configuration signal 120a and the second partition configuration signal 120b are at a low level, the third switch transistor T3 is turned on, and the first switch transistor T1 and the second switch transistor T2 are turned off, so that the third clock signal CLK3 (60HZ) is input into the gate drive circuit of the refresh execution module 140, and the gate drive circuit of the refresh execution module 140 controls the 61st to 90th row scan lines 310 to scan row by row, so that the display panel 30060HZ refresh area is refreshed in the last 1 / 3 time period, while the 240HZ and 120HZ refresh areas are not refreshed in the last 1 / 3 time period.

[0055] In this way, different partitions are controlled to refresh the display in sequence in different time periods, so as to improve the display effect and reduce the refresh power consumption.

[0056] Example 2

[0057] The difference between the second embodiment of the present application and the first embodiment is that the partition control module 120 includes a touch unit and a signal conversion unit, and controls the refresh rate of different positions according to the touch position.

[0058] Figure 4 A schematic diagram showing the structure of the connection between the metal signal wiring and the partition control module is shown. Figure 5 A coordinate diagram of the signal and wavelength at different frequencies of the display panel is shown.

[0059] In the examples of this application, see Figure 4 As shown, the touch function circuit is formed using metal signal traces 121 on a different layer from the scan lines 310 and data lines of the display panel 300. When the user touches the screen, the touch signal is fed back to the touch unit (not shown in the figure). The touch unit can capture the vertical coordinate (Y axis) of the touch operation and thus determine the size and boundary position of each partition required by the user.

[0060] It is worth mentioning that no matter the user touches the screen with a finger or taps the screen to determine the refresh area boundary, the touch unit only recognizes the vertical coordinate of the last touch point.

[0061] In an embodiment of the present application, a signal conversion unit (not shown in the figure) is integrated into a control chip (IC) and electrically connected to the touch unit. It is configured to convert the vertical coordinate obtained by the touch unit into a step waveform signal with a level jump point.

[0062] It is understandable that, in some embodiments, the partition control module 120 may be a control chip.

[0063] When the touch unit recognizes the longitudinal coordinate of the touch point position, the signal conversion unit converts the longitudinal coordinate into a step waveform signal and transmits the step waveform signal to the gate of the switching transistor to control the opening and closing of different switching transistors, thereby controlling different clock signals to be input into different partitions, thereby controlling the refresh in different partitions.

[0064] In this way, by reusing the touch metal layer to capture the touch position signal, the boundary detection circuit required for partition refresh is eliminated, reducing manufacturing costs; and the step wave partition configuration signal is generated in real time based on the touch coordinates to improve the refresh area boundary accuracy, and only the user operation-related areas are displayed at a high refresh rate, while the non-touch area maintains a low refresh rate, effectively reducing the refresh power consumption of the display panel 300; and the high-frequency refresh area completely covers the touch operation track, so that the dynamic image blur rate of the touch area is reduced, thereby improving the display effect of the related area.

[0065] For example, the display panel 300 has a total of 90 scan lines 310, the refresh rate corresponding to the first 30 lines (1 to 30 lines) is 120HZ, the refresh rate corresponding to the middle 30 lines (31 to 60 lines) is 240HZ, and the refresh rate corresponding to the last 30 lines (61 to 90 lines) is 60HZ. That is, the display panel 300 can be divided into three refresh areas, and the refresh rates corresponding to each refresh area are different, namely 120HZ, 240HZ and 60HZ. And the signal size of the 240HZ refresh area is set to 3T, the wavelength is H, the signal size of the 120HZ refresh area is 2T, the wavelength is 2H, the signal size of the 60HZ refresh area is T, and the wavelength is 3H, then the output waveform is as follows Figure 5 As shown, the waveform is a signal fed back to the signal conversion unit by the display panel 300, and the signal conversion unit outputs a corresponding partition configuration signal (such as Figure 2 As shown, the touch signal turns on the corresponding switching transistor, allowing the clock signal to enter the driver circuit and control the refresh rate of the corresponding area. In this way, the touch signal is used to determine the size and boundary position of each partition required by the user, thereby determining the area to be refreshed. The desired area is refreshed in real time, while unneeded areas are paused or maintained at a low refresh rate, effectively reducing power consumption and costs.

[0066] For an example, see Figure 1 、 Figure 2 、 Figure 4 and Figure 5As shown, when a user touches the middle area of ​​the display panel 300 (corresponding to the positions of the scan lines 310 in rows 31-60), the touch unit captures the Y-axis coordinate (signal magnitude 3T), the signal conversion unit converts the Y-axis coordinate into a staircase waveform, and outputs the first partition configuration signal 120a based on the staircase waveform signal. The first partition configuration signal 120a can be input at a high level during the middle 1 / 3 time period, while the second and third partition configuration signals 120b and 120c are at a low level. The first switch transistor T1 is turned on, and the second and third switch transistors T2 and T3 are turned off, so that the first clock signal CLK1 is input to the gate drive circuit of the refresh execution module 140. The gate drive circuit of the refresh execution module 140 controls the scan lines 310 in rows 31-60 to perform progressive scanning, so that the 240Hz refresh area of ​​the display panel 300 is refreshed in the middle 1 / 3 time period, while the 120Hz and 60Hz refresh areas are not refreshed in the middle 1 / 3 time period.

[0067] Example 3

[0068] The difference between the third embodiment of the present application and the first or second embodiment is that the switching transistor, the first partition configuration signal 120a, the second partition configuration signal 120b and the third partition configuration signal 120c in the first and second embodiments are eliminated, and in the third embodiment the display driving system 100 further includes a picture detection module (not shown in the figure), which is configured to identify changes in the graphic data of the display panel 300 area.

[0069] Figure 6 A schematic diagram of the connection structure between the high-frequency group, the low-frequency group and the refresh execution module is shown. Figure 7 A schematic diagram of the structure of partition configuration signals and various clock signals is shown. Figure 8 Shows the level structure diagram of each signal.

[0070] In the examples of this application, see Figure 6 As shown, the clock input module 110 is configured to receive two sets of clock signals with different frequencies. The high-speed set is CLK1a-CLK4a, and the low-speed set is CLK5a-CLK6a. The two sets of clock signals are connected through independent input interfaces, and the highest and lowest frequencies meet the following requirement: the highest frequency ≥ 2 times the lowest frequency.

[0071] In the examples of this application, see Figure 6 As shown, the partition control module 120 includes a fourth partition configuration signal AP1 and a fifth partition configuration signal AP2 to control the input of the high refresh group clock and the input of the low refresh group clock respectively.

[0072] The partition control module 120 may be a control chip, and the fourth partition configuration signal AP1 and the fifth partition configuration signal AP2 may be output via the control chip.

[0073] In the embodiment of the present application, the picture detection module may be configured to output a high-level fifth partition configuration signal AP2 when it is identified that the regional graphic data of the display panel 300 has not changed for N consecutive frames, where N≥2.

[0074] For example, the picture detection module can be configured to output a high-level fifth partition configuration signal AP2 when the graphic data in the display panel 300 area has not changed for two consecutive frames. The fifth partition configuration signal AP2 can control the display panel 300 area that has not changed for two consecutive frames not to be refreshed, while the refresh rate of the remaining areas can be adjusted, thereby achieving the purpose of saving power consumption by adjusting the local refresh rate.

[0075] It should be noted that, in some embodiments, the picture detection module can also be configured to output a high-level fifth partition configuration signal AP2 when the display area graphic data has not changed for 3 consecutive frames, 4 frames or 5 frames. The specific design can be based on different embodiments.

[0076] In the examples of this application, see Figure 6 As shown, the signal distribution module 130 may include a first transistor T4 and a second transistor T5. The first transistor T4 and the second transistor T5 are both NMOS transistors. The gates of the first transistor T4 and the second transistor T5 can receive the fourth partition configuration signal AP1 and the fifth partition configuration signal AP2, respectively, to control the on and off of the first transistor T4 and the second transistor T5, thereby inputting clock signals of different frequencies into the refresh execution module 140.

[0077] In the examples of this application, see Figure 6 As shown, the refresh execution module 140 includes a Zn level transmission unit (not shown) and a Gn output unit (not shown). The Zn level transmission unit is capable of receiving the clock signal from the signal distribution module 130 and transmitting it to the subsequent Zn unit via a shift register. When the fourth partition configuration signal AP1 is activated, the level transmits the high refresh group clock, and when the fifth partition configuration signal AP2 is activated, the level transmits the low refresh group clock. Based on the clock signal transmitted by the Zn level transmission unit, the Gn output unit outputs a scan pulse of a corresponding pulse width to the scan line 310.

[0078] For example, the clock input module 110 receives two groups of clocks: a high refresh group: CLK1a-CLK4a, and a low refresh group: CLK5a-CLK6a. The partition control module 120 outputs a fourth partition configuration signal AP1 and a fifth partition configuration signal AP2. The fourth partition configuration signal AP1 is connected to the gate of the first transistor T4 of the signal distribution module 130, and the fifth partition configuration signal AP2 is connected to the gate of the second transistor T5 of the signal distribution module 130. Figure 6 、 Figure 7 and Figure 8 As shown, when the display panel 300 requires a higher refresh rate, the fourth partition configuration signal AP1 is high voltage and the fifth partition configuration signal AP2 is low voltage. At this time, the CLK1a-CLK4a clock signal of the high frequency group is input, and the Zn level transmission unit transmits the high frequency refresh frequency level to the Gn output unit, outputs a clock pulse that matches the partition refresh rate, and drives the scan line 310 to refresh at a high frequency refresh frequency.

[0079] When the image detection module detects that two consecutive frames of an area of ​​the display panel 300 remain the same, the area is in a static state, and the static area is stopped from refreshing or refreshed at a lower rate, so as to adjust the local refresh rate and achieve the purpose of saving power consumption. Figure 6 、 Figure 7 and Figure 8 As shown, at this time, the fifth partition configuration signal AP2 is high voltage, the fourth partition configuration signal AP1 is low voltage, the CLK5a-CLK6a clock signal of the low-frequency group is input, and the Zn level transmission unit transmits the low-frequency refresh frequency level to the Gn output unit, outputs a clock pulse that matches the partition refresh rate, drives the scan line 310 to refresh at a low-frequency refresh rate, and reduces the refresh rate, thereby reducing the power consumption of the display panel 300.

[0080] Example 4

[0081] The difference between the fourth embodiment of the present application and the third embodiment is that the high refresh group and the low refresh group are cancelled, and the signal distribution module 130 is configured to respond to the global control signal AP and output a shutdown voltage to the designated area to suppress the refresh operation.

[0082] Figure 9 A schematic structural diagram of the global control signal and the third transistor is shown. Figure 10 The level structure diagram of each signal provided is shown.

[0083] In the embodiment of the present application, the clock input module 110 is configured to receive a dynamic area clock signal. When the static area is shut down, the clock signal input is not cut off, and the clock signal transmission is only suppressed through the signal distribution module 130 described below.

[0084] In the examples of this application, see Figure 9 and Figure 10As shown, the signal distribution module 130 may include a VGL sink circuit controlled by a global control signal AP. This VGL sink circuit includes a third transistor T6, which may be an NMOS transistor. When the global control signal AP controls the third transistor T6 to turn on, the off-state voltage is injected into the gate of the input unit of the refresh execution module 140Gn through a path, maintaining the gate node of the driving transistor at a low potential.

[0085] In the embodiment of the present application, the refresh execution module 140 includes a Zn level transmission unit and a Gn output unit. When the global control signal AP is high, the shutdown voltage is preferentially transmitted to the Gn output unit, overriding the clock signal. After receiving the shutdown voltage, the gate of the Gn output unit remains at a low level, and no scan pulse is output. This changes the output of the refresh execution module 140, preventing the refresh of that area of ​​the display panel 300, thereby reducing the refresh power consumption of the display panel 300.

[0086] That is, this embodiment uses different refresh rates to display different areas, see Figure 9 and Figure 10 As shown, when the picture detection module recognizes that the graphic data in the display panel 300 area has not changed for N consecutive frames (N≥2), it outputs a high-level global control signal AP, turns on the third transistor T6, and injects the turn-off voltage VGL into the gate node of the driving transistor, thereby changing the output of the Gn output unit so that the area is not refreshed, thereby reducing refresh power consumption.

[0087] It is worth mentioning that the driving capability of the global control signal AP is greater than the conduction threshold of the driving transistor to ensure that when the turn-off voltage is injected, the gate voltage of the Gn input unit is forced to be pulled down to a low voltage to prevent the static area from being refreshed incorrectly.

[0088] Example 5

[0089] Embodiment 5 of the present application provides a display device, which may include a timing controller 200, a display panel 300, and the display drive system 100 of Embodiment 1, Embodiment 2, Embodiment 3, or Embodiment 4. The timing controller 200 is capable of outputting at least two clock signals of different frequencies, for example, CLK1 = 240 Hz, CLK2 = 120 Hz, and CLK3 = 60 Hz. The display panel 300 may include at least two refresh areas with different refresh rates, for example, an upper 30% area with a 120 Hz refresh rate, a middle 40% area with a 240 Hz refresh rate, and a lower 30% area with a 60 Hz refresh rate.

[0090] Figure 11 It shows a schematic diagram of the connection structure of the display panel, timing controller and display drive system.

[0091] Among them, see Figure 11As shown, the clock input module 110 in the display driving system 100 receives the clock signal output by the timing controller 200 , and the refresh execution module 140 connects the scan lines 310 of different refresh areas of the display panel 300 .

[0092] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0093] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A display driving system for performing partition refresh on a display panel, characterized in that: The display driving system includes: A clock input module configured to receive at least two clock signals of different frequencies; A partition control module is configured to generate a partition configuration signal, wherein the partition configuration signal is used to configure at least two refresh areas, each of the refresh areas having an independent boundary position and refresh rate; a signal distribution module connected to the clock input module and the partition control module, wherein the signal distribution module is configured to distribute clock signals of different frequencies to scan lines of corresponding areas according to the partition configuration signal; or the signal distribution module is configured to output a shutdown voltage signal to a designated area in response to a global control signal to inhibit a refresh operation; The refresh execution module includes a gate driving circuit, wherein the gate driving circuit includes a driving transistor, and is used to drive the scan line according to the output of the signal distribution module.

2. The display driving system according to claim 1, wherein: The partition control module includes: A touch unit capable of capturing a longitudinal coordinate of a touch operation; The signal conversion unit is configured to convert the vertical coordinate into a step waveform signal with a level jump point.

3. The display driving system according to claim 1, wherein: The signal distribution module includes a plurality of circuit units, and the plurality of circuit units are arranged between adjacent clock signal lines; Each of the circuit units includes a switching transistor, a gate of the switching transistor receives the partition configuration signal, a first electrode of the switching transistor is connected to a clock signal, and a second electrode of the switching transistor is connected to a scan line driving circuit of a corresponding area.

4. The display driving system according to claim 1, wherein: The signal distribution module inputs a turn-off voltage to the gate node of the driving transistor in response to a global control signal; the driving capability of the global control signal is greater than the conduction threshold of the driving transistor.

5. The display driving system according to claim 1, wherein: The gate drive circuit outputs a clock pulse matching a partition refresh rate when the signal distribution module is configured to output a clock pulse matching a partition refresh rate according to the partition configuration signal; The gate driving circuit maintains a low potential at the gate node of the driving transistor when the signal distribution unit is configured to respond to a global control signal.

6. The display driving system according to claim 2, wherein: The signal wiring of the touch control unit is arranged in a different layer from the scanning lines and data lines of the display panel.

7. The display driving system according to claim 1, wherein: The display driving system further includes a picture detection module configured to output a high-level global control signal when identifying that the graphic data in the display panel area has not changed for N consecutive frames, where N≥2.

8. The display driving system according to claim 1, wherein: The clock input module includes at least two frequency values, and the highest frequency value and the lowest frequency value satisfy: the highest frequency value ≥ 2 times the lowest frequency value.

9. The display driving system according to claim 3, wherein: The partition control module includes multiple groups of partition configuration signals, the wavelength of each group of partition configuration signals matches the frequency of the corresponding clock signal, and the duty cycle of the partition configuration signal is set according to the ratio of the number of rows in the refresh area.

10. A display device, characterized in that: include: A timing controller outputs at least two clock signals of different frequencies; The display panel includes at least two refresh areas with different refresh rates; as well as The display driving system according to any one of claims 1 to 9, wherein the clock input module receives at least two clock signals of different frequencies output by the timing controller, and the refresh execution module connects the scan lines of different refresh areas of the display panel.

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