Wireless charging system, wireless charging chip module and electronic equipment

Abstract

The invention provides a wireless charging system, a wireless charging chip module and electronic equipment. When the wireless charging system is in a standby mode, the system control circuit sends a first indication signal to the wireless charging transmitting circuit. And after the control signal sent by the application processor is received, the wireless charging transmitting circuit is started according to the first indication signal and the control signal, so that the wireless charging system does not need to be integrated with a CPU (Central Processing Unit), and a wireless charging transmitting function is realized. Or under the condition that the wireless charging system is in the standby mode, after the first starting signal sent by the detection circuit is received, the system control circuit transmits the second indication signal to the wireless charging receiving circuit. And the wireless charging receiving circuit is started according to the second indication signal, so that the basic power distribution state machine is started, and the wireless charging system can realize a wireless charging receiving function without integrating a CPU (Central Processing Unit). Therefore, an SRAM and an NVM do not need to be arranged in the wireless charging system, and the cost of the wireless charging system is reduced.

Description

Technical Field

[0001] The present application relates to the field of wireless charging technology, and in particular to a wireless charging system, a wireless charging chip module, and an electronic device. Background Art

[0002] In recent years, wireless charging technology has developed rapidly, particularly in the mobile phone sector. Wireless charging technology now supports both wireless charging and reverse wireless charging. This allows devices supporting reverse wireless charging to charge other wireless charging-capable devices in an emergency. Early implementations of this technology involved combining transmitter and receiver chips. However, with the advancement of wireless charging technology, these chips have been integrated into a single chip, allowing it to function as both a wireless charging receiver and a wireless charging transmitter. This allows a single chip to perform the functions of two chips, significantly increasing the integration level of wireless charging systems, simplifying their design, and reducing development costs.

[0003] In related technologies, wireless charging systems are essentially system-on-chip (SOC) systems. SOC systems typically include a central processing unit (CPU) and multiple peripherals. After the SOC system is powered on, the CPU implements the wireless charging QI protocol receiving or transmitting functions through multiple peripherals, enabling the SOC system to receive or transmit energy. The CPU's operation relies on static random-access memory (SRAM) and non-volatile memory (NVM) in multiple peripherals for storing programs.

[0004] However, since SRAM and NVM require additional customization and testing costs, and occupy a larger area, the SOC system in the related art has a high cost problem. Summary of the Invention

[0005] The present application provides a wireless charging system, a wireless charging chip module, and an electronic device, which can reduce the cost of the wireless charging system.

[0006] In a first aspect, the present application provides a wireless charging system, the wireless charging system comprising: an IIC communication circuit, a wireless charging receiving circuit, a wireless charging transmitting circuit, a system control circuit, and a detection circuit;

[0007] The IIC communication circuit is connected to the wireless charging transmitting circuit and the wireless charging receiving circuit respectively through the IIC bus. The IIC communication circuit and the system control circuit are also connected to the application processor. The system control circuit is also connected to the wireless charging transmitting circuit, the wireless charging receiving circuit and the detection circuit respectively.

[0008] The detection circuit is configured to send a detection signal to the system control circuit when the wireless charging system is in a standby mode, wherein the detection signal is used to indicate that a wireless charging device is connected to the wireless charging system;

[0009] The system control circuit is configured to send a first instruction signal to the wireless charging transmitting circuit; or, upon receiving the detection signal or a first start signal sent by the application processor, transmit a second instruction signal to the wireless charging receiving circuit, wherein the first start signal is configured to control the wireless charging system to enter a wireless charging receiving mode from the standby mode;

[0010] The wireless charging transmitting circuit is configured to start according to the first indication signal and the control signal after receiving the control signal sent by the application processor through the IIC communication circuit, so as to enable the wireless charging system to enter the wireless charging transmitting mode;

[0011] The wireless charging receiving circuit is configured to start up according to the second indication signal, so as to start up a basic power distribution state machine in the wireless charging receiving circuit, thereby enabling the wireless charging system to enter the wireless charging receiving mode.

[0012] With the wireless charging system provided in the first aspect, when the wireless charging system is in standby mode, the system control circuit can send a first indication signal to the wireless charging transmitting circuit, allowing the wireless charging transmitting circuit to obtain the first indication signal. Thus, upon receiving a control signal sent by the application processor via the IIC communication circuit, the wireless charging transmitting circuit can be activated based on the first indication signal and the control signal. Consequently, the wireless charging system can enter the wireless charging transmitting mode and implement the wireless charging transmitting function simply by controlling the wireless charging transmitting circuit to be activated by the application processor, without requiring an integrated CPU. Alternatively, upon receiving a detection signal sent by the detection circuit indicating that a wireless charging device has been connected to the wireless charging system, or a first activation signal sent by the application processor to control the wireless charging system from standby mode to wireless charging receiving mode, the system control circuit can transmit a second indication signal to the wireless charging receiving circuit, allowing the wireless charging receiving circuit to obtain the second indication signal. Thus, the wireless charging receiving circuit can be activated based on the second indication signal, causing the basic power distribution state machine in the wireless charging receiving circuit to be activated, thereby causing the wireless charging system to enter the wireless charging receiving mode. Furthermore, the wireless charging system can enter the wireless charging receiving mode and implement the wireless charging receiving function without requiring an integrated CPU. In summary, wireless charging systems can implement wireless charging transmitters and receivers without integrating a CPU, eliminating the need for SRAM and NVM. Consequently, the system eliminates the need for additional customization and testing costs, occupies a smaller area, and reduces system costs.

[0013] In one possible design, the wireless charging system further includes: a common circuit, the common circuit including: an analog-to-digital conversion controller and a linear voltage regulator controller;

[0014] The analog-to-digital conversion controller is respectively connected to the system control circuit, the wireless charging receiving circuit and the linear voltage regulator controller, and the analog-to-digital conversion controller is also connected to the IIC bus;

[0015] The analog-to-digital conversion controller is configured to start before the wireless charging system enters the standby mode;

[0016] The analog-to-digital conversion controller is further configured to, when the wireless charging system is in the wireless charging receiving mode, obtain the second indication signal from the system control circuit, and control the corresponding linear voltage regulator circuit to start up through the linear voltage regulator controller according to the second indication signal;

[0017] The analog-to-digital conversion controller is further configured to, when the wireless charging transmitting circuit or the wireless charging receiving circuit is in a communication state, and when the frequency shift keying circuit in the wireless charging transmitting circuit or the amplitude shift keying circuit in the wireless charging receiving circuit is not operating, sequentially sample and calculate the first output current and the first coil voltage of the wireless charging system to obtain the second output current and the second coil voltage, respectively.

[0018] In one possible design, the analog-to-digital conversion controller is specifically configured to, when the frequency shift keying circuit or the amplitude shift keying circuit is not operating, sample the first output current to obtain an output sampling current; and before the linear voltage regulator circuit is started, sample the first output current according to a verification enable signal to obtain an offset current; and after the linear voltage regulator circuit is started, sample the first output current according to the verification enable signal to obtain a verification current; and after the first output current is sampled, sample the first coil voltage to obtain a coil sampling voltage.

[0019] The analog-to-digital conversion controller is further specifically configured to calculate the output sampling current, the offset current, and the verification current to obtain the second output current, and to calculate the coil sampling voltage to obtain the second coil voltage.

[0020] In one possible design, the analog-to-digital conversion controller is further specifically configured to, after obtaining the coil sampling voltage, sequentially sample the first output voltage and the first temperature of the wireless charging system to obtain the output sampling voltage and the sampling temperature; and after calculating the second coil voltage, sequentially calculate the output sampling voltage and the sampling temperature to obtain the second output voltage and the second temperature.

[0021] In one possible design, the second output current is calculated according to the following formula 1, the second coil voltage is calculated according to the following formula 2, the second output voltage is calculated according to the following formula 3, and the second temperature is calculated according to the following formula 4:

[0022]

[0023] Among them, I out2 For the second output current, I adc is the output sampling current, I calibration is the calibration current, I offset is the offset current, Gain is the first constant;

[0024]

[0025] Among them, V rect2is the second coil voltage, V adc1 is the coil sampling voltage, offset is the second constant, and Gain is the first constant;

[0026]

[0027] Among them, V out2 For the second output voltage, V adc2 is the output sampling voltage, offset is the second constant, and Gain is the first constant;

[0028]

[0029] Among them, T die2 is the second temperature, T adc is the sampling temperature.

[0030] In one possible design, the analog-to-digital conversion controller includes an arithmetic logic circuit, and the arithmetic logic circuit includes a first calculation circuit and a second calculation circuit;

[0031] The first calculation circuit and the second calculation circuit are both connected to first configuration information, the first configuration information is used to configure a basic operation performed by the first calculation circuit or the second calculation circuit, a first input end of the first calculation circuit is used to receive a first physical parameter, the first physical parameter is a second input end of the first calculation circuit is used to receive a second physical parameter, an output end of the first calculation circuit is connected to the first input end of the second calculation circuit, the second input end of the second calculation circuit is used to receive a third physical parameter, and the second calculation circuit is used to output a calculation result;

[0032] The arithmetic logic unit is used to use the first calculation circuit to perform the first multiplication operation or the first division operation in Formula 1, Formula 2, Formula 3, or Formula 4, and to use the second calculation circuit to perform the second multiplication operation or the second division operation in Formula 1, Formula 2, Formula 3, or Formula 4.

[0033] In one possible design, the wireless charging receiving circuit includes: a basic power distribution state machine, an amplitude shift keying circuit, and a frequency shift keying demodulation circuit;

[0034] The basic power distribution state machine is connected to the analog-to-digital conversion controller and the amplitude shift keying circuit respectively, and the amplitude shift keying circuit and the frequency shift keying demodulation circuit are both connected to the IIC bus;

[0035] After the wireless charging receiving circuit is started, when the wireless charging receiving circuit is in a communication state:

[0036] The basic power distribution state machine is configured to obtain the second coil voltage and the second output current from the analog-to-digital conversion controller;

[0037] The basic power distribution state machine is further configured to generate the first data packet according to the second coil voltage and the second output current in accordance with the Qi protocol, and send the first data packet to the amplitude shift keying circuit;

[0038] The amplitude shift keying circuit is used to generate and send a carrier modulation signal according to the first data packet to send the first data packet;

[0039] The frequency shift keying demodulation circuit is used to receive a first feedback data packet corresponding to the first data packet.

[0040] In one possible design, the first data packet includes: a signal strength data packet, a device identification data packet, a configuration data packet, a control error data packet, and a received power data packet;

[0041] The basic power distribution state machine is specifically configured to obtain the signal strength data packet according to the second coil voltage, and sequentially send the signal strength data packet, the device identification data packet, and the configuration data packet to the amplitude shift keying circuit, so as to send the signal strength data packet, the device identification data packet, and the configuration data packet through the carrier modulation signal;

[0042] The basic power distribution state machine is further specifically used to calculate the control error data packet according to the second coil voltage and the target coil voltage after the signal strength data packet, the device identification data packet and the configuration data packet are sent in sequence, and send the control error data packet to the amplitude shift keying circuit to send the control error data packet through the carrier modulation signal, or calculate the received power data packet according to the second coil voltage and the second output current, and send the received power data packet to the amplitude shift keying circuit to send the received power data packet through the carrier modulation signal.

[0043] In one possible design, the wireless charging transmitting circuit includes: a pulse width modulation circuit and an amplitude shift keying demodulation circuit;

[0044] The pulse width modulation circuit and the amplitude shift keying demodulation circuit are both connected to the IIC bus;

[0045] After the wireless charging transmitting circuit is started, when the wireless charging transmitting circuit is in a communication state:

[0046] The pulse width modulation circuit is configured to receive the to-be-sent data and the second configuration information sent by the application processor after receiving a configuration signal sent by the application processor via the IIC communication circuit, wherein the configuration signal is used to set parameters of the pulse width modulation circuit to control the full-bridge circuit to perform energy transmission;

[0047] The pulse width modulation circuit is further configured to package the data to be transmitted to obtain a second data packet, and generate and send a pulse width modulation signal according to the second configuration information to transmit the second data packet;

[0048] The amplitude shift keying demodulation circuit is configured to receive a second feedback data packet of the second data packet, and demodulate and store the second feedback data packet.

[0049] In one possible design, the pulse width modulation circuit includes: a first buffer, a frequency shift keying circuit, and a pulse width modulation signal output circuit;

[0050] The first buffer and the pulse width modulation signal output circuit are both connected to the IIC bus, and the first buffer is further connected to the pulse width modulation signal output circuit via the frequency shift keying circuit;

[0051] The first buffer is configured to receive the data to be sent and the second configuration information, and send the data to be sent and the second configuration information to the frequency shift keying circuit;

[0052] The frequency shift keying circuit is used to package the data to be sent to obtain a second data packet, and adjust the duty cycle and frequency of the pulse width modulation signal in the pulse width modulation signal output circuit according to the second configuration information to generate the pulse width modulation signal.

[0053] In one possible design, the amplitude shift keying demodulation circuit includes: a plurality of second buffers and a plurality of amplitude shift keying demodulation components;

[0054] The plurality of second buffers are connected to the IIC bus, and the plurality of second buffers are also connected one by one to the plurality of amplitude shift keying demodulation components;

[0055] The multiple amplitude shift keying demodulation components are used to receive the second feedback data packet, demodulate the second feedback data packet, and store the demodulated second feedback data packet in the corresponding multiple second buffers.

[0056] In one possible design, the wireless charging system further includes: an interrupt circuit;

[0057] The application processor is connected to the IIC bus via the interrupt circuit;

[0058] The frequency shift keying demodulation circuit is further configured to send a first interrupt signal to the application processor through the interrupt circuit after receiving the first feedback data packet;

[0059] Alternatively, the pulse width modulation circuit is further configured to send a second interrupt signal to the application processor through the interrupt circuit after sending the second data packet;

[0060] Alternatively, the amplitude shift keying demodulation circuit is further configured to send a third interrupt signal to the application processor through the interrupt circuit after demodulating and storing the second feedback data packet.

[0061] In one possible design, the system control circuit is further configured to, when the wireless charging system is in the wireless charging receiving mode, transmit a third indication signal to the wireless charging receiving circuit upon receiving a second start signal sent by the application processor, wherein the second start signal is configured to enter the standby mode from the wireless charging receiving mode;

[0062] The wireless charging receiving circuit is configured to shut down according to the third indication signal, so as to shut down the basic power distribution state machine.

[0063] In a second aspect, the present application provides a wireless charging chip module, which includes: an IIC communication interface, a wireless charging receiving chip, a wireless charging transmitting chip, a system control chip, and a detection chip;

[0064] The IIC communication interface is connected to the wireless charging transmitter chip and the wireless charging receiver chip respectively through the IIC bus. The IIC communication interface and the system control chip are also connected to the application processor. The system control chip is also connected to the wireless charging transmitter chip, the wireless charging receiver chip and the detection chip respectively.

[0065] The detection chip is configured to send a detection signal to the system control chip when the wireless charging chip module is in standby mode, wherein the detection signal is used to indicate that a wireless charging device is connected to the wireless charging chip module;

[0066] The system control chip is configured to send a first indication signal to the wireless charging transmitting chip; or, upon receiving the detected signal or the first start signal sent by the application processor, transmit a second indication signal to the wireless charging receiving chip, wherein the first start signal is configured to control the wireless charging chip module to enter the wireless charging receiving mode from the standby mode;

[0067] The wireless charging transmitting chip is configured to start according to the first indication signal and the control signal after receiving the control signal sent by the application processor through the IIC communication interface, so as to enable the wireless charging chip module to enter the wireless charging transmitting mode;

[0068] The wireless charging receiving chip is configured to start up according to the second indication signal, so as to start up a basic power distribution state machine in the wireless charging receiving chip, thereby enabling the wireless charging chip module to enter the wireless charging receiving mode.

[0069] In one possible design, the wireless charging chip module further includes: a common chip; the common chip includes: an analog-to-digital conversion control chip and a linear voltage regulation control chip;

[0070] The analog-to-digital conversion control chip is respectively connected to the system control chip, the wireless charging receiving chip and the linear voltage stabilization control chip, and the analog-to-digital conversion control chip is also connected to the IIC bus;

[0071] The analog-to-digital conversion control chip is configured to start before the wireless charging chip module enters the standby mode;

[0072] The analog-to-digital conversion control chip is further configured to obtain the second indication signal from the system control chip when the wireless charging chip module is in the wireless charging receiving mode, and control the corresponding linear voltage regulator circuit to start up through the linear voltage regulator control chip according to the second indication signal;

[0073] The analog-to-digital conversion control chip is further configured to, when the wireless charging transmitting chip or the wireless charging receiving chip is in a communication state, sequentially sample and calculate the first output current and the first coil voltage of the wireless charging chip module when the frequency shift keying circuit in the wireless charging transmitting chip or the amplitude shift keying circuit in the wireless charging receiving chip is not working, to obtain the second output current and the second coil voltage, respectively.

[0074] The analog-to-digital conversion control chip is respectively connected to the system control chip, the wireless charging receiving chip and the linear voltage stabilization control chip, and the analog-to-digital conversion control chip is also connected to the IIC bus.

[0075] The beneficial effects of the wireless charging chip module provided in the second aspect and the various possible designs of the second aspect can be referred to the beneficial effects brought about by the first aspect and the various possible implementation methods of the first aspect, and will not be repeated here.

[0076] In a third aspect, the present application provides an electronic device, comprising: the wireless charging chip module in the second aspect above.

[0077] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0079] Figure 1 A structural diagram of a SOC system provided for related technologies;

[0080] Figure 2 A schematic diagram of the working principle of the Qi wireless charging protocol provided for related technologies;

[0081] Figure 3 A schematic diagram of the structure of a wireless charging system provided in an embodiment of the present application;

[0082] Figure 4 A schematic diagram of the working process of a wireless charging system provided in an embodiment of the present application;

[0083] Figure 5 A schematic diagram of the working process of an analog-to-digital conversion controller in a wireless charging system provided in an embodiment of the present application;

[0084] Figure 6 A schematic diagram of the structure of an arithmetic logic circuit provided in an embodiment of the present application;

[0085] Figure 7 A schematic diagram of the working process of a basic power distribution state machine in a wireless charging receiving circuit provided in an embodiment of the present application;

[0086] Figure 8 This is a working timing diagram of a basic power distribution state machine in a wireless charging receiving circuit provided in an embodiment of the present application;

[0087] Figure 9 This is a schematic diagram of the structure of a wireless charging transmitting circuit in a wireless charging system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0088] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0089] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0090] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0091] Reference Figure 1 , Figure 1 A structural diagram of a SOC system provided for related technologies. Figure 1As shown, a SOC system may generally include a CPU and multiple peripherals. Multiple peripherals and the CPU are connected to the CPU bus. Multiple peripherals may include: a frequency-shift keying (FSK1) module, a frequency-shift keying demodulation (FSKDM1) module, an amplitude-shift keying (ASK1) module, an amplitude-shift keying demodulation (ASKDM1) module, an analog to digital converter (ADC), a timer (TIMER), SRAM, and NVM.

[0092] When the SOC system serves as the wireless charging receiver, after the SOC system is powered on, the CPU implements the wireless charging receiving function of the QI protocol through the FSKDM1 module, ASK1 module, and ADC and TIMER as general peripherals, thereby completing energy reception.

[0093] When the SOC system serves as the wireless charging transmitter, after the SOC system is powered on, the CPU implements the wireless charging transmission function of the Qi protocol through the FSK1 module, ASKDM1 module, and ADC and TIMER as general peripherals, thereby realizing energy transmission.

[0094] Among them, the operation of the CPU depends on SRAM and NVM.

[0095] However, since SRAM and NVM require additional customization and testing costs, and occupy a larger area, the SOC system in the related art has a high cost problem.

[0096] At the same time, when the SOC system is installed on the circuit board, it is difficult to perform maintenance such as modification, upgrade, and repair of the system software running on it.

[0097] In addition, the operation of the CPU requires a high-frequency clock to be present all the time, resulting in higher power consumption of the SOC system, and the operation of the CPU depends on the system software, resulting in slow operation speed and slow response speed of the SOC system.

[0098] In the Qi wireless charging protocol, the order and time of sending data packets by the wireless charging receiver are relatively fixed. Figure 2 , Figure 2 A schematic diagram of the working principle of the Qi protocol is provided for related technologies. It details the order in which the Qi wireless charging protocol sends data packets in the baseline power profile (BPP) mode.

[0099] After powering up, the wireless charging receiver will sequentially send information related to the signal strength (SS) data packet SIG, the device identification ID data packet, the configuration (CFG) data packet, the control error (CE) data packet, and the received power (RP) data packet.

[0100] This process can be implemented entirely in hardware without the involvement of an application processor (AP). Extended power profile (EPP), magnetic power profile (MPP), or even proprietary protocols can be transparently transmitted by the AP.

[0101] When used as a wireless charging transmitter, the application processor AP, which acts as the energy sender, is always present. In this way, the application processor AP can realize the wireless charging transmission function of the Qi protocol through transparent transmission.

[0102] To this end, the present application provides a wireless charging system. This system does not require an integrated CPU and can operate simply by enabling a BPP state machine or implementing a transparent transmission function, enabling the wireless charging system to implement either a wireless charging receiving function or a wireless charging transmitting function. Consequently, the wireless charging system does not require SRAM and NVM, reducing the cost of the wireless charging system.

[0103] Reference Figure 3 , Figure 3 This is a schematic diagram of the structure of a wireless charging system provided in an embodiment of the present application. Figure 3 As shown, the wireless charging system 1000 may include: an IIC communication circuit 300 , a wireless charging receiving circuit 200 , a wireless charging transmitting circuit 100 , a system control circuit 400 and a detection circuit 500 .

[0104] The IIC communication circuit 300 is connected to the wireless charging transmitting circuit 100 and the wireless charging receiving circuit 200 respectively through the IIC bus. The IIC communication circuit 300 and the system control circuit 400 are also connected to the application processor AP. The system control circuit 400 is also connected to the wireless charging transmitting circuit 100, the wireless charging receiving circuit 200 and the detection circuit 500 respectively.

[0105] Among them, the IIC communication circuit 300, the wireless charging receiving circuit 200, the wireless charging transmitting circuit 100, the system control circuit 400 and the detection circuit 500 can be set separately or integrated, and the embodiment of the present application does not specifically limit this.

[0106] The following combination Figure 4 , Figure 4 This is a schematic diagram of the workflow of a wireless charging system provided in an embodiment of the present application. The working principle of the wireless charging system 1000 is described in detail. The content is as follows:

[0107] like Figure 4 As shown, the wireless charging system 100 enters the initialization state TRIM from the idle state IDLE1 and the waiting state WAIT_CLK in sequence. In the initialization state TRIM, the wireless charging system 100 downloads initialization data to complete initialization, so that the wireless charging system 100 enters the standby mode STAND_BY.

[0108] When the wireless charging system 1000 is in the standby mode STAND_BY, the system control circuit 400 may send a first indication signal to the wireless charging transmitting circuit 100 to enable the wireless charging transmitting circuit 100 to determine that the wireless charging system 1000 is in the standby mode STAND_BY.

[0109] Based on this, after receiving the control signal sent by the application processor AP via the IIC communication circuit 300, the wireless charging transmitter circuit 100 can be activated according to the first indication signal and the control signal, enabling the circuits in the wireless charging transmitter circuit 100 to be activated. In other words, the activation of the wireless charging transmitter circuit 100 is achieved by the application processor AP through transparent transmission, meaning that the wireless charging system 1000 has a transparent transmission function. Furthermore, the wireless charging system 1000 does not require an integrated CPU; simply by controlling the activation of the wireless charging transmitter circuit 100 via the application processor AP, it can enter the wireless charging transmitter mode TX_MODE and implement the wireless charging transmitter function. Consequently, the wireless charging system 1000 does not need to have SRAM and NVM, eliminating the need for additional customization and testing costs. Furthermore, the system 1000 occupies a smaller area, thereby reducing the cost of the wireless charging system 1000.

[0110] When the wireless charging system 1000 is in the standby mode STAND_BY, upon receiving the detection signal AC_OK sent by the detection circuit 500 or the first start signal RT_MODE1 sent by the application processor AP, the system control circuit 400 can transmit a second indication signal to the wireless charging receiving circuit 200, so that the wireless charging receiving circuit 200 determines that the wireless charging system 1000 is in the wireless charging receiving mode RX_MODE.

[0111] The detection signal AC_OK is used to indicate that a wireless charging device is connected to the wireless charging system 1000 , and the first start signal RT_MODE1 is used to control the wireless charging system 1000 to enter the wireless charging receiving mode RX_MODE from the standby mode STAND_BY.

[0112] In the wireless charging receiving mode RX_MODE, the system control circuit 400 may enable the protection logic.

[0113] Based on this, the wireless charging receiving circuit 200 can be activated according to the second indication signal, thereby activating the basic power distribution state machine 210 in the wireless charging receiving circuit 200, causing the wireless charging system 1000 to enter the wireless charging receiving mode RX_MODE. Furthermore, the wireless charging system 1000 can enter the wireless charging receiving mode RX_MODE and implement the wireless charging receiving function without integrating a CPU. Consequently, the wireless charging system 1000 does not need to include SRAM and NVM, eliminating the need for additional customization and testing costs. Furthermore, the system 1000 occupies a smaller area, thereby reducing the cost of the wireless charging system 1000.

[0114] The wireless charging transmission mode TX_MODE and the wireless charging reception mode RX_MODE are in an OR relationship. When the wireless charging system 100 enters the wireless charging transmission mode TX_MODE, the wireless charging system 100 will not simultaneously enter the wireless charging reception mode RX_MODE. When the wireless charging system 100 enters the wireless charging reception mode RX_MODE, the wireless charging system 100 will not simultaneously enter the wireless charging transmission mode TX_MODE.

[0115] In summary, wireless charging system 1000 can implement wireless charging transmission or reception without integrating a CPU, eliminating the need for SRAM and NVM in wireless charging system 1000. Consequently, wireless charging system 1000 eliminates the need for additional customization and testing costs and occupies a smaller area, reducing the cost of wireless charging system 1000.

[0116] Among them, compared with the area occupied by the SOC system in the related art, which is close to 1.93mm 2 The wireless charging system 1000 of the present application only needs a memory for storing digital logic and initialization data, so the wireless charging system 1000 occupies a smaller area. Among them, the area occupied by the wireless charging system 1000 of the present application is close to 1.1mm 2 .

[0117] In some examples, when the wireless charging system 1000 is in the wireless charging receiving mode RX_MODE, upon receiving the second start signal RT_MODE2 sent by the application processor AP, the system control circuit 400 can transmit a third indication signal to the wireless charging receiving circuit 200, so that the wireless charging receiving circuit 200 can determine that the wireless charging system 1000 exits the wireless charging receiving mode RX_MODE.

[0118] The second start signal RT_MODE2 is used to enter the standby mode STAND_BY from the wireless charging receiving mode RX_MODE.

[0119] Therefore, the wireless charging receiving circuit 200 can be turned off according to the third indication signal, so as to turn off the basic power distribution state machine 210, so that the wireless charging system 1000 no longer receives energy.

[0120] When the wireless charging system 1000 is in the wireless charging receiving mode RX_MODE, the wireless charging system 1000 acts as a wireless charging receiving end. When the wireless charging system 1000 is in the wireless charging transmitting mode TX_MODE, the wireless charging system 1000 acts as a wireless charging transmitting end.

[0121] The wireless charging system provided by the present application, when the wireless charging system is in standby mode, can send a first indication signal to the wireless charging transmitting circuit, so that the wireless charging transmitting circuit can obtain the first indication signal. In this way, after receiving the control signal sent by the application processor through the IIC communication circuit, the wireless charging transmitting circuit can be started according to the first indication signal and the control signal. Furthermore, the wireless charging system does not need to integrate a CPU, and can enter the wireless charging transmitting mode and realize the wireless charging transmitting function simply by controlling the wireless charging transmitting circuit to start by the application processor. Alternatively, when the wireless charging system is in standby mode, upon receiving a detection signal sent by the detection circuit to indicate that a wireless charging device has been connected to the wireless charging system or a first start signal sent by the application processor to control the wireless charging system to enter the wireless charging receiving mode from the standby mode, the system control circuit can transmit a second indication signal to the wireless charging receiving circuit, so that the wireless charging receiving circuit can obtain the second indication signal. In this way, the wireless charging receiving circuit can be started according to the second indication signal, so that the basic power distribution state machine in the wireless charging receiving circuit is started, so that the wireless charging system enters the wireless charging receiving mode. Furthermore, the wireless charging system can enter the wireless charging receiving mode and realize the wireless charging receiving function without integrating a CPU. In summary, wireless charging systems can implement wireless charging transmitters and receivers without integrating a CPU, eliminating the need for SRAM and NVM. Consequently, the system eliminates the need for additional customization and testing costs, occupies a smaller area, and reduces system costs.

[0122] Based on the description of the above embodiment, a possible implementation of the wireless charging system 1000 is exemplified. Figure 3 As shown, the wireless charging system 1000 may further include: a common circuit 600 .

[0123] The common circuit 600 may include an analog-to-digital conversion controller 610 and a linear voltage regulator controller 620 .

[0124] The analog-to-digital conversion controller 610 is connected to the system control circuit 400 , the wireless charging receiving circuit 200 , and the linear voltage regulator controller 620 , respectively. The analog-to-digital conversion controller 610 is also connected to the IIC bus.

[0125] Before the wireless charging system 1000 enters the standby mode STAND_BY, the analog-to-digital conversion controller 610 is started, that is, the analog-to-digital conversion controller 610 is enabled.

[0126] Thus, when the wireless charging system 1000 is in the wireless charging receiving mode RX_MODE, the analog-to-digital conversion controller 610 can obtain the second indication signal from the system control circuit 400. Furthermore, the analog-to-digital conversion controller 610 can control the corresponding linear voltage regulator circuit to start up through the linear voltage regulator controller 620 based on the second indication signal.

[0127] When the wireless charging transmitting circuit 100 or the wireless charging receiving circuit 200 is in a communication state, when the frequency shift keying circuit 112 in the wireless charging transmitting circuit 100 or the amplitude shift keying circuit 220 in the wireless charging receiving circuit 200 is not operating, the analog-to-digital conversion controller 610 can sequentially sample and calculate the first output current Iout1 and the first coil voltage Vrect1 of the wireless charging system 1000 to obtain the second output current Iout2 and the second coil voltage Vrect2, respectively.

[0128] In some examples, when the frequency-shift keying circuit 112 or the amplitude-shift keying circuit 220 is not operating, the analog-to-digital conversion controller 610 can sample the first output current Iout1 to obtain the output sampled current Iadc. Furthermore, before the linear voltage regulator circuit is started, when the calibration enable signal CALI_EN is at a high level, the analog-to-digital conversion controller 610 can sample the first output current Iout1 to obtain the offset current Ioffset. Furthermore, after the linear voltage regulator circuit is started, when the calibration enable signal CALI_EN is at a high level, the analog-to-digital conversion controller 610 can sample the first output current Iout1 to obtain the calibration current Icalibration. After sampling the first output current Iout1, the analog-to-digital conversion controller 610 can sample the first coil voltage Vrect1 to obtain the coil sampled voltage Vadc1.

[0129] Thus, after obtaining the coil sampling voltage Vadc1, the analog-to-digital conversion controller 610 can sequentially sample the first output voltage Vout1 and the first temperature Tdie1 of the wireless charging system 1000 to obtain the output sampling voltage Vadc2 and the sampling temperature Tadc.

[0130] In this way, the analog-to-digital conversion controller 610 can calculate the output sampling current Iadc, the offset current Ioffset and the calibration current Icalibration to obtain the second output current Iout2, and calculate the coil sampling voltage Vadc1, the output sampling voltage Vadc2 and the sampling temperature Tadc in sequence to obtain the second coil voltage Vrect2, the second output voltage Vout2 and the second temperature Tdie2.

[0131] In the wireless charging receiving mode RX_MODE, the system control circuit 400 may obtain the second output voltage Vout2 and the second temperature Tdie2 from the analog-to-digital conversion controller 610 to activate the protection logic.

[0132] The following combination Figure 5 , Figure 5 This is a schematic diagram of the workflow of an analog-to-digital conversion controller in a wireless charging system provided in an embodiment of the present application. The working principle of the analog-to-digital conversion controller 610 is described in detail. The content is as follows:

[0133] like Figure 5 As shown, the analog-to-digital conversion controller 610 enters the enabled state WAIT_ADC_EN from the idle state IDLE2. In the enabled state WAIT_ADC_EN, the analog-to-digital conversion controller 610 is enabled. Thus, after being enabled, the analog-to-digital conversion controller 610 sequentially enters the output current sampling state IOUT_SAMPLE, the coil voltage sampling state VRECT_SAMPLE, the output voltage sampling state VOUT_SAMPLE, and the temperature sampling state TDIE_SAMPLE at sampling periods of, for example, 1 ms. Thus, when the frequency shift keying circuit 112 or the amplitude shift keying circuit 220 is not operating, that is, when the busy signal of the frequency shift keying circuit 112 or the amplitude shift keying circuit 220 is detected to be released, the analog-to-digital conversion controller 610 can sequentially sample the first output current Iout1, the first coil voltage Vrect1, the first output voltage Vout1, and the first temperature Tdie1 at sampling periods of 1 ms.

[0134] When the analog-to-digital conversion controller 610 is in the output current sampling state IOUT_SAMPLE, the analog-to-digital conversion controller 610 can sample the first output current Iout1 to obtain the output sampled current Iadc. Thus, the analog-to-digital conversion controller 610 enters a state for determining whether the linear voltage regulator circuit is enabled from the output current sampling state IOUT_SAMPLE. In this state, if MLDO_EN is low, that is, if the linear voltage regulator circuit is not enabled, then when the analog-to-digital conversion controller 610 controls the calibration enable signal CALI_EN to be high, the analog-to-digital conversion controller 610 samples the first output current Iout1 in the output current sampling state IOUT_SAMPLE to obtain the offset current Ioffset. This means that the analog-to-digital conversion controller 610 enters the offset value acquisition state GET_OFFSET and controls the calibration enable signal CALI_EN to return to a low level.

[0135] If MLDO_EN is high, that is, if the linear voltage regulator circuit is enabled, the analog-to-digital conversion controller 610 enters a state to determine whether the sampling period meets 100ms to determine whether to update the calibration current Icalibration. In this state, if the sampling period meets 100ms, when the analog-to-digital conversion controller 610 controls the calibration enable signal CALI_EN to be high, the first output current Iout1 is sampled to obtain the calibration current Icalibration. In other words, the analog-to-digital conversion controller 610 enters the calibration value acquisition state GET_CAL to update the calibration current Icalibration and controls the calibration enable signal CALI_EN to return to a low level. If the sampling period does not meet 100ms, the calibration current Icalibration remains unchanged, that is, it remains the calibration current Icalibration of the previous sampling period.

[0136] Based on this, after sampling the first output current Iout1, the analog-to-digital conversion controller 610 enters the coil voltage sampling state VRECT_SAMPLE, allowing the analog-to-digital conversion controller 610 to sample the first coil voltage Vrect1 and obtain the coil sampled voltage Vadc1. After obtaining the coil sampled voltage Vadc1, the analog-to-digital conversion controller 610 sequentially enters the output voltage sampling state VOUT_SAMPLE and the temperature sampling state TDIE_SAMPLE, allowing the analog-to-digital conversion controller 610 to sequentially sample the first output voltage Vout1 and the first temperature Tdie1 of the wireless charging system 1000 to obtain the output sampled voltage Vadc2 and the sampled temperature Tadc. Then, the analog-to-digital conversion controller 610 enters the calculation state CALCULATE, so that the analog-to-digital conversion controller 610 can calculate the output sampling current Iadc, the offset current Ioffset and the calibration current Icalibration to obtain the second output current Iout2, calculate the coil sampling voltage Vadc1 to obtain the second coil voltage Vrect2, calculate the output sampling voltage Vadc2 to obtain the second output voltage Vout2, and calculate the sampling temperature Tadc to obtain the second temperature Tdie2.

[0137] The second output current Iout2 can be calculated according to the following formula 1:

[0138]

[0139] Among them, I out2 is the second output current, I adc is the output sampling current, I calibration is the calibration current, I offset is the offset current, and Gain is the first constant.

[0140] The second coil voltage Vrect2 can be calculated according to the following formula 2:

[0141]

[0142] Among them, V rect2 is the second coil voltage, V adc1 is the coil sampling voltage, offset is the second constant, and Gain is the first constant.

[0143] The second output voltage Vout2 can be calculated according to the following formula 3:

[0144]

[0145] Among them, V out2 is the second output voltage, V adc2 is the output sampling voltage, offset is the second constant, and Gain is the first constant.

[0146] The second temperature Tdie2 can be calculated according to the following formula 4:

[0147]

[0148] Among them, T die2 is the second temperature, T adc is the sampling temperature.

[0149] In some examples, analog-to-digital conversion controller 610 may include arithmetic logic circuitry.

[0150] Reference Figure 6 , Figure 6 This is a schematic diagram of the structure of an arithmetic logic circuit provided in an embodiment of the present application. Figure 6 As shown, the arithmetic logic circuit may include a first calculation circuit ALU_0 and a second calculation circuit ALU_1.

[0151] Both the first calculation circuit ALU_0 and the second calculation circuit ALU_1 are connected to the first configuration information cfg. The first configuration information cfg is used to configure the basic operations performed by the first calculation circuit ALU_0 or the second calculation circuit ALU_1. The first input end of the first calculation circuit ALU_0 is used to receive the first physical parameter parameter0. The first physical parameter parameter0 is the second input end of the first calculation circuit ALU_0 is used to receive the second physical parameter parameter1. The output end of the first calculation circuit ALU_0 is connected to the first input end of the second calculation circuit ALU_1. The second input end of the second calculation circuit ALU_1 is used to receive the third physical parameter parameter2. The second calculation circuit ALU_1 is used to output the calculation result.

[0152] The first configuration information cfg may include first configuration information cfg0 and first configuration information cfg1.

[0153] Among them, the basic operation can be a multiplication operation or a division operation, and the embodiments of the present application do not make specific limitations on this.

[0154] The arithmetic logic unit can use the first calculation circuit ALU_0 to perform the first multiplication operation or the first division operation in Formula 1, Formula 2, Formula 3, or Formula 4, and use the second calculation circuit ALU_1 to perform the second multiplication operation or the second division operation in Formula 1, Formula 2, Formula 3, or Formula 4.

[0155] Among them, since the operation parameter of the second calculation circuit ALU_1 is the operation result of the first calculation circuit ALU_0, the arithmetic logic circuit can quickly complete continuous multiplication and division operations, continuous division and multiplication operations, continuous multiplication and multiplication operations, and continuous division and division operations.

[0156] When the analog-to-digital conversion controller 610 is in the calculation state CALCULATE, the analog-to-digital conversion controller 610 can execute the first multiplication operation or the first division operation, and the second multiplication operation or the second division operation in Formula 1, Formula 2, Formula 3, or Formula 4 through the arithmetic logic circuit. In this way, the analog-to-digital conversion controller 610 can quickly obtain the second output current Iout2, the second coil voltage Vrect2, the second output voltage Vout2, and the second temperature Tdie2.

[0157] Among them, because the arithmetic logic circuit uses a high-speed clock, the arithmetic logic circuit has a faster calculation speed. In addition, the arithmetic logic circuit occupies a very small area, and the calculation results are also more accurate.

[0158] When the analog-to-digital conversion controller 610 executes the first multiplication operation and the second division operation in Formula 1 through the arithmetic logic circuit, the first physical parameter parameter0 is I adc -I calibration -I offset , the second physical parameter parameter1 is The third physical parameter parameter2 is the first constant Gain.

[0159] When the analog-to-digital conversion controller 610 executes the first multiplication operation and the second division operation in Formula 2 through the arithmetic logic circuit, the first physical parameter parameter0 is V adc1 -offset, the second physical parameter parameter1 is the first constant Gain, and the third physical parameter parameter2 is

[0160] When the analog-to-digital conversion controller 610 executes the first multiplication operation and the second division operation in Formula 3 through the arithmetic logic circuit, the first physical parameter parameter0 is V adc2 -offset, the second physical parameter parameter1 is the first constant Gain, and the third physical parameter parameter2 is

[0161] When the analog-to-digital conversion controller 610 executes the first multiplication operation and the second division operation in Formula 4 through the arithmetic logic circuit, the first physical parameter parameter0 is T adc1 , the second physical parameter parameter1 is -741, and the third physical parameter parameter2 is 1000.

[0162] Based on the description of the above embodiment, a possible implementation of the wireless charging receiving circuit 200 is exemplified. Figure 3 As shown, the wireless charging receiving circuit 200 may include: a basic power distribution state machine 210 , an amplitude shift keying circuit 220 and a frequency shift keying demodulation circuit 230 .

[0163] The basic power distribution state machine 210 is connected to the analog-to-digital conversion controller 610 and the amplitude shift keying circuit 220 respectively. The amplitude shift keying circuit 220 and the frequency shift keying demodulation circuit 230 are both connected to the IIC bus.

[0164] After the wireless charging receiving circuit 200 is started, when the wireless charging receiving circuit 200 is in the communication state:

[0165] The basic power distribution state machine 210 may obtain the second coil voltage Vrect2 and the second output current Iout2 from the analog-to-digital conversion controller 610 , so that the basic power distribution state machine 210 may obtain the second coil voltage Vrect2 and the second output current Iout2 .

[0166] In this manner, the basic power profile state machine 210 can generate a first data packet, namely, an ASK data packet, according to the Qi protocol based on the second coil voltage Vrect2 and the second output current Iout2. Furthermore, the basic power profile state machine 210 can send the first data packet to the amplitude shift keying circuit 220, so that the amplitude shift keying circuit 220 can receive the first data packet.

[0167] In this way, the amplitude shift keying circuit 220 can generate and send the carrier modulation signal ASK_M according to the first data packet to send the first data packet.

[0168] Furthermore, the frequency shift keying demodulation circuit 230 can receive the first feedback data packet corresponding to the first data packet, implement communication with the wireless charging receiving end, and enable the wireless charging system 1000 to perform wireless energy transmission.

[0169] Among them, after the wireless charging receiving circuit 200 is started, the basic power distribution state machine 210 automatically starts and runs, and when the wireless charging receiving circuit 200 is in the communication state, there is no need for the application processor AP to participate. Even if the electronic device containing the wireless charging system 1000 is in the off state, that is, in the scenario of a dead battery, it can still be completed automatically.

[0170] In some examples, the first data packet may include: a signal strength data packet, a device identification data packet, a configuration data packet, a control error data packet, and a received power data packet.

[0171] The basic power profile state machine 210 can obtain a signal strength data packet based on the second coil voltage Vrect2. Furthermore, the basic power profile state machine 210 can sequentially send the signal strength data packet, the device identification data packet, and the configuration data packet to the amplitude shift keying circuit 220, thereby sequentially transmitting the signal strength data packet, the device identification data packet, and the configuration data packet via the carrier modulation signal ASK_M.

[0172] After the signal strength data packet, device identification data packet, and configuration data packet are sequentially transmitted, the basic power distribution state machine 210 can calculate a control error data packet based on the second coil voltage Vrect2 and the target coil voltage Vrect-target. Furthermore, the basic power distribution state machine 210 can send the control error data packet to the amplitude shift keying circuit 220, which transmits the control error data packet via the carrier modulation signal ASK_M. Alternatively, the basic power distribution state machine 210 can calculate a received power data packet based on the second coil voltage Vrect2 and the second output current Iout2. Furthermore, the basic power distribution state machine 210 can send a received power data packet to the amplitude shift keying circuit 220, which transmits the received power data packet via the carrier modulation signal ASK_M.

[0173] The strength (SS) data packet can be calculated according to the following formula 5, the control error (CE) data packet can be calculated according to the following formula 6, and the received power (RP) data packet can be calculated according to the following formula 7:

[0174] Val1=V rect2 ×256 / 10000 Formula 5

[0175] Val2=(V rect-target -V rect2 )×128 / 5000Formula 6

[0176]

[0177] Among them, Val1 is the voltage corresponding to the strength (SS) data packet, V rect2 is the second coil voltage, Val2 is the voltage corresponding to the control error (CE) data, V rect-target is the target coil voltage, I out2 is the second output current.

[0178] The following combination Figure 7 and Figure 8 , Figure 7 A schematic diagram of the working process of a basic power distribution state machine in a wireless charging receiving circuit provided in an embodiment of the present application; Figure 8 This is a timing diagram of the operation of a basic power distribution state machine in a wireless charging receiving circuit provided in an embodiment of the present application. The working principle of the basic power distribution state machine 210 is described in detail as follows:

[0179] like Figure 7As shown, after the wireless charging system 1000 is powered on, the basic power distribution state machine 210 begins in the idle state IDLE3 and waits for the wake-up (Twake) time before calculating and sending a signal strength (SS) packet. After completing the SS packet, the basic power distribution state machine 210 waits for a preset time, Tstart, and then sequentially sends a device identification (ID) packet and a configuration (CFG) packet.

[0180] Among them, Figure 8 As shown, after the signal strength (SS) data packet, the device identification (ID) data packet and the configuration (CFG) data packet are respectively sent, the corresponding interrupt indication signal INT is all at a low level, indicating that the signal strength (SS) data packet is sent, the device identification (ID) data packet is sent and the configuration (CFG) data packet is sent.

[0181] like Figure 7 As shown, after the configuration (CFG) data packet is sent, the wireless charging system 1000 enters the energy transmission stage. In this stage, the basic power distribution state machine 210 can wait for the configured interval time Tnext, and then calculate and send the control error (CE) data packet or the received power (RP) data packet in sequence through the switch SWITCH according to the configured interval time Tnext.

[0182] Among them, Figure 8 As shown in FIG, when the configuration (CFG) packet is sent, the interrupt indication signal INT is low, indicating that the configuration (CFG) packet has been sent. At the same time, the status indication signal PG changes from low to high, indicating that the wireless charging system 1000 has entered the energy transfer phase.

[0183] In addition, if Figure 8 As shown in FIG, after a control error (CE) data packet is sent, the output voltage VOUT of the wireless charging system begins to increase.

[0184] The time between sending each control error (CE) data packet or each received power (RP) data packet is the interval time Tnext.

[0185] During the process of sequentially calculating and sending a control error (CE) data packet or a received power (RP) data packet, the application processor AP may actively interrupt the process by sending a private (PP) data packet.

[0186] The calculation of the signal strength (SS) data packet, the control error (CE) data packet, or the received power (RP) data packet may reuse an arithmetic logic circuit.

[0187] Based on the description of the above embodiment, a possible implementation of the wireless charging transmitting circuit 100 is exemplified. Figure 3 As shown, the wireless charging transmitting circuit 100 may include: a pulse width modulation circuit 110 and an amplitude shift keying demodulation circuit 120 .

[0188] The pulse width modulation circuit 110 and the amplitude shift keying demodulation circuit 120 are both connected to the IIC bus.

[0189] After the wireless charging transmitting circuit 100 is started, when the wireless charging transmitting circuit 100 is in the communication state:

[0190] After receiving the configuration signal sent by the application processor AP through the IIC communication circuit 300 , the pulse width modulation circuit 110 may receive the to-be-sent data and the second configuration information sent by the application processor AP.

[0191] The configuration signal is used to set parameters of the pulse width modulation circuit 110 to control the full-bridge circuit to perform energy transmission.

[0192] In this way, the pulse width modulation circuit 110 can package the data to be transmitted to obtain a second data packet, namely an FSK data packet. In addition, the pulse width modulation circuit 110 can generate and send a pulse width modulation signal PWM according to the second configuration information to send the second data packet.

[0193] Furthermore, the ASK demodulation circuit 120 may receive a second feedback data packet of the second data packet, and may demodulate and store the second feedback data packet.

[0194] In some embodiments, the wireless charging transmitting circuit 100 may further include: a Q-value detection circuit 130 and a foreign object detection circuit 140 .

[0195] The Q-value detection circuit 130 and the foreign object detection circuit 140 are both connected to the IIC bus.

[0196] Based on the description of the above embodiment, a possible implementation of the pulse width modulation circuit 110 is exemplified. Figure 3 As shown, the pulse width modulation circuit 110 may include: a first buffer 113 , a frequency shift keying circuit 112 and a pulse width modulation signal output circuit 112 .

[0197] The first buffer 113 and the pulse width modulation signal output circuit 112 are both connected to the IIC bus. The first buffer 113 is further connected to the pulse width modulation signal output circuit 112 via the frequency shift keying circuit 112 .

[0198] The first buffer 113 can receive the data to be sent and the second configuration information, and can send the data to be sent and the second configuration information to the frequency shift keying circuit 112 so that the frequency shift keying circuit 112 can obtain the data to be sent and the second configuration information.

[0199] In this way, the frequency shift keying circuit 112 can package the data to be transmitted to obtain a second data packet. Furthermore, the frequency shift keying circuit 112 can adjust the duty cycle and frequency of the pulse width modulation signal PWM in the pulse width modulation signal output circuit 112 by shifting and determining whether the binary bit is 0 or 1 based on the second configuration information to generate the pulse width modulation signal PWM, thereby transmitting the second data packet.

[0200] Based on the description of the above embodiment, an exemplary possible implementation of the amplitude shift keying demodulation circuit 120 is as follows. Figure 3 As shown, the amplitude shift keying demodulation circuit 120 may include: a plurality of second buffers 122 and a plurality of amplitude shift keying demodulation components 121 .

[0201] The plurality of second buffers 122 are connected to the IIC bus, and the plurality of second buffers 122 are also connected one by one to the plurality of amplitude shift keying demodulation components 121 .

[0202] The multiple ASK demodulation components 121 can receive the second feedback data packet, demodulate the second feedback data packet, and store the demodulated second feedback data packet in the corresponding multiple second buffers 122 .

[0203] The demodulation and storage of the second feedback data packet are realized by using multiple second buffers 122 and multiple amplitude shift keying demodulation components 121, which can improve the accuracy and efficiency of demodulation.

[0204] Based on the description of the above embodiment, another possible implementation of the wireless charging system 1000 is exemplified. Figure 3 As shown, the wireless charging system 1000 may further include an interruption circuit 600 .

[0205] The application processor AP is connected to the IIC bus via the interrupt circuit 600 .

[0206] After receiving the first feedback data packet, the FSK demodulation circuit 230 may send a first interrupt signal to the application processor AP through the interrupt circuit 600 , so that the application processor AP may determine that the communication between the wireless charging system 100 and the wireless charging receiving end is completed.

[0207] Alternatively, after sending the second data packet, the pulse width modulation circuit 110 may send a second interrupt signal to the application processor AP through the interrupt circuit 600 , so that the application processor AP can determine that the sending of the second data packet is complete.

[0208] Alternatively, after demodulating and storing the second feedback data packet, the amplitude shift keying demodulation circuit 120 may send a third interrupt signal to the application processor AP through the interrupt circuit 600 , so that the application processor AP can independently determine the received second feedback data packet.

[0209] An embodiment of the present application also provides a wireless charging chip module, which includes: an IIC communication interface, a wireless charging receiving chip, a wireless charging transmitting chip, a system control chip and a detection chip.

[0210] The IIC communication interface is connected to the wireless charging transmitter chip and the wireless charging receiver chip through the IIC bus. The IIC communication interface and the system control chip are also connected to the application processor. The system control chip is also connected to the wireless charging transmitter chip, the wireless charging receiver chip and the detection chip.

[0211] The detection chip is used to send a detection signal to the system control chip when the wireless charging chip module is in standby mode. The detection signal is used to indicate that a wireless charging device is connected to the wireless charging chip module.

[0212] The system control chip is configured to send a first indication signal to the wireless charging transmitting chip; or, upon receiving a detection signal or a first start signal sent by the application processor, transmit a second indication signal to the wireless charging receiving chip.

[0213] The first start signal is used to control the wireless charging chip module to enter the wireless charging receiving mode from the standby mode.

[0214] The wireless charging transmitting chip is used to start according to the first indication signal and the control signal after receiving the control signal sent by the application processor through the IIC communication interface, so as to enable the wireless charging chip module to enter the wireless charging transmitting mode.

[0215] The wireless charging receiving chip is configured to start up according to the second indication signal, so as to start up the basic power distribution state machine in the wireless charging receiving chip, so that the wireless charging chip module enters the wireless charging receiving mode.

[0216] In some examples, the wireless charging chip module also includes: a common chip; the common chip includes: an analog-to-digital conversion control chip and a linear voltage regulation control chip.

[0217] The analog-to-digital conversion control chip is respectively connected to the system control chip, the wireless charging receiving chip and the linear voltage regulator control chip, and the analog-to-digital conversion control chip is also connected to the IIC bus.

[0218] The analog-to-digital conversion control chip is used to start before the wireless charging chip module enters the standby mode.

[0219] The analog-to-digital conversion control chip is also used to obtain a second indication signal from the system control chip when the wireless charging chip module is in the wireless charging receiving mode, and control the corresponding linear voltage regulator circuit to start through the linear voltage regulator control chip according to the second indication signal.

[0220] The analog-to-digital conversion control chip is further used to, when the wireless charging transmitting chip or the wireless charging receiving chip is in a communication state and the frequency shift keying circuit in the wireless charging transmitting chip or the amplitude shift keying circuit in the wireless charging receiving chip is not working, sequentially sample and calculate the first output current and the first coil voltage of the wireless charging chip module to obtain the second output current and the second coil voltage respectively.

[0221] The wireless charging chip module provided in the embodiment of the present application has the same beneficial effects as the wireless charging system provided in the embodiment of the present application, and will not be described in detail here.

[0222] An embodiment of the present application also provides an electronic device, including: a wireless charging chip module.

[0223] In this application, electronic devices may include but are not limited to: mobile phones, routers, vehicle-mounted devices and smart home devices.

[0224] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be repeated here.

[0225] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A wireless charging system, characterized in that: The wireless charging system includes: an IIC communication circuit, a wireless charging receiving circuit, a wireless charging transmitting circuit, a system control circuit and a detection circuit; The IIC communication circuit is connected to the wireless charging transmitting circuit and the wireless charging receiving circuit respectively through the IIC bus. The IIC communication circuit and the system control circuit are also connected to the application processor. The system control circuit is also connected to the wireless charging transmitting circuit, the wireless charging receiving circuit and the detection circuit respectively. The detection circuit is configured to send a detection signal to the system control circuit when the wireless charging system is in a standby mode, wherein the detection signal is used to indicate that a wireless charging device is connected to the wireless charging system; The system control circuit is configured to send a first instruction signal to the wireless charging transmitting circuit; or, upon receiving the detection signal or a first start signal sent by the application processor, transmit a second instruction signal to the wireless charging receiving circuit, wherein the first start signal is configured to control the wireless charging system to enter a wireless charging receiving mode from the standby mode; The wireless charging transmitting circuit is configured to start according to the first indication signal and the control signal after receiving the control signal sent by the application processor through the IIC communication circuit, so as to enable the wireless charging system to enter the wireless charging transmitting mode; The wireless charging receiving circuit is configured to start up according to the second indication signal, so as to start up a basic power distribution state machine in the wireless charging receiving circuit, thereby enabling the wireless charging system to enter the wireless charging receiving mode.

2. The system according to claim 1, wherein: The wireless charging system further includes: a common circuit, the common circuit including: an analog-to-digital conversion controller and a linear voltage regulator controller; The analog-to-digital conversion controller is respectively connected to the system control circuit, the wireless charging receiving circuit and the linear voltage regulator controller, and the analog-to-digital conversion controller is also connected to the IIC bus; The analog-to-digital conversion controller is configured to start before the wireless charging system enters the standby mode; The analog-to-digital conversion controller is further configured to, when the wireless charging system is in the wireless charging receiving mode, obtain the second indication signal from the system control circuit, and control the corresponding linear voltage regulator circuit to start up through the linear voltage regulator controller according to the second indication signal; The analog-to-digital conversion controller is further configured to, when the wireless charging transmitting circuit or the wireless charging receiving circuit is in a communication state, and when the frequency shift keying circuit in the wireless charging transmitting circuit or the amplitude shift keying circuit in the wireless charging receiving circuit is not operating, sequentially sample and calculate the first output current and the first coil voltage of the wireless charging system to obtain the second output current and the second coil voltage, respectively.

3. The system according to claim 2, characterized in that The analog-to-digital conversion controller is specifically configured to, when the frequency shift keying circuit or the amplitude shift keying circuit is not operating, sample the first output current to obtain an output sampling current; and before the linear voltage regulator circuit is started, sample the first output current according to a verification enable signal to obtain an offset current; and after the linear voltage regulator circuit is started, sample the first output current according to a verification enable signal to obtain a verification current; and after the sampling of the first output current is completed, sample the first coil voltage to obtain a coil sampling voltage; The analog-to-digital conversion controller is further specifically configured to calculate the output sampling current, the offset current, and the verification current to obtain the second output current, and to calculate the coil sampling voltage to obtain the second coil voltage.

4. The system according to claim 3, characterized in that The analog-to-digital conversion controller is further specifically configured to, after obtaining the coil sampling voltage, sequentially sample the first output voltage and the first temperature of the wireless charging system to obtain the output sampling voltage and the sampling temperature; and, after calculating the second coil voltage, sequentially calculate the output sampling voltage and the sampling temperature to obtain the second output voltage and the second temperature.

5. The system according to claim 4, characterized in that The second output current is calculated according to the following formula 1, the second coil voltage is calculated according to the following formula 2, the second output voltage is calculated according to the following formula 3, and the second temperature is calculated according to the following formula 4: Among them, I out2 For the second output current, I adc is the output sampling current, I calibration is the calibration current, I offset is the offset current, Gain is the first constant; Among them, V rect2 is the second coil voltage, V adc1 is the coil sampling voltage, offset is the second constant, and Gain is the first constant; Among them, V out2 For the second output voltage, V adc2 is the output sampling voltage, offset is the second constant, and Gain is the first constant; Among them, T die2 is the second temperature, T adc is the sampling temperature.

6. The system according to claim 5, characterized in that The analog-to-digital conversion controller includes an arithmetic logic circuit, and the arithmetic logic circuit includes a first calculation circuit and a second calculation circuit; The first calculation circuit and the second calculation circuit are both connected to first configuration information, the first configuration information is used to configure a basic operation performed by the first calculation circuit or the second calculation circuit, a first input end of the first calculation circuit is used to receive a first physical parameter, the first physical parameter is a second input end of the first calculation circuit is used to receive a second physical parameter, an output end of the first calculation circuit is connected to the first input end of the second calculation circuit, the second input end of the second calculation circuit is used to receive a third physical parameter, and the second calculation circuit is used to output a calculation result; The arithmetic logic unit is used to use the first calculation circuit to perform the first multiplication operation or the first division operation in Formula 1, Formula 2, Formula 3, or Formula 4, and to use the second calculation circuit to perform the second multiplication operation or the second division operation in Formula 1, Formula 2, Formula 3, or Formula 4.

7. The system according to claim 2, wherein: The wireless charging receiving circuit includes: a basic power distribution state machine, an amplitude shift keying circuit and a frequency shift keying demodulation circuit; The basic power distribution state machine is connected to the analog-to-digital conversion controller and the amplitude shift keying circuit respectively, and the amplitude shift keying circuit and the frequency shift keying demodulation circuit are both connected to the IIC bus; After the wireless charging receiving circuit is started, when the wireless charging receiving circuit is in a communication state: The basic power distribution state machine is configured to obtain the second coil voltage and the second output current from the analog-to-digital conversion controller; The basic power distribution state machine is further configured to generate the first data packet according to the second coil voltage and the second output current in accordance with the Qi protocol, and send the first data packet to the amplitude shift keying circuit; The amplitude shift keying circuit is used to generate and send a carrier modulation signal according to the first data packet to send the first data packet; The frequency shift keying demodulation circuit is used to receive a first feedback data packet corresponding to the first data packet.

8. The system according to claim 7, characterized in that The first data packet includes: a signal strength data packet, a device identification data packet, a configuration data packet, a control error data packet and a received power data packet; The basic power distribution state machine is specifically configured to obtain the signal strength data packet according to the second coil voltage, and sequentially send the signal strength data packet, the device identification data packet, and the configuration data packet to the amplitude shift keying circuit, so as to sequentially send the signal strength data packet, the device identification data packet, and the configuration data packet via the carrier modulation signal; The basic power distribution state machine is further specifically used to calculate the control error data packet according to the second coil voltage and the target coil voltage after the signal strength data packet, the device identification data packet and the configuration data packet are sent in sequence, and send the control error data packet to the amplitude shift keying circuit to send the control error data packet through the carrier modulation signal, or calculate the received power data packet according to the second coil voltage and the second output current, and send the received power data packet to the amplitude shift keying circuit to send the received power data packet through the carrier modulation signal.

9. The system according to claim 1, wherein: The wireless charging transmitting circuit includes: a pulse width modulation circuit and an amplitude shift keying demodulation circuit; The pulse width modulation circuit and the amplitude shift keying demodulation circuit are both connected to the IIC bus; After the wireless charging transmitting circuit is started, when the wireless charging transmitting circuit is in a communication state: The pulse width modulation circuit is configured to receive the to-be-sent data and the second configuration information sent by the application processor after receiving a configuration signal sent by the application processor via the IIC communication circuit, wherein the configuration signal is used to set parameters of the pulse width modulation circuit to control the full-bridge circuit to perform energy transmission; The pulse width modulation circuit is further configured to package the data to be transmitted to obtain a second data packet, and generate and send a pulse width modulation signal according to the second configuration information to transmit the second data packet; The amplitude shift keying demodulation circuit is configured to receive a second feedback data packet of the second data packet, and demodulate and store the second feedback data packet.

10. The system according to claim 9, characterized in that The pulse width modulation circuit includes: a first buffer, a frequency shift keying circuit and a pulse width modulation signal output circuit; The first buffer and the pulse width modulation signal output circuit are both connected to the IIC bus, and the first buffer is further connected to the pulse width modulation signal output circuit via the frequency shift keying circuit; The first buffer is configured to receive the data to be sent and the second configuration information, and send the data to be sent and the second configuration information to the frequency shift keying circuit; The frequency shift keying circuit is used to package the data to be sent to obtain a second data packet, and adjust the duty cycle and frequency of the pulse width modulation signal in the pulse width modulation signal output circuit according to the second configuration information to generate the pulse width modulation signal.

11. The system according to claim 9, wherein: The amplitude shift keying demodulation circuit includes: a plurality of second buffers and a plurality of amplitude shift keying demodulation components; The plurality of second buffers are connected to the IIC bus, and the plurality of second buffers are also connected one by one to the plurality of amplitude shift keying demodulation components; The multiple amplitude shift keying demodulation components are used to receive the second feedback data packet, demodulate the second feedback data packet, and store the demodulated second feedback data packet in the corresponding multiple second buffers.

12. The system according to claim 7 or 9, characterized in that The wireless charging system further includes: an interrupt circuit; The application processor is connected to the IIC bus via the interrupt circuit; The frequency shift keying demodulation circuit is further configured to send a first interrupt signal to the application processor through the interrupt circuit after receiving the first feedback data packet; Alternatively, the pulse width modulation circuit is further configured to send a second interrupt signal to the application processor through the interrupt circuit after sending the second data packet; Alternatively, the amplitude shift keying demodulation circuit is further configured to send a third interrupt signal to the application processor through the interrupt circuit after demodulating and storing the second feedback data packet.

13. The system according to any one of claims 1 to 11, characterized in that: The system control circuit is further configured to, when the wireless charging system is in the wireless charging receiving mode, transmit a third indication signal to the wireless charging receiving circuit upon receiving a second start signal sent by the application processor, wherein the second start signal is configured to enter the standby mode from the wireless charging receiving mode; The wireless charging receiving circuit is configured to shut down according to the third indication signal, so as to shut down the basic power distribution state machine.

14. A wireless charging chip module, characterized in that: The wireless charging chip module includes: an IIC communication interface, a wireless charging receiving chip, a wireless charging transmitting chip, a system control chip and a detection chip; The IIC communication interface is connected to the wireless charging transmitter chip and the wireless charging receiver chip respectively through the IIC bus. The IIC communication interface and the system control chip are also connected to the application processor. The system control chip is also connected to the wireless charging transmitter chip, the wireless charging receiver chip and the detection chip respectively. The detection chip is configured to send a detection signal to the system control chip when the wireless charging chip module is in standby mode, wherein the detection signal is used to indicate that a wireless charging device is connected to the wireless charging chip module; The system control chip is configured to send a first indication signal to the wireless charging transmitting chip; or, upon receiving the detection signal or the first start signal sent by the application processor, transmit a second indication signal to the wireless charging receiving chip, wherein the first start signal is configured to control the wireless charging chip module to enter the wireless charging receiving mode from the standby mode; The wireless charging transmitting chip is configured to start according to the first indication signal and the control signal after receiving the control signal sent by the application processor through the IIC communication interface, so as to enable the wireless charging chip module to enter the wireless charging transmitting mode; The wireless charging receiving chip is configured to start up according to the second indication signal, so as to start up a basic power distribution state machine in the wireless charging receiving chip, thereby enabling the wireless charging chip module to enter the wireless charging receiving mode.

15. The wireless charging chip module according to claim 14, wherein: The wireless charging chip module further includes: a common chip; the common chip includes: an analog-to-digital conversion control chip and a linear voltage regulation control chip; The analog-to-digital conversion control chip is respectively connected to the system control chip, the wireless charging receiving chip and the linear voltage stabilization control chip, and the analog-to-digital conversion control chip is also connected to the IIC bus; The analog-to-digital conversion control chip is configured to start before the wireless charging chip module enters the standby mode; The analog-to-digital conversion control chip is further configured to obtain the second indication signal from the system control chip when the wireless charging chip module is in the wireless charging receiving mode, and control the corresponding linear voltage regulator circuit to start up through the linear voltage regulator control chip according to the second indication signal; The analog-to-digital conversion control chip is further configured to, when the wireless charging transmitting chip or the wireless charging receiving chip is in a communication state, sequentially sample and calculate the first output current and the first coil voltage of the wireless charging chip module when the frequency shift keying circuit in the wireless charging transmitting chip or the amplitude shift keying circuit in the wireless charging receiving chip is not working, to obtain the second output current and the second coil voltage, respectively.

16. An electronic device, characterized in that: include: The wireless charging chip module according to claim 14 or 15.

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