Full-localization navigation resolving system based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor)

Abstract

The invention relates to a full-localization navigation resolving system based on an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). The full-localization navigation resolving system comprises an FPG A chip and a DSP chip, the FPGA chip is connected with the DSP chip, and the FPGA chip is responsible for collecting, caching and preprocessing IMU and GPS data and transmitting the data to the DSP chip through DMA and an interrupt mechanism; the DSP chip is connected with external equipment through the Ethernet controller, the DSP chip is responsible for real-time navigation resolving tasks, outputs real-time attitude, speed and position information by adopting an extended Kalman filtering algorithm and combining IMU and GPS data, and performs data interaction with an external upper computer or a control system through the Ethernet controller chip. According to the invention, the bottleneck of a localized high-precision navigation resolving system is solved, and the real-time performance, the stability and the autonomous controllability are higher by optimizing hardware resource configuration, a power management scheme and a data flow design.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of inertial navigation solution, and relates to a navigation solution system, in particular, a navigation solution system based on FPGA and DSP. BACKGROUND

[0002] With the continuous development of Global Positioning System (GPS) and Inertial Navigation System (INS) technology, navigation solution systems have been widely applied in the fields of aviation, aerospace, unmanned driving, intelligent manufacturing, etc. However, the existing navigation solution systems generally have the following technical bottlenecks:

[0003] 1. Technical bottleneck of high-precision navigation solution

[0004] At present, many navigation solution systems rely on foreign processor platforms. Although these platforms have high computing power, they are mainly aimed at high-end markets, with high cost and high technical threshold. In addition, the dependence on foreign core technology makes the system face risks in actual application, especially the risk of supply chain problems or technical blockade in critical moments. Therefore, using a self-controlled domestic processor platform can effectively avoid these risks and improve the autonomy and security of China's navigation solution technology.

[0005] 2. Insufficient application of domestic FPGA and DSP chips in navigation field

[0006] Although domestic FPGA and DSP chips have gradually developed and been applied in recent years, there are still many challenges in the field of high-precision navigation solution. The existing domestic FPGA and DSP chips are often not comparable to international advanced products in terms of computing power, data transmission rate, power consumption control, etc. For example, although some domestic FPGA chips have high logic units, they often face performance bottlenecks under the demand of high parallelism and high-speed data transmission. At the same time, the floating-point operation capability and system scheduling efficiency of domestic DSP chips also have certain room for improvement.

[0007] 3. Interoperability and ecological problems of domestic chips

[0008] Although domestic FPGA and DSP chips are gradually maturing, the compatibility of their hardware interfaces and ecological systems still needs to be further improved. There are great interface differences between existing chips, which makes data exchange, control and scheduling between different platforms more difficult, reducing the flexibility and expandability of the system. In addition, since the ecological system of domestic chips is still in the development stage, the existing development tools, debugging tools and algorithm libraries are relatively limited, with high use threshold, which to some extent affects the widespread application of domestic FPGA and DSP chips in the field of navigation solution.

[0009] Through the analysis of the above problems, the problems of insufficient domestic chips, dependence on core technology and high cost in the existing navigation solution system are proposed, and a navigation solution system based on the cooperative work of domestic FPGA and DSP chips is proposed.

[0010] Through retrieval, no existing technical disclosure documents similar to the present application are found. SUMMARY

[0011] The purpose of the present application is to overcome the shortcomings of the prior art, provide a navigation solution system based on FPGA and DSP, utilize the cooperative work of Fudan Microelectronics JFMK50 series FPGA chips and Galaxy Flying FT-C6748 series DSP chips, combine domestic power management chips, Flash memory chips, Ethernet chips and serial chips, etc., and solve the bottleneck of domestic high-precision navigation solution system. Through optimizing hardware resource configuration, power management scheme and data flow design, the bottleneck in the prior art is overcome, and higher real-time performance, stability and autonomous controllability are achieved, which can be applied in a wider range of scenarios.

[0012] The present application solves the practical problems by adopting the following technical solutions:

[0013] A navigation solution system based on FPGA and DSP, comprising: an FPGA chip, a DSP chip;

[0014] The FPGA chip and the DSP chip are connected, the FPGA chip is responsible for collecting, caching and preprocessing IMU and GPS data, and the data is transmitted to the DSP chip through DMA and interrupt mechanism;

[0015] The DSP chip is connected with external devices through an Ethernet controller, the DSP chip is responsible for real-time navigation solution task, adopts extended Kalman filtering algorithm, combines IMU and GPS data, outputs real-time attitude, speed and position information, and interacts with external host computer or control system through the Ethernet controller chip.

[0016] Moreover, the FPGA chip and the DSP chip are connected through an EMIFA parallel bus to realize real-time transmission of data.

[0017] Moreover, the external storage of the FPGA and DSP chips adopts Flash memory chip SM25Q128 for data storage.

[0018] Moreover, the power supply module of the FPGA and DSP chips adopts SM4644 power management chip to supply power.

[0019] Moreover, the power management chip includes multiple power supply rails, and the PGOOD signal and the RUN pin of the SM4644 power management chip ensure that the power supply groups of the FPGA and the DSP chip are started in sequence.

[0020] Moreover, the FPGA collects external IMU and GPS information through a serial chip integrated with an isolation power supply.

[0021] Moreover, the FPGA chip sends a 1kHz synchronization clock to the three fiber-optic gyroscopes, and the fiber-optic gyroscopes latch data and send the data to the FPGA chip at the rising edge of the synchronization clock; the FPGA chip is connected to the serial chip through an extended I / O pin, and is used for receiving three-way fiber-optic gyroscope data.

[0022] Moreover, the FPGA chip is also connected to an accelerometer force feedback loop, the accelerometer force feedback loop adopts a binary width adjustment loop, the width adjustment frequency is 1kHz, and the sampling frequency of the accelerometer is 1kHz; after the FPGA chip collects fiber-optic gyroscope and accelerometer data at 1kHz, the FPGA chip obtains inertial element data with a frequency of 200Hz through accumulation or subsampling compensation, stores the data in an on-chip RAM, and sends the data to a DSP chip through an EMIFA bus for real-time calculation.

[0023] Advantages and beneficial effects of the present application:

[0024] 1. The present application proposes a nationalization navigation solution system based on FPGA and DSP, which utilizes the parallel processing capability of the FPGA chip and the floating point operation capability of the DSP chip to ensure that the system can still maintain excellent performance under high-frequency navigation solution tasks.

[0025] 2. The solution system of the present application involves all components provided by domestic manufacturers, avoiding the risk of foreign technology blockade and improving the technical autonomy of China in the field of high-precision navigation solution.

[0026] 3. The present application can realize high-precision and high-efficiency navigation solution, and is a highly autonomous and controllable technical solution, which has wide application in the field of high-precision navigation solution with nationalization demand. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is the overall structure block diagram of the nationalization navigation solution system based on FPGA and DSP of the present application;

[0028] Figure 2 is the power management chip electrical schematic diagram of the present application for meeting the power-on sequence of the system;

[0029] Figure 3 is the working timing diagram of the nationalization navigation solution system based on FPGA and DSP of the present application. DETAILED DESCRIPTION

[0030] The application will be further described in detail below with reference to the accompanying drawings:

[0031] A navigation solution system based on FPGA and DSP, as shown in the figure, comprises an FPGA chip and a DSP chip. Figure 1 The FPGA chip and the DSP chip are connected, the FPGA chip is responsible for collecting, caching and preprocessing IMU and GPS data, and the data is transmitted to the DSP chip through DMA and interrupt mechanism.

[0032] The FPGA chip and the DSP chip are connected, the FPGA chip is responsible for collecting, caching and preprocessing IMU and GPS data, and the data is transmitted to the DSP chip through DMA and interrupt mechanism.

[0033] The DSP chip is connected with external devices through an Ethernet controller, the DSP chip is responsible for real-time navigation solution task, adopts extended Kalman filtering algorithm, combines IMU and GPS data, and outputs real-time attitude, speed and position information, and performs data interaction with external host computer or control system through the Ethernet controller chip.

[0034] In the embodiment, the FPGA chip and the DSP chip are connected through an EMIFA parallel bus to realize real-time transmission of data.

[0035] In the embodiment, the external storage of the FPGA and DSP chips adopts a Flash memory chip SM25Q128 to store data.

[0036] In the embodiment, the power supply module of the FPGA and DSP chips adopts an SM4644 power management chip to supply power.

[0037] In the embodiment, the power management chip comprises a plurality of power supply rails, and the PGOOD signal and the RUN pin of the SM4644 power management chip ensure that each power supply group of the FPGA and the DSP chip is started in sequence.

[0038] In the embodiment, the FPGA collects external IMU and GPS information through a serial chip integrated with an isolation power supply.

[0039] In the embodiment, the FPGA chip sends a 1kHz synchronization clock to three fiber gyroscopes, the fiber gyroscopes latch data at the rising edge of the synchronization clock and send the data to the FPGA chip; the FPGA chip is connected with the serial chip through an extended I / O pin to receive three-way fiber gyroscope data.

[0040] In the embodiment, the FPGA chip is also connected with an accelerometer force feedback loop, the accelerometer force feedback loop adopts a binary width adjustment loop, the width adjustment frequency is 1 kHz, the sampling frequency of the accelerometer is 1 kHz; after the FPGA chip collects the fiber-optic gyroscope and accelerometer data at 1 kHz, the inertia element data with a frequency of 200 Hz is obtained through accumulation or subsample compensation, the data is stored by using an on-chip RAM, and the DSP chip is sent through an EMIFA bus for real-time calculation.

[0041] The composition, function and role of each component in the system are further described as follows:

[0042] The core processor of the system adopts a domestic Fudan Microelectronics JFMK50 series FPGA chip and a Galaxy Flying Pigeon FT-C6748 series DSP chip, and realizes real-time data transmission and calculation functions through an EMIFA parallel bus.

[0043] The FPGA chip is responsible for collecting, caching and preprocessing IMU (accelerometer and fiber-optic gyroscope) and GPS data, and delivering the data to the DSP chip through a DMA and an interrupt mechanism, so as to ensure smooth data transmission and processing.

[0044] The DSP chip is responsible for real-time navigation calculation tasks, adopts an extended Kalman filter (EKF) algorithm, combines IMU and GPS data, outputs real-time attitude, speed and position information, and performs data interaction with an external host computer or a control system through an Ethernet controller chip.

[0045] The external storage of the FPGA and DSP chips adopts an SM25Q128 series Flash storage chip of Shenzhen Guomicroelectronics to store data, which can provide fast reading and writing functions and ensure high reliability of data.

[0046] The power supply of the system adopts an SM4644 power management chip of Shenzhen Guomicroelectronics, which can provide accurate power start timing control. The system includes multiple power supply rails (1.0 V, 1.1 V, 1.8 V, 3.3 V), and the PGOOD signal and the RUN pin of the SM4644 power management chip can ensure that each power supply group of the FPGA and the DSP chip is started in sequence, so as to avoid system failure caused by unstable power supply signals.

[0047] The system adopts a GLb2682 series integrated isolation power RS422 transceiver chip of Zhongke Geli Microelectronics to collect external IMU and GPS information, and the internal integrated isolation power serial chip can effectively improve the reliability of data transmission.

[0048] The system uses the CS5500 Ethernet controller chip from the 58th Institute of Electronic Science and Technology to achieve real-time communication between the DSP chip and the external host computer or control system, ensuring the rapid transmission of navigation solution results and efficient interaction with external systems.

[0049] The working principle of the present invention is:

[0050] A nationally produced navigation solution system based on FPGA and DSP, such as Figure 1 As shown, the system includes an FPGA chip, a DSP chip, a power management chip, a Flash memory chip, a serial communication chip, and an Ethernet controller chip. The FPGA chip and DSP chip are connected via an EMIFA parallel bus; the FPGA chip and DSP chip are each connected to the Flash chip via an SPI interface; the FPGA chip's external I / O pins are connected to the serial port chip; the DSP chip's external SPI interface is connected to the Ethernet controller chip; and the power management chip generates multiple power rails required by the system: 1.0V, 1.1V, 1.8V, and 3.3V.

[0051] The FPGA chip used is from the Fudan Microelectronics JFMK50 series, featuring 52,160 logic units, 210 user I / Os, and 2,700 KB of high-performance RAM, meeting the requirements of complex logic designs. The FPGA chip is responsible for collecting and preprocessing IMU (accelerometer, fiber optic gyroscope) and GPS data. Specific functions include transmitting a 1kHz synchronous clock to three fiber optic gyros, which latch data on the rising edge of the synchronous clock and transmit it to the FPGA chip. The FPGA chip extends a serial port controller through its I / O pins to receive data from three fiber optic gyroscopes (FOGs). The accelerometer signal is sampled at 1kHz and binary pulse-width modulation (PWM) is used to control the accelerometer force feedback loop. First, differential capacitance detection is performed through switch demodulation. System static errors are eliminated through integral amplification, and the control margin is improved through an analog correction network. The output voltage undergoes A / D conversion and is acquired by the FPGA to obtain a digital acceleration pulse signal. This signal is then modulated by the FPGA and output as a PWM control signal. Under the control of the PWM signal, a constant current source applies alternating positive and negative current to the accelerometer torquer via a polarity switch to achieve dynamic balance of the pendulum position. After acquiring FOG and accelerometer data at 1kHz, the FPGA chip obtains inertial element data at a frequency of 200Hz through accumulation or sub-sampling compensation. This data is stored in on-chip RAM and sent to the DSP chip via the EMIFA bus for real-time analysis.

[0052] The DSP chip selects Galaxy FT-C6748 series, whose main frequency can reach 460MHz, and operation capacity can reach 2700MFLOPS, satisfying high load floating point operation requirement. The DSP chip is responsible for executing navigation solution task, adopts high precision navigation algorithm such as extended Kalman filter (EKF), combines the accelerometer output information with the initial speed and position information of the carrier to obtain the current speed and position information of the carrier through integral solution, and further solves the required correction angular velocity of the platform tracking geographic coordinate system. The correction angular velocity obtained by the solution is used to correct the output data of the corresponding fiber optic gyroscope, and the platform is applied with the correction angular velocity through the stable loop, so that the platform coordinate system can track the geographic coordinate system in real time. Meanwhile, the DSP chip is connected with the Ethernet controller chip through SPI interface, and realizes data communication with external devices (such as host computer and control system).

[0053] The power management chip selects SM4644 series of Shenzhen Guo Microelectronics. It can provide multiple power rails (1.0V, 1.1V, 1.8V, 3.3V) meeting the system requirements, and realizes timing control of each power rail through PGOOD signal and RUN pin, ensuring stable start of each power supply group of FPGA and DSP chips in sequence. As shown in Figure 2 , after the power of SM4644 is turned on, the 1.0V core voltage of the FPGA chip is generated first, then the output signal PGOOD of the first road enables the second road voltage output, that is, the 1.8V auxiliary voltage of the FPGA chip. Finally, the output signal PGOOD of the second road enables the 1.1V core voltage and 3.3V I / O voltage of the DSP chip, and the power-on start is completed. Each power supply is configured with a capacitor array filter of 0.1μF and 47μF to ensure the reliability of the power supply signal.

[0054] The working timing diagram of the navigation solution system is shown in Figure 3 , clk1 is the 1kHz synchronization clock sent by the FPGA chip to the three fiber optic gyroscopes, and the rising edge is valid; clk2 is the 200Hz signal for triggering the DSP chip interrupt of the FPGA chip, and the falling edge is valid; clk3 is the 200Hz synchronization clock of the system to the outside, and the rising edge is valid. The three clocks are obtained by frequency division of the FPGA chip.

[0055] At the rising edge of clk1, the three fiber-optic gyroscopes start sending data, and the counter values of the three accelerometers are latched. After time t1, the FPGA receives three sets of gyro data and three sets of accelerometer data, which constitute a complete set of inertial element data, and the data is placed in the buffer of the FPGA chip. After five sets of inertial element data are collected, the FPGA chip starts the sub-sample compensation program, and after time t2, the sub-sample compensation is completed, and an interrupt signal is sent to the DSP chip at the falling edge of clk2. In the GPIO interrupt of the DSP chip, a calculation flag is set, and in the main program, the flag is judged. If it is correct, the data is received for navigation calculation, and after the calculation, the attitude information of the platform obtained by the calculation is sent to external equipment (such as a host computer and a control system). t3 is the calculation time of the DSP chip plus the transmission time of the attitude information.

[0056] It should be emphasized that the embodiments described in the present application are illustrative rather than restrictive, and therefore the present application includes but is not limited to the embodiments described in the specific embodiments. Any other embodiments derived by those skilled in the art according to the technical solutions of the present application also belong to the scope of protection of the present application.

Claims

1. A navigation solution system based on FPGA and DSP, characterized in that: Include: FPGA chip, DSP chip; The FPGA chip and DSP chip are connected, the FPGA chip is responsible for collecting, buffering and preprocessing IMU and GPS data, and the data is transmitted to the DSP chip through DMA and interrupt mechanism; The DSP chip is connected with external device through Ethernet controller, the DSP chip is responsible for real-time navigation solution task, adopts extended Kalman filtering algorithm, combines IMU and GPS data, outputs real-time attitude, speed and position information, and carries out data interaction with external host computer or control system through Ethernet controller chip.

2. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The FPGA chip and DSP chip are connected through EMIFA parallel bus, and the real-time transmission of data is realized.

3. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The external storage of the FPGA and DSP chips adopts Flash memory chip SM25Q128 for data storage.

4. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The power supply module of the FPGA chip and DSP chip adopts SM4644 power management chip to supply power for them.

5. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The power management chip includes a plurality of power supply rails, and the PGOOD signal and RUN pin of the SM4644 power management chip ensure that each power supply group of the FPGA and DSP chip starts in order.

6. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The FPGA collects external IMU and GPS information through the serial chip with integrated isolation power supply.

7. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The FPGA chip sends 1kHz synchronization clock to three fiber gyroscopes, and the fiber gyroscopes latch data at the rising edge of the synchronization clock and send it to the FPGA chip; the FPGA chip is connected with the serial chip through extended I / O pin, which is used for receiving three-way fiber gyroscope data.

8. The FPGA and DSP based navigation solution system according to claim 1, characterized in that: The FPGA chip is also connected with the accelerometer force feedback loop, the accelerometer force feedback loop adopts binary width adjustment loop, the width adjustment frequency is 1kHz, and the sampling frequency of the accelerometer is 1kHz; after the FPGA chip collects the fiber gyroscope and accelerometer data at 1kHz, the frequency of the inertial element data is 200Hz through accumulation or subsampling compensation, the data is stored by using on-chip RAM, and is sent to the DSP chip through EMIFA bus for real-time solution.

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