Voltage regulator with transient response feedback circuit

Abstract

The invention relates to a voltage regulator with a transient response feedback circuit. In described examples, an integrated circuit (IC) (200) includes an error amplifier (109), first and second resistors (134, 136), first and second transistors (130, 180), and a current source (206). A control terminal of the first transistor (130) is coupled to an output of the error amplifier (109). A first terminal of the second transistor (180) is coupled to a first terminal of the first transistor (130) and a first terminal of the first resistor (134). A control terminal of the second transistor (180) is coupled to a second terminal of the first resistor (134), a second terminal of the second resistor (136), and a first input of the error amplifier (109). A first terminal of the current source (206) is coupled to a second terminal of the second transistor (180).

Description

TECHNICAL FIELD

[0001] This application relates generally to voltage regulators, and more specifically to improving load transient response in low-dropout voltage regulators. BACKGROUND

[0002] In a voltage regulator, the drop-out voltage is the difference between the supply voltage (or input voltage) and the output voltage. In a low-dropout (LDO) voltage regulator, this difference can be relatively small. For example, an LDO voltage regulator with a 1.7 volt (V) supply voltage can have a 1.5 V output voltage. An LDO voltage regulator is a type of DC linear voltage regulator. In some examples, an LDO voltage regulator can be used to maintain an approximately constant low-noise voltage output in response to an unregulated potentially highly variable supply voltage, e.g., from a battery, and in response to a variable load. SUMMARY

[0003] In described examples, an integrated circuit (IC) includes an error amplifier, first and second resistors, first and second transistors, and a current source. A control terminal of the first transistor is coupled to an output of the error amplifier. A first terminal of the second transistor is coupled to a first terminal of the first transistor and a first terminal of the first resistor. A control terminal of the second transistor is coupled to a second terminal of the first resistor, a second terminal of the second resistor, and a first input of the error amplifier. A first terminal of the current source is coupled to a second terminal of the second transistor. BRIEF DESCRIPTION OF DRAWINGS

[0004] FIG. 1A A first portion of a circuit diagram showing an example voltage-regulated system including an LDO voltage regulator with load transient response feedback circuitry is shown.

[0005] From FIG. 1A Continued FIG. 1B A second portion of a circuit diagram showing an example voltage-regulated system including an LDO voltage regulator with load transient response feedback circuitry is shown.

[0006] FIG. 2 is a first functional block diagram and circuit diagram of the example voltage-regulated system of FIG. 1.

[0007] FIG. 3 is a second functional block diagram of the voltage-regulated system of FIG. 1. DETAILED DESCRIPTION

[0008] Generally, an LDO voltage regulator provides a regulated or target output voltage V OUT which is partially determined by V OUTfeedback to various components within the circuit. In some architectures, after a rapid increase or decrease in current demand of a load (load transient), the voltage regulator can experience a V OUT deviation from the target voltage and cause V OUT a corrective change in the behavior of the regulator to return to the target level. For example, the load demand can change sufficiently, or within a sufficiently short period of time, that the feedback control is too slow to adequately regulate V OUT In other words, the response time of the feedback loop that controls the voltage regulation by the LDO voltage regulator can be too long (slow) to prevent V OUT from leaving the target level or target range. In response to V OUT and control the level of compensation current provided to the output node can be used to improve the load transient response time of the LDO voltage regulator.

[0009] Metal oxide semiconductor field effect transistors (MOSFETs) are numbered M[channel type][number], where the number increases for each different transistor of the same channel type. Channel types include n-channel MOSFETs (NMOS) and p-channel MOSFETs (PMOS). The channel type of each transistor is merely an example, and other examples can substitute another transistor of a different type for any of the illustrated transistors. Further, the same reference numbers or other reference designators are used in the figures to designate structurally and / or functionally related features.

[0010] FIG. 1A and 1B A circuit diagram showing a first example voltage-regulated system 100 including an LDO voltage regulator 102 having a load transient response feedback circuit 104 (referred to herein as feedback circuit 104) is shown. The LDO voltage regulator 102 has two feedback loops: the feedback circuit 104 and a negative feedback loop including a differential amplifier (ring amplifier 109) and a passFET 130 and responsive to a voltage signal V REF (control signal) and V IN (feedback signal). The voltage-regulated system 100 also includes a load capacitor 106 and a first current source 108. The first current source 108 corresponds to the load current demand and can be described as providing a current I LOAD In some examples, the LDO voltage regulator 102 is fabricated on an integrated circuit (IC). In some examples, other portions of the voltage-regulated system 100 are fabricated on the IC.

[0011] The LDO voltage regulator 102 includes a ring amplifier 109 having a first stage 110, a second stage 112, and a third stage 114. The LDO voltage regulator 102 also includes a second current source 116 configured to provide a current I BIAS , a first n-channel MOSFET (MN1) 118, a second n-channel MOSFET (MN2) 120, a third n-channel MOSFET (MN3) 122, a fourth n-channel MOSFET (MN4) 124, a first p-channel MOSFET (MP1) 126, a second p-channel MOSFET (MP2) 128, a second capacitor 129, a third p-channel MOSFET (MP3, referred to as a passFET) 130, a fifth n-channel MOSFET (MN5) 132, a first resistor (R1) 134 having a resistance R1, a second resistor (R2) 136 having a resistance R2, a first voltage source 138 providing a voltage V DD , and a ground 140 providing a ground voltage V SS . In some examples, the first voltage source 138 is an analog high voltage rail, and the ground 140 is an analog low voltage rail.

[0012] FIG. 1B includes the feedback circuit 104, the load capacitor 106, the first current source 108, the MP2 128, the second capacitor 129, the passFET 130, the MN5 132, and the first and second resistors 134 and 136. FIG. 1B also shows V OUT node 186 and node A 188 (described below). FIG. 1A Other components of the voltage regulated system 100 are shown in FIG. 2. The correspondence between the conductive lines FIG. 1A to FIG. 1B connected in FIG. 2 is indicated using the signals carried by these lines. V G PASSFET is the signal provided to the gate of the passFET 130. In FIG. 1A and 1B other signals shared between the components of FIG. 2 are V DD , V IN , V BIAS , V REF , and V SS , which are described below.

[0013] The first stage 110 of the ring amplifier 109 includes a fourth p-channel MOSFET (MP4) 142, a fifth p-channel MOSFET (MP5) 144, a sixth n-channel MOSFET (MN6) 146, a seventh n-channel MOSFET (MN7) 148, an eighth n-channel MOSFET (MN8) 150, a ninth n-channel MOSFET (MN9) 152, a tenth n-channel MOSFET (MN10) 154, and a third capacitor 156.

[0014] The second stage 112 of the ring amplifier 109 includes a second voltage source 158 providing a first offset voltage, a third voltage source 160 providing a second offset voltage, a sixth p-channel MOSFET (MP6) 162, an eleventh n-channel MOSFET (MN11) 164, a seventh p-channel MOSFET (MP7) 166, an eighth p-channel MOSFET (MP8) 168, a twelfth n-channel MOSFET (MN12) 170, and a thirteenth n-channel MOSFET (MN13) 172.

[0015] The third stage 114 of the ring amplifier 109 includes a ninth p-channel MOSFET (MP9) 174, a fourteenth n-channel MOSFET (MN14) 176, and a fifteenth n-channel MOSFET (MN15) 178.

[0016] The feedback circuit 104 includes a sixteenth n-channel MOSFET (MN16) 180, a seventeenth n-channel MOSFET (MN17) 182, and an eighteenth n-channel MOSFET 184.

[0017] A first terminal of the second current source 116 is connected to the first voltage source 138. A second terminal of the second current source 116 is connected to the gate and drain of MN1 118, the gate of MN2 120, the gate of MN8 150, the drain of MN5 132, and the gate of MN17 182. The source of MN1 118 is connected to the drain of MN3 122. The source of MN3 122 is connected to ground 140. The source of MN5 132 is connected to ground 140, and the gate of MN5 132 is configured to receive an inverted ENABLE signal ( / EN).

[0018] The source of MP1 126 is connected to the first voltage source 138. The gate and drain of MP1 126 are connected to the gates of MP4 142 and MP5 144 and the drain of MN2 120, and these connections have a voltage V PBIAS The source of MN2 120 is connected to the drain of MN4 124, and the source of MN4 124 is connected to ground 140. The gate of MN3 122 is connected to the gate of MN4 124, which is configured to receive a reference voltage V REFthe reference terminal 125, the gate of MN7 148, and the gate of MN18 184.

[0019] The source of MP4 142 is connected to the source of MP5 144 and the first voltage source 138. The drain of MP4 142 is connected to the drain of MN6 146 and the gate of MN10 154. The drain of MP5 144 is connected to the drain of MN7 148, the gate of MN9 152, a first terminal (e.g., a capacitor plate) of a third capacitor 156, a positive terminal of a second voltage source 158, a negative terminal of a third voltage source 160, and the drain of MN13 172. A second terminal of the third capacitor 156 is connected to the first voltage source 138. The source of MN13 172 is connected to ground 140. The gate of MN13 172 receives an inverted ENABLE signal.

[0020] The gate of MN6 146 is connected to the first terminal of Rl 134, the first terminal of R2 136, and the gate of MN16 180. The source of MN6 146 is connected to the source of MN7 148 and the drain of MN8 150. The source of MN8 150 is connected to the drains of MN9 152 and MN10 154. The source of MN9 152 is connected to the source of MN10 154 and ground 140.

[0021] The negative terminal of the second voltage source 158 is connected to the gates of MP6 162 and MN11 164. The source of MP6 162 is connected to the first voltage source 138. The drain of MP6 162 is connected to the drain of MN11 164, the drain of MP7 166, and the gate of MP9 174. The source of MP7 166 is connected to the first voltage source 138, and the gate of MP7 166 receives an ENABLE signal (EN). The source of MP9 174 is connected to the first voltage source 138. The source of MN11 164 is connected to ground 140.

[0022] The positive terminal of the third voltage source 160 is connected to the gates of MP8 168 and MN12 170. The source of MP8 168 is connected to the first voltage source 138. The drain of MP8 168 is connected to the drain of MN12 170, the gate of MN14 176, and the drain of MN15 178. The sources of MN12 170, MN14 176, and MN15 178 are connected to ground 140. The gate of MN15 178 is configured to receive an inverted ENABLE signal.

[0023] The drain of MP9 174 is connected to the drains of MN14 176 and MP2 128, the gate of passFET 130, and the first terminal of second capacitor 129. The source of MP2 128 is connected to first voltage source 138, and the gate of MP2 128 is configured to receive the ENABLE signal. The source of MP3 130 is connected to first voltage source 138.

[0024] The second terminal of second capacitor 129 is connected to output node (V OUT node) 186. The voltage at V OUT node 186 is V OUT . The voltage at V OUT node 186 is V COUT . OUT The drain of MP9 174 is connected to the drains of MN14 176 and MP2 128, the gate of passFET 130, and the first terminal of second capacitor 129. The source of MP2 128 is connected to first voltage source 138, and the gate of MP2 128 is configured to receive the ENABLE signal. The source of MP3 130 is connected to first voltage source 138.

[0025] A ring amplifier, such as ring amplifier 109, has certain similarities in function to an operational amplifier. Ring amplifier 109 receives inputs including a reference voltage V REF (from reference terminal 125), and a feedback voltage V OUT in response to V IN . Ring amplifier 109 controls the gate voltage of passFET 130 using a negative feedback loop in response to the difference between V REF and V IN . V OUT is adjusted by the level of current (I PASSFET ) through passFET 130. Thus, V REF is determined in response to V OUT , as described further below. In some examples, V REF is determined using a bandgap voltage reference and / or a configurable voltage adjustment circuit, such as a variable resistor or other variable resistance.

[0026] In some examples, the bandwidth and gain of the ring amplifier 109 dynamically change depending on a settling phase of the ring amplifier 109. The settling phase of the ring amplifier 109 includes a start-up phase (or a slew phase), a ringing phase, and a steady state phase. In the start-up phase, for example, when the LDO voltage regulator 102 is starting up after a power-on reset (POR), the ring amplifier 109 has a relatively high bandwidth, a high slew rate, and a low direct current (DC) gain, and operates in response to the feedback loop of V REF and V OUT as a relatively fast loop. Thus, the start-up phase enables fast settling of V OUT . In some examples, the start-up phase corresponds to V OUT that is significantly higher or lower (thus, far away) from a target voltage. Here, the slew rate of the LDO voltage regulator 102 refers to the rate at which the LDO voltage regulator 102 controls V OUT to change (AV OUT / At). In one example, the start-up voltage is zero volts, the target V OUT is 1.4 volts, and V OUT settles within a 10% error margin of the target V OUT during the start-up phase.

[0027] In the steady state phase, when the LDO voltage regulator 102 is operating such that V OUT is close to the target voltage, the ring amplifier 109 has a relatively low bandwidth, a low slew rate, and a high DC gain, and operates in response to the feedback loop of V REF and V OUT as a relatively slow loop. Thus, the steady state phase enables improved accuracy and load regulation of the LDO voltage regulator 102.

[0028] Using the ring amplifier 109 in the LDO voltage regulator 102 can provide some or all of the following benefits. In some examples, because the ring amplifier 109 is capable of separately providing high bandwidth and high gain in different operating phases, the ring amplifier 109 reduces current and device area requirements of the LDO voltage regulator 102 relative to an operational amplifier. Moreover, because the ring amplifier 109 enables high slew rate for large V OUT correction, and accurate low noise operation during operation within a target V OUT range, the size of an external capacitor can be reduced or avoided.

[0029] MN1 118, MN2 120, MN8 150, and MN17 182 form a current mirror such that they are mirrored to respective gate-source voltages (V GS) has a proportional current response curve. MN1 118 is a diode-connected MOSFET that receives current I BIAS ( from the second current source 116) at its gate and drain. Thus, the voltage at the gates of MN1 118, MN2 120, MN8 150, and MN17 182 is V BIAS . The source voltages of MN1 118, MN2 120, and MN17 182 are responsive to the drain voltages of MN3 122, MN4 124, and MN18 184, respectively. MN3 122, MN4 124, and MN18 184 each have a V REF = V GS .

[0030] The first stage 110 of the ring amplifier 109 is a differential amplifier with an output responsive to V REF and V IN . V IN is responsive to V OUT as follows. R1 134 and R2 136 together form a resistive voltage divider. Node A 188 is connected to a terminal of R1 134, a terminal of R2 136, and the gates of MN16 180 and MN6 146 (as described, MN6 146 is in the first stage 110). The voltage at node A 188 is V IN . Thus, V IN = V OUT x R2 / (R1 + R2), so that the target V OUT = V REF x (1 + R1 / R2).

[0031] The first stage 110 outputs to the positive terminal of the second voltage source 158, the negative terminal of the third voltage source 160, and the drain of MN13 172. If the ENABLE signal has a deactivation value, such as a voltage corresponding to a logic 0, then MN13 172 turns on, coupling the output of the first stage 110 to ground 140 and discharging the third capacitor 156. If the ENABLE signal is set with an activation value, such as a voltage corresponding to a logic 1, then MN13 172 turns off, allowing normal output of the first stage 110 to the second stage 112.

[0032] In the second stage 112, MP6 162, MN11 164, and the second voltage source 158 together form a first skewed inverter 207 (see FIG. 2 ). MP8 168, MN12 170, and the third voltage source 160 together form a second skewed inverter 208. The upper voltage boundary of the target V OUT range of the LDO voltage regulator 102 is responsive to the first skewed inverter 207, and the lower voltage boundary of the target VOUT The lower voltage boundary of the range is responsive to the second skew inverter 208. In some examples, when the LDO voltage regulator 102 is operating at the target V OUT The ring amplifier 109 does not alter the gate voltage of the passFET 130 when the LDO voltage regulator 102 is operating at the target V OUT The target V OUT range is also referred to as the target V GS The surrounding deadband.

[0033] In the second stage 112, the first skew inverter 207 outputs to the gate of the MP9 174 via the drains of the MP6 162 and MN11 164, and the second skew inverter 208 outputs to the gate of the MN14 176 via the drains of the MP8 168 and MN12 170. If the ENABLE signal has the deactivation value, then the MP7 166 and MN15 178 are on. Turning on the MP7 166 couples the gate of the MP9 174 to the first voltage source 138, turning off the MP9 174, and turning on the MN15 178 couples the gate of the MN14 176 to the ground 140, turning off the MN14 176. If the ENABLE signal has the activation value, then the MP7 166 and MN15 178 are off, allowing normal output of the second stage 112 to the third stage 114.

[0034] The output from the second stage 112 controls the third stage 114 to charge or discharge the second capacitor 129 by controlling the MP9 174 or MN14 176, respectively, to turn on by varying amounts. If the second stage 112 lowers the gate voltage of the MP9 174 to turn on the MP9 174 more, then the MP9 174 more strongly couples the second capacitor 129 to the first voltage source 138, which increases the charging of the second capacitor 129. The increased charging of the second capacitor 129 increases the gate voltage of the passFET 130, which decreases the V GS of the passFET 130 to decrease the current I OUT flowing through the passFET 130 to the V PASSFET node 186. Decreasing I PASSFET decreases V OUT .

[0035] If the second stage 112 increases the gate voltage of the MN14 176 to turn on the MN14 176 more, then the MN14 176 more strongly couples the second capacitor 129 to the ground 140, which increases the discharging of the second capacitor 129. The discharging of the second capacitor 129 decreases the gate voltage of the passFET 130, which increases the V GS of the passFET 130 to increase the current I OUT flowing through the passFET 130 to the VPASSFET . Increasing I PASSFET will increase V OUT . Regarding FIG. 2 The operation of feedback circuit 104 (and similar feedback circuit 204) is further described. As described above, the functionality of third stage 114 is summarized in Table 1 :

[0036] Table 1

[0037] signal V OUT V REF changes in the case of V OUT <V REF changes in the case of MP9 174 of V GS ]]> decrease increase MN14 176 of V GS ]]> increase decrease second capacitor 129 voltage charge discharge V GS ]]> increase decrease I PASSFET ]] decrease increase V OUT ]]> decrease increase

[0038] FIG. 2 is a circuit diagram of a second example voltage-regulated system 200 that includes an LDO voltage regulator 202 with a load transient response feedback circuit 204. In voltage-regulated system 200, first stage 110 of ring amplifier 109 is (or is represented as) an inverter with two inputs and one output, corresponding to an error amplifier with an inverting output. The non-inverting input of first stage 110 receives V REF , and the inverting input of first stage 110 is connected to node A 188 and receives V IN .

[0039] Feedback circuit 204 includes a third current source 206 that provides a current I COMP (V OUT bias compensation current). In some examples, third current source 206 corresponds to MN17 182 of FIG. 1 (or MN17 182 together with MN18 184). Thus, feedback circuit 204 is similar in some respects to feedback circuit 104 of FIG. 1. I COMP is responsive to the drain voltage of MN17 182 (see FIG. 1). The drain voltage of MN17 182 is responsive to the gate voltage V IN .

[0040] In second stage 112 of ring amplifier 109, MP6 162 and MN11 164 are represented as (or can be replaced by) a first inverter 210. MP8 168 and MN12 170 are represented as (or can be replaced by) a second inverter 212. As described above, first inverter 210 and second voltage source 158 together form a first skewed inverter 207, and second inverter 212 and third voltage source 160 together form a second skewed inverter 208. The output of first inverter 210 is connected to the gate of MP9 174, and the output of second inverter 212 is connected to MN14 176.

[0041] As described above, the slew rate of the ring amplifier 109 is reduced when operating in steady state. The ring amplifier 109 can take an operationally significant amount of time to return to high slew rate operation. Thus, when the voltage regulated system 200 experiences a change in I OUT that is sufficient to cause V OUT to deviate from the target V LOAD range (overshoot or undershoot), the LDO voltage regulator 202 can take an operationally significant amount of time to return V OUT to the target voltage range.

[0042] Overshoot refers to V OUT increasing above the target voltage range. Similarly, undershoot refers to V OUT decreasing below the target voltage range. The relatively slow feedback loop of the LDO voltage regulator 202 allows V OUT to move further away from the target range before the LDO voltage regulator 202 is able to begin pulling V OUT back toward the target. Thus, an increase in the delay of the ring amplifier 109 can cause an increase in overshoot or undershoot. In some examples, the amplitude of the overshoot or undershoot caused by a load transient is responsive to the amplitude of the load transient and the responsive delay of the ring amplifier 109.

[0043] The operation of the negative feedback loop of the ring amplifier 109 in response to undershoot is described first, followed by the operation of the feedback circuit 204 in response to undershoot. Undershoot is used as a representative example; the operation in response to overshoot is similar, except that signals having increased levels in response to undershoot exhibit decreased levels, and signals having decreased levels in response to undershoot exhibit increased levels.

[0044] I PASSFET is provided to the V OUT node, and I COMP , I RESDIV , I LOAD , and I COUT are provided from the V OUT node. This relationship is shown in Equation 1:

[0045] I PASSFET = I COMP + I RESDIV + I LOAD + I COUT Equation 1

[0046] Equation 1 can be rearranged to describe the current balance equal to I COUT , as shown in Equation 2.

[0047] I COUT = I PASSFET - I COMP - IRESDIV -I LOAD Equation 2

[0048] V OUT can be described as the voltage at the first terminal of the load capacitor 106. The load capacitor 106 charges or discharges to increase or decrease V OUT The formula relating the current and voltage changes of the load capacitor 106 is shown in Equation 3.

[0049] ΔV OUT =I COUT ×Δt / C OUT Equation 3

[0050] Therefore, when the load demand increases (corresponding to I LOAD increases), the load capacitor discharges (corresponding to I COUT decreases (or becomes negative). This behavior is described by Equation 4:

[0051] I COUT =I PASSFET -I COMP -I RESDIV -I LOAD <0 Equation 4

[0052] Equation 3 shows I COUT Discharge makes ΔV OUT becomes negative, making V OUT For the purpose of this analysis, C OUT and Δt can be described as positive constants. In some examples, V OUT Decreases rapidly in response to an increase in load demand.

[0053] V OUT Dropping V IN The voltage output from the first stage 110 decreases, which causes the voltage output from the first stage 110 to decrease. The decrease in the output voltage of the first stage 110 causes the output of the second stage 112 (corresponding to the gate voltages of MP9 174 and MN14 176) to increase at different rates. Due to the offset voltages provided by the second voltage source 158 and the third voltage source 160, these gate voltages increase to different levels. The different settling gate voltages cause the current through the drain-source path of MN14 176 to be greater than the current through the source-drain path of MP9 174, thereby discharging the second capacitor 129 and causing the gate voltage of the passFET 130 to decrease. This causes the V GS becomes more negative, turning passFET 130 on more, causing the voltage across passFET 130 to decrease and V OUT Increase.

[0054] Now describe the operation in response to V OUT deviation from the target voltage. The decrease in V OUT as the gate voltage of MNl6 180. This causes the drain voltage of MNl7 182 to decrease, and thus the drain-source voltage of MNl7 182 to decrease. As a result, the current I IN through the drain-source path of MNl7 182 decreases. Equation 2 shows that I COMP decreases causes I COMP to increase (become more positive), which charges the load capacitor 106, increasing V COUT . This compensates for the increased load demand. OUT

[0055] In some examples, this compensation occurs relatively quickly compared to the response of the feedback loop of the ring amplifier 109 shortly after a change in load demand, also shortly after the ring amplifier 109 operates in the steady state phase. Recall that when in the steady state phase, the ring amplifier 109 has a relatively slow slew rate, and in some examples, it can take a significant amount of time for the ring amplifier 109 to transition from the steady state phase to a phase that achieves a higher slew rate. Thus, the feedback circuit 204 provides a fast feedback response to reduce the amplitude of the overshoot or undershoot, while the corresponding response propagates through the feedback loop of the ring amplifier 109. This shortens the time it takes for the LDO voltage regulator 200 to return to stable, steady state operation. In some examples, the use of the feedback circuit 204 enables one or more of the benefits that can include a shortening of the settling time or the ability to use the ring amplifier 109 with the corresponding benefits as described above.

[0056] In one example, the load demand increases by 30 milliamps over a duration of between 10 nanoseconds and 1 microsecond. In an example without the feedback circuit 204, this causes V OUT to decrease from the target voltage of 1.4 volts to an undershoot level of 1.1 volts before V OUT begins to return toward the target voltage. In an example with the feedback circuit 204, the load demand increase causes V OUT to decrease from the target voltage of 1.4 volts to an undershoot level of 1.2 volts before V OUT begins to return toward the target voltage.

[0057] In some examples, the design of the feedback circuit 204 is responsive to an amount of DC bias current at the VOUT node 186 that is consistent with design constraints, and an amount of undershoot and / or overshoot that is consistent with design constraints.

[0058] FIG. 3 ​is a circuit diagram of a third example voltage-regulated system 300 including an LDO voltage regulator 302 with a load transient response feedback circuit 204. The third voltage-regulated system 300 includes a voltage source 304, a control circuit 306, and a load 308. The LDO voltage regulator 302 includes a ring amplifier 109, an inverter 310, a passFET 130, R1 134, R2 136, and the feedback circuit 204.

[0059] A voltage source terminal of the voltage source 304 is connected to a voltage source terminal of the control circuit 306 and the ring amplifier 109, and to a source of the passFET 130. A ground terminal of the voltage source 304 is connected to a ground terminal of the control circuit 306, the ring amplifier 109, and the load 308, a terminal of R2 136, and a terminal of the third current source 206.

[0060] A first output of the control circuit 306 provides an ENABLE signal to an EN terminal of the ring amplifier 109 and an input of the inverter 310. The EN terminal is connected to gates of MP7 166 and MP2 128. An output of the inverter 310 is connected to a / EN terminal of the ring amplifier 109. The / EN terminal is connected to gates of MN13 172 and MN15 178.

[0061] A second output of the control circuit 306 provides a V REF input to an inverting input of the ring amplifier 109. A non-inverting input of the ring amplifier 109 receives a V IN from node A 188. An output of the ring amplifier 109 is connected to a gate of the passFET 130. An input terminal of the load 308 is connected to node V OUT 186.

[0062] Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

[0063] In some examples, an error amplifier other than a ring amplifier is used, such as an operational amplifier.

[0064] In some examples, the error amplifier, such as a ring amplifier, includes more, different, and / or fewer stages than described herein.

[0065] In some examples, V OUT is connected to the error amplifier input without a resistive voltage divider.

[0066] In some examples, a different structure than the skew inverter described herein is used to set the deadband, such as a current-starvation inverter or an inverter coupled to a transistor that uses a gate voltage control that is responsive to a designed deadband boundary voltage.

[0067] The term "coupled" is used throughout the specification. This term can encompass a connection, a communication, or a signal path between components consistent with the functionality described in the specification. For example, if device A provides a signal to control device B to perform some action, then device A is coupled to device B in a first instance, or device A is coupled to device B via intermediate component C in a second instance, provided that intermediate component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

[0068] In this specification, the term "and / or," where used, e.g., in a form such as A, B, and / or C, means any combination or subset of A, B, and C, e.g.: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A, B, and C. Also, as used in this document, the phrase "at least one of A or B" (or "at least one of A and B") means embodiments including any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0069] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) at a manufacturing time or thereafter to perform the function upon a signal or inputs being applied to the device, or to change the device's responsiveness to

[0070] As used herein, the terms "terminal," "node," "interconnect," "pin," "solder ball," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote an interconnect or a terminal end between device elements, circuit elements, ICs, devices, or other electronic or semiconductor components.

[0071] Circuits or devices described herein as including certain components can actually be adapted to be coupled to those components to form the described circuitry or devices. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) can actually include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or IC package), and can be adapted to be coupled to at least some of the passive elements and / or sources to form the described structures at a time of manufacture or after a time of manufacture, e.g., by an end user and / or a third party.

[0072] Although the use of particular transistors is described herein, other transistors (or equivalent devices) can be used instead with minimal or no changes to the remaining circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs - e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) can be used instead of, or in conjunction with, the devices disclosed herein. The transistors can be depletion mode devices, drain extended devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Further, the devices can be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0073] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise noted, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, resistors or capacitors shown and described herein as a single component can actually be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, resistors or capacitors shown and described herein as a single component can actually be multiple resistors or capacitors respectively coupled in series between the same two nodes as the single resistor or capacitor.

[0074] While certain elements of the described examples can be included in an IC and others are external to the IC, in other example embodiments, additional or fewer features can be incorporated into an IC. Also, some or all features shown as external to an IC can be incorporated into the IC, and / or some features shown as internal to an IC can be incorporated outside the IC. As used herein, the term "integrated circuit" or "IC" means one or more circuits that are: (i) incorporated in a semiconductor substrate / on the semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in the same printed circuit board.

[0075] In the above description, the use of the phrase "ground" includes chassis ground, line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection as would be appropriate to the teachings of the present specification. Unless otherwise indicated, "about," "approximately," or "substantially" before a value means + / - 10% of the stated value, or a reasonable range of values near zero if the value is zero. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. An integrated circuit (IC) comprising: an error amplifier having a first input, a second input, and an output; a first resistor and a second resistor each having a first terminal and a second terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the first transistor coupled to the output of the error amplifier; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor and the first terminal of the first resistor, and the control terminal of the second transistor coupled to the second terminals of the first and second resistors and to the first input of the error amplifier; and a current source having a first terminal and a second terminal, the first terminal of the current source coupled to the second terminal of the second transistor.

2. The IC of claim 1, wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor coupled to the second input of the error amplifier.

3. The IC of claim 1, wherein the current source includes a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and wherein the error amplifier includes a fourth transistor having a first terminal, a second terminal, and a control terminal; the IC further comprising a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the control terminals of the third, fourth, and fifth transistors.

4. The IC of claim 1, wherein the current source includes: and a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor; the IC further comprising: a fifth transistor having a first terminal, a second terminal, and a control terminal; a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor coupled to the control terminals of the third and fifth transistors; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the second terminal of the fifth transistor; and an eighth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the sixth transistor, and the control terminal of the eighth transistor coupled to the control terminals of the fourth and seventh transistors. ​ 5. The IC of claim 1, wherein the error amplifier is a ring amplifier.

6. The IC of claim 1, wherein the error amplifier, the first and second resistors, the first and second transistors, and the current source together form a low dropout voltage regulator having a deadband; and wherein the error amplifier includes: a first stage that is a differential amplifier and is configured to receive the first and second inputs of the error amplifier; a second stage, a range of the deadband is responsive to the second stage; and a third stage that is configured to provide a gate voltage to the control terminal of the first transistor.

7. The IC of claim 1, wherein the error amplifier includes: a differential amplifier having a first input, a second input, and an output, the first and second inputs of the differential amplifier being coupled to the first and second inputs of the error amplifier, respectively; a second stage having an input, a first output, and a second output, the input of the second stage being coupled to the output of the differential amplifier; and a third stage having a first input, a second input, and an output, the first input of the third stage being coupled to the first output of the second stage, the second input of the third stage being coupled to the second output of the second stage, and the output of the third stage being coupled to the control terminal of the first transistor.

8. The IC of claim 7, wherein the second stage includes a first inverter and a second inverter, the first and second inverters each having an input and an output, the inputs of the first and second inverters each being coupled to the input of the second stage, and the outputs of the first and second inverters being coupled to the first and second outputs of the second stage, respectively.

9. The IC of claim 8, wherein the second stage includes a first voltage source and a second voltage source, the first and second voltage sources each having first and second terminals, the first terminal of the first voltage source being coupled to the input of the first inverter, the second terminal of the first voltage source being coupled to the output of the differential amplifier and the first terminal of the second voltage source, and the second terminal of the second voltage source being coupled to the input of the second inverter.

10. The IC of claim 7, wherein the third stage includes: a third transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the third transistor being coupled to the first output of the second stage; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the first terminal of the fourth transistor and the control terminal of the first transistor, and the control terminal of the fourth transistor being coupled to the second output of the second stage.

11. The IC of claim 7, further comprising: an inverter including an input and an output; a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the output of the differential amplifier; a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second output of the second stage, and the control terminals of the third and fourth transistors coupled to the output of the inverter; a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the first output of the second stage; and a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor coupled to the control terminal of the first transistor, and the control terminals of the fifth and sixth transistors coupled to the input of the inverter.

12. A system comprising: a control circuit including a reference voltage terminal; an error amplifier having a first input, a second input, and an output, the first input of the error amplifier coupled to the reference voltage terminal of the control circuit; a first resistor and a second resistor each having a first terminal and a second terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the first transistor coupled to the output of the error amplifier; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor and the first terminal of the first resistor, and the control terminal of the second transistor coupled to the second terminals of the first and second resistors and to the second input of the error amplifier; and a current source having a first terminal and a second terminal, the first terminal of the current source coupled to the second terminal of the second transistor.

13. The system of claim 12, wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor coupled to the second input of the error amplifier.

14. The system of claim 12, wherein the current source includes a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and wherein the error amplifier includes a fourth transistor having a first terminal, a second terminal, and a control terminal; the system further comprising a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the control terminals of the third transistor, the fourth transistor, and the fifth transistor.

15. The system of claim 12, wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor; the system further comprising: a fifth transistor having a first terminal, a second terminal, and a control terminal; a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor coupled to the control terminals of the third and fifth transistors; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the second terminal of the fifth transistor; and an eighth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the sixth transistor, and the control terminal of the eighth transistor coupled to the control terminals of the fourth and seventh transistors.

16. The system of claim 12, wherein the error amplifier, the first and second resistors, the first and second transistors, and the current source together form a low dropout voltage regulator having a deadband; and wherein the error amplifier includes: a first stage that is a differential amplifier and is configured to receive the first and second inputs of the error amplifier; a second stage, a range of the deadband responsive to the second stage; and a third stage configured to provide a gate voltage to the control terminal of the first transistor.

17. The system of claim 12, wherein the error amplifier includes: a differential amplifier having a first input, a second input, and an output, the first and second inputs of the differential amplifier coupled to the first and second inputs of the error amplifier, respectively; a second stage having an input, a first output, and a second output, the input of the second stage coupled to the output of the differential amplifier; and a third stage having a first input, a second input, and an output, the first input of the third stage coupled to the first output of the second stage, the second input of the third stage coupled to the second output of the second stage, and the output of the third stage coupled to the control terminal of the first transistor.

18. The system of claim 17, wherein the second stage includes a first inverter and a second inverter, the first and second inverters each having an input and an output, the inputs of the first and second inverters each coupled to the input of the second stage, and the outputs of the first and second inverters coupled to the first and second outputs of the second stage, respectively.

19. The system of claim 18, wherein the second stage includes a first voltage source and a second voltage source, the first and second voltage sources each having first and second terminals, the first terminal of the first voltage source coupled to the input of the first inverter, the second terminal of the first voltage source coupled to the output of the differential amplifier and the first terminal of the second voltage source, and the second terminal of the second voltage source coupled to the input of the second inverter.

20. The system of claim 17, wherein the control circuit includes an enable output and the error amplifier includes an enable input, the enable output of the control circuit coupled to the enable input of the error amplifier.

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