Host and operating method thereof, memory system and operating method thereof, and electronic device

Abstract

The embodiment of the invention discloses a host and an operation method thereof, a memory system and an operation method thereof, and electronic equipment. The host is coupled with a memory system supporting a partitioned namespace function; a memory system includes a memory device including K dies; the K tube cores are divided into N interference intervals, each interference interval comprises at least one tube core, and one storage block in each tube core in each interference interval jointly forms a partition; k and N are positive integers greater than or equal to 2; the host is configured to send a command to the memory system so as to execute corresponding operation on each partition corresponding to the command at the same time; the partitions corresponding to the command belong to different interference intervals.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and relate to, but are not limited to, a host and an operating method thereof, a memory system and an operating method thereof, and an electronic device. BACKGROUND

[0002] With the rapid development of data storage technology, more and more data storage systems appear in electronic devices used by people, such as solid state drives (SSD) and the like. The SSD has been widely used in military, vehicle-mounted, industrial, medical and aviation fields due to its fast read-write speed, anti-vibration, low power consumption, no noise, low heat and light weight. SUMMARY

[0003] Therefore, embodiments of the present disclosure provide a host and an operating method thereof, a memory system and an operating method thereof, and an electronic device.

[0004] In a first aspect, embodiments of the present disclosure provide a host, which is coupled with a memory system supporting a partition namespace function; the memory system includes a memory device, and the memory device includes K dies; the K dies are divided into N interference intervals, each of the interference intervals includes at least one of the dies, and one memory block in each of the dies in the interference interval collectively constitutes a partition; K and N are positive integers greater than or equal to 2; and the host is configured to: send a command to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command; and each partition corresponding to the command belongs to different interference intervals.

[0005] In a second aspect, embodiments of the present disclosure provide an operating method of a host, which is coupled with a memory system supporting a partition namespace function; the memory system includes a memory device, and the memory device includes K dies; the K dies are divided into N interference intervals, each of the interference intervals includes at least one of the dies, and one memory block in each of the dies in the interference interval collectively constitutes a partition; K and N are positive integers greater than or equal to 2; and the method includes: sending a command to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command; and each partition corresponding to the command belongs to different interference intervals.

[0006] In a third aspect, the embodiments of the present disclosure provide a memory system, which comprises a memory device and a memory controller coupled with the memory device, and supports a partitioned namespace function; the memory device comprises K dies; the K dies are divided into N interference intervals, each of which comprises at least one of the dies, and one memory block in each of the dies in the interference interval jointly constitutes a partition; K and N are positive integers greater than or equal to 2; the memory controller is configured to: receive a first command queue; the first command queue comprises a plurality of read-write commands; obtain capacity information of the partition, a maximum parallelism of the memory system, and logical address information carried by each read-write command; obtain interference interval information corresponding to the read-write command according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the read-write command; and divide the plurality of read-write commands into M command sets according to the interference interval information contained in the read-write commands; wherein the interference interval information contained in each read-write command in a same command set is different, and M is a positive integer.

[0007] In a fourth aspect, the embodiments of the present disclosure provide an operation method of a memory system, which comprises a memory device and a memory controller coupled with the memory device, and supports a partitioned namespace function; the memory system comprises a memory device, and the memory device comprises K dies; the K dies are divided into N interference intervals, each of which comprises at least one of the dies, and one memory block in each of the dies in the interference interval jointly constitutes a partition; K and N are positive integers greater than or equal to 2; the method comprises: receiving a first command queue; the first command queue comprises a plurality of read-write commands; obtaining capacity information of the partition, a maximum parallelism of the memory system, and logical address information carried by each read-write command; obtaining interference interval information corresponding to the read-write command according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the read-write command; and dividing the plurality of read-write commands into M command sets according to the interference interval information contained in the read-write commands; wherein the interference interval information contained in each read-write command in a same command set is different, and M is a positive integer.

[0008] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, comprising a host and a memory system coupled to the host and supporting a partition namespace function; the memory system comprises a memory device, the memory device comprising K dies; the K dies are divided into N interference intervals, the interference intervals comprising at least one of the dies, and a storage block in each of the dies in the interference intervals together constitutes a partition; K and N are positive integers greater than or equal to 2; the host is configured to: send a command to the memory system to simultaneously execute corresponding operations on each partition corresponding to the command; the partitions corresponding to the command belong to different interference intervals; the memory system is configured to: receive the command to simultaneously execute corresponding operations on each partition corresponding to the command.

[0009] In the disclosed embodiments, a host sends a command to the memory system to simultaneously execute corresponding operations on multiple partitions corresponding to the command. Because each partition corresponding to the command belongs to a different interference interval, the multiple dies occupied by each partition will not be duplicated. Therefore, even if the corresponding operation is executed simultaneously on multiple partitions, the dies will not be busy, and I / O parallelism is increased. In addition, because the size of each partition in the disclosed embodiment is smaller than the size of a virtual storage block, garbage collection overhead is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0011] Figure 1A A schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure.

[0012] Figure 1B A schematic structural diagram of a memory card provided in an embodiment of the present disclosure.

[0013] Figure 1C A schematic diagram of the structure of a solid-state drive provided in an embodiment of the present disclosure.

[0014] Figure 1D and Figure 1E A schematic structural diagram of a memory device including a memory array and peripheral circuits provided in an embodiment of the present disclosure.

[0015] Figure 2 Illustration of a configuration using large partitions for a memory system.

[0016] Figure 3 Diagram of a configuration using small partitions for a memory system.

[0017] Figure 4 FIG. 1 is a schematic diagram of a configuration mode used by a memory system in an embodiment of the present disclosure.

[0018] Figure 5 FIG. 4 is a schematic diagram of a process of forming a plurality of block input / output requests into M request sets and outputting M commands in a host provided by an embodiment of the present disclosure.

[0019] Figure 6 FIG. 5 is a schematic diagram of a process of forming a plurality of block input / output requests into at least one request group in a block device layer of a host in an embodiment of the present disclosure.

[0020] Figure 7 FIG. 6 is a schematic diagram of selecting a target partition in an embodiment of the present disclosure.

[0021] Figure 8 FIG. 7 is a schematic diagram of selecting a target partition in an embodiment of the present disclosure. Figure Two .

[0022] Figure 9 FIG. 8 is a schematic diagram of a configuration mode used by a memory system in an embodiment of the present disclosure. Figure Two .

[0023] Figure 10 FIG. 9 is a schematic diagram of a flow of an operation method of a host provided by an embodiment of the present disclosure.

[0024] Figure 11 FIG. 10 is a schematic diagram of rearranging a first command queue into a second command queue in a memory controller provided by an embodiment of the present disclosure.

[0025] Figure 12 FIG. 11 is a schematic diagram of a flow of an operation method of a memory controller provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description and the accompanying drawings, in which preferred embodiments of the present application are illustrated. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this description, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] As Figure 1AAs shown, the embodiments of the present disclosure show an example system 10 that can include a host 20 and a memory system 30. Wherein the example system 10 can include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device with a memory 34 therein; the host 20 can be a processor (e.g., a Central Processing Unit (CPU) or a System on Chip (SoC) (e.g., an Application Process (AP)) of the electronic device.

[0029] In an embodiment of the present disclosure, the host 20 can be configured to send data to or receive data from the memory system 30. Here, the memory system 30 can include a memory controller 32 and one or more memory devices 34. Wherein the memory device 34 can include, but is not limited to, a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM), a Nano Random Access Memory (NRAM), etc.

[0030] In an embodiment of the disclosure, a memory controller (Memory Controller) 32 can be coupled to the memory device 34 and the host 20, and used to control the memory device 34. Exemplarily, the memory controller 32 can be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 32 can also be designed to operate in a high duty cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC), and the SSD or eMMC can be used as a data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0031] Further, the memory controller 32 can manage data in the memory device 34 and communicate with the host. The memory controller 32 can be configured to control the memory device 34 to read, erase, and program, etc. operations; can also be configured to manage various functions regarding data stored or to be stored in the memory device 34, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.; can also be configured to process error checking and correction (ECC) regarding data read from or written into the memory device 34. In addition, the memory controller 32 can also perform any other suitable functions, such as formatting the memory device 34, or communicating with external devices (e.g., a host) according to a specific communication protocol, etc. Figure 1AFor example, the memory controller 32 can communicate with the external host through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-E (Peripheral Component Interconnect Express) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Development Equipment (IDE) protocol, the Firewire protocol, etc.

[0032] In one embodiment of the present disclosure, the memory controller 32 and one or more memory devices 34 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 30 can be implemented and packaged into different types of terminal electronic products. Figure 1B As shown, the memory controller 32 and the single memory device 34 can be integrated together to form a memory card 40. The memory card 40 may include a PC card (Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 40 may also include a computer that connects the memory card 40 to a host (e.g., Figure 1A The memory card connector 42 is coupled to the host 20 in the embodiment. Figure 1C In another embodiment shown in FIG, the memory controller 32 and the plurality of memory devices 34 may be integrated together to form an SSD 50. The SSD 50 may also include a processor that connects the SSD 50 to a host (e.g., Figure 1ASSD connector 52 coupled to the host 20 in the system 10). In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0033] It should be noted that the memory involved in the embodiments of the present disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information made by semiconductor integrated circuit process. Exemplarily, Figure 1D is a schematic diagram of an optional memory device 34 in the embodiments of the present disclosure. As shown in the figure, Figure 1D The memory device 34 can include a storage array 62 and a peripheral circuit 64 coupled to the storage array 62, etc. Here, the storage array can be a NAND flash storage array, in which storage cells are arranged in the form of a NAND storage string 66 array, and each NAND storage string 66 extends vertically above a substrate. In some embodiments, each NAND storage string 66 can include a plurality of storage cells coupled in series and stacked vertically. Each storage cell holds a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured within the storage cell region. In addition, the storage cells in the above-mentioned storage array 62 can be floating gate type storage cells including floating gate transistors, or charge trapping type storage cells including charge trapping transistors.

[0034] In the embodiments of the present disclosure, the above-mentioned storage cells can be single level cells (SLC) that have two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first threshold voltage range, and a second storage state "1" can correspond to a second threshold voltage range. In other embodiments, each storage cell can be a multi level cell (MLC) capable of storing more than a single bit of data. For example, an MLC can store two bits per cell. Each storage cell can also be a triple level cell (TLC), or each storage cell can also be a quad level cell (QLC). Each MLC can be programmed to a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC can be programmed to one of three possible nominal storage values by writing that value to the storage cell, causing the storage cell to program from an erased state to one of three possible programmed states. A fourth nominal storage value can be used to correspond to the erased state.

[0035] In embodiments of the present disclosure, the peripheral circuit 64 described above can be coupled to the memory array through bit lines (BLs), word lines (WLs), source lines, source select gates (SSGs), and drain select gates (DSGs). Here, the peripheral circuit 64 can include any suitable analog, digital, and mixed-signal circuitry for facilitating relevant operations of the memory array by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell via the bit lines, word lines, source lines, SSGs, or DSGs, etc. Moreover, the peripheral circuit 64 can also include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Exemplarily, as shown in Figure 1E FIG. 1. The peripheral circuit 64 can include page buffers (PBs) / sense amplifiers 71, column decoders / bit line drivers 72, row decoders / word line drivers 73, voltage generators 74, control logic units 75, latch circuitry 76, an interface 77, and a data bus 78. In other embodiments, the peripheral circuit 64 can also include additional peripheral circuitry not shown in Figure 1E

[0036] A memory system with zone namespace (ZNS) function exposes the underlying logic to the host, which enables the host to perform data placement and garbage collection more efficiently, and thus brings many advantages to the whole memory system.

[0037] In some embodiments, the memory system with ZNS function can use a configuration manner of large zones, where a large zone refers to a zone corresponding to a virtual block (VB). Figure 2 A schematic diagram of using the configuration manner of large zones for a memory system. As shown in Figure 2 Each die includes a plurality of blocks. The plurality of blocks are sequentially numbered, for example, starting from 0. The plurality of blocks at the same position (i.e., the same number) in different dies form a virtual block. For example, Block0 of die 0, Block0 of die 1, Block0 of die 2, and Block0 of die 3 form a large zone. In other words, each large zone spans 4 dies. It can be understood that, Figure 2 The 4 dies in FIG. 1 are only examples, and in some embodiments, each large zone can span 16-128 dies. Embodiments of the present disclosure do not limit the number of dies in the memory system. ​

[0038] For the above embodiment, although the large partition configuration mode can improve the parallelism of IO, it has the disadvantage of large garbage collection (GC) overhead. The actual application scenarios of users include the multi-reading scenario of the recommendation system. At this time, the large garbage collection overhead reduces the read-write performance.

[0039] In some embodiments, the memory system with ZNS function can use a small partition configuration mode, where a small partition refers to one partition corresponding to one storage block. Figure 3 A schematic diagram of using a small partition configuration mode for a memory system. As shown in Figure 3 Each die includes a plurality of storage blocks. The plurality of storage blocks are sequentially numbered, for example, starting from 0. Each storage block in a die constitutes a small partition. For example, Block0 of die 0 is a small partition, Block0 of die 1 is a small partition, Block0 of die 2 is a small partition, and Block0 of die 3 is a small partition. In other words, each small partition spans 1 die. When multiple write data are written to disk, from the probability point of view, some dies are relatively busy and the tasks are accumulated, and some dies are relatively idle, which affects the write bandwidth.

[0040] For the above embodiment, although the small partition configuration mode can solve the problem of large garbage collection overhead, it reduces the IO parallelism.

[0041] The large partition configuration mode and the small partition configuration mode each have advantages and disadvantages. The choice of which scheme is a trade-off between garbage collection overhead and parallelism. The large partition configuration mode leads to excessive garbage collection overhead, which affects read-write performance. The small partition configuration mode reduces the parallelism, which also affects the performance.

[0042] To solve one or more of the above problems, the embodiments of the present disclosure provide a host coupled with a memory system supporting a partition namespace function; the memory system includes a memory device including K dies; the K dies are divided into N interference intervals, each of the interference intervals includes at least one of the dies, and one storage block in each die in the interference interval collectively constitutes a partition; K and N are positive integers greater than or equal to 2; the host is configured to: send a command to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command; and each partition corresponding to the command belongs to different interference intervals.

[0043] Embodiments of the present disclosure propose a concept of disturbance area (DA), different disturbance areas include at least one die and do not include all the dies. Whether different partitions can simultaneously perform corresponding operations is determined based on whether the different partitions correspond to the same disturbance area. If the partitions corresponding to two IOs come from the same group of dies (a group of dies can include one or more dies, but cannot include all the dies), they cannot be parallel and will interfere with each other, which is referred to as coming from the same disturbance area. If the partitions corresponding to two IOs do not come from the same group of dies (a group of dies can include multiple dies), they can be parallel and will not interfere with each other, which is referred to as coming from different disturbance areas. Figure 4 In the example shown in FIG. 2, partition 1 and partition 5 come from disturbance area 1, so the two IOs corresponding to partition 1 and partition 5 will interfere with each other. Partition 2 and partition 6 come from disturbance area 2, so the two IOs corresponding to partition 2 and partition 6 will interfere with each other. Partition 3 and partition 7 come from disturbance area 3, so the two IOs corresponding to partition 3 and partition 7 will interfere with each other. Partition 4 and partition 8 come from disturbance area 4, so the two IOs corresponding to partition 4 and partition 8 will interfere with each other.

[0044] Figure 4 In the example shown in FIG. 2, a storage block at the same position (i.e., with the same number) in each die in the same disturbance area forms a partition. That is, Block0 in die 0 and Block0 in die 1 form partition 0. Block1 in die 0 and Block1 in die 1 form partition 4.

[0045] In other embodiments, Block0 in die 0 and Block1 in die 1 can form a partition. Block1 in die 0 and Block0 in die 1 form another partition. That is, one storage block in each die forms a partition.

[0046] It should be noted that in the embodiments of the present disclosure, the K dies are divided into at least two disturbance areas, that is, one disturbance area does not include all the K dies, because when a disturbance area includes all the dies, it is equivalent to using a large partition configuration, which will cause the same problem as using a large partition configuration.

[0047] In the embodiments of the present disclosure, the host sends a command to the memory system to simultaneously perform corresponding operations on a plurality of partitions corresponding to the command. Since the partitions corresponding to the command belong to different disturbance areas, the plurality of dies occupied by the partitions will not be repeated, so that even if the corresponding operations are simultaneously performed on the plurality of partitions, the dies will not be busy, and the IO parallelism is also increased. Moreover, since the size of each partition in the present disclosure is smaller than the size of a virtual storage block, the garbage collection overhead is also reduced.

[0048] In some embodiments, as shown in Figure 5 The host is further configured to:

[0049] generate a plurality of block input / output (IO) requests, and obtain capacity information of the partition and a maximum parallelism of the memory system; the block IO requests carrying logical address information.

[0050] obtain interference interval information corresponding to the block IO requests according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the block IO requests.

[0051] add the corresponding interference interval information in the block IO requests and output the block IO requests.

[0052] divide a plurality of the block IO requests into M request sets according to the interference interval information contained in the block IO requests, wherein the interference interval information contained in each block IO request in a same request set is different, and the M is a positive integer.

[0053] generate M commands conforming to the interface standard of the memory system, each of the commands corresponding to one of the request sets.

[0054] Input / output devices can be divided into two categories: block devices and character devices. Block devices store information in fixed-size blocks, each of which has its own address. SSD is a common block device. Character devices send or receive byte streams without considering any block structure and cannot be addressed. Mouse is a common character device.

[0055] In some embodiments, the file system layer of the host can receive a plurality of input / output (IO) requests submitted by a user and generate a plurality of block input / output (IO, BIO) requests. BIO is an IO operation that describes a block device. BIO not only contains all the information required for this IO operation, but also contains the state during the execution of the IO. According to the information in the BIO, the system can complete the specified IO operation.

[0056] The information contained in the BIO includes but is not limited to: logical address information, command type (e.g., read or write), data size, etc. Here, the logical address information can be the logical block address (LBA) of the data block, which can mean the address of a data block or the data block pointed to by an address.

[0057] The host is coupled with the memory system, and the host can also acquire the capacity information of each partition in the memory system and the maximum parallelism of the memory system through the memory system.

[0058] In some embodiments, the capacity information of each partition can be the same. In other embodiments, the capacity information of each partition can also be different.

[0059] In some embodiments, the maximum parallelism of the memory system is equal to the number of interference intervals. In other embodiments, the maximum parallelism of the memory system can be a preset value. In still other embodiments, the maximum parallelism of the memory system can also be related to the characteristics of the memory system itself such as bandwidth.

[0060] In some embodiments, the firmware can provide the maximum parallelism of the memory system to the host. Specifically, the firmware can place this information in the vendor specific log page, and the host can acquire the maximum parallelism of the memory system by sending a get log page instruction to the memory system.

[0061] According to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the block input / output request, the interference interval information corresponding to the block input / output request can be obtained.

[0062] In the embodiments of the present disclosure, the calculated interference interval information can be added to the BIO, so that the interference interval information can be included in each BIO. The file system layer of the host outputs the BIO carrying the interference interval information to the block device layer of the host.

[0063] The block device layer receives multiple BIOs, and the IO scheduler in the block device layer merges the multiple BIOs into at least one request set. In the embodiments of the present disclosure, the IO scheduler avoids merging the BIOs from different partitions but belonging to the same interference interval into the same request set when merging the BIOs, so as to improve the parallelism and avoid performance degradation caused by the busy die. As shown in FIG. 4, it includes four request sets, and the interference interval information of the BIOs included in each request set is different. For example, the request set 1 includes four BIOs, which correspond to interference interval 1, interference interval 2, interference interval 3, and interference interval 6 respectively. The above four interference interval information is different. Figure 5

[0064] The block device layer outputs multiple request sets to the driver layer, and one request set can correspond to one corresponding command encapsulated according to the interface protocol of the memory system in the driver layer. After encapsulation, the driver layer outputs multiple commands to the memory system. ​

[0065] For the host, it can be coupled with various types of memory systems. Different memory systems have different interface protocols, including but not limited to USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc. By encapsulating each request set into a corresponding command conforming to the interface protocol of the memory system, the corresponding memory system can correctly receive the command and execute the command.

[0066] The memory system receives the command, so that the corresponding operations of the command can be simultaneously performed on each partition corresponding to the command, and each partition corresponding to the command belongs to different interference intervals.

[0067] The embodiments of the present disclosure can execute BIO based on the IO scheduler in the block device layer in the kernel state. Since the IO scheduler itself exists in the block device layer, the embodiments of the present disclosure have less changes to the host, and only need to improve the function of the IO scheduler, so that it can group each block input / output request based on the interference interval information, so that the interference interval information contained in each block input / output request in the same request set is different, that is, the function required by the embodiments of the present disclosure can be realized.

[0068] In some embodiments, the host is configured to:

[0069] According to the capacity information of the partition and the logical address information carried by the block input / output request, the partition corresponding to the block input / output request is obtained.

[0070] According to the partition corresponding to the block input / output request and the maximum parallelism, the interference interval information corresponding to the input / output request is obtained.

[0071] The embodiments of the present disclosure are exemplarily explained with the same capacity information of each partition, the capacity of each partition being 300M, and the maximum parallelism of the memory system being 4.

[0072] Suppose the logical address information carried by the first input / output request is 500M, and the logical address information carried by the second input / output request is 1600M. For the first input / output request, its partition number is [500M / 300M]=1, where [ ] is the rounding symbol, and its corresponding interference interval information is 1 (1 / 4=0 remainder 1, the remainder is used to determine the interference interval information), so it belongs to interference interval 1. For the second input / output request, its partition number is [1600M / 300M]=5, and its corresponding interference interval information is 1 (5 / 4=0 remainder 1), so it also belongs to interference interval 1.

[0073] In some embodiments, the plurality of block input / output requests constitute at least one request group, and each block input / output request in the same request group carries the same interference interval information; the M is equal to the number of block input / output requests in the request group with the largest number of block input / output requests in the at least one request group.

[0074] In some embodiments, the plurality of block input / output requests can be constituted into at least one request group in the block device layer. In combination with Figure 5 and Figure 6 , the plurality of BIOs in the file system layer are divided into 7 request groups in the block device layer, and each BIO in the same request group carries the same interference interval information. For example, each BIO in request group 1 carries interference interval information DA=1. Figure 5 Figure 6 In some embodiments, the number M of request sets can be determined by the number of block input / output requests in the request group with the largest number of block input / output requests in the at least one request group. As shown in

[0075] In some embodiments, the number M of request sets can be determined by the number of block input / output requests in the request group with the largest number of block input / output requests in the at least one request group. As shown in Figure 6 , the number of BIOs contained in request group 1 is the largest, which is 3, so the number of request sets can be equal to 3 or greater than 3.

[0076] In some embodiments, the host is further configured to:

[0077] repeat the first operation M times to obtain the M request sets; the first operation includes selecting one block input / output request from each request group to constitute one request set, and the same block input / output request is only included in one request set.

[0078] Next, the above embodiments will be described by taking Figure 6 as an example.

[0079] Figure 6 ​, request group 1 includes 3 BIOs with DA=1, request group 2 includes 2 BIOs with DA=2, request group 3 includes 1 BIO with DA=3, request group 4 includes 1 BIO with DA=4, request group 5 includes 1 BIO with DA=5, request group 6 includes 1 BIO with DA=6, and request group 7 includes 1 BIO with DA=7.

[0080] In some embodiments, one BIO can be selected from each request group and placed in a request set until the number of BIOs in the request set reaches 0. In this embodiment, request set 1 = (DA=1, DA=2, DA=3, DA=4, DA=5, DA=6, DA=7), request set 2 = (DA=1, DA=2, DA=3, DA=6), and request set 3 = (DA=1).

[0081] The above embodiment can achieve the situation where the number of request sets formed is the minimum and the IO parallelism contained in a single request set is the maximum, thereby effectively saving the time for processing multiple BIOs and improving processing efficiency.

[0082] In some embodiments, an absolute value of a difference between the numbers of the write requests included in any two request sets among the plurality of request sets is less than or equal to a preset value.

[0083] In some embodiments, multiple BIOs can be grouped as evenly as possible so that the absolute value of the difference in the number of BIOs contained in any two request sets in the M request sets is less than or equal to a preset value. For example, the preset value can be 1. Figure 6 The 12 BIOs shown are evenly grouped. In some embodiments, they can be divided into three groups: request set 1 = (DA = 1, DA = 2, DA = 3, DA = 6), request set 2 = (DA = 1, DA = 2, DA = 5, DA = 6), and request set 3 = (DA = 1, DA = 3, DA = 4, DA = 7). This embodiment can simultaneously achieve a minimum number of request sets and similar resources occupied by each request set each time it is processed, thus avoiding stalls caused by an excessive number of write requests in a request set and insufficient memory.

[0084] In other embodiments, the preset value may also be other values, which may be set according to actual application requirements, and the present disclosure does not limit this.

[0085] In some embodiments, the host is configured to send the command to the memory system to simultaneously perform read and write operations on each partition corresponding to the request set corresponding to the command.

[0086] In the embodiments of the present disclosure, the command can include a read command, a write command, and a read-write mixed command, etc.

[0087] In some embodiments, the host is configured to:

[0088] Obtain the interference interval to which each of the plurality of partitions belongs.

[0089] Select part of the plurality of partitions as target partitions; the interference intervals to which the plurality of target partitions belong are different.

[0090] Send the command to the memory system to write the data to be written into the plurality of target partitions, so as to simultaneously execute the write operation on the plurality of target partitions corresponding to the command.

[0091] In some embodiments, as shown in Figure 4 The host is coupled to the memory system, and the host can obtain the interference interval information of each partition through the memory system, so as to determine the interference interval to which each partition belongs. For example, the memory system can inform the host that the interference interval information of partition 0 is 0, the interference interval information of partition 1 is 1, and so on.

[0092] Part of the plurality of partitions are selected as target partitions, and the interference intervals to which the target partitions belong are different. This is because, when the interference intervals to which the target partitions belong are all different, even if the write operation is simultaneously executed on the target partitions, the die is not busy, and the IO parallelism is increased. Moreover, the actual size of each partition is smaller than the size of a virtual storage block, which reduces the garbage collection overhead.

[0093] The host sends a command to the memory system, and the command needs to meet the interface protocol of the connected memory system, so that the memory system can correctly receive the command and execute the command. Moreover, the command can simultaneously execute the write operation on the plurality of target partitions.

[0094] In some embodiments, the host is configured to: obtain the starting logical block address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition; and obtain the interference interval to which each of the plurality of partitions belongs according to the starting logical block address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition.

[0095] In the embodiments of the present disclosure, the host can obtain the start logical block address (SLBA) of each partition of the memory system from the memory system with ZNS function coupled thereto. For example, the host can obtain the start logical block address of each partition of the memory system by sending a query instruction to the memory system.

[0096] The embodiments of the present disclosure are exemplarily described with the same capacity information of each partition, the capacity of each partition being 300M, and the maximum parallelism of the memory system being 4. It is assumed that the start logical block address of the first partition is 300M. The start logical block address of the second partition is 1500M. For the first partition, its partition number is [300M / 300M] = 1, where [] is the rounding symbol, and its corresponding interference interval information is 1 (1 / 4 = 0 remainder 1, the remainder is used to determine the interference interval information), so it belongs to interference interval 1. For the second partition, its partition number is [1500M / 300M] = 5, and its corresponding interference interval information is 1 (5 / 4 = 0 remainder 1), so it also belongs to interference interval 1.

[0097] The embodiments of the present disclosure can calculate the interference interval to which each of the plurality of partitions belongs according to the start logical block address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition, so that the target partition can be selected based on the corresponding interference interval of each partition. By avoiding selecting partitions with the same interference interval information as the target partition, the write operation can be performed on multiple partitions at the same time without causing die busy and other problems.

[0098] In some embodiments, the host is configured to:

[0099] According to the hotness and data type of the data to be written, the number of target partitions required is determined.

[0100] For example, for a flash friendly file system (F2FS), it includes two types of storage blocks: NODE type storage blocks and DATA type storage blocks, where the NODE type storage blocks are used to store index data of files, and the DATA type storage blocks store actual data of files. Therefore, the data to be written includes NODE type and DATA type, and needs to be written into the corresponding type of storage block.

[0101] Data can be divided into three categories according to the degree of hotness, including hot, warm, and cold. In some embodiments, the data temperature can be related to the frequency of data usage, and in other embodiments, the data temperature can be defined based on the data type. For example, the data block of a directory can be fixed as hot data. In other embodiments, the data temperature can be defined based on other data characteristics.

[0102] Therefore, for the above-mentioned flash-friendly file system, as shown in Figure 7 The above-mentioned six data correspond to six different partitions, so the number of required target partitions is six.

[0103] It should be understood that the above-mentioned flash-friendly file system including six data is only an example. In some embodiments, the degree of hotness of the data of the flash-friendly file system can include only one or two, or even more than three. The data type of the data of the flash-friendly file system can also include one or more than two. The present disclosure does not limit this.

[0104] In addition, the present disclosure can also be applied to other file systems, not limited to various other flash file systems, hard disk file systems, etc.

[0105] In the embodiments of the present disclosure, based on the degree of hotness and the data type of the data of F2FS, the number of six required target partitions is determined, and the six partitions can be partition 1 (DA=1), partition 2 (DA=2), partition 3 (DA=3), partition 4 (DA=4, partition 5 (DA=5), and partition 6 (DA=6). It should be understood that the selection of the six target partitions in the above-mentioned embodiments is only an example, and in fact, only the interference intervals corresponding to the six target partitions are different.

[0106] In some embodiments, the host is configured to determine the number of required target partitions according to the number of application programs from which the to-be-written data comes.

[0107] In some embodiments, if there are 6 different applications (APPs) issuing requests, and data from different APPs need to be written into different partitions, the target partitions corresponding to 6 different interference intervals need to be opened to operate the 6 different APPs at the same time. The number of target partitions required is 6. The 6 partitions can be partition 1 (DA = 1), partition 2 (DA = 2), partition 3 (DA = 3), partition 4 (DA = 4), partition 5 (DA = 5), and partition 6 (DA = 6). It should be understood that the number of APPs and the selection of 6 target partitions in the above embodiments are only examples, and in fact, only the interference intervals corresponding to the 6 target partitions need to be different.

[0108] In some embodiments, the host is configured to: when one of the plurality of target partitions is full, select a new partition from the plurality of partitions as a new target partition; the interference interval to which the new target partition belongs is different from the interference interval to which the target partition that is not full among the plurality of target partitions belongs.

[0109] In combination with Figure 8 and Figure 9 , if partition 6 is full, a new target partition needs to be opened, and a new partition is selected from the plurality of partitions as a new target partition (for example, partition 15 (DA = 7)), the interference interval to which the new target partition belongs is different from the interference interval to which the target partition that is not full among the plurality of target partitions belongs, so that the die busy problem is not caused.

[0110] The embodiments of the present disclosure also provide an operation method of a host, the host being coupled with a memory system supporting a partition namespace function; the memory system comprising a memory device, the memory device comprising K dies; the K dies are divided into N interference intervals, each of the interference intervals comprising at least one of the dies, and one memory block in each of the dies in the interference interval collectively forming a partition; K and N are positive integers greater than or equal to 2; as Figure 10 shown, the method comprises:

[0111] Step S1, sending a command to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command; each partition corresponding to the command belongs to different interference intervals.

[0112] In the embodiments of the present disclosure, a host sends a command to a memory system to simultaneously perform corresponding operations on a plurality of partitions corresponding to the command. Since the partitions corresponding to the command belong to different interference intervals, the plurality of dies occupied by each partition will not be repeated, so that even if the corresponding operations are simultaneously performed on the plurality of partitions, the dies will not be busy, and the IO parallelism is also increased. Moreover, since the size of each partition in the present disclosure is smaller than the size of a virtual storage block, the garbage collection overhead is also reduced.

[0113] In some embodiments, the method further comprises:

[0114] generating a plurality of block input / output requests, and obtaining capacity information of the partition and maximum parallelism of the memory system; the block input / output request carries logical address information;

[0115] obtaining interference interval information corresponding to the block input / output request according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the block input / output request;

[0116] adding the corresponding interference interval information in the block input / output request and outputting the block input / output request;

[0117] dividing a plurality of block input / output requests into M request sets according to the interference interval information contained in the block input / output request, wherein the interference interval information contained in each block input / output request in the same request set is different, and M is a positive integer;

[0118] generating M commands conforming to the interface standard of the memory system, each of the commands corresponding to one of the request sets.

[0119] In some embodiments, the dividing a plurality of block input / output requests into M request sets according to the interference interval information contained in the block input / output request comprises:

[0120] dividing the plurality of block input / output requests into at least one request group, the interference interval information carried by each input / output request in the same request group being the same; and M is equal to the number of block input / output requests in the request group with the largest number of block input / output requests in the at least one request group.

[0121] In some embodiments, the dividing a plurality of block input / output requests into M request sets according to the interference interval information contained in the block input / output request further comprises:

[0122] The first operation is repeated M times to obtain the M request sets; the first operation comprises selecting one block input / output request from each of the request groups to form one request set, and the same block input / output request is only included in one request set.

[0123] In some embodiments, the interference interval information corresponding to the input / output request is obtained according to the logical address information carried by the input / output request, the capacity information of the partition, and the maximum parallelism, and the interference interval information corresponding to the input / output request is obtained.

[0124] The partition corresponding to the input / output request is obtained according to the capacity information of the partition and the logical address information carried by the input / output request.

[0125] The interference space information corresponding to the input / output request is obtained according to the partition corresponding to the input / output request and the maximum parallelism.

[0126] In some embodiments, the method further comprises:

[0127] The command is sent to the memory system to simultaneously perform read / write operations on each partition corresponding to the request set corresponding to the command.

[0128] In some embodiments, the method further comprises:

[0129] Obtaining the interference interval to which each of the plurality of partitions belongs;

[0130] Selecting part of the plurality of partitions as target partitions; the interference intervals to which the plurality of target partitions each belong are different;

[0131] The command is sent to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command.

[0132] The command is sent to the memory system to write the data to be written into the plurality of target partitions, so as to simultaneously perform write operations on the plurality of target partitions.

[0133] In some embodiments, the interference interval to which each of the plurality of partitions belongs is obtained by:

[0134] Obtaining the starting logical address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition;

[0135] The interference interval to which each of the plurality of partitions belongs is obtained according to the starting logical address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition.

[0136] In some embodiments, the method further comprises:

[0137] According to the degree of hotness and the type of the data to be written, the number of the target partitions required is determined.

[0138] In some embodiments, the method further comprises:

[0139] According to the category of the application program from which the data to be written comes, the number of the target partitions required is determined.

[0140] In some embodiments, the method further comprises:

[0141] When one of the target partitions is full, a new partition is selected from the plurality of partitions as a new target partition; the interference interval to which the new target partition belongs is different from the interference interval to which the target partition that is not full belongs.

[0142] As to the method in the above embodiments, the specific execution method has been described in detail in the embodiments of the product corresponding to the method, and will not be described in detail here.

[0143] In some embodiments, the memory controller comprises a hardware queue (Hardware Queue) that receives M read-write commands and outputs every N read-write commands as a command group. Wherein, M and N are integers, and M is greater than N. For the first command group, it includes the first read-write command to the Nth read-write command in the M read-write commands, for the second command group, it includes the N+1th read-write command to the 2Nth read-write command in the M read-write commands, and so on. In this embodiment, N read-write commands are sequentially selected from M read-write commands as a command group output in the order of first-in-first-out.

[0144] For the above embodiments, if the interference interval corresponding to the N read-write commands in a command group has at least two same interference intervals, at least part of the dies will be busy and unable to implement simultaneous read-write operations on the N read-write commands. Thus, the performance of the memory controller is reduced.

[0145] To solve the above problems, the embodiments of the present disclosure also provide a memory system, the memory system comprises a memory device and a memory controller coupled with the memory device, and the memory system supports a partition namespace function; the memory device comprises K dies; the K dies are divided into N interference intervals, each interference interval comprises at least one die, and a storage block in each die in the interference interval collectively constitutes a partition; K and N are positive integers greater than or equal to 2; the memory controller is configured to:

[0146] receiving a first command queue; the first command queue comprising a plurality of read-write commands.

[0147] obtaining capacity information of the partition, maximum parallelism of the memory system, and logical address information carried by each of the read-write commands.

[0148] obtaining interference interval information corresponding to each of the read-write commands according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the read-write commands.

[0149] dividing the plurality of read-write commands into M command sets according to the interference interval information contained in the read-write commands; wherein the interference interval information contained in each of the read-write commands in a same command set is different, and M is a positive integer.

[0150] In the embodiments of the present disclosure, a first hardware queue of a memory controller receives a first command queue, and the first command queue comprises a plurality of read-write commands.

[0151] Here, the plurality of read-write commands can be a plurality of read commands, a plurality of write commands, and a plurality of read-write hybrid commands.

[0152] In some embodiments, the number of the plurality of read-write commands in the first command queue can be equal to a preset number. In some embodiments, the preset number can be greater than or equal to the maximum parallelism of the memory system. In other embodiments, the preset number can be a positive integer greater than or equal to 2.

[0153] In other embodiments, the number of the plurality of read-write commands in the first command queue can be equal to the number of read commands within a preset time.

[0154] A reschedule pool of the memory controller receives all the read-write commands in the first command queue and re-schedules them. The reschedule pool divides the plurality of read-write commands into M command sets according to the interference interval information contained in the read-write commands. The interference interval information contained in each of the read-write commands in a same command set is different.

[0155] The reschedule pool sequentially outputs the M command sets to a second hardware queue.

[0156] In some embodiments, the memory controller is further configured to simultaneously perform read-write operations on the partitions corresponding to each of the plurality of read-write commands in a same command set.

[0157] In the embodiments of the present disclosure, the interference interval information corresponding to each of the read-write commands can be added in the first hardware queue, or the interference interval information corresponding to each of the read-write commands can be added in the reschedule pool.

[0158] In the embodiments of the present disclosure, the capacity information of the partition, the maximum parallelism of the memory system and the logical address information carried by each read-write command are obtained. According to the capacity information of the partition, the maximum parallelism and the logical address information carried by the read-write command, the interference interval information corresponding to the read-write command is obtained.

[0159] The embodiments of the present disclosure are exemplarily described with the same capacity information of each partition, the capacity of each partition being 300M and the maximum parallelism of the memory system being 4.

[0160] Suppose that the logical address information carried by the first read-write command is 500M and the logical address information of the second read-write command is 1600M. For the first read-write command, the partition number thereof is [500M / 300M]=1, where [] is the rounding symbol, and the interference interval information corresponding thereto is 1 (1 / 4=0 with a remainder of 1, and the remainder is used to determine the interference interval information), so it belongs to the interference interval 1. For the second read-write command, the partition number thereof is [1600M / 300M]=5, and the interference interval information corresponding thereto is 1 (5 / 4=0 with a remainder of 1), so it also belongs to the interference interval 1.

[0161] In the embodiments of the present disclosure, the plurality of read-write commands received are rearranged to obtain M command sets, and the read-write operation is simultaneously performed on the partitions corresponding to the plurality of read-write commands in the same command set. Since the partitions corresponding to the plurality of read-write commands in the same command set belong to different interference intervals, the plurality of dies occupied by each partition will not be repeated, so that even if the corresponding operation is simultaneously performed on the plurality of partitions, the dies will not be busy, and the IO parallelism is also increased. Moreover, since the size of each partition in the present disclosure is smaller than the size of a virtual storage block, the garbage collection overhead is also reduced.

[0162] In some embodiments, the memory controller is further configured to:

[0163] The plurality of read-write commands are divided into M command groups according to the interference interval information contained in the read-write command, and the interference interval information corresponding to each read-write command in the same command group is the same.

[0164] The second operation is repeatedly performed M times to obtain the M command sets; the second operation includes selecting one read-write command from each command group to form one command set, and the same read-write command is only included in one command set.

[0165] Hereinafter, the above embodiments are described with the following examples. Figure 11

[0166] ​The first command queue may include 8 commands, for example, command 1 (DA=0), command 2 (DA=0), command 3 (DA=1), command 4 (DA=1), command 5 (DA=2), command 6 (DA=2), command 7 (DA=3) and command 8 (DA=1).

[0167] Commands with the same interference interval information are placed in the same command group.

[0168] Therefore, the first command group includes command 1 (DA=0) and command 2 (DA=0). The second command group includes command 3 (DA=1), command 4 (DA=1), and command 8 (DA=1). The third command group includes command 5 (DA=2) and command 6 (DA=2). The fourth command group includes command 7 (DA=3).

[0169] In some embodiments, a command can be selected from each command group and placed in a command set until the number of commands in the command set is 0. In this embodiment, command set 1 = (command 1 (DA=0), command 3 (DA=1), command 5 (DA=2), command 7 (DA=3)), command set 2 = (command 2 (DA=0), command 4 (DA=1), command 6 (DA=2)), and command set 3 = (command 8 (DA=1)).

[0170] For the above embodiment, the number of command sets constructed can be minimized, and the IO parallelism contained in a single command set can be maximized, thereby effectively saving time for processing multiple commands and improving processing efficiency.

[0171] In some embodiments, an absolute value of a difference between the numbers of the write requests included in any two command sets among the plurality of command sets is less than or equal to a preset value.

[0172] In some embodiments, the multiple commands may be grouped as evenly as possible so that the absolute value of the difference in the number of commands included in any two command sets in the multiple command sets is less than or equal to a preset value. For example, the preset value may be 1.

[0173] Will Figure 11 The 8 commands shown are evenly grouped. In some embodiments, they can be divided into 4 groups, command set 1 = (command 1 (DA = 0), command 3 (DA = 1), command 5 (DA = 2)), command set 2 = (command 2 (DA = 0), command 4 (DA = 1), command 6 (DA = 2)), command set 3 = (command 8 (DA = 1), command 7 (DA = 3)).

[0174] For this embodiment, the number of command sets formed can be minimized and the resources occupied by each command set during each processing can be similar, avoiding the situation of too many write requests in a command set and insufficient memory, causing the situation of lag.

[0175] In other embodiments, the preset value can also be other numerical values, which can be set according to actual application requirements. The present disclosure does not limit here.

[0176] The present disclosure also provides an operation method of a memory system, the memory system including a memory device and a memory controller coupled with the memory device, and the memory system supporting a partitioned namespace function; the memory system includes a memory device, the memory device including K dies; the K dies are divided into N interference intervals, each interference interval including at least one of the dies, and one memory block in each die in the interference interval collectively constituting a partition; K and N are positive integers greater than or equal to 2; as shown in the figure, the method includes: Figure 12

[0177] Step S2, receiving a first command queue; the first command queue includes a plurality of read-write commands.

[0178] Step S3, obtaining capacity information of the partition, maximum parallelism of the memory system, and logical address information carried by each read-write command.

[0179] Step S4, obtaining interference interval information corresponding to the read-write command according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the read-write command.

[0180] Step S5, dividing a plurality of read-write commands into M command sets according to the interference interval information included in the read-write commands; wherein the interference interval information included in each read-write command in the same command set is different, and M is a positive integer.

[0181] In the present disclosure, M command sets are obtained by rearranging a plurality of received read-write commands, and read-write operations are simultaneously performed on the partitions corresponding to each of the plurality of read-write commands in the same command set. Since each partition corresponding to the plurality of read-write commands in the same command set belongs to a different interference interval, the plurality of dies occupied by each partition will not be repeated, so that even if the corresponding operations are simultaneously performed on a plurality of partitions, the dies will not be busy, and the IO parallelism is also increased. Moreover, since the size of each partition in the present disclosure is smaller than the size of a virtual memory block, the garbage collection overhead is also reduced.

[0182] ​In some embodiments, the dividing the plurality of read-write commands into M command sets according to the interference interval information included in the read-write commands comprises:

[0183] The dividing the plurality of read-write commands into M command groups according to the interference interval information included in the read-write commands, the interference interval information corresponding to each read-write command in a same command group is identical.

[0184] The repeating the second operation M times to obtain the M command sets, the second operation comprising selecting one read-write command from each command group to form one command set, and a same read-write command being included in only one command set.

[0185] In some embodiments, the method further comprises:

[0186] Simultaneously performing read-write operations on each corresponding partition of the plurality of read-write commands in a same command set.

[0187] As to the method in the above-mentioned embodiments, the specific execution method has been described in detail in the embodiments of the product corresponding to the method, and will not be described in detail here.

[0188] The embodiments of the present disclosure also provide an electronic device, which comprises a host and a memory system coupled with the host and supporting a partitioned namespace function. The memory system comprises a memory device, the memory device comprising K dies; the K dies are divided into N interference intervals, each interference interval comprising at least one die, and one memory block in each die in the interference interval collectively forming a partition; K and N are positive integers greater than or equal to 2; and the host is configured to:

[0189] sending a command to the memory system to simultaneously perform a corresponding operation on each partition corresponding to the command; each partition corresponding to the command belongs to different interference intervals.

[0190] The memory system is configured to:

[0191] receiving the command to simultaneously perform a corresponding operation on each partition corresponding to the command.

[0192] In the embodiments of the present disclosure, the electronic device includes but is not limited to a personal computer, a digital camera, a mobile phone, a smart watch, a smart home, etc.

[0193] It should be understood that any reference to an "embodiment" or "one embodiment" or "an embodiment" or "one implementation" or "one implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the disclosure. The appearance of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, many of the implementations described herein are implemented in one or more of hardware, software, firmware, or combinations thereof. Various modifications to these implementations can be made by those skilled in the art, to the full extent allowed by the patent laws, without departing from the scope of the present disclosure. Accordingly, the various implementations described herein can be implemented in a variety of ways.

[0194] It should be noted that, as used in this document, the terms "includes," "including," "has," "having," or the like are intended to be open-ended: thus, a process, method, article, or apparatus that includes a series of elements is not required to have only those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Also, the terms "a" or "an" or the like are intended to mean "one or more" or "at least one," unless otherwise indicated.

[0195] The above description is only the preferred implementation of the present disclosure. The protection scope of the present disclosure is not limited to this, and any modification or replacement within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure.

Claims

1. A host, characterized by, The host is coupled with a memory system supporting a partition namespace function; the memory system comprises a memory device, the memory device comprises K dies; the K dies are divided into N interference intervals, each interference interval comprises at least one of the dies, and one memory block in each die in the interference interval jointly constitutes a partition; K and N are positive integers greater than or equal to 2; the host is configured to: send a command to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command; each partition corresponding to the command belongs to different interference intervals.

2. The host of claim 1, wherein, The host is further configured to: generate a plurality of block input / output requests, and obtain capacity information of the partitions and a maximum parallelism of the memory system; the block input / output requests carry logical address information; obtain interference interval information corresponding to the block input / output requests according to the capacity information of the partitions, the maximum parallelism, and the logical address information carried by the block input / output requests; add the corresponding interference interval information in the block input / output requests and output the block input / output requests; divide a plurality of the block input / output requests into M request sets according to the interference interval information contained in the block input / output requests, wherein the interference interval information contained in each block input / output request in a same request set is different, and M is a positive integer; generate M commands conforming to an interface standard of the memory system, and each command corresponds to a request set.

3. The host of claim 2, wherein, The plurality of block input / output requests constitute at least one request group, and the block input / output requests in a same request group carry the same interference interval information; M is equal to the number of block input / output requests in a request group with the largest number of block input / output requests in the at least one request group.

4. The host of claim 3, wherein, The host is further configured to: repeat a first operation M times to obtain the M request sets; the first operation comprises selecting one block input / output request from each request group to form a request set, and a same block input / output request is only contained in one request set.

5. The host of claim 2, wherein, The host is configured to: obtain a partition corresponding to the block input / output request according to the capacity information of the partitions and the logical address information carried by the block input / output request; obtain interference interval information corresponding to the block input / output request according to the partition corresponding to the block input / output request and the maximum parallelism.

6. The host of claim 2, wherein, The host is configured to: send the command to the memory system to simultaneously perform read / write operations on each partition corresponding to a request set corresponding to the command.

7. The host of claim 1, wherein, The host is configured to: obtain interference intervals to which a plurality of the partitions respectively belong; select part of the partitions as target partitions from the plurality of the partitions; the interference intervals to which the plurality of the target partitions respectively belong are different; send the command to the memory system to write to-be-written data into the plurality of the target partitions, to simultaneously perform write operations on the plurality of target partitions corresponding to the command.

8. The host of claim 7, wherein, The host is configured to: obtaining a starting logical address of each partition of the memory system, a maximum parallelism of the memory system, and capacity information of the partition; obtaining a plurality of interference intervals to which each of the plurality of partitions belongs according to the starting logical address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition.

9. The host of claim 7, wherein, The host is configured to: determine the number of target partitions required according to the degree of hotness and the type of data of the data to be written.

10. The host of claim 7, wherein, The host is configured to: determine the number of target partitions required according to the number of application programs from which the data to be written comes.

11. The host of claim 7, wherein, The host is configured to: When one of the plurality of target partitions is full, a new partition is selected from the plurality of partitions as a new target partition; the interference interval to which the new target partition belongs is different from the interference interval to which the target partition that is not full belongs.

12. An operation method of a host, the method comprising: The host is coupled to a memory system supporting a partition namespace function; the memory system includes a memory device including K dies; the K dies are divided into N interference intervals, each of the interference intervals includes at least one of the dies, and one memory block in each of the dies in the interference interval collectively constitutes a partition; K and N are positive integers greater than or equal to 2; the method comprises: sending a command to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command; each partition corresponding to the command belongs to different interference intervals.

13. The method of operation of claim 12, wherein, The method further comprises: generating a plurality of block input / output requests, obtaining capacity information of the partition, and obtaining a maximum parallelism of the memory system; the block input / output request carries logical address information; obtaining interference interval information corresponding to the block input / output request according to the capacity information of the partition, the maximum parallelism, and the logical address information carried by the block input / output request; adding corresponding interference interval information in the block input / output request and outputting the block input / output request; dividing a plurality of block input / output requests into M request sets according to the interference interval information included in the block input / output request, wherein the interference interval information included in each block input / output request in the same request set is different, and M is a positive integer; generating M commands conforming to the interface standard of the memory system, each command corresponding to a request set.

14. The method of claim 13, wherein, The dividing of a plurality of block input / output requests into M request sets according to the interference interval information included in the block input / output request comprises: dividing the plurality of block input / output requests into at least one request group, the interference interval information carried by each block input / output request in the same request group being the same; M is equal to the number of block input / output requests in the request group with the largest number of block input / output requests in the at least one request group.

15. The method of operation of claim 14, wherein, The dividing of a plurality of block input / output requests into M request sets according to the interference interval information included in the block input / output request further comprises: The first operation is repeated M times to obtain the M request sets; the first operation includes selecting one block input / output request from each of the request groups to form one request set, and the same block input / output request is only included in one request set.

16. The method of claim 13, wherein, The interference interval information corresponding to the input / output request is obtained according to the logical address information carried by the input / output request, the capacity information of the partition, and the maximum parallelism. The partition corresponding to the block input / output request is obtained according to the capacity information of the partition and the logical address information carried by the block input / output request. The interference space information corresponding to the block input / output request is obtained according to the partition corresponding to the input / output request and the maximum parallelism.

17. The method of claim 12, wherein, The command is sent to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command. The command is sent to the memory system to simultaneously perform read / write operations on each partition corresponding to the request set corresponding to the command.

18. The method of claim 12, wherein, The method further includes: Obtaining the interference intervals to which each of the plurality of partitions belongs; Selecting part of the plurality of partitions as target partitions; the interference intervals to which each of the plurality of target partitions belongs are different. The command is sent to the memory system to simultaneously perform corresponding operations on each partition corresponding to the command. The command is sent to the memory system to simultaneously perform write operations on the plurality of target partitions.

19. The method of operation of claim 18, wherein, The interference intervals to which each of the plurality of partitions belongs are obtained, including: Obtaining the starting logical address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition; The interference intervals to which each of the plurality of partitions belongs are obtained according to the starting logical address of each partition of the memory system, the maximum parallelism of the memory system, and the capacity information of the partition.

20. The method of claim 18, wherein, The method further includes: According to the degree of hotness and the type of data of the to-be-written data, the number of target partitions required is determined.

21. The method of claim 18, wherein, The method further includes: According to the type of the application program from which the to-be-written data comes, the number of target partitions required is determined.

22. The method of claim 18, wherein, The method further includes: When one of the plurality of target partitions is full, a new partition is selected from the plurality of partitions as a new target partition; the interference interval to which the new target partition belongs is different from the interference interval to which the target partition that is not full among the plurality of target partitions belongs.

23. A memory system, comprising: The memory system includes a memory device and a memory controller coupled to the memory device, and the memory system supports a partition namespace function; the memory device includes K dies; the K dies are divided into N interference intervals, each of the interference intervals includes at least one die, and one memory block in each die in the interference interval collectively forms a partition; K and N are positive integers greater than or equal to 2; the memory controller is configured to: Receive a first command queue; the first command queue includes a plurality of read / write commands; obtaining capacity information of the partitions, maximum parallelism of the memory system, and logical address information carried by each of the read-write commands; obtaining interference interval information corresponding to the read-write commands according to the capacity information of the partitions, the maximum parallelism, and the logical address information carried by the read-write commands; dividing the read-write commands into M command sets according to the interference interval information included in the read-write commands, wherein the interference interval information included in each read-write command in a same command set is different, and M is a positive integer.

24. The memory system of claim 23, wherein, The memory controller is further configured to: divide the read-write commands into M command groups according to the interference interval information included in the read-write commands, wherein the interference interval information corresponding to each read-write command in a same command group is the same; repeat the second operation M times to obtain the M command sets, wherein the second operation includes selecting one read-write command from each command group to form one command set, and a same read-write command is included in only one command set.

25. The memory system of claim 23, wherein, The memory controller is configured to: perform read-write operations on the partitions corresponding to each of the read-write commands in a same command set simultaneously.

26. An operating method of a memory system, characterized by, The memory system includes a memory device and a memory controller coupled to the memory device, and supports a partitioned namespace function; the memory system includes a memory device, and the memory device includes K dies; the K dies are divided into N interference intervals, each of the interference intervals includes at least one die, and one memory block in each die in the interference interval forms one partition; K and N are positive integers greater than or equal to 2; and the method includes: receiving a first command queue; the first command queue includes a plurality of read-write commands; obtaining capacity information of the partitions, maximum parallelism of the memory system, and logical address information carried by each of the read-write commands; obtaining interference interval information corresponding to the read-write commands according to the capacity information of the partitions, the maximum parallelism, and the logical address information carried by the read-write commands; dividing the read-write commands into M command sets according to the interference interval information included in the read-write commands, wherein the interference interval information included in each read-write command in a same command set is different, and M is a positive integer.

27. The method of operation of claim 26, wherein, The dividing the read-write commands into M command sets according to the interference interval information included in the read-write commands includes: dividing the read-write commands into M command groups according to the interference interval information included in the read-write commands, wherein the interference interval information corresponding to each read-write command in a same command group is the same; repeating the second operation M times to obtain the M command sets, wherein the second operation includes selecting one read-write command from each command group to form one command set, and a same read-write command is included in only one command set.

28. The method of claim 26, wherein, The method further includes: performing read-write operations on the partitions corresponding to each of the read-write commands in a same command set simultaneously.

29. An electronic device, comprising: The electronic device includes a host and a memory system coupled to the host and supporting a partitioned namespace function; The memory system includes a memory device including K dies; the K dies are divided into N interference zones, each of the interference zones including at least one of the dies, and one memory block in each of the dies in the interference zone collectively forming a partition; K and N are positive integers greater than or equal to 2; and the host is configured to: send a command to the memory system to simultaneously perform a corresponding operation on each partition corresponding to the command; and each partition corresponding to the command belongs to different interference zones; The memory system is configured to: receive the command to simultaneously perform a corresponding operation on each partition corresponding to the command.

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