A method for decoding NAND Flash data, a computer device, and a storage medium.

Abstract

This application proposes a method, computer device, and storage medium for decoding NAND Flash data. The method includes: receiving a modulation request for an original codeword and performing BPSK modulation on the original codeword to obtain a first value and a second value; adding noise to the first and second values ​​according to a preset Gaussian distribution to obtain a target Gaussian distribution and a target codeword; when there are overlapping regions in the target Gaussian distribution, calculating the boundaries of the overlapping regions to obtain a target boundary to obtain a target region; dividing the target region into LLR regions to obtain thresholds for multiple LLR regions; performing LLR quantization on the target codeword according to the thresholds of the multiple LLR regions to obtain LLR information of the target codeword; and inputting the LLR information of the target codeword into LDPC for decoding to obtain decoded information. This application makes the decoding error correction performance obtained by LDPC simulation more reliable, practical, and closer to the decoding error correction performance in NAND Flash module applications.

Description

Technical Field

[0001] This application relates to the field of NAND Flash data decoding technology, and in particular to a NAND Flash data decoding method, computer device and storage medium. Background Technology

[0002] In related technologies, NAND Flash, as a type of flash memory, is widely used in various electronic devices and is an indispensable and crucial component. NAND Flash types include SLC, MLC, TLC, and QLC. Due to the physical characteristic of bit flipping in the stored data, almost all NAND Flash modules require the use of an ECC module. Currently, LDPC code is the most common ECC code for NAND Flash modules. LDPC typically has good error correction capabilities to cope with bit flipping in NAND Flash data.

[0003] The decoding and error correction performance of LDPC typically depends on its iterative algorithm and, more importantly, its parity check matrix. LDPC simulation is the most important way to verify its decoding iterative algorithm and parity check matrix. Currently, the mainstream LDPC simulation uses Gaussian white noise as the noise model to simulate NAND Flash noise: that is, after LDPC codewords are BPSK modulated, they are then noised with Gaussian white noise, resulting in noisy codewords. Finally, LDPC decodes this noisy codeword, completing one LDPC simulation decoding. By repeatedly performing the above operation, the performance of the LDPC decoding iterative algorithm and parity check matrix can be evaluated after the test volume reaches the standard. However, this method is difficult to use for reliability assessment in real-world NAND Flash applications. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for decoding NAND Flash data, a computer device, and a storage medium, aiming to improve the reliability and practicality of decoding and error correction performance.

[0005] In a first aspect, embodiments of this application provide a method for decoding NAND Flash data, including:

[0006] Receive the modulation request of the original codeword and perform BPSK modulation on the original codeword to obtain a first value and a second value;

[0007] Noise is added to the first and second values ​​according to a preset Gaussian distribution to obtain the target Gaussian distribution and the target codeword.

[0008] When the target Gaussian distribution has overlapping regions, the boundary of the overlapping regions is calculated to obtain the target boundary and thus the target region.

[0009] The target region is divided into LLR regions to obtain the thresholds of multiple LLR regions;

[0010] The target codeword is LLR quantized based on the thresholds of multiple LLR regions to obtain the LLR information of the target codeword;

[0011] The LLR information of the target codeword is input into LDPC for decoding to obtain the decoded information.

[0012] According to some embodiments of this application, the target Gaussian distribution includes a first initial Gaussian distribution and a second initial Gaussian distribution, and the target codeword includes a first initial codeword and a second initial codeword.

[0013] According to some embodiments of this application, the step of adding noise to the first value and the second value according to a preset Gaussian distribution to obtain a target Gaussian distribution and a target codeword includes:

[0014] Noise is added to the first value according to a preset first Gaussian distribution to obtain a first initial Gaussian distribution and a first initial codeword;

[0015] The second value is noise-added according to the preset second Gaussian distribution to obtain the second initial Gaussian distribution and the second initial codeword.

[0016] According to some embodiments of this application, calculating the boundary of the overlapping region to obtain the target region includes:

[0017] Obtain the preset value covered by the first initial Gaussian distribution;

[0018] The boundary of the overlapping region is calculated based on the preset value, the first value, the second value, the first initial Gaussian distribution, and the second initial Gaussian distribution to obtain the target boundary and thus the target region.

[0019] According to some embodiments of this application, the step of calculating the boundary of the overlapping region based on the preset value, the first value, the second value, the first initial Gaussian distribution, and the second initial Gaussian distribution to obtain the target boundary and thus the target region includes:

[0020] The first initial boundary of the overlapping region is obtained based on the preset value, the first value, and the first initial Gaussian distribution.

[0021] The second initial boundary of the overlapping region is obtained based on the preset value, the second value, and the second initial Gaussian distribution;

[0022] The boundary of the overlapping region is calculated based on the first initial boundary and the second initial boundary to obtain the target boundary and thus the target region.

[0023] According to some embodiments of this application, the threshold for dividing the target region into multiple LLR regions includes:

[0024] The target region is divided into multiple LLR regions.

[0025] The boundaries of the multiple LLR regions are obtained by calculating based on the inverse cumulative distribution function or LDPC and a preset cumulative distribution;

[0026] The threshold of the multiple LLR regions is obtained by obtaining the midpoint of the multiple LLR regions based on the boundaries of the multiple LLR regions.

[0027] According to some embodiments of this application, the step of performing LLR quantization on the target codeword based on thresholds of multiple LLR regions to obtain the LLR information of the target codeword includes:

[0028] Obtain the LLR value of the target codeword;

[0029] The LLR value is compared with thresholds of multiple LLR regions to determine the LLR region to which the LLR value belongs;

[0030] The LLR value is quantized according to the LLR region to which it belongs.

[0031] According to some embodiments of this application, the step of inputting the LLR information of the target codeword into LDPC for decoding to obtain decoded information includes:

[0032] According to the parity-check matrix structure of the LDPC code, iterative decoding operations are performed based on the LLR information;

[0033] When a preset stopping condition is met, the iteration stops and the decoded information is output. The preset stopping condition includes at least one of the following: the number of iterations of decoding operation reaches a preset number threshold, the decoded information satisfies a preset verification equation, and the difference between the decoded information of two consecutive iterations is less than a preset difference threshold.

[0034] Secondly, embodiments of this application provide a computer device, including:

[0035] At least one memory;

[0036] At least one processor;

[0037] At least one computer program;

[0038] The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the NAND Flash data decoding method described in the first aspect above.

[0039] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program for causing a computer to execute the NAND Flash data decoding method described in the first aspect.

[0040] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: First, a modulation request for the original codeword is received and BPSK modulation is performed on the original codeword to obtain a first value and a second value; noise is added to the first value and the second value according to a preset Gaussian distribution to obtain a target Gaussian distribution and a target codeword; when there is an overlapping region in the target Gaussian distribution, the boundary of the overlapping region is calculated to obtain the target boundary to obtain the target region; the target region is divided into LLR regions to obtain thresholds for multiple LLR regions; the target codeword is LLR quantized according to the thresholds of the multiple LLR regions to obtain the LLR information of the target codeword; the LLR information of the target codeword is input into LDPC for decoding to obtain decoding information. The embodiments of this application make the decoding error correction performance obtained by LDPC simulation more reliable and practical and closer to the decoding error correction performance in NAND Flash module applications, and can be used to evaluate whether LDPC can meet the error correction performance requirements of different NAND Flash in various application scenarios.

[0041] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0042] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0043] Figure 1 This is a flowchart illustrating a method for decoding NAND Flash data according to an embodiment of this application;

[0044] Figure 2 This is a schematic diagram of the process for obtaining the target Gaussian distribution and the target codeword according to an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of the process for obtaining the target region provided in one embodiment of this application;

[0046] Figure 4 This is a schematic diagram of the process for obtaining the target region provided in another embodiment of this application;

[0047] Figure 5 This is a schematic diagram of a process for obtaining thresholds for multiple LLR regions according to an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the process for obtaining LLR information of a target codeword according to an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of the process for obtaining decoded information provided in one embodiment of this application;

[0050] Figure 8 This is a schematic diagram of the overall process of a NAND Flash data decoding method provided in one embodiment of this application;

[0051] Figure 9 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. Detailed Implementation

[0052] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0053] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0054] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0055] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0056] First, let's analyze some of the terms used in this application:

[0057] LLR sign bit (Log-Likelihood Ratio Sign Bit): A binary flag used in communication systems to indicate whether the value of the log-likelihood ratio (LLR) is positive or negative.

[0058] NAND Flash (Non-Volatile Memory, NVM): Based on the floating-gate MOSFET structure, it achieves long-term data storage through charge storage, requiring no continuous power supply. Its name comes from its circuit structure, which is a NAND gate logic array, and it is widely used in solid-state drives (SSDs), USB flash drives, mobile phone storage, and other fields.

[0059] LDPC (Low-Density Parity-Check Code) is a high-performance linear block error-correcting code, named for the extremely low percentage of 1s in its parity-check matrix (low-density characteristic). Its core principle is to construct parity-check relationships for codewords using a sparse parity-check matrix, effectively correcting noise and interference introduced during transmission. LDPC codes have low decoding complexity and can be implemented in parallel, making them widely used in modern communication systems (such as 5G, Wi-Fi, and satellite communications) and storage systems (such as hard drives and flash memory). Its working principle involves using an iterative decoding algorithm (such as the belief propagation algorithm) to transmit reliability information (usually LLR, log-likelihood ratio) between variable nodes and check nodes, gradually correcting errors in the received data until the check condition is met or the maximum number of iterations is reached.

[0060] BPSK (Binary Phase Shift Keying) is a fundamental digital modulation technique, belonging to the phase shift keying (PSK) modulation method. Its principle is to represent binary digital information (0 and 1) by changing the phase of the carrier wave. Typically, two phase states differing by 180° are used to correspond to "0" and "1" in binary, respectively. In BPSK modulation, when transmitting "0", the carrier phase may be 0°; when transmitting "1", the carrier phase may be 180° (or vice versa). The receiver recovers the original binary information by detecting changes in the carrier phase.

[0061] The NAND Flash data decoding method provided in this application is specifically illustrated through the following embodiments.

[0062] This application's embodiments can acquire and process relevant data based on artificial intelligence (AI) technology. AI is the theory, methods, technology, and application system that uses digital computers or computers-controlled machines to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results. Basic AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing technology, operating / interactive systems, and mechatronics. AI software technologies mainly include computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0063] The NAND Flash data decoding method provided in this application relates to the field of NAND Flash data decoding technology. The NAND Flash data decoding method provided in this application can be applied to a terminal, a server, or software running on either the terminal or the server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can implement the NAND Flash data decoding method, but is not limited to the above forms.

[0064] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0065] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent will be obtained first. Furthermore, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user will be obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent will the necessary user-related data for the normal operation of the embodiments of this application be obtained.

[0066] See Figure 1 , Figure 1 This is a flowchart illustrating a method for decoding NAND Flash data according to an embodiment of this application. The method for decoding NAND Flash data according to an embodiment of this application includes, but is not limited to, steps S110 to S160, which will be described in turn below.

[0067] Step S110: Receive the modulation request of the original codeword and perform BPSK modulation on the original codeword to obtain the first value and the second value.

[0068] It should be noted that BPSK (Binary Phase Shift Keying) is a modulation method that converts binary data into analog signals: the original codeword is a binary sequence, such as 0 and 1. The BPSK modulation rule is usually: 0 is mapped to the first value (such as +1), and 1 is mapped to the second value (such as -1).

[0069] Step S120: Add noise to the first and second values ​​according to the preset Gaussian distribution to obtain the target Gaussian distribution and the target codeword;

[0070] It should be noted that the preset Gaussian distribution has a mean of 0 and a variance of σ. 2 The normal distribution is obtained by adding Gaussian noise to the first value (+1) and the second value (-1) after modulation. The target codeword obtained after adding noise is the actual received signal. The target Gaussian distribution refers to the probability distribution of the two signals (original +1 and original -1) after adding noise.

[0071] Step S130: When there are overlapping regions in the target Gaussian distribution, calculate the boundary of the overlapping region to obtain the target boundary and thus the target region.

[0072] It should be noted that when two Gaussian distributions overlap, the overlapping region needs to be determined. The two Gaussian distributions (centered at +1 and -1 respectively) will have an intersection point, and the target boundary is the intersection point of these two distributions.

[0073] Step S140: Divide the target region into LLR regions to obtain the thresholds of multiple LLR regions;

[0074] It should be noted that LLR (log-likelihood ratio) represents the logarithm of the probability ratio of receiving a 0 instead of a 1. The formula for calculating LLR is: LLR = ln[P(0|r) / P(1|r)].

[0075] Step S150: Perform LLR quantization on the target codeword based on the thresholds of multiple LLR regions to obtain the LLR information of the target codeword;

[0076] Step S160: Input the LLR information of the target codeword into LDPC for decoding to obtain the decoded information.

[0077] It should be noted that the quantized LLR information is input into the LDPC decoder. The decoder uses a parity check matrix and an iterative algorithm to perform error correction. After multiple iterations, it outputs the final decoded information.

[0078] In one embodiment, a modulation request for the original codeword is received. The original codeword is a binary sequence, modulated using BPSK modulation, where binary "0" is mapped to a first value +1, and binary "1" is mapped to a second value -1. The modulation is based on a preset Gaussian distribution (mean 0, variance σ). 2A noise sequence is generated and superimposed onto the first and second values ​​respectively, resulting in a noisy target Gaussian distribution. This target Gaussian distribution is the convolution result of the original signal distribution and the Gaussian noise distribution. Analysis of the target Gaussian distribution reveals an overlap between the Gaussian distribution representing "0" (centered near +1) and the Gaussian distribution representing "1" (centered near -1). The target boundary of the overlapping region is calculated by finding the points where the probability density functions of the two Gaussian distributions are equal. The target region is then divided into LLR (log-likelihood ratio) regions. Based on a preset quantization precision, the target region is divided into multiple sub-regions, and a threshold for each region is determined. Based on the obtained multiple LLR region thresholds, the obtained target codewords are LLR quantized. The obtained LLR information is input into an LDPC decoder, and iterative decoding is performed using a belief propagation algorithm. The decoder processes the received LLR information according to the parity check matrix and outputs the decoded information after a preset number of iterations. This embodiment of the application realizes a complete communication process from signal modulation, noisy addition, quantization to decoding, and can accurately recover the original information even in the presence of noise interference.

[0079] It is worth noting that the scheme proposed in this application makes the decoding and error correction performance obtained by LDPC simulation more reliable and practical, and closer to the decoding and error correction performance when NAND Flash module is used. It can also be used to evaluate whether LDPC can meet the error correction performance requirements of different NAND Flash in various application scenarios.

[0080] In one embodiment, the target Gaussian distribution includes a first initial Gaussian distribution and a second initial Gaussian distribution, and the target codeword includes a first initial codeword and a second initial codeword.

[0081] It should be noted that the first initial Gaussian distribution (mean 0, standard deviation σ1) and the second initial Gaussian distribution (mean 0, standard deviation σ2) can have the same or different standard deviations.

[0082] See Figure 2 , Figure 2 This is a schematic diagram of the process for obtaining a target Gaussian distribution and a target codeword according to an embodiment of this application; regarding the above step S120, which adds noise to the first and second values ​​according to the preset Gaussian distribution to obtain the target Gaussian distribution and the target codeword, it includes, but is not limited to, steps S210 to S220, and each step will be described in turn below.

[0083] Step S210: Add noise to the first value according to the preset first Gaussian distribution to obtain the first initial Gaussian distribution and the first initial codeword;

[0084] Step S220: Add noise to the second value according to the preset second Gaussian distribution to obtain the second initial Gaussian distribution and the second initial codeword.

[0085] In one embodiment, the first value received after BPSK modulation (assumed to be +1, corresponding to the original codeword "0") has a first initial Gaussian distribution of N(μ1, ..., ...) ), where μ1=1, =0.5, generate a noise sequence matching the length of the first value based on N(1, 0.5), and superimpose the noise sequence onto the first value to obtain the first initial codeword:

[0086] In one embodiment, the second initial Gaussian distribution of the received BPSK modulated second value (assumed to be -1, corresponding to the original codeword "1") is N(μ2, ), where μ2=-1, =0.5, generate a noise sequence based on N(-1, 0.5), and superimpose the noise sequence onto the second value to obtain the second initial codeword.

[0087] It is worth noting that different symbols may be subject to noise interference with different characteristics during transmission (such as differences in noise intensity in different frequency bands). In this application embodiment, by setting independent Gaussian distribution models for the two values ​​after BPSK modulation, noise interference in the actual communication environment can be simulated more accurately.

[0088] See Figure 3 , Figure 3 This is a schematic diagram of the process for obtaining the target region provided in one embodiment of this application; regarding the above step S130, which calculates the boundary of the overlapping region to obtain the target region, including but not limited to steps S310 to S320, each step will be described in turn below.

[0089] Step S310: Obtain the preset value of the first initial Gaussian distribution coverage;

[0090] Step S320: Calculate the boundary of the overlapping region based on the preset value, the first value, the second value, the first initial Gaussian distribution, and the second initial Gaussian distribution to obtain the target boundary and thus the target region.

[0091] It should be noted that when the preset value is 99.7%, the boundary threshold is based on a Gaussian distribution covering 99.7% of the distribution; when the preset value is 99.9%, the boundary threshold is based on a Gaussian distribution covering 99.9% of the distribution. The preset value can be adjusted according to the actual situation.

[0092] In one embodiment, the boundary of the overlapping region is calculated using preset values, a first value, a second value, a first initial Gaussian distribution, and a second initial Gaussian distribution to obtain the left quantile and the right quantile. The upper boundary and the lower boundary of the overlapping region are obtained based on the left quantile and the right quantile. The target boundary is obtained based on the upper boundary and the lower boundary of the overlapping region to obtain the target region.

[0093] See Figure 4 , Figure 4 This is a schematic diagram of the process for obtaining the target region provided in another embodiment of this application; regarding the above step S320, the boundary of the overlapping region is calculated according to the preset value, the first value, the second value, the first initial Gaussian distribution and the second initial Gaussian distribution to obtain the target boundary and thus obtain the target region, including but not limited to steps S410 to S430, each step will be described in turn below.

[0094] Step S410: Obtain the first initial boundary of the overlapping region based on the preset value, the first value, and the first initial Gaussian distribution;

[0095] Step S420: Obtain the second initial boundary of the overlapping region based on the preset value, the second value, and the second initial Gaussian distribution;

[0096] Step S430: Calculate the boundary of the overlapping area based on the first initial boundary and the second initial boundary to obtain the target boundary and thus the target area.

[0097] In one embodiment, when the preset value is 99.7%, the first value is 1, the second value is -1, and the first initial Gaussian distribution is N(1, ..., ...) ),in =0.5, we obtain the left quantile: 1-3*σ1, which is the lower boundary of the overlapping region, i.e., the first initial boundary. The right quantile: -1+3*σ2, which is the upper boundary of the overlapping region, i.e., the second initial boundary, is covered by the second Gaussian distribution covering 99.7% of the distribution. Thus, the boundary of the overlapping region is [1-3*σ1, -1+3*σ2].

[0098] See Figure 5 , Figure 5 This is a flowchart illustrating the process of obtaining thresholds for multiple LLR regions according to an embodiment of this application. Regarding step S140, which involves dividing the target region into LLR regions to obtain thresholds for multiple LLR regions, steps S510 to S530 are included, and each step will be described in turn below.

[0099] Step S510: Divide the target region into LLR regions to obtain multiple LLR regions;

[0100] Step S520: Calculate the boundaries of multiple LLR regions based on the inverse cumulative distribution function or LDPC and the preset cumulative distribution;

[0101] Step S530: Obtain the midpoints of multiple LLR regions based on their boundaries to obtain the thresholds of multiple LLR regions.

[0102] In one embodiment, the quantization level of the LLR region is set: taking 10 levels of LLR region quantization as an example (corresponding to LDPC 5-bit soft decoding mode), the bit threshold can be divided into 10 LLR regions: [high confidence 1, medium-high confidence 1, medium confidence 1, medium-low confidence 1, low confidence 1, low confidence 0, medium-low confidence 0, medium confidence 0, medium-high confidence 0, high confidence 0]; the overlapping boundary obtained above is used as the boundary between high confidence and medium-high confidence, and the 8 LLR regions [medium-high confidence 1, medium confidence 1, medium-low confidence 1, low confidence 1, low confidence 0, medium-low confidence 0, medium confidence 0, medium-high confidence 0] are in the overlapping region. To divide overlapping regions into LLR regions: Each LLR region can be configured to have the same cumulative distribution size, and the boundary of each LLR region can be calculated using the inverse cumulative distribution function. Alternatively, based on the characteristics of the LDPC algorithm (e.g., low-confidence variable nodes have a greater impact on the propagation of information to check nodes), the cumulative distribution of low-confidence regions can be set to be smaller, followed by higher-confidence regions, and then the boundary of each LLR region can be calculated based on the cumulative distribution value set for each confidence region.

[0103] See Figure 6 , Figure 6 This is a schematic diagram of the process for obtaining LLR information of a target codeword according to an embodiment of this application; regarding the above step S150, LLR quantization is performed on the target codeword according to the threshold of multiple LLR regions to obtain the LLR information of the target codeword, including but not limited to steps S610 to S630, each step will be described in turn below.

[0104] Step S610: Obtain the LLR value of the target codeword;

[0105] Step S620: Compare the LLR value with the thresholds of multiple LLR regions to determine the LLR region to which the LLR value belongs;

[0106] Step S630: Quantize the LLR value according to the LLR region to which the LLR value belongs.

[0107] In one embodiment, obtaining the log-likelihood ratio (LLR) value of the target codeword, decoding the target codeword, and calculating its corresponding LLR value involves a detailed comparison of the LLR value obtained in the previous step with thresholds for multiple pre-defined LLR regions. This comparison determines which specific LLR region the LLR value belongs to, and region segmentation facilitates more precise subsequent processing of the LLR value. Finally, based on the LLR region to which the LLR value belongs, a quantization operation is performed on the LLR value. The quantization operation involves mapping the LLR value to the corresponding quantization level to facilitate further signal processing or data transmission. This quantization effectively reduces data complexity while maintaining necessary information integrity.

[0108] See Figure 7 , Figure 7 This is a schematic diagram of the process for obtaining decoding information provided in one embodiment of this application; regarding the above step S160, the LLR information of the target codeword is input into LDPC for decoding to obtain decoding information, including but not limited to steps S710 to S720, each step will be described in turn below.

[0109] Step S710: Perform iterative decoding operations based on LLR information according to the parity check matrix structure of the LDPC code;

[0110] Step S720: When the preset stopping condition is met, stop the iteration and output the decoding information. The preset stopping condition includes at least one of the following: the number of iterations of decoding operation reaches a preset number threshold, the decoding information satisfies the preset verification equation, and the difference between the decoding information of the two iterations is less than a preset difference threshold.

[0111] It should be noted that a maximum number of iterations is set to prevent excessive decoding time from affecting real-time performance. A counter is incremented by 1 after each iteration. When the maximum number of iterations is set to 50, the iteration stops and the decoded information is output regardless of whether the decoding is successful, provided the counter is at 50. The decoded information must satisfy all verification constraints (i.e., H×) after iterations. If the variable = 0, and c is the hard decision vector, then decoding is successful and the process can be stopped early. Calculate H× after each iteration. If the result is a vector of all zeros, the iteration stops. Assuming that the decoded information satisfies all check equations after a certain iteration, even if the current iteration count is only 20 (less than 50), it can still terminate early, saving the computational resources of 30 iterations. When the difference between the decoded information of two consecutive iterations is extremely small (e.g., the number of different bits is less than 2), it indicates that the decoding has converged, and continuing the iteration will not improve performance. The iteration can then be stopped, and the Hamming distance d between the k-th and (k-1)-th decoded information is calculated. If d ≤ 1 (a preset threshold), the iteration stops.

[0112] See Figure 8 , Figure 8 This is a schematic diagram of the overall process of a NAND Flash data decoding method provided in one embodiment of this application.

[0113] Step S8001: Perform BPSK modulation on the original codeword;

[0114] Step S8002: Generate Gaussian distributions A and B;

[0115] Step S8003: Add noise to Gaussian distribution A to obtain Gaussian distribution A_N, and add noise to Gaussian distribution B to obtain Gaussian distribution B_N;

[0116] Step S8004: Calculate the overlapping region of the two Gaussian distributions;

[0117] Step S8005: Design the quantization level of the LLR region;

[0118] Step S8006: Divide the overlapping regions into LLR regions;

[0119] Step S8007: Calculate the LLR value for each LLR region;

[0120] Step S8008: Perform LLR quantization on the noise codeword N based on the LLR value of each LLR region;

[0121] Step S8009: Input the LLR information of the noise codeword N into LDPC to complete the decoding.

[0122] In one embodiment, the original codeword is modulated by binary phase shift keying (BPSK) to convert the original codeword into a corresponding BPSK signal for subsequent processing and transmission. Next, two Gaussian distributions are generated, named Gaussian distribution A and Gaussian distribution B, respectively. These two Gaussian distributions will be used in the subsequent noise addition process. The distribution of the random variable has a specific mean and variance. After generating Gaussian distribution A and Gaussian distribution B, these two distributions will be used for noise addition. Gaussian distribution A is used to generate the noisy Gaussian distribution A_N, and similarly, Gaussian distribution B is used to generate the noisy Gaussian distribution B_N. The overlap region of the two Gaussian distributions A_N and B_N is calculated. The overlap region represents the part that may overlap between the two distributions under the influence of noise. After determining the overlap region, the quantization level of the LLR region is designed. The quantization level refers to discretizing the continuous LLR value into a finite number of levels to facilitate processing and storage in the digital system. According to the designed quantization level, the overlap region is divided into several sub-regions, each sub-region corresponding to a specific LLR value. The LLR value of each LLR region is calculated. The LLR value is an important indicator for measuring the similarity between the received signal and the original signal. It helps to determine the original information contained in the received signal. Based on the LLR value of each LLR region, the noise codeword N is LLR quantized, mapping each codeword in the noise codeword N to its corresponding LLR value, thus obtaining the quantized noise codeword. The LLR information of the noise codeword N is then input into the decoder of the low-density parity-check (LDPC) code to complete the decoding process.

[0123] In one embodiment, by fine-tuning the threshold of the boundary of the two Gaussian distribution overlapping regions and adjusting the threshold of the LLR region within the overlapping region, the performance of decoding and error correction obtained by LDPC simulation is made more reliable and practical, and can be used to evaluate whether LDPC can meet the error correction performance requirements of different NAND Flash in various application scenarios.

[0124] This application also provides a computer device comprising: at least one memory, at least one processor, and at least one computer program. The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement any of the NAND Flash data decoding methods described in the above embodiments. This computer device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0125] See Figure 9 , Figure 9 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application. The computer device includes:

[0126] The processor 910 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0127] The memory 920 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 920 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 920 and is called and executed by the processor 910 to execute the NAND Flash data decoding method of the embodiments of this application.

[0128] The input / output interface 930 is used to implement information input and output;

[0129] The communication interface 940 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0130] Bus 950 transmits information between various components of the device (e.g., processor 910, memory 920, input / output interface 930, and communication interface 940);

[0131] The processor 910, memory 920, input / output interface 930 and communication interface 940 are connected to each other within the device via bus 950.

[0132] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for decoding NAND Flash data.

[0133] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0134] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0135] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0136] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0137] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0138] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0139] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0141] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0143] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0144] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method of decoding NAND Flash data, the method comprising: The method comprises the following steps: receiving a modulation request of an original code word and performing BPSK modulation on the original code word to obtain a first value and a second value; adding noise to the first value and the second value according to a preset Gaussian distribution to obtain a target Gaussian distribution and a target code word, wherein the target Gaussian distribution comprises a first initial Gaussian distribution and a second initial Gaussian distribution, and the target code word comprises a first initial code word and a second initial code word; when the target Gaussian distribution has an overlapping area, obtaining a preset value covered by the first initial Gaussian distribution; calculating a boundary of the overlapping area according to the preset value, the first value, the second value, the first initial Gaussian distribution and the second initial Gaussian distribution to obtain a target boundary and a target area; performing LLR area division on the target area to obtain a plurality of LLR areas; calculating a boundary of each of the plurality of LLR areas according to an inverse cumulative distribution function; obtaining a midpoint of each of the plurality of LLR areas according to the boundary of each of the plurality of LLR areas to obtain a threshold value of each of the plurality of LLR areas; performing LLR quantization on the target code word according to the threshold value of each of the plurality of LLR areas to obtain LLR information of the target code word; inputting the LLR information of the target code word into an LDPC for decoding to obtain decoding information.

2. The method of claim 1, wherein, The method of adding noise to the first value and the second value according to a preset Gaussian distribution to obtain a target Gaussian distribution and a target code word comprises: adding noise to the first value according to a preset first Gaussian distribution to obtain a first initial Gaussian distribution and a first initial code word; adding noise to the second value according to a preset second Gaussian distribution to obtain a second initial Gaussian distribution and a second initial code word.

3. The method of claim 1, wherein, The method of calculating a boundary of the overlapping area according to the preset value, the first value, the second value, the first initial Gaussian distribution and the second initial Gaussian distribution to obtain a target boundary and a target area comprises: obtaining a first initial boundary of the overlapping area according to the preset value, the first value and the first initial Gaussian distribution; obtaining a second initial boundary of the overlapping area according to the preset value, the second value and the second initial Gaussian distribution; calculating a boundary of the overlapping area according to the first initial boundary and the second initial boundary to obtain a target boundary and a target area.

4. The method of claim 1, wherein, The method of performing LLR quantization on the target code word according to the threshold value of each of the plurality of LLR areas to obtain LLR information of the target code word comprises: obtaining an LLR value of the target code word; comparing the LLR value with the threshold value of each of the plurality of LLR areas to determine an LLR area to which the LLR value belongs; quantizing the LLR value according to the LLR area to which the LLR value belongs.

5. The method of claim 1, wherein, The method of inputting the LLR information of the target code word into an LDPC for decoding to obtain decoding information comprises: performing iterative decoding operation on the LLR information based on a check matrix structure of the LDPC code. When a preset stopping condition is met, the iteration is stopped and the decoding information is output, wherein the preset stopping condition comprises at least one of the following: the number of times of the iterative decoding operation reaches a preset number threshold, the decoding information satisfies a preset check equation, and the difference between the decoding information of the iteration before and after is less than a preset difference threshold.

6. A computer device, comprising: Comprising: at least one memory; at least one processor; at least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method of any one of claims 1 to 5.

7. A computer readable storage medium characterized by The computer readable storage medium stores a computer program, and the computer program is used to make a computer execute the method of any one of claims 1 to 5.

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