Hardware acceleration circuit, method, and integrated circuit

Abstract

The application discloses a hardware acceleration circuit, a method and an integrated circuit. The hardware acceleration circuit comprises: an interface circuit configured to read first data and first parameters, output second data and second parameters to the outside, and read third data, wherein the first parameters comprise a target precision constraint value, and the third data comprises coefficients of a polynomial expansion; a control circuit configured to instruct the interface circuit to read the first data and the third data according to the first parameters, enable an operation circuit to perform an operation, and instruct the interface circuit to output the second data and the second parameters; and the operation circuit is configured to perform a double-precision floating-point function operation on the first data based on the first parameters and the third data to obtain the second data and the second parameters; the double-precision floating-point function operation comprises one or all of a transcendental operation based on the polynomial expansion and a format processing operation, and an order of the polynomial expansion is determined based on the target precision constraint value. The application has the technical effect of improving the efficiency of the double-precision floating-point function operation.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a hardware acceleration circuit, method, and integrated circuit. Background Technology

[0002] In fields such as navigation algorithms, scientific simulations, and engineering analysis, numerous computational tasks involving double-precision floating-point functions need to be completed within a limited timeframe. While double-precision floating-point numbers offer high representation precision and computational accuracy, their complex operations often consume significant computational resources and time. Although general-purpose processors or graphics processing units (GPUs) can implement these operations through instruction sets, they may still suffer from high latency, high energy consumption, and insufficient parallelism when dealing with massive amounts of data and applications with high real-time requirements. Therefore, the efficiency of double-precision floating-point function operations warrants attention. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a hardware acceleration circuit, method, and integrated circuit to improve the efficiency of double-precision floating-point function operations. In a first aspect, a hardware acceleration circuit is provided, comprising: an interface circuit, a control circuit, and an arithmetic circuit; the interface circuit is configured to read first data and a first parameter, and to output second data and a second parameter to the outside, and is further configured to read third data, wherein the first data is double-precision floating-point input data, the second data is a double-precision floating-point calculation result, the first parameter includes a target precision constraint value, and the third data includes coefficients of a polynomial expansion in the double-precision floating-point function operation; the control circuit is configured to read the first parameter through the interface circuit, and, according to the first parameter, instruct the interface circuit to read the first data and the third data, enable the arithmetic circuit to perform operations, and instruct the interface circuit to output the second data and the second parameter; at least one arithmetic circuit is configured to perform a double-precision floating-point function operation on the first data based on the first parameter and the third data to obtain the second data and the second parameter; wherein the double-precision floating-point function operation includes one or all of the following: transcendental operations based on polynomial expansion and format processing operations, wherein the order of the polynomial expansion is determined based on the target precision constraint value.

[0004] The above hardware acceleration circuit, by co-designing the interface circuit, control circuit and arithmetic circuit, and combining it with a pre-stored set of polynomial expansion coefficients, reduces memory access times and computational latency. It can flexibly adjust the polynomial expansion order according to the target precision constraint value to balance computational speed and accuracy, supports multiple types of double-precision floating-point function operations, and can effectively improve the efficiency of double-precision floating-point function operations.

[0005] Optionally, the interface circuit includes: a main bus interface module for reading first data and / or third data, and transmitting second data to the outside; and a slave bus interface module for reading first parameters and transmitting second parameters to the outside.

[0006] Optionally, it also includes: a buffer configured to cache first data read by the interface circuit and second data generated by the arithmetic circuit; the buffer includes: a first storage unit and a second storage unit, used to cache a first part and a second part of the first data, and to cache a first part and a second part of the second data, respectively, the first part and the second part being divided based on a buffer segmentation method; the first storage unit and the second storage unit are configured to provide the first data to the arithmetic circuit and / or output the second data to the interface circuit when the arithmetic circuit performs double-precision floating-point function operations.

[0007] Optionally, it also includes: a register circuit for caching the first parameter received through the interface circuit and the second parameter written through the control circuit.

[0008] Optionally, the arithmetic circuit includes: a multiplication module configured to calculate the product of the powers of the polynomial expansion of the first data based on the first parameter and the third data; and an addition module configured to perform an accumulation operation based on the result of the product of the powers to determine the partial or final sum of the polynomial expansion.

[0009] Optionally, the arithmetic circuit may further include: a preprocessing module configured to determine the computational range of the first data before polynomial expansion; and a result postprocessing module configured to perform format processing operations on the partial sum or the final sum.

[0010] Optionally, the control circuit is also configured to determine the target operation flow of the operation circuit according to the first parameter, and control the multiplication operation module, the addition operation module, the preprocessing module and the result postprocessing module to execute at least one operation step of the double-precision floating-point function operation according to the preset operation order. The operation step includes: operation range determination, multiplication operation, addition operation and inversion operation.

[0011] Optionally, the first parameter may also include at least one of the following: operation type, number of operands, and number of input data; the second parameter may include at least one of the following: result overflow, result underflow, illegal operation, and inaccurate result. Transcendental operations may include at least one of the following: trigonometric function operations and power function operations; format processing operations may include at least one of the following: rounding operation, integer operation, and absolute value operation.

[0012] Secondly, a hardware acceleration method is provided for performing double-precision floating-point function operations using the hardware acceleration circuit provided in the first aspect above. The method includes: a control interface circuit reading first data, first parameters, and third data, wherein the first data is double-precision floating-point input data, the first parameters include a target precision constraint value, and the third data includes coefficients of the polynomial expansion in the double-precision floating-point function operation; an enable operation circuit performing a double-precision floating-point function operation on the first data based on the first parameters and the third data to determine second data and second parameters, wherein the double-precision floating-point function operation includes one or all of the following: transcendental operations or format processing operations based on polynomial expansion, wherein the order of the polynomial expansion is determined based on the target precision constraint value, and the second data is the double-precision floating-point calculation result; and outputting the second data and second parameters to the outside.

[0013] Thirdly, an integrated circuit is provided, comprising: a memory configured to pre-store third data, the third data including coefficients of a polynomial expansion in a double-precision floating-point function operation; and a hardware acceleration circuit provided in the first aspect, configured to read first data, first parameters, and third data, perform a double-precision floating-point function operation on the first data based on the first parameters and third data, and determine second data and second parameters, wherein the double-precision floating-point function operation includes one or all of a transcendental operation or a format processing operation based on a polynomial expansion, wherein the order of the polynomial expansion is determined based on a target precision constraint value. Attached Figure Description

[0014] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below:

[0015] Figure 1 The diagram shows a schematic of the structure of a hardware acceleration circuit provided in some embodiments of this application;

[0016] Figure 2 The diagram shows a schematic representation of a computational circuit provided in some embodiments of this application.

[0017] Figure 3 This paper illustrates a signal flow diagram of a hardware acceleration circuit provided in some embodiments of this application;

[0018] Figure 4 This illustration shows a schematic diagram of a state transition logic for an operational circuit provided in some embodiments of this application;

[0019] Figure 5 A flowchart illustrating a hardware acceleration method provided in some embodiments of this application is shown. Detailed Implementation

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0021] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0022] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first,” “second,” etc., are used only to distinguish and describe related objects and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone,” “b alone,” or “a and b.” “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone,” “a2 alone,” “a3 alone,” “a1 and a2,” “a1 and a3,” “a2 and a3,” or “a1, a2 and a3.”

[0023] Double-precision floating-point arithmetic is widely used in numerical computation and scientific engineering, mainly involving transcendental operations such as trigonometric functions, exponential functions, power functions, and logarithmic functions, as well as format processing operations such as rounding, integer division, and absolute value taking. In implementation, double-precision floating-point transcendental operations typically rely on polynomial expansion methods (such as Taylor expansion and Chebyshev expansion), obtaining approximate values ​​by calculating the exponents of each polynomial and performing addition. Higher polynomial order results in higher precision, but also increases the required computational resources and time. The precision requirements vary across different application scenarios. For example, navigation calculations may require higher orders to ensure minimal error, while some real-time control applications prioritize computational speed over extremely high precision. Existing hardware accelerator solutions often employ fixed polynomial orders or fixed computation paths when implementing double-precision floating-point arithmetic, resulting in an inability to flexibly adjust computational precision and resource allocation for different tasks. Furthermore, the data flow path within the accelerator, the scheduling order of computation modules, and the organization of data caches directly affect overall computational latency and energy efficiency. If configurable and parallel management of the computation process cannot be achieved at the hardware level, it will be difficult to flexibly switch between different precision requirements and different operation types, thus limiting the applicability and performance potential of the accelerator. In view of this, this application proposes a hardware acceleration circuit, method, and integrated circuit that flexibly configures the polynomial expansion order based on computational requirements, thereby achieving a balance between computational precision and computational efficiency. It also supports various double-precision floating-point function operation types, possesses efficient data reading, caching, and parallel processing capabilities, reduces memory access latency, and improves the computational efficiency of double-precision floating-point functions.

[0024] Figure 1A schematic diagram of a hardware acceleration circuit provided in some embodiments of this application is shown. The hardware acceleration circuit 100 is used for double-precision floating-point function operations and includes: an interface circuit 110, a control circuit 120, and an arithmetic circuit 130. The interface circuit 110 is configured to read first data and a first parameter, and to output second data and the second parameter to the outside. It is also configured to read third data, wherein the first data is double-precision floating-point input data, the second data is the double-precision floating-point calculation result, the first parameter includes a target precision constraint value, and the third data includes coefficients used for polynomial expansion in double-precision floating-point function operations. The control circuit 120 is configured to... 0 reads the first parameter, and instructs the interface circuit to read the first data and the third data according to the first parameter, enables the arithmetic circuit 130 to perform the operation, and instructs the interface circuit 110 to output the second data and the second parameter to the outside; at least one arithmetic circuit 130 is configured to perform a double-precision floating-point function operation on the first data based on the first parameter and the third data to obtain the second data and the second parameter, wherein the double-precision floating-point function operation includes one or all of the following: transcendental class operation based on polynomial expansion and format processing class operation, wherein the order of the polynomial expansion is determined based on the target precision constraint value.

[0025] The above-described hardware acceleration circuit implementation can be used for double-precision floating-point function operations. This hardware acceleration circuit includes at least an interface circuit 110, a control circuit 120, and at least one arithmetic circuit 130. The first data is the double-precision floating-point input data, and the second data is the calculation result of the first data after double-precision floating-point calculation. The first data and the first parameter can be stored in a memory external to the hardware acceleration circuit, such as memory 10 or other memory. Therefore, the first data, the first parameter, and the third data can be stored in the same or different memories, without limitation. Taking the third data stored in memory 10 as an example, after its deployment and power-on initialization, the third data can be pre-stored. The third data is the set of coefficients for polynomial expansion in double-precision floating-point function operations. For example, the third data can be the Taylor expansion coefficient set {1, -1 / 3!, 1 / 5!, -1 / 7!, ...} of the sine function sin(x), or an exponential function. The set of Taylor expansion coefficients is {1, 1 / 1!, 1 / 2!, 1 / 3!, ...}, or the polynomial expansion coefficients of the natural logarithm function ln(1+x) are {1, -1 / 2, 1 / 3, -1 / 4, ...}. These coefficients can be stored in double-precision floating-point format and can correspond to different expansion orders (such as 4th, 6th, 8th, etc.). The required order range can be indicated by the target precision constraint value in the first parameter. By pre-storing the third data in memory 10, dynamic calculation of factorials or coefficients during the operation can be avoided, thereby reducing latency and hardware overhead. Furthermore, based on the above set of coefficients, it can be determined that, according to the mathematical rules of Taylor expansion, although the functions of the expansion objects are different, there are many cases of repeated coefficients. For the same coefficients, they do not need to be stored repeatedly. Therefore, the third data will not occupy too much storage space in memory 10.

[0026] Interface circuit 110 is configured, under the instruction of control circuit 120, to first acquire a first parameter related to the calculation. This first parameter may include the address, bit width, and upcoming operational logic (e.g., trigonometric functions, exponential functions) of the first data to be read. Based on this, it can read the corresponding first and third data from memory 10. Simultaneously, after the calculation is completed, it outputs the calculated second data and the second parameter associated with the result to the outside. The second parameter can be used to indicate the state of the calculation result (i.e., the second data). For example, the second parameter may include status indicators describing the calculation state, such as result overflow, result underflow, illegal operation, or inaccurate result. Outputting the second data and second parameter to the outside not only outputs the calculation result but also determines the precision, accuracy, or other status of the second data based on the second parameter. The reading of the first and third data can be synchronous or asynchronous, without limitation. Control circuit 120 responds to the first parameter (e.g., the first parameter can at least characterize the operation type and target precision constraint value), issues reading and output control commands to interface circuit 110, and enables calculation circuit 130 to perform the calculation. When the first parameter indicates the execution of a transcendental operation, the control circuit 120 enables the arithmetic circuit 130 to process the first data according to the polynomial expansion process. The arithmetic circuit 130 performs polynomial expansion calculations on the first data with the support of polynomial coefficients provided by the third data. The order of the expansion is determined by the target precision constraint value in the first parameter (for example, selecting the appropriate order to complete the calculation while meeting the target precision). This target precision constraint value can be determined before the calculation. For example, when the hardware acceleration circuit is applied to the field of navigation and positioning technology, the positioning accuracy of the navigation system can be flexibly adjusted by setting the target precision constraint value. For scenarios with high precision requirements, the target precision constraint value can be increased, so that the double-precision floating-point function calculation has more expansion terms and obtains higher navigation accuracy. For scenarios with low precision requirements, the target precision constraint value can be decreased, and the amount of computation can be reduced accordingly.

[0027] Taking the sine function sinx, or written as "sin(x)", as an example, the hardware calculation of this function is approximated by a Taylor series expansion, as shown in Equation 1:

[0028]

[0029] The more terms expanded, the more accurate the result, but the greater the computational cost. The number of terms in the series expansion can be configured through a target precision constraint value, essentially telling the computation unit in the hardware which term to expand to. For example, a target precision constraint value indicates that when expanding to 7 terms, the expansion should proceed to x. 15 / 15!, at this point the error is approximately 7.65 × 10! -13 The target accuracy constraint value is expanded to 15 terms, and then expanded to x. 31 / 31!, at this point the error is approximately 1.22 × 10. -34This allows for dynamic control of calculation precision as needed. When the first parameter indicates the execution of a format processing operation, the control circuit 120 enables the arithmetic circuit 130 to directly perform the corresponding format processing on the first data according to the format processing flow to obtain the second data. This can be achieved without calling polynomial coefficients. For example, with the rounding function, it can be achieved by directly truncating or adjusting the decimal part of the floating-point number, or by correctly rounding positive and negative numbers. When processing absolute value functions, the sign bit of the floating-point number can be directly cleared (i.e., positive numbers remain unchanged, and negative numbers become positive), which is achieved through bitwise operations or offsetting. Both of these operation methods can coexist, and no specific restrictions are placed here. The output of the arithmetic circuit 130 is provided to the interface circuit 110 as the second data. The interface circuit 110 outputs this second data along with the second parameter derived from the result. The second parameter can at least reflect the status information related to the operation result. In one embodiment, the arithmetic circuit 130 can be implemented as a single arithmetic unit, with the control circuit 120 sequentially switching between different arithmetic types to complete different tasks. In another embodiment, the arithmetic circuit 130 can include multiple parallel arithmetic units, with the control circuit 120 selecting one or more arithmetic units to participate in the current task based on one or more first parameters to adapt to different throughput requirements. Additionally, in some embodiments, the memory 10 can also be configured as part of the hardware acceleration circuit 100, thus using the memory 10 as a dedicated memory for the set of coefficients in the polynomial expansion during double-precision floating-point function operations, and calling the coefficients as needed; no specific limitations are imposed here. Through the above structure and process, the pre-stored third data of coefficients reduces the burden of coefficient generation or loading during operation. The division of labor between the interface circuit 110 and the control circuit 120 clarifies the responsibilities for data handling and operation triggering. The target precision constraint value can be used to determine the order of the polynomial expansion, helping to make a controllable trade-off between precision and computational overhead. The unified output of results and parameters improves the adaptability of the device in different application scenarios and reduces unnecessary computation and transmission overhead. The hardware acceleration circuit in the above embodiments, by co-designing the interface circuit, control circuit and arithmetic circuit, and combining it with a pre-stored set of polynomial expansion coefficients, can reduce the number of memory accesses and operation latency, while flexibly adjusting the polynomial expansion order according to the target precision constraint value to balance operation speed and accuracy, and supports a variety of double-precision floating-point function operation types, thereby improving the overall operation efficiency and applicability.

[0030] Continue to refer to Figure 1 The interface circuit 110 includes: a main bus interface module 111 for reading first data and / or third data, and transmitting second data to the outside; and a slave bus interface module 112 for reading first parameters and transmitting second parameters to the outside.

[0031] Specifically, the main bus interface module 111 is used to read the first data or the third data from the memory 10 under the scheduling of the control circuit 120, and transmit the second data to the external device through the main bus after the double-precision floating-point function operation is completed, so as to realize high-speed transmission of large data volume; the slave bus interface module 112 is used to read the first parameter under the scheduling of the control circuit 120, and transmit the second parameter to the external device after the operation is completed, so as to realize fine transmission and control of different types of parameters.

[0032] In a specific example, the master bus interface module 111 can be implemented through the master interface of the Advanced High-performance Bus (AHB), and the slave bus interface module 112 can be implemented through the slave interface of AHB.

[0033] With this dual-bus interface design, the main bus interface module 111 focuses on high-throughput transmission of numerical data, while the slave bus interface module 112 focuses on fast access and update of computational parameters. This effectively separates data flow and control flow at the hardware level, avoiding delays caused by bus occupancy conflicts, thereby improving overall data interaction efficiency and system response speed.

[0034] Continue to refer to Figure 1 It also includes: a buffer 140, configured to cache first data read by the interface circuit 110, and a second data generated by the arithmetic circuit 130; the buffer 140 includes: a first storage unit and a second storage unit, used to cache a first part and a second part of the first data, and to cache a first part and a second part of the second data, respectively, wherein the first part and the second part are divided based on a buffer segmentation method; the first storage unit and the second storage unit are configured to provide the first data to the arithmetic circuit or output the second data to the interface circuit when the arithmetic circuit performs double-precision floating-point function operations.

[0035] In the above hardware acceleration circuit embodiments, the buffer 140 can be used as an intermediate cache and parallel data supply during data transmission and computation. On the one hand, it caches the first data read by the interface circuit 110 from the memory 10, and on the other hand, it caches the second data generated by the arithmetic circuit 130 after performing double-precision floating-point function operations. The first part and the second part are divided based on the segmentation method of the buffer. For example, the data can be segmented according to the width of the internal transmission path, so that the originally continuous data is physically divided into two storage units that can be accessed in parallel or serially, thereby supporting the reading or writing of two segments of data. Taking the specific working process of parallel access as an example, the first storage unit and the second storage unit are configured to provide the first data to the arithmetic circuit in parallel when the arithmetic circuit 130 performs double-precision floating-point function operations. That is, the two parts of the first data are transmitted to the arithmetic unit simultaneously within one clock cycle, so that the power operations of each order in the polynomial expansion calculation can quickly obtain the required complete input data. After the operation is completed, the first storage unit and the second storage unit can also output the second data to the interface circuit 110 in parallel. That is, the result data is transmitted in parallel in one bus access, thereby reducing the bus occupancy time and improving the data return efficiency.

[0036] In the first embodiment of the buffer 140, the buffer 140 can be implemented using a hardware architecture of two banks. Each bank can be set as a static random access memory (SRAM). The two banks correspond to the first storage unit and the second storage unit, respectively. The access width of each bank can be matched with the bus width of the interface circuit (e.g., the first part corresponds to the data width of one access on the bus, and the second part corresponds to the next continuous data segment). This approach allows the interface circuit to complete the serial or parallel scheduling of the two parts of data internally through the buffer even if the bus width of the interface circuit itself is limited (e.g., it can only access the data width corresponding to the first part once). This reduces the requirements for the bandwidth and access speed of the interface circuit.

[0037] In the second embodiment of buffer 140, buffer 140 adopts a hardware architecture with two banks (each bank being SRAM). When the interface circuit 110 is a 32-bit bus interface, buffer 140 can utilize each SRAM to achieve complete access to 64-bit data, thereby sequentially transmitting the lower 32 bits and the higher 32 bits of data while maintaining a constant 32-bit bus bandwidth. This achieves the equivalent of 64-bit data processing, reducing the area overhead of the interface circuit 110 without expanding the bus width. Furthermore, the dual-bank structure reduces dependence on the capacity of a single bank, thereby reducing storage redundancy and improving area efficiency, while ensuring efficient reading and writing of double-precision floating-point data. The above embodiments can still meet the supply requirements of double-precision floating-point data without increasing the bus bandwidth of the interface circuit. This not only improves the data throughput of the computation and result output stages but also alleviates the performance pressure on the interface circuit in terms of bus width and access frequency through segmented caching and parallel access. The overall architecture achieves efficient data flow processing without increasing the complexity of the interface hardware.

[0038] Continue to refer to Figure 1 It also includes: a register circuit 150 for caching the first parameter received through the interface circuit 110, and a second parameter written through the control circuit 120.

[0039] The register circuit 150 in the above embodiments can be used to cache the first parameter and the second parameter. The first parameter may include information such as the operation type, the number of operands, the number of input data, and the target precision constraint value. The second parameter may include status indicators such as result overflow, result underflow, illegal operation, or inaccurate result. The register circuit 150 can be implemented using a multi-register array structure, with each register allocated to store parameters of a specific category. For example, operation control parameters, precision parameters, and status indicator parameters can be stored in different register groups, thereby enabling fast parameter location and retrieval. For instance, when the control circuit 120 receives the first parameter from the system through the interface circuit 110, such as when the first parameter is issued by the central processing unit, the first parameter can be cached by the register circuit 150 in the configuration register. Alternatively, when the control circuit 120 outputs the second parameter through the interface circuit 110, the second parameter can be cached in the register circuit 150, for example, in the status register. In this case, the register circuit 150 can support the control circuit 120 to update the operation status of the operation circuit 130 in the status register. For example, if an operation determines that the current first data has an overflow result, the corresponding status register of the register circuit 150 is set to "01". If the result is inaccurate, the status register is updated to "00".

[0040] In another optional implementation, register circuit 150 can also support batch writing and batch reading of parameters to reduce the number of bus interactions and improve data transmission efficiency. By setting register circuit 150, a stable parameter cache layer can be formed between interface circuit 110 and control circuit 120. This not only avoids parameter loss or invalidation due to bus occupation or delay during operation, but also allows for the reuse of unchanged parameter information in multiple operations, reducing the number of accesses to external memory, thereby reducing overall system latency and improving the processing efficiency of hardware acceleration circuits.

[0041] Figure 2 The diagram shows a schematic of an arithmetic circuit provided in some embodiments of this application. The arithmetic circuit 200 includes: a multiplication module 210 configured to calculate the product of the powers of the polynomial expansion of the first data based on a first parameter and third data; and an addition module 220 configured to perform an accumulation operation based on the result of the product of the powers to determine the partial or final sum of the polynomial expansion.

[0042] In the above application, assuming the first data is sinx and the operation type is a sine function, and the third data is a pre-stored set of polynomial expansion coefficients, for example... The first parameter, indicating the target precision constraint value, determines the number of terms in the polynomial expansion (e.g., 7 terms). The arithmetic circuit 130 first generates the power terms required for the polynomial expansion using the multiplication module 210: obtaining x in the initial period and simultaneously calculating x... 2 Subsequent exponentiation terms are obtained recursively, for example, x 3 =x×x 2 x 5 =x 3 ×x 2 x 7 =x 5 ×x 2 And so on, thus avoiding repeated multiplication, or multiplying in turn, for example, x 2 =x×x,x 3 =x×x×x, temporarily storing x and then multiplying it cyclically, without specific restrictions. Subsequently, the multiplication module 210 sequentially multiplies each power term with its corresponding coefficient to obtain the product value of that term. For example, the first term T1 = 1×x, the second term T2 = (1 / 3!)×x 3 The third term T3 = (1 / 5!) × x 5 The fourth term, T4, is equal to (1 / 7!) × x. 7This process continues until the last term is constrained by the target precision value. The product value of each term is immediately fed into the addition module 220 and added to the partial sum from the previous round, continuously updating the partial sum. For example, when x = 1.0 and the target precision is 7 terms, the result calculated by the multiplication module 210 and the addition module 220 is approximately 0.8414709848. This final result differs from the mathematical library's sin1≈0.841470984807 by approximately 10... -13 Within the order of magnitude. The multiplication module 210 of the above hardware acceleration circuit is responsible for generating the value of each term by "power term × coefficient", and the addition module 220 is responsible for the division of labor of term-by-term accumulation to form the result. By recursively generating power terms, the number of multiplications can be reduced, improving the hardware computing efficiency. Furthermore, the balance between computing accuracy and computing latency can be flexibly controlled according to the target accuracy constraint value given in the first parameter.

[0043] Continue to refer to Figure 2 The arithmetic circuit 130 further includes: a preprocessing module 230 configured to determine the calculation range of the first data before polynomial expansion; and a result postprocessing module 240 configured to perform format processing operations on the partial sum or the final sum.

[0044] In the above embodiments, the preprocessing module 230 is used to determine the calculation range of the first data before polynomial expansion. For example, when performing trigonometric function operations, since trigonometric function operations have a certain periodicity and symmetry, such as in the calculation of the function sinx, only the function value in the interval [0, π] can be calculated, while in the interval [π, 2π], the function value in the interval [0, π] can be directly used, and the result postprocessing module 240 can invert the value of sinx, so that the function value can be obtained without performing specific calculations. Polynomial expansion operations are not repeated in the interval outside [0, π], thereby reducing the number of multiplication and addition calculations, reducing the overall operation latency and power consumption, while ensuring calculation accuracy. The result postprocessing module is used to perform format processing operations after the partial or final sum is obtained from the polynomial expansion, such as rounding operations (e.g., rounding to the nearest even number), floor operations (e.g., floor to zero, floor up, or floor down), or absolute value operations, to meet the requirements of different application scenarios for the result numerical format. For example, in some numerical computing environments, if the target output precision is IEEE 754 double-precision format, the result post-processing module can round the internal calculation results to conform to the representation range of 53 significant binary bits. When performing absolute value operations, the result post-processing module 240 can directly clear the sign bit without changing the mantissa, thus efficiently obtaining the absolute value result. The preprocessing module 230 can also perform exponent alignment, for example, when calculating 1 × 10⁻⁶. -5 +1×10 -4 At that time, the preprocessing module 230 can be used to process 1×10 -4Transformed to 10×10 -5 This facilitates computation. In the above embodiments of the hardware acceleration circuit, the preprocessing module 230 helps determine the computation interval and improves computational efficiency, while the result postprocessing module 240 ensures that the output results meet specific numerical formats or data processing requirements, thereby improving the adaptability and output consistency of the hardware acceleration circuit in different computational tasks.

[0045] In some embodiments of this application, the control circuit 120 is further configured to determine the target operation flow of the operation circuit 130 according to the first parameter, and control the multiplication operation module 210, the addition operation module 220, the preprocessing module 230 and the result postprocessing module 240 to perform at least one operation step of double-precision floating-point function operation according to a preset operation order. The operation step includes: operation range determination, multiplication operation, addition operation and inversion operation.

[0046] In some embodiments of this application, when the first parameter indicates that the operation type is a trigonometric function operation, the control circuit 120 first starts the preprocessing module to map the input first data to a predetermined principal value interval, such as [0, π], to reduce the computational load by utilizing the periodicity and symmetry of the function. Then, the control multiplication module 210 calculates the product of each power term in the polynomial expansion based on the third data (the set of polynomial expansion coefficients). Next, the control addition module 220 accumulates the products of the aforementioned power terms term by term to obtain the partial or final sum of the polynomial expansion. During the Taylor expansion process, the control circuit 120 can coordinate the order of multiplication and addition calculations between the multiplication module 210 and the addition module 220, thereby ultimately determining the second data. After obtaining the calculation result, the control circuit 120 starts the result post-processing module to perform format processing operations based on the original interval position of the first data. For example, when the input value is in the interval [π, 2π], the calculation result of sinx is inverted, thereby directly obtaining the function value within the target interval. In some implementations, the control circuit 120 can also allocate different first data to different instances of the arithmetic circuit 130 for parallel execution to improve the overall computational throughput. In one arithmetic circuit 130, the control circuit 120 can sequentially put the multiplication module 210, addition module 220, preprocessing module 230, and result postprocessing module 240 into operation according to a preset operation order, forming a pipelined processing flow. This results in the distribution of the total workload among multiple arithmetic circuits 130 and the computation and execution of a single task within one arithmetic circuit 130, thereby coordinating the entire computation process and improving computational efficiency.

[0047] In some embodiments of this application, the first data is double-precision floating-point input data, and the first parameter further includes at least one of the following: operation type, number of operands, and number of input data; the second data is the double-precision floating-point calculation result, and the second parameter includes at least one of the following: result overflow, result underflow, illegal operation, and result inaccuracy. Transcendental operations include at least one of the following: trigonometric function operations and power function operations; format processing operations include at least one of the following: rounding operations, integer operations, and absolute value operations.

[0048] The operation type can be used to distinguish the specific type of double-precision floating-point function operation, such as trigonometric function operation or power function operation. The number of operands can be used to specify the polynomial order used when performing transcendental operations based on polynomial expansion. For example, when calculating functions like cosx and sinx, it determines to use the first few terms of the Taylor expansion. The input data quantity parameter indicates the number of double-precision floating-point data to be calculated in the current batch, assisting the control circuit 120 in scheduling the operation circuit 130 for parallel or pipelined operation. The target precision constraint parameter sets the desired calculation precision. The operation circuit can select an appropriate polynomial order or rounding strategy based on this precision constraint to reduce the computational load while ensuring precision. In the second parameter, result overflow indicates that the absolute value of the calculation result exceeds the maximum value range that a double-precision floating-point number can represent. For example, when the exponent part exceeds the maximum representable exponent, it typically returns positive infinity or negative infinity. Underflow occurs when the absolute value of a calculated result is less than the smallest non-zero value that a double-precision floating-point number can represent. For example, if the exponent is lower than the smallest representable exponent, the result approaches zero and may be represented as a denormalized number or zero. Illegal operations occur when the operation does not conform to mathematical definitions, such as performing a square root operation on a negative number, dividing by zero, or multiplying zero by infinity. Such operations result in an undefined value and may return a "Not a Number" (NaN) flag. Inaccurate results occur when the calculated result is within the range of double-precision floating-point representation, but rounding or truncation causes a deviation from the true mathematical result. For example, rounding to the nearest representable value, or an insufficient order in a polynomial expansion leading to approximation errors.

[0049] Figure 3 The diagram illustrates the signal flow of a hardware acceleration circuit provided in some embodiments of this application. Figure 3 The circuit structure is based on Figure 1Based on this, taking the interface circuit 110 as an example with a 32-bit width, the names of the various signals (data) in the figure include: m_rdata[31:0] is the data read by the main bus interface module 111 from external memory or peripherals, which is the first data. m_wdata[31:0] is the result data written by the main bus interface module 111 to the outside, which comes from the second data in the buffer 140. m_haddr[31:0] is the address signal for the main bus interface module 111 to access the memory 10, which is used to locate the storage location of the first data or the third data (polynomial coefficients). m_hwrite is the write enable signal of the main bus interface module 111, which can be a high level to indicate a write operation. m_hsize[2:0] is the bit width information of the data accessed by the main bus interface module 111, such as 32 bits or 64 bits, which can be used to determine the reading method of the first part and the second part of the first data. m_hready is the handshake signal to prepare for data transmission. wdata[31:0] is the control or parameter data written from the external host received by the bus interface module 112, which is the first parameter. haddr[31:0] is the address signal for accessing the register circuit or control circuit from the bus interface module 112. hwrite is the write enable signal from the bus interface module 112, for example, a high level can indicate writing to the register circuit 150. hsize[2:0] is the bit width information for accessing data from the bus interface module 112. rdata[31:0] is the read data returned from the bus interface module 112 to the external host, i.e., the second parameter. hready is the handshake signal from the bus interface module 112 indicating that it is ready to transmit data. src_data is the first data provided by the buffer 140 to the arithmetic circuit 130. result is the second data output by the arithmetic circuit to the buffer 140. bf_ctrl is the control signal of the buffer 140, used to manage the writing and output order of the second data. data_cnt_i is the number of input data received by the control circuit 120, which can correspond to the number of input data in the first parameter. ctrl is the control signal issued by the control circuit 120, which can enable the interface circuit 110 to receive or send data. `data_info` is the first parameter passed from the bus interface module 112 or register circuit 150, including the operation type, number of operands, target precision constraint value, etc. `sys_busy` is the system busy signal; a high level indicates that the operation circuit is currently performing an operation and cannot receive new tasks. `intr` is the interrupt signal, used to notify the external host when an operation is completed or an error occurs. `bf_data_info` is the data information signal of buffer 140, which can be used by control circuit 120 to instruct the main bus interface module 111 to store data in buffer 140, and to instruct the operation circuit 130 to read data from a specific location in buffer 140.`state` is a status signal output by the arithmetic circuit to the control circuit 120 to indicate the current arithmetic stage state, such as "data fetching stage," "calculation stage," or "result transmission stage." `enable` is an arithmetic enable signal used to control the circuit 120 to start the arithmetic circuit 130 to execute a specific operation. `cal_type` is an operation type signal, such as sin, cos, pow, etc., which corresponds to the "operation type" in the first parameter. See further details. Figure 2 The external input first data (double-precision floating-point input data) src_data and the constant data constant_data in the first parameter, such as the polynomial coefficients of 1 / 2!, 1 / 4!, 1 / 6!, etc., are sent to the arithmetic circuit 130. When the enable signal enabled provided by the control circuit is valid, the first part of the first data src_data, src_A, is range-controlled by the preprocessing module 230, and the value of A and its sign bit signA are output. The multiplication module 210 receives A and calculates A sequentially according to the constant data. 2 A 4 A 6 ...The terms of equal powers and their corresponding factorial reciprocals (-1)^(n-1)A^(2n-1) / (2n-1)! are added sequentially by the addition module 220, which performs cumulative addition or subtraction operations on each term to obtain the sum of the polynomial expansion. The result post-processing module 240 combines signA to generate the final sign bit sign_C and performs floating-point normalization on sum. frac_C represents the fractional part (i.e., mantissa) of the floating-point number, used to accurately describe the significant digits of the value. exp_C represents the exponent part of the floating-point number, which is the exponent field in the double-precision floating-point format, used to represent the magnitude of the value. The second data and second parameters in double-precision floating-point format are output (e.g., result overflow = 0, result underflow = 0, illegal operation = 0, inaccuracy = 0).

[0050] The signal flow process in the above embodiment takes the execution of cos x operation as an example. First parameters are written from the bus interface module 112 to the register circuit 150, including operation type = cos, number of input data = 1, number of operands = 5 (polynomial order), and target precision constraint value = 1e-15. The control circuit 120 receives the first parameters and instructs the main bus interface module 111 to read the first data (a double-precision floating-point value of x, e.g., x = 1.0471975512) and the third data (polynomial expansion coefficients of cos x, e.g., 1, -1 / 2!, 1 / 4!, -1 / 6!, 1 / 8!) from the memory 10. The first data is divided into a high 32 bits (first part) and a low 32 bits (second part) and stored in the buffer 140. The control circuit 120 sends the cal_type=cos signal, the enable signal, and the bf_data_info signal to the arithmetic circuit 130 to read data at the specific location in the buffer. The preprocessing module determines the calculation range of x in the interval [0,π]. Then, the multiplication module 210 calculates x sequentially. 2 x 4 ...Then, the addition module 220 performs polynomial accumulation based on the coefficients to obtain an approximate value of cosx. If x exceeds a certain range of π, the preprocessing module will reduce the actual amount of computation by inverting or changing the sign, for example, cos(π+θ)=-cosθ. The result of the operation (double-precision floating-point format) is stored in the buffer 140, with the high 32 bits (first part) and the low 32 bits (second part) stored separately. The main bus interface module 111 writes the second data back to the outside and outputs the second parameters (including whether there is overflow, whether it is inaccurate, etc.) from the bus interface module 112.

[0051] The arithmetic circuit 130 in the above embodiments can form four state transition logics during operation. Figure 4 This illustration shows a schematic diagram of a computational circuit state transition logic provided in some embodiments of this application. When transitioning between different operating states, the idle state indicates that the system has no task and is waiting for an external start command (e.g., ...). Figure 3The enable signal is used to enter the data fetch state (get_data). The entry condition is that the transfer state indicator signal transfer_done=0 and the system busy signal sys_busy=0. The trigger condition is when enable=1 (start operation instruction) is received, and the system enters the data fetch state get_data. At this time, the first data is read from the interface circuit 110. The system busy signal sys_busy=1 is executed, and the interrupt intr_clr=0 is cleared at the same time. The bus request signal hbus_req=1 is set to prepare to write to the buffer 140. The address signal of the buffer 140 is haddr=start_addr+cnt_in*4 (addressing by word offset), the data width is hsize=3'b010 (word), and the data ready condition data_ready is indicated. The system enters the calculation state calculates, calls the operation circuit 130, and executes the multiplication operation module 210, the addition operation module 220, the preprocessing module 230, etc. During the calculation, overflow, underflow, invalid NaN result or invalid operation are continuously monitored. After the calculation is completed, cal_done=1, enter the transfer state, write the second data of the calculation result to the buffer 140, and output it to the outside through the interface circuit 110. At this time, the transfer state indicator signal transfer_done=1, the calculation enable signal cal_en=0, and initiate a bus write request hbus_req=1, the write direction hwrite=1, and indicate the result storage address haddr=result_addr and hsize=3'b010(word). After the data transmission is completed, return to the idle state.

[0052] Figure 5 A flowchart illustrating a hardware acceleration method provided in some embodiments of this application is shown. This hardware acceleration method is used to perform double-precision floating-point function operations using the hardware acceleration circuit provided in the above embodiments, including:

[0053] S510: The control interface circuit reads the first data, the first parameter, and the third data. The first data is double-precision floating-point input data, the first parameter includes the target precision constraint value, and the third data includes the coefficients of the polynomial expansion in the double-precision floating-point function operation.

[0054] S520: The enable operation circuit performs a double-precision floating-point function operation on the first data based on the first parameter and the third data to determine the second data and the second parameter. The double-precision floating-point function operation includes one or all of the following: a transcendental operation based on polynomial expansion or a format processing operation, wherein the order of the polynomial expansion is determined based on the target precision constraint value, and the second data is the result of the double-precision floating-point calculation.

[0055] S530: Outputs second data and second parameters to the outside.

[0056] For details of the above embodiments, please refer to the solutions and beneficial effects involved in the above hardware acceleration circuit, which will not be repeated here.

[0057] Based on the same technical concept, this application also provides an integrated circuit, including: a memory configured to pre-store third data, the third data being used for coefficients of polynomial expansion in double-precision floating-point function operations; and a hardware acceleration circuit provided in the above embodiments, configured to read first data, first parameters, and third data, perform double-precision floating-point function operations on the first data based on the first parameters and third data, and determine second data and second parameters. The double-precision floating-point function operations include one or all of the following: transcendental operations or format processing operations based on polynomial expansion, wherein the order of the polynomial expansion is determined based on a target precision constraint value. This hardware acceleration circuit can act as the bearer of double-precision floating-point function calculations for a central processing unit (or other processing unit), allowing the central processing unit to offload such calculations to the hardware acceleration circuit for computation, thereby reducing the processing pressure on the central processing unit. Furthermore, due to the structural design of the hardware acceleration circuit in this application, such as directly reading the third data through an interface circuit, the hardware acceleration circuit avoids frequent access to memory via the system bus, thus reducing bus usage and further reducing the system's processing pressure, freeing up more resources for the central processing unit, and improving the overall processing efficiency of the processing system.

[0058] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A hardware acceleration circuit, comprising: Comprise: Interface circuit, control circuit and operation circuit; The interface circuit is configured to read first data and first parameters, and output second data and second parameters to the outside, and is also configured to read third data, wherein the first data is double-precision floating-point input data, the second data is double-precision floating-point calculation result, the first parameter includes target precision constraint value, and the third data includes coefficient of polynomial expansion in double-precision floating-point function operation, and the second parameter at least includes one of result overflow, result underflow, illegal operation and result inaccuracy; The interface circuit includes: a main bus interface module for reading the first data and / or the third data, and transmitting the second data to the outside; and a slave bus interface module for reading the first parameter and transmitting the second parameter to the outside; The control circuit is configured to read the first parameter through the interface circuit, instruct the interface circuit to read the first data and the third data according to the first parameter, enable the operation circuit to operate, and instruct the interface circuit to output the second data and the second parameter; At least one operation circuit is configured to perform double-precision floating-point function operation on the first data based on the first parameter and the third data, to obtain the second data and the second parameter; Wherein, the double-precision floating-point function operation includes one or all of transcendental operation and format processing operation based on polynomial expansion, wherein the order of polynomial expansion is determined based on the target precision constraint value.

2. The hardware acceleration circuit of claim 1, wherein, Further comprise: Buffer area configured to cache the first data read by the interface circuit, and configured to cache the second data generated by the operation circuit; The buffer area includes: a first storage unit and a second storage unit for respectively caching a first part and a second part of the first data, and respectively caching a first part and a second part of the second data, the first part and the second part being divided based on the buffer area segmentation mode; The first storage unit and the second storage unit are configured to provide the first data to the operation circuit and / or output the second data to the interface circuit when the operation circuit performs the double-precision floating-point function operation.

3. The hardware acceleration circuit of claim 1, wherein, Further comprise: Register circuit for caching the first parameter received through the interface circuit and caching the second parameter written through the control circuit.

4. The hardware acceleration circuit of any of claims 1 to 3, wherein, The operation circuit includes: Multiplication operation module configured to calculate the product of each order power term of polynomial expansion of the first data based on the first parameter and the third data; Addition operation module configured to perform accumulation operation based on the result of the product of each order power term to determine the partial sum or final sum of the polynomial expansion.

5. The hardware acceleration circuit of claim 4, wherein, The operation circuit further includes: Preprocessing module configured to determine the calculation range of the first data before the polynomial expansion; Result post-processing module configured to perform the format processing operation on the partial sum or the final sum.

6. The hardware acceleration circuit of claim 5, wherein, The control circuit is further configured to determine a target operation flow of the operation circuit according to the first parameter, and control the multiplication operation module, the addition operation module, the preprocessing module and the result post-processing module to perform at least one operation link of the double-precision floating-point function operation in a preset operation sequence, the operation link including operation interval determination, multiplication operation, addition operation and negation operation.

7. The hardware acceleration circuit of any of claims 1 to 3, wherein, The first parameter further includes at least one of operation type, operation item number and input data number. The transcendental operation includes at least one of trigonometric function operation and power function operation. The format processing operation includes at least one of rounding operation, integer operation and absolute value operation.

8. A hardware acceleration method, characterized by, A method for performing double-precision floating-point function operation by the hardware acceleration circuit of any one of claims 1 to 7, comprising: controlling the interface circuit to read first data, first parameter and third data, wherein the first data is double-precision floating-point input data, the first parameter includes a target precision constraint value, and the third data includes coefficients of polynomial expansion in the double-precision floating-point function operation, and the second parameter includes at least one of result overflow, result underflow, illegal operation and result inaccuracy; wherein the master bus interface module is controlled to read the first data and / or the third data and transmit the second data to the outside, and the slave bus interface module is controlled to read the first parameter and transmit the second parameter to the outside; enabling the operation circuit to perform the double-precision floating-point function operation on the first data based on the first parameter and the third data to determine second data and a second parameter, the double-precision floating-point function operation including one or all of a transcendental operation or a format processing operation based on polynomial expansion, wherein the order of the polynomial expansion is determined based on the target precision constraint value, and the second data is a double-precision floating-point calculation result; outputting the second data and the second parameter to the outside.

9. An integrated circuit, characterized by comprising: a memory configured to pre-store third data including coefficients of polynomial expansion in the double-precision floating-point function operation; the hardware acceleration circuit of any one of claims 1 to 7 is configured to read first data, first parameter and the third data, perform the double-precision floating-point function operation on the first data based on the first parameter and the third data, and determine second data and a second parameter, the double-precision floating-point function operation including one or all of a transcendental operation or a format processing operation based on polynomial expansion, wherein the order of the polynomial expansion is determined based on the target precision constraint value.

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