Display device

Abstract

The invention provides a display device which is characterized in that two cascaded gate drive circuits are spaced by X gate drive circuits, and the phase difference of first clock signals corresponding to the two cascaded gate drive circuits is (X + 1) H, the effective level of a first gate control signal corresponding to the compensation transistor and the effective level of a second gate control signal corresponding to the data transistor are at least partially overlapped; the effective level of a second gate control signal corresponding to the data transistor is located between two first effective levels of a first clock signal applied by a gate drive circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is larger than 0 and smaller than (X + 1) H, therefore, in the same sub-pixel, the effective level of the second gate control signal corresponding to the data transistor does not coincide with the moment when the voltage drop of the first gate control signal corresponding to the compensation transistor occurs, and the problem of uneven display is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device. BACKGROUND

[0002] In order to realize the sub-region frequency division design of the display panel corresponding to different display regions with different display frequencies, the frequency of the gate control signal generated by each stage of the gate drive circuit in the display drive circuit can be controlled to control the frequency of the sub-pixel of the display panel corresponding to different display regions to refresh the display data. The multiple gate control signals output by the multiple-stage gate drive circuit are switched from the gate control signal with the effective pulse to the gate control signal without the effective pulse, or from the gate control signal without the effective pulse to the gate control signal with the effective pulse, that is, the frequency of the multiple gate control signals is switched.

[0003] The multiple-stage cascaded gate drive circuit generates the voltage corresponding to the effective level of the multiple gate control signals according to the voltage supplied by a constant power supply terminal. However, when the gate drive circuit needs to output the gate control signal with the effective pulse, the constant power supply terminal acts on the gate drive circuit, so that the load corresponding to the constant power supply terminal instantaneously increases by a first increment, resulting in a decrease in the voltage supplied by the constant power supply terminal (i.e. load drawing), a decrease in the effective level of the gate control signal generated by the gate drive circuit, and a voltage drop problem of the gate control signal output by the gate drive circuit. When the gate drive circuit needs to output the gate control signal without the effective pulse, the load corresponding to the constant power supply terminal increases by an increment smaller than the first increment. Therefore, the gate drive circuit that needs to output the gate control signal with the effective pulse is different from the gate drive circuit that needs to output the gate control signal without the effective pulse in the load formed on the constant power supply terminal. Therefore, when the display panel adopts frequency division display, due to the frequency switching of the multiple gate control signals, the load formed on the constant power supply terminal by the multiple-stage gate drive circuit is different before and after the frequency division, resulting in a difference in the voltage drop change of the gate control signal applied to the sub-pixel near the frequency division position. Moreover, the voltage drop change of the gate control signal is caused by the periodic change of the clock signal used by the gate drive circuit.

[0004] As shown in FIG. 1, the voltage drop problem of the multiple gate control signals is more serious (as shown in the change of the multiple gate control signal Nscan in the dashed box in FIG. 1) before the frequency division (i.e. when the frequency division control signal NLF has a low level). After the frequency division (i.e. when the frequency division control signal NLF has a high level), the voltage drop problem of part of the gate control signals is less serious. Therefore, near the frequency division position, part of the sub-pixels refresh the display data (as shown in FIG. 2). Figure 1 Figure 1 Figure 1 ​​The voltage variation of the gate control signal corresponding to the time (i.e., the tw stage in the figure) when the sub-pixels refresh display data is relatively large, and the voltage variation of the gate control signal corresponding to the time when part of the sub-pixels refresh display data is relatively small, so that the charging of the plurality of sub-pixels is different, resulting in display brightness difference, and causing display unevenness. SUMMARY

[0005] The display device provided by the embodiments of the present application can improve the display unevenness.

[0006] The display device provided by the embodiments of the present application can improve the display unevenness.

[0007] The application provides a display device, by spacing X gate driving circuits between two gate driving circuits in cascade in a display driving circuit, the phase difference of a first clock signal corresponding to the two gate driving circuits in cascade is (X+1)H, the period of the first gate control signal output by each gate driving circuit changes from XH to (X+1)H, and the interval of the first gate control signal is lengthened. By making the effective level of the first gate control signal corresponding to the compensation transistor and the effective level of the second gate control signal corresponding to the data transistor at least partially overlap in at least one sub-pixel, the data transistor and the compensation transistor of the at least one sub-pixel have a stage of simultaneous conduction, and the charging of the sub-pixel is realized. By making the effective level of the second gate control signal corresponding to the data transistor between the two first effective levels of the first clock signal applied by the gate driving circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H, the effective level of the second gate control signal corresponding to the data transistor does not coincide with the moment of voltage drop of the first gate control signal corresponding to the compensation transistor in the same sub-pixel, so that the effective level of the second gate control signal corresponding to the data transistor is in the interval of the voltage drop change of the first gate control signal corresponding to the compensation transistor in the same sub-pixel, and the data transistor is turned on in the interval of the first gate control signal applied by the compensation transistor with a smaller voltage drop change, so as to reduce the charging difference of the multiple sub-pixels at the corresponding frequency division position, and improve the display unevenness problem. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0009] Figure 1 is a timing diagram of the gate control signal corresponding to the part of the sub-pixels at the frequency division position of the display panel provided by the embodiment of the present application;

[0010] Figure 2 is a cascade structure schematic diagram of the multi-stage gate driving circuit in the related art;

[0011] Figure 3 is a timing diagram of the gate control signal corresponding to the part of the sub-pixels at the frequency division position of the display panel provided by the embodiment of the present application; Figure 2

[0012] Figure 4 is a structure schematic diagram of the display device provided by the embodiment of the present application; ​

[0013] Figures 5A-5B is a structural schematic diagram of a sub-pixel provided by an embodiment of the present application;

[0014] Figure 6 is a cascaded structural schematic diagram of a multi-stage gate drive circuit provided by an embodiment of the present application;

[0015] Figure 7 is a timing diagram of a plurality of first gate control signals and a plurality of second gate control signals provided by an embodiment of the present application;

[0016] Figure 8 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0017] Figures 9A-9B is a timing diagram corresponding to a gate drive circuit provided by an embodiment of the present application;

[0018] Figure 10 is a timing diagram corresponding to a sub-pixel provided by an embodiment of the present application;

[0019] Figure 11 is a schematic diagram of high-frequency and low-frequency picture display principles provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0021] Specifically, the purpose of the partitioned frequency display of the display panel is to apply different display modes corresponding to different frequencies to realize display for different display regions of the same display screen. For example, in the interface environment of playing a video, the video content is displayed in the middle region of the screen, and the top and bottom regions of the screen can be used to display static pictures. The partitioned frequency display technology is a UI picture processing mode of the above-mentioned type, in which the video region is displayed at a high refresh frequency of 120Hz, and the regions displaying static pictures at the top and bottom are displayed at a low refresh frequency of 1Hz, so as to achieve the purpose of power saving and power consumption saving.

[0022] By controlling the level state of the gate control signal received by the compensation transistor and the reset transistor in the sub-pixel, the sub-pixel frequency division display technology can be realized. Therefore, at the position corresponding to the frequency division (i.e. the junction of high and low frequencies), the level of the multiple gate control signals received by the compensation transistor and the reset transistor corresponding to the sub-pixel will change from having an effective level to not having an effective level. The effective level output of the gate control signal is supplied by a constant power supply, and in the output level stage, the constant power supply is in communication with the output end outputting the gate control signal, which is considered as an instantaneous increase in the load of the constant power supply from the perspective of the resistance-capacitance load, thereby causing a voltage drop in the level of the gate control signal output by the current stage gate drive circuit. When switching between high and low frequencies, the level of the multiple gate control signals changes from having an effective level to not having an effective level, which causes the voltage drop of the gate control signal to change inconsistently, and then when the sub-pixel at the corresponding frequency division position refreshes the display data in the corresponding data writing stage, a fixed-width display unevenness problem occurs.

[0023] The inventor finds that the voltage drop change of the gate control signal received by the compensation transistor and the reset transistor is also caused by the periodic transformation of the clock signal used by the gate drive circuit generating the gate signal, and the period of the clock signal used by the gate drive circuit will affect the period of the voltage drop change of the gate control signal generated by the gate drive circuit. For example, Figure 2 is a cascade structure schematic diagram of the multi-stage gate drive circuit in the related art, Figure 3 is a timing diagram of the gate control signal output by the cascade structure shown in Figure 2 . Among them, Nscana is the gate control signal generated by the gate drive circuit before frequency division, and Nscanb is the gate control signal generated by the gate drive circuit after frequency division. If the period of the clock signal used by the gate drive circuit is 4H, then the period of the voltage drop change of the gate control signal generated by the gate drive circuit is 1H, and therefore, there will be a charging difference for each row of sub-pixels near the corresponding frequency division position, thereby causing a display unevenness problem in multiple rows of sub-pixels.

[0024] Therefore, the present application provides a display device to improve the above-mentioned display unevenness problem.

[0025] Figure 4 is a structure schematic diagram of the display device provided by the embodiment of the present application, and the present application provides a display device, which comprises a display panel DP and a display drive circuit Dc.

[0026] The display panel DP includes a plurality of sub-pixels Spi, a plurality of scan lines, and a plurality of data lines DL. The plurality of scan lines are electrically connected between the display driving circuit Dc and the plurality of sub-pixels Spi. The plurality of data lines DL are configured to transmit a plurality of data signals. The plurality of data lines DL are electrically connected between the source driving circuit SDC and the plurality of sub-pixels Spi. The source driving circuit SDC is configured to generate the plurality of data signals.

[0027] Figures 5A-5B FIG. 1 is a structural diagram of a sub-pixel Spi according to an embodiment of the present application. Each sub-pixel Spi includes a light emitting device Di and a pixel driving circuit for driving the light emitting device Di to emit light.

[0028] Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, or the like.

[0029] The pixel driving circuit at least includes a driving transistor Tdr, a data transistor Tda, and a compensation transistor Tc.

[0030] The driving transistor Tdr is connected in series between the first voltage terminal Vdd and the second voltage terminal Vss with the light emitting device Di. The driving transistor Tdr is configured to generate a driving current to drive the light emitting device Di to emit light according to a data signal transmitted by a corresponding data line DL.

[0031] The data transistor Tda and the compensation transistor Tc are configured to transmit the data signal to a control terminal of the driving transistor Tdr.

[0032] Optionally, a control terminal of the compensation transistor Tc is configured to receive a corresponding first gate control signal Nscan1. An input terminal of the compensation transistor Tc is electrically connected with an output terminal of the driving transistor Tdr. An output terminal of the compensation transistor Tc is electrically connected with the control terminal of the driving transistor Tdr.

[0033] A control terminal of the data transistor Tda is configured to receive a corresponding second gate control signal Pscan1. An input terminal of the data transistor Tda is electrically connected with a corresponding data line DL. The input terminal of the data transistor Tda is configured to receive a corresponding data signal. An output terminal of the data transistor Tda is electrically connected with an input terminal of the driving transistor Tdr.

[0034] Optionally, the compensation transistor Tc includes an oxide transistor or a silicon transistor.

[0035] Optionally, the compensation transistor Tc is a P-type transistor or an N-type transistor. The data transistor Tda is a P-type transistor or an N-type transistor.

[0036] Please continue to refer to Figures 5A-5BThe pixel driving circuit of at least one sub-pixel Spi includes a reset transistor Tr, a control terminal of the reset transistor Tr is configured to receive a third gate control signal Nscan2, an input terminal of the reset transistor Tr is electrically connected with a reset line, the input terminal of the reset transistor Tr is configured to receive a reset signal Vr, and an output terminal of the reset transistor Tr is electrically connected with a control terminal of the driving transistor Tdr.

[0037] Optionally, the reset transistor Tr includes an oxide transistor or a silicon transistor. Optionally, the reset transistor Tr is a P-type transistor or an N-type transistor.

[0038] Optionally, in the same sub-pixel Spi, an effective level of the first gate control signal Nscan1 received by the control terminal of the compensation transistor Tc partially coincides with an effective level of the third gate control signal Nscan2 received by the control terminal of the reset transistor Tr, so as to reset the potentials of the output terminal and the control terminal of the driving transistor Tdr by using the reset signal Vr.

[0039] Please continue to refer to Figures 5A-5B The pixel driving circuit of each sub-pixel Spi further includes a first initial transistor Ti1, a control terminal of the first initial transistor Ti1 is configured to receive a first scanning signal Pscan2, an input terminal of the first initial transistor Ti1 is configured to receive a first reset signal Vi1, and an output terminal of the first initial transistor Ti1 is electrically connected with an anode of the light emitting device Di.

[0040] Optionally, the pixel driving circuit of each sub-pixel Spi further includes a light emitting control transistor, the light emitting control transistor is electrically connected between the input terminal of the driving transistor Tdr and the first voltage terminal Vdd, and / or is electrically connected between the output terminal of the driving transistor Tdr and the light emitting device Di.

[0041] Optionally, please continue to refer to Figures 5A-5B The light emitting control transistor includes a first light emitting control transistor Te1 and a second light emitting control transistor Te2, the input terminal and the output terminal of the first light emitting control transistor Te1 are electrically connected between the first voltage terminal Vdd and the input terminal of the driving transistor Tdr, the input terminal and the output terminal of the second light emitting control transistor Te2 are electrically connected between the light emitting device Di and the output terminal of the driving transistor Tdr, and the control terminals of the first light emitting control transistor Te1 and the second light emitting control transistor Te2 are configured to receive a light emitting control signal EM.

[0042] Please continue to refer to Figures 5A-5B The pixel driving circuit of each sub-pixel Spi further includes a first storage capacitor Cst1, the first storage capacitor Cst1 is connected in series between the first voltage terminal Vdd and the control terminal of the driving transistor Tdr.

[0043] Optionally, please continue to refer to Figure 5B The pixel driving circuit of each sub-pixel Spi further comprises a second storage capacitor Cst2, and the second capacitor Cst2 is connected in series between the control end of the driving transistor Tdr and the control end of the data transistor Tda.

[0044] Optionally, please continue to refer to Figure 5B The pixel driving circuit of each sub-pixel Spi further comprises a second initial transistor Ti2, the control end of the second initial transistor Ti2 is electrically connected with a corresponding fourth scan line SL4, the input end of the second initial transistor Ti2 is configured to receive a second reset signal Vi2, and the output end of the second initial transistor Ti2 is electrically connected with the input end of the driving transistor Tdr.

[0045] Optionally, the control end of the first initial transistor Ti1 and the control end of the second initial transistor Ti2 are electrically connected, so that the first initial transistor Ti1 and the second initial transistor Ti2 are controlled by the same first scan signal Pscan2, and the anode potential of the light emitting device Di and the input potential of the driving transistor Tdr are synchronously reset.

[0046] Please continue to refer to Figure 4 and Figures 5A-5B The display driving circuit Dc is configured to output a plurality of first gate control signals Nscan1 to the control end of the compensation transistor Tc of the plurality of sub-pixels Spi, and output a plurality of second gate control signals Pscan1 to the control end of the data transistor Tda of the plurality of sub-pixels Spi.

[0047] Optionally, please continue to refer to Figure 4 The plurality of scan lines comprises a plurality of first scan lines SL1 and a plurality of second scan lines SL2, the plurality of first gate control signals Nscan1 are output to the control end of the compensation transistor Tc of the plurality of sub-pixels Spi through the plurality of first scan lines SL1, and the plurality of second gate control signals Pscan1 are output to the control end of the data transistor Tda of the plurality of sub-pixels Spi through the plurality of second scan lines SL2.

[0048] Optionally, the plurality of scan lines comprises a plurality of third scan lines SL3 and a plurality of fourth scan lines SL4, and the display panel DP comprises a plurality of light emitting control lines EML. The plurality of third scan lines SL3 are configured to transmit a plurality of third gate control signals Nscan2, the plurality of fourth scan lines SL4 are configured to transmit a plurality of first scan signals Pscan2, and the plurality of light emitting control lines EML are configured to transmit a plurality of light emitting control signals EM. The control end of the reset transistor Tr is electrically connected with a corresponding third scan line SL3, the control end of the first initial transistor Ti1 is electrically connected with a corresponding fourth scan line SL4, and the control end of the light emitting control transistor is electrically connected with a corresponding light emitting control line EML.

[0049] Figure 6 is a cascaded structure schematic diagram of a multi-stage gate drive circuit provided by an embodiment of the present application. The display drive circuit Dc includes a first gate drive unit configured to generate a plurality of first gate control signals Nscan1, the first gate drive unit including a plurality of frequency division control lines FL and a plurality of gate drive circuits GA.

[0050] The plurality of frequency division control lines FL are electrically connected to the plurality of gate drive circuits GA, and the plurality of frequency division control lines FL are configured to transmit a frequency division control signal to the plurality of gate drive circuits GA to control the level of at least one of the plurality of first gate control signals Nscan1, so that the frequency division control signal applied by the plurality of gate drive circuits GA controls the conduction state of the compensation transistor Tc of the plurality of sub-pixels Spi, and in turn controls whether the content displayed by the corresponding sub-pixel Spi changes, so that the display panel DP realizes partitioned frequency division display.

[0051] Each gate drive circuit GA is configured to generate a plurality of first gate control signals Nscan1 according to a corresponding start signal STV and a first clock signal XCK.

[0052] Please continue to refer to Figure 6 , the two gate drive circuits GA in phase cascade are separated by X gate drive circuits GA, and the phase difference of the corresponding first clock signals XCK of the two gate drive circuits GA in phase cascade is (X+1)H, so that the period of the voltage drop change of the first gate control signal Nscan1 output by each gate drive circuit GA changes from XH in the related art to (X+1)H, and the interval length of the voltage drop change of the first gate control signal Nscan1 is increased.

[0053] It should be noted that Figure 6 only shows the cascaded relationship schematic diagram of the plurality of gate drive circuits GA when X=1, but does not limit X=1. That is, in some embodiments, X can be greater than 1.

[0054] At least one of the sub-pixels Spi, the effective level of the first gate control signal Nscan1 corresponding to the compensation transistor Tc at least partially overlaps with the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda is located between the two first effective levels of the first clock signal XCK applied by the gate drive circuit GA corresponding to the compensation transistor Tc, and the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than (X+1)H, so that the data transistor Tda and the compensation transistor Tc of at least one of the sub-pixels Spi have a stage of simultaneous conduction, realizing the charging of the sub-pixel Spi. Moreover, because the period of the voltage drop change of the first gate control signal Nscan1 is (X+1)H, and the first clock signal XCK applied by the gate drive circuit GA has an effective level, the first gate control signal Nscan1 generated by the gate drive circuit GA will also have a voltage drop problem. Thus, the time corresponding to the voltage drop problem of the first gate control signal Nscan1 is when the first clock signal XCK applied by the gate drive circuit GA generating the first gate control signal Nscan1 has an effective level, and the phase difference between the time when the first clock signal XCK starts to have an effective level and the time when the first gate control signal Nscan1 starts to have an effective level is (X+1)H. Therefore, by controlling the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels to be greater than 0 and less than (X+1)H, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda in the same sub-pixel Spi is located within the interval period of the voltage drop change of the first gate control signal Nscan1 corresponding to the compensation transistor Tc, so that the data transistor Tda is turned on within the interval of the smaller voltage drop change of the first gate control signal Nscan1 applied by the compensation transistor Tc, to reduce the charging difference of the plurality of sub-pixels Spi at the corresponding frequency division position, and then improve the display unevenness problem. X≥1, and H represents a unit time length. Optionally, H can correspond to a row period.

[0055] Optionally, the gate drive circuit GA of the (X+1)th stage is cascaded, the gate drive circuit GA of the (X+1)th+1 stage is cascaded, and the gate drive circuit GA of the (X+1)th+X+1 stage is cascaded. Wherein, r≥0.

[0056] As Figure 7 is a timing diagram of a plurality of first gate control signals and a plurality of second gate control signals provided by the embodiment of the present application. Please continue to refer to Figures 6-7For example, when X = 1, the two gate drive circuits GA in phase cascade are spaced by one gate drive circuit GA, and the phase difference of the first clock signal XCK corresponding to the two gate drive circuits GA in phase cascade is 2H. That is, the gate drive circuits GA in odd-numbered stages are cascaded, and the gate drive circuits GA in even-numbered stages are cascaded. The interval time difference of the first gate control signal Nscan1 output by each gate drive circuit GA, in which the voltage drop changes, is 2H. The effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda is greater than 0 and less than 2H from the phase of one of the two first effective levels.

[0057] For example, when X = 1, the two gate drive circuits GA in phase cascade are spaced by one gate drive circuit GA, and the phase difference of the first clock signal XCK corresponding to the two gate drive circuits GA in phase cascade is 2H. That is, the gate drive circuits GA in odd-numbered stages are cascaded, and the gate drive circuits GA in even-numbered stages are cascaded. The interval time difference of the first gate control signal Nscan1 output by each gate drive circuit GA, in which the voltage drop changes, is 2H. The effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda is greater than 0 and less than 2H from the phase of one of the two first effective levels. Figure 7 For example, when X = 1, the two gate drive circuits GA in phase cascade are spaced by one gate drive circuit GA, and the phase difference of the first clock signal XCK corresponding to the two gate drive circuits GA in phase cascade is 2H. That is, the gate drive circuits GA in odd-numbered stages are cascaded, and the gate drive circuits GA in even-numbered stages are cascaded. The interval time difference of the first gate control signal Nscan1 output by each gate drive circuit GA, in which the voltage drop changes, is 2H. The effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda is greater than 0 and less than 2H from the phase of one of the two first effective levels.

[0058] Optionally, the phase difference between the start signal STV corresponding to the nth gate drive circuit GA and the start signal STV corresponding to the (n+1)th gate drive circuit GA is 1H, so that the gate drive circuits GA in odd-numbered stages and the gate drive circuits GA in even-numbered stages output the first gate control signal Nscan1 to the plurality of sub-pixels Spi in turn. Wherein, n is an odd number.

[0059] Optionally, please continue to refer to Figure 6, the starting signal STV corresponding to the first-stage gate driving circuit GA is the first starting signal stv1, the starting signal STV corresponding to the second-stage gate driving circuit GA is the second starting signal stv2, and the starting signal STV corresponding to the u-stage gate driving circuit GA is the first gate control signal Nscan1 output by the u-v-stage gate driving circuit GA or the signal at the second node Q2 of the u-v-stage gate driving circuit GA. Here, u≥2 and v≥1, and the u-v-stage gate driving circuit GA represents a gate driving circuit GA which is cascaded before the u-stage gate driving circuit GA and has a difference of v in the stage number from the u-stage gate driving circuit GA.

[0060] Optionally, the starting signal STV corresponding to the third-stage gate driving circuit GA is the first gate control signal Nscan1 output by the first-stage gate driving circuit GA or the signal at the second node Q2 of the first-stage gate driving circuit GA, and the starting signal STV corresponding to the fourth-stage gate driving circuit GA is the first gate control signal Nscan1 output by the second-stage gate driving circuit GA or the signal at the second node Q2 of the second-stage gate driving circuit GA.

[0061] Optionally, the starting signal STV corresponding to the u-stage gate driving circuit GA is the signal at the second node Q2 of the u-v-stage gate driving circuit GA, so that the first gate control signal Nscan1 output by the multi-stage gate driving circuit GA can be switched from no valid level output to valid level output, and the refresh frequency corresponding to the plurality of display areas of the display panel DP can be switched between high refresh frequency and low refresh frequency.

[0062] Optionally, the phase difference between the first starting signal stv1 and the second starting signal stv2 is 1H, so that the phase difference between the starting signal STV corresponding to the n-stage gate driving circuit GA and the starting signal STV corresponding to the n+1-stage gate driving circuit GA is 1H.

[0063] Optionally, X can also be greater than 1. For example, when X=2, the first-stage gate driving circuit GA(1), the fourth-stage gate driving circuit GA(4), the seventh-stage gate driving circuit GA(7), etc. are cascaded, the second-stage gate driving circuit GA(2), the fifth-stage gate driving circuit GA(5), the eighth-stage gate driving circuit GA(8), etc. are cascaded, and the third-stage gate driving circuit GA(3), the sixth-stage gate driving circuit GA(6), the ninth-stage gate driving circuit GA(9), etc. are cascaded.

[0064] Correspondingly, the starting signal STV corresponding to the first-stage gate drive circuit GA (1) is the first starting signal stv1, the starting signal STV corresponding to the second-stage gate drive circuit GA (2) is the second starting signal stv2, the starting signal STV corresponding to the third-stage gate drive circuit GA (3) is the third starting signal, the starting signal STV corresponding to the fourth-stage gate drive circuit GA (4) is the signal of the second node Q2 of the first-stage gate drive circuit GA (1), the starting signal STV corresponding to the fifth-stage gate drive circuit GA (5) is the signal of the second node Q2 of the second-stage gate drive circuit GA (2), the starting signal STV corresponding to the sixth-stage gate drive circuit GA (6) is the signal of the second node Q2 of the third-stage gate drive circuit GA (3), and so on, so that the cascade relationship of the multi-stage gate drive circuit GA is obtained.

[0065] The two gate drive circuits GA in phase cascade are spaced by two gate drive circuits GA, and the phase difference of the first clock signals XCK corresponding to the two gate drive circuits GA in phase cascade is 3H. The phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than 3H.

[0066] Similarly, when X>2, the cascade relationship of the multi-stage gate drive circuit GA and the relationship between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels can also be obtained, which will not be described here.

[0067] Optionally, the plurality of gate drive circuits GA are electrically connected with Y clock lines, and the Y clock lines are configured to transmit corresponding first clock signals XCK to the plurality of gate drive circuits GA; wherein Y=2(X+1).

[0068] Optionally, please continue to refer to Figure 6 , X=1, the plurality of gate drive circuits GA are electrically connected with 4 (i.e. Y=4) clock lines, and the Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3 and a fourth clock line CKL4. The first clock line CKL1 transmits a corresponding first clock signal XCK to the 4k+1-stage gate drive circuit GA, the second clock line CKL2 transmits a corresponding first clock signal XCK to the 4k+2-stage gate drive circuit GA, the third clock line CKL3 transmits a corresponding first clock signal XCK to the 4k+3-stage gate drive circuit GA, and the fourth clock line CKL4 transmits a corresponding first clock signal XCK to the 4k+4-stage gate drive circuit GA; wherein k≥0.

[0069] Optionally, X=2, the plurality of gate driving circuits GA are electrically connected with 6 clock lines (i.e. Y=6), and the 6 clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a fifth clock line and a sixth clock line. The first clock line CKL1 transmits a corresponding first clock signal XCK to the 6k+1th gate driving circuit GA, the second clock line CKL2 transmits a corresponding first clock signal XCK to the 6k+2th gate driving circuit GA, the third clock line CKL3 transmits a corresponding first clock signal XCK to the 6k+3th gate driving circuit GA, the fourth clock line CKL4 transmits a corresponding first clock signal XCK to the 6k+4th gate driving circuit GA, the fifth clock line transmits a corresponding first clock signal XCK to the 6k+5th gate driving circuit GA, and the sixth clock line transmits a corresponding first clock signal XCK to the 6k+6th gate driving circuit GA; wherein k≥0.

[0070] Optionally, in some embodiments, to further reduce power consumption and reduce the layout space occupied by the display driving circuit Dc, each gate driving circuit GA can be configured to output a second gate control signal Pscan1 in addition to the first gate control signal Nscan1. That is, each gate driving circuit GA is configured to generate a plurality of second gate control signals Pscan1 according to the corresponding start signal STV, the first clock signal XCK and the second clock signal CK.

[0071] Optionally, each gate driving circuit GA includes a first output end Nout and a second output end Pout, the first output end Nout is configured to output the first gate control signal Nscan1, and the second output end Pout is configured to output the second gate control signal Pscan1. The plurality of first scan lines SL1 are electrically connected between the first output ends Nout of the plurality of gate driving circuits GA and the control ends of the compensation transistors Tc of the plurality of sub-pixels Spi, and the plurality of second scan lines SL2 are electrically connected between the second output ends Pout of the plurality of gate driving circuits GA and the control ends of the data transistors Tda of the plurality of sub-pixels Spi.

[0072] Optionally, to improve display differences, the phase difference between the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda and one of the two first effective levels is greater than 0 and less than (X+1)H, so that the first gate control signal Nscan1 and the second gate control signal Pscan1 corresponding to the same sub-pixel Spi are generated by gate driving circuits GA of different levels.

[0073] Optionally, in the mth row of the plurality of sub-pixels Spi, a control terminal of the compensation transistor Tc is electrically connected to the pth gate driving circuit GA(p) to receive a pth first gate control signal Nscan1(p) output by the pth gate driving circuit GA(p); and a control terminal of the data transistor Tda is electrically connected to the (p+1)th gate driving circuit GA(p+1) to receive a (p+1)th second gate control signal Pscan1(p+1) output by the (p+1)th gate driving circuit GA(p+1); wherein m≥1 and p≥1.

[0074] By making the number of stages of the gate driving circuit GA corresponding to the data transistor Tda greater than the number of stages of the gate driving circuit GA corresponding to the compensation transistor Tc in the same sub-pixel Spi, the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda can correspond to the interval period in which the voltage drop of the first gate control signal Nscan1 changes, so as to improve the display difference of the plurality of sub-pixels Spi.

[0075] Optionally, in some embodiments, in the mth row of the plurality of sub-pixels Spi, a control terminal of the compensation transistor Tc is electrically connected to a first output terminal Nout of the pth gate driving circuit GA(p), and a control terminal of the data transistor Tda is electrically connected to a second output terminal Pout of the (p-1)th gate driving circuit GA(p-1), so as to control the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda to correspond to the interval period in which the voltage drop of the first gate control signal Nscan1 changes.

[0076] Optionally, in the same sub-pixel Spi, the gate driving circuit GA corresponding to the data transistor Tda and the gate driving circuit GA corresponding to the compensation transistor Tc are not cascaded, so as to control the effective level of the second gate control signal Pscan1 corresponding to the data transistor Tda to correspond to the interval period in which the voltage drop of the first gate control signal Nscan1 changes.

[0077] Please continue to refer to Figure 6 and Figure 7For example, when X=1, the control terminal of the compensation transistor Tc in the mth row of the plurality of sub-pixels Spi is electrically connected to the 7th gate drive circuit GA(7), and the control terminal of the data transistor Tda can be electrically connected to the second output terminal Pout of the 8th gate drive circuit GA(8), the second output terminal Pout of the 6th gate drive circuit GA(6), the second output terminal Pout of the 4th gate drive circuit GA(4), or the second output terminal Pout of the 2nd gate drive circuit GA(2). The effective level of the first gate control signal Nscan1 output by the 7th gate drive circuit GA(7) partially overlaps with the effective level of the second gate control signal Pscan1 output by the 8th gate drive circuit GA(8), the 6th gate drive circuit GA(6), the 4th gate drive circuit GA(4), and the 2nd gate drive circuit GA(2). Similarly, when X≥2, the number of gate drive circuits GA that can be matched with the compensation transistor Tc and the data transistor Tda in the same sub-pixel Spi can be obtained.

[0078] Optionally, please continue to refer to Figure 6 The plurality of gate drive circuits GA are electrically connected to Z clock lines, and the Z clock lines are configured to transmit corresponding second clock signals CK to the plurality of gate drive circuits GA; wherein Z=2(X+1).

[0079] Optionally, the Y clock lines can be shared as the Z clock lines, so as to reduce the number of clock lines used by the display drive circuit Dc, and facilitate reducing the frame size of the display panel DP.

[0080] For example, when X=1, the Z clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. The third clock line CKL3 transmits a corresponding second clock signal CK to the 4k+1th gate drive circuit GA, the fourth clock line CKL4 transmits a corresponding second clock signal CK to the 4k+2th gate drive circuit GA, the first clock line CKL1 transmits a corresponding second clock signal CK to the 4k+3th gate drive circuit GA, and the second clock line CKL2 transmits a corresponding second clock signal CK to the 4k+4th gate drive circuit GA.

[0081] For another example, when X=2 and Z clock lines are included, the Z clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a fifth clock line and a sixth clock line. The fourth clock line CKL4 transmits a corresponding second clock signal CK to the 6k+1 stage gate driving circuit GA, the fifth clock line transmits a corresponding second clock signal CK to the 6k+2 stage gate driving circuit GA, the sixth clock line transmits a corresponding second clock signal CK to the 6k+3 stage gate driving circuit GA, the first clock line CKL1 transmits a corresponding second clock signal CK to the 6k+4 stage gate driving circuit GA, the second clock line CKL2 transmits a corresponding second clock signal CK to the 6k+5 stage gate driving circuit GA, and the third clock line CKL3 transmits a corresponding second clock signal CK to the 6k+6 stage gate driving circuit GA.

[0082] Similarly, when X>2, the matching relationship between the multi-stage gate driving circuit GA and the Z clock lines can also be obtained.

[0083] It can be understood that the first gate control signal Nscan1 and the second gate control signal Pscan1 can also be provided by different gate driving units. That is, in the display driving circuit Dc, the number of gate driving units can be set to be multiple, and the gate driving circuit GA can be configured to output only the first gate control signal Nscan1 or the second gate control signal Pscan1. For example, the display device can include two gate driving units. The multiple first output terminals Nout of one gate driving unit output multiple first gate control signals Nscan1, and the multiple first output terminals Nout of one gate driving unit output multiple second gate control signals Pscan1.

[0084] Optionally, the first gate control signal Nscanl generated by the plurality of gate driving circuits GA can be output to the control terminal of the reset transistor Tr of the plurality of sub-pixels Spi as the third gate control signal Nscan2 via the plurality of third scan lines SL3. The first gate control signal Nscanl received by the reset transistor Tr and the first gate control signal Nscanl received by the compensation transistor Tc in the same sub-pixel Spi are generated by different stages of the gate driving circuit GA. Optionally, the control terminal of the reset transistor Tr of the sub-pixel Spi located in the mth row receives the first gate control signal Nscanl of the p-D stage (p-D), and the control terminal of the compensation transistor Tc of the sub-pixel Spi located in the mth row receives the first gate control signal Nscanl of the p+E stage (p+E). Wherein, D≥1, E≥1. As in the plurality of sub-pixels Spi located in the mth row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the gate driving circuit GA of the p+1 stage (p+1), and the control terminal of the reset transistor Tr is electrically connected to the first output terminal Nout of the gate driving circuit GA of the p-2 stage.

[0085] As in the plurality of sub-pixels Spi located in the 8th row, the control terminal of the compensation transistor Tc is electrically connected to the first output terminal Nout of the gate driving circuit GA of the 9th stage (9), and the control terminal of the reset transistor Tr is electrically connected to any one of the second output terminal Pout of the gate driving circuit GA of the 1st stage (1) to the second output terminal Pout of the gate driving circuit GA of the 7th stage (7).

[0086] Optionally, in some embodiments, the first gate control signal Nscanl received by the compensation transistor Tc and the third gate control signal Nscan2 received by the reset transistor Tr in the same sub-pixel Spi are generated by the gate driving circuits GA included in different gate driving units. For example, one gate driving unit included in the display driving circuit Dc generates a plurality of first gate control signals Nscanl output to the control terminal of the compensation transistor Tc of the plurality of sub-pixels Spi, and another gate driving unit included in the display driving circuit Dc generates a plurality of third gate control signals Nscan2 output to the control terminal of the reset transistor Tr of the plurality of sub-pixels Spi. It can be understood that the design of the gate driving unit electrically connected to the control terminal of the reset transistor Tr of the plurality of sub-pixels Spi can refer to the design of the gate driving unit electrically connected to the control terminal of the compensation transistor Tc of the plurality of sub-pixels Spi.

[0087] Optionally, in some embodiments, the second gate control signal Pscanl generated by the plurality of gate driving circuits GA can be output to the control terminal of the first initial transistor Tii of the plurality of sub-pixels Spi as the first scan signal Pscan2 via the plurality of fourth scan lines SL4.

[0088] Optionally, in some embodiments, a gate driving unit can be separately arranged to provide the required first scanning signal Pscan2 for the first initial transistor Ti1 of the plurality of sub-pixels Spi.

[0089] It can be understood that the display driving circuit Dc can separately arrange a gate driving unit to provide the required light-emitting control signal EM for the light-emitting control transistor of the plurality of sub-pixels Spi.

[0090] Figure 8 is a structural schematic diagram of the gate driving circuit provided by the embodiment of the present application, each gate driving circuit GA includes a node control module 10, a first output module 20 and a first frequency division module 30.

[0091] The node control module 10 is electrically connected with the first node Q1 and the second node Q2 of the gate driving circuit GA of the present stage, and the node control module 10 is configured to control the signals transmitted to the first node Q1 and the second node Q2 according to the corresponding first clock signal XCK and the start signal STV.

[0092] The first output module 20 is electrically connected with the first node Q1, and the first output module 20 is configured to output the first gate control signal Nscan1 according to the corresponding frequency division control signal and the signal of the first node Q1.

[0093] The first frequency division module 30 is electrically connected with the first node Q1, the second node Q2 and the first output module 20, and the first frequency division module 30 is configured to control the signal transmission between the first node Q1 and the first output module 20 according to the corresponding frequency division control signal and the signal of the second node Q2.

[0094] Optionally, please continue to refer to Figure 8 , the node control module 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5.

[0095] The control end of the first transistor T1 is configured to receive the corresponding start signal STV, and the input end of the first transistor T1 is electrically connected with the first power supply end NVGL.

[0096] The control end of the second transistor T2 is electrically connected with the control end of the first transistor T1, the input end of the second transistor T2 is electrically connected with the second power supply end PVGH, and the output end of the second transistor T2 is electrically connected with the output end of the first transistor T1.

[0097] The control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected with the output end of the first transistor T1, and the output end of the third transistor T3 is electrically connected with the first node Q1.

[0098] The control terminal of the fourth transistor T4 is electrically connected with the first node Q1, the input terminal of the fourth transistor T4 is electrically connected with the third power supply terminal PVGL, and the output terminal of the fourth transistor T4 is electrically connected with the second node Q2.

[0099] The control terminal of the fifth transistor T5 is electrically connected with the first node Q1, the input terminal of the fifth transistor T5 is electrically connected with the second power supply terminal PVGH, and the output terminal of the fifth transistor T5 is electrically connected with the second node Q2.

[0100] Optionally, the first transistor T1 has two control terminals, and the fourth transistor T4 has two control terminals. The first control terminal and the second control terminal of the first transistor T1 are configured to receive corresponding start signals STV, and the first control terminal and the second control terminal of the fourth transistor T4 are electrically connected with the first node Q1.

[0101] Optionally, the node control module 10 of the at least one gate drive circuit GA includes a sixth transistor T6. The control terminal of the sixth transistor T6 is electrically connected with the second node Q2, the input terminal of the sixth transistor T6 is electrically connected with the first power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected with the first node Q1.

[0102] Optionally, the sixth transistor T6 has two control terminals, and the first control terminal and the second control terminal of the sixth transistor T6 are electrically connected with the second node Q2.

[0103] Optionally, the node control module 10 of the at least one gate drive circuit GA includes a seventh transistor T7 and an eighth transistor T8.

[0104] The control terminal of the seventh transistor T7 is configured to receive a corresponding first clock signal XCK, and the output terminal of the seventh transistor T7 is electrically connected with the first node Q1.

[0105] The control terminal of the eighth transistor T8 is electrically connected with the second node Q2, the input terminal of the eighth transistor T8 is electrically connected with the second power supply terminal PVGH, and the output terminal of the eighth transistor T8 is electrically connected with the input terminal of the seventh transistor T7.

[0106] Optionally, the seventh transistor T7 has two control terminals, and the first control terminal and the second control terminal of the seventh transistor T7 are configured to receive a corresponding first clock signal XCK.

[0107] Please continue to refer to Figure 8 , the first frequency division module 30 includes a first frequency division transistor Tf1, a second frequency division transistor Tf2, and a first capacitor C1.

[0108] The control end of the first frequency division transistor Tf1 is electrically connected with the second node Q2 of the gate drive circuit GA of the current stage, and the input end of the first frequency division transistor Tf1 is configured to receive a corresponding frequency division control signal.

[0109] The control end of the second frequency division transistor Tf2 is electrically connected with the output end of the first frequency division transistor Tf1, the input end of the second frequency division transistor Tf2 is electrically connected with the first node Q1, and the output end of the second frequency division transistor Tf2 is electrically connected with the first output module 20 through the third node Q3.

[0110] The first end of the first capacitor C1 is electrically connected with the control end of the second frequency division transistor Tf2, and the second end of the first capacitor C1 is electrically connected with the third node Q3.

[0111] Optionally, in order to reduce the number of frequency division control lines FL used by the display drive circuit Dc, a plurality of first frequency division modules 30 can be electrically connected with the same frequency division control line FL, so as to realize the level control of the plurality of first gate control signals Nscan1 by the frequency division control signal transmitted by the frequency division control line FL.

[0112] Optionally, the plurality of frequency division control lines FL includes a first frequency division control line FL1, the first frequency division control line FL1 is electrically connected with the first frequency division module 30 of the multi-stage gate drive circuit GA, and the first frequency division control line FL1 provides the first frequency division control signal NLF to the first frequency division module 30 of the multi-stage gate drive circuit GA.

[0113] It can be understood that a plurality of first frequency division modules 30 can be electrically connected with a plurality of frequency division control lines FL, so as to realize the level control of a plurality of first gate control signals Nscan1 by a plurality of frequency division control signals transmitted by a plurality of frequency division control lines FL.

[0114] Please continue to refer to Figure 8 , the first output module 20 includes a first output transistor To1 and a second output transistor To2.

[0115] The control end of the first output transistor To1 is electrically connected with the third node Q3, and the input end of the first output transistor To1 is electrically connected with the fourth power supply end NVGH.

[0116] The control end of the second output transistor To2 is electrically connected with the first node Q1, the input end of the second output transistor To2 is electrically connected with the first power supply end NVGL, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected with the first output end Nout of the gate drive circuit GA of the current stage.

[0117] Optionally, the second output transistor To2 has two control terminals, i.e., the first control terminal and the second control terminal of the second output transistor To2 are electrically connected with the first node Q1.

[0118] Optionally, please continue to refer to Figure 8 , the at least one gate drive circuit GA further comprises a first control module 40, the first control module 40 comprises a first switch transistor Ts1 and a second switch transistor Ts2, so that the first gate control signal Nscan1 output by the gate drive circuit GA has better stability.

[0119] The control terminal of the first switch transistor Ts1 is configured to receive a corresponding first clock signal XCK, and the output terminal of the first switch transistor Ts1 is electrically connected with the third node Q3.

[0120] The control terminal of the second switch transistor Ts2 is electrically connected with the second node Q2 of the gate drive circuit GA at the current stage, the input terminal of the second switch transistor Ts2 is electrically connected with the second power supply terminal PVGH, and the output terminal of the second switch transistor Ts2 is electrically connected with the input terminal of the first switch transistor Ts1.

[0121] Optionally, the first switch transistor Ts1 has two control terminals, and the first control terminal and the second control terminal of the first switch transistor Ts1 are configured to receive a corresponding first clock signal XCK.

[0122] Optionally, when the gate drive circuit GA outputs the first gate control signal Nscan1 and the second gate control signal Pscan1 at the same time, the gate drive circuit GA further comprises a second output module 50 for outputting the second gate control signal Pscan1. That is, the at least one gate drive circuit GA comprises the second output module 50, the second output module 50 is electrically connected with the first node Q1 and the second node Q2, and the second output module 50 is configured to output the second gate control signal Pscan1 according to the corresponding second clock signal CK, the signal of the first node Q1 and the signal of the second node Q2.

[0123] Optionally, please continue to refer to Figure 8 , the second output module 50 comprises a third output transistor To3, a fourth output transistor To4 and a second capacitor C2.

[0124] The control terminal of the third output transistor To3 is electrically connected with the first node Q1, and the input terminal of the third output transistor To3 is configured to receive a corresponding second clock signal CK.

[0125] The control terminal of the fourth output transistor To4 is electrically connected with the second node Q2, the input terminal of the fourth output transistor To4 is electrically connected with the second power supply terminal PVGH, and the output terminal of the fourth output transistor To4 and the output terminal of the third output transistor To3 are electrically connected with the second output terminal Pout of the gate drive circuit GA of the current stage.

[0126] The first terminal of the second capacitor C2 is electrically connected with the control terminal of the third output transistor To3, and the second terminal of the second capacitor C2 is electrically connected with the second output terminal Pout of the gate drive circuit GA of the current stage.

[0127] Optionally, in some embodiments, the second output module 50 of at least one gate drive circuit GA comprises a third switch transistor Ts3, the control terminal of the third switch transistor Ts3 is configured to receive a switch control signal SC, the input terminal of the third switch transistor Ts3 is electrically connected with the first node Q1, and the output terminal of the third switch transistor Ts3 is electrically connected with the control terminal of the third output transistor To3.

[0128] Optionally, the switch control signal SC received by the control terminal of the third switch transistor Ts3 of the gate drive circuit GA(p) of the pth stage corresponds to the signal of the second node Q2 of the gate drive circuit GA(p-C) of the (p-C)th stage. Wherein C≥1.

[0129] The switch control signal SC received by the control terminal of the eleventh transistor T11 of the gate drive circuit GA(1)~GA(4) corresponds to a low-level signal VGL, and the control terminal of the eleventh transistor T11 of each gate drive circuit GA after the gate drive circuit GA(4) of the fourth stage is electrically connected with the second node Q2 in the previous three or four gate drive circuits GA. The switch control signal SC corresponding to the gate drive circuit GA(5) of the fifth stage corresponds to the signal of the second node Q2 of the gate drive circuit GA(2) of the second stage, and the switch control signal SC corresponding to the gate drive circuit GA(6) of the sixth stage corresponds to the signal of the second node Q2 of the gate drive circuit GA(3) of the third stage; or, the switch control signal SC corresponding to the gate drive circuit GA(5) of the fifth stage corresponds to the signal of the second node Q2 of the gate drive circuit GA(1) of the first stage. The switch control signal SC corresponding to the gate drive circuit GA(6) of the sixth stage corresponds to the signal of the second node Q2 of the gate drive circuit GA(2) of the second stage. Similarly, the switch control signals SC corresponding to the gate drive circuits GA of the remaining stages can also be obtained.

[0130] Optionally, in some embodiments, a second frequency division module 60 can also be arranged in the gate drive circuit GA to control the level of the plurality of second gate control signals Pscan1.

[0131] Please continue to refer toFigure 8 The at least one gate drive circuit GA comprises a second frequency division module 60 electrically connected with the first node Q1, the second node Q2 and the second output module 50. The second frequency division module 60 is configured to control the signal transmission between the first node Q1 and the corresponding second output module 50 according to the corresponding frequency division control signal and the signal of the second node Q2. Correspondingly, a plurality of frequency division control lines FL are configured to transmit the frequency division control signal to the plurality of gate drive circuits GA to control the level of at least one of the plurality of second gate control signals Pscan1.

[0132] Optionally, the second frequency division module 60 comprises a third frequency division transistor Tf3, a fourth frequency division transistor Tf4 and a third capacitor C3.

[0133] The control terminal of the third frequency division transistor Tf3 is electrically connected with the second node Q2 of the gate drive circuit GA at the current stage, and the input terminal of the third frequency division transistor Tf3 is configured to receive the corresponding frequency division control signal.

[0134] The control terminal of the fourth frequency division transistor Tf4 is electrically connected with the output terminal of the third frequency division transistor Tf3, the input terminal of the fourth frequency division transistor Tf4 is electrically connected with the first node Q1, and the output terminal of the fourth frequency division transistor Tf4 is electrically connected with the second output module 50.

[0135] The first terminal of the third capacitor C3 is electrically connected with the control terminal of the fourth frequency division transistor Tf4, and the second terminal of the third capacitor C3 is electrically connected with the output terminal of the fourth frequency division transistor Tf4.

[0136] Optionally, the output terminal of the fourth frequency division transistor Tf4 is electrically connected with the input terminal of the third switch transistor Ts3, so as to control the signal transmission between the second output module 50 and the first node Q1 through the fourth frequency division transistor Tf4 and the third switch transistor Ts3.

[0137] Optionally, in order to reduce the number of frequency division control lines FL used by the gate control unit, the second frequency division modules of the plurality of gate drive circuits GA can be electrically connected to the same frequency division control line FL.

[0138] It can be understood that the second frequency division modules of the plurality of gate drive circuits GA can also be electrically connected to different frequency division control lines FL, so that the second frequency division modules of the plurality of gate drive circuits GA can be independently controlled.

[0139] Optionally, to make the levels of the plurality of first gate control signals Nscan1 and the plurality of second gate control signals Pscan1 independently controllable, the first frequency division module 30 and the second frequency division module in the same gate drive circuit GA are electrically connected with different frequency division control lines FL. Optionally, the plurality of frequency division control lines FL includes a first frequency division control line FL1 and a second frequency division control line FL2. The first frequency division control line FL1 is electrically connected with the first frequency division module 30 of the multi-stage gate drive circuit GA, the second frequency division control line FL2 is electrically connected with the second frequency division module 60 of the multi-stage gate drive circuit GA, and the second frequency division control line FL2 transmits a second frequency division control signal PLF to the second frequency division module 60 of the multi-stage gate drive circuit GA.

[0140] Optionally, in some embodiments, the at least one gate drive circuit GA further includes a second control module 70, and the second control module 70 includes a fourth switch transistor Ts4 and a fifth switch transistor Ts5.

[0141] The control terminal of the fourth switch transistor Ts4 is configured to receive a corresponding first clock signal XCK, and the output terminal of the fourth switch transistor Ts4 is electrically connected with the input terminal of the third switch transistor Ts3.

[0142] The control terminal of the fifth switch transistor Ts5 is electrically connected with the second node Q2 of the current stage gate drive circuit GA, the input terminal of the fifth switch transistor Ts5 is electrically connected with the second power supply terminal PVGH, and the output terminal of the fifth switch transistor Ts5 is electrically connected with the input terminal of the fourth switch transistor Ts4.

[0143] Optionally, the fourth switch transistor Ts4 has two control terminals, and the first control terminal and the second control terminal of the fourth switch transistor Ts4 are configured to receive a corresponding first clock signal XCK.

[0144] Optionally, please continue to refer to Figure 8 , the at least one gate drive circuit GA further includes a reset module 80, the reset module 80 is electrically connected with the first node Q1, and the reset module 80 is configured to control the signal transmission between the second power supply terminal PVGH and the first node Q1 according to a reset control signal Ctl.

[0145] Optionally, the reset module 80 includes a reset transistor Tre, the control terminal of the reset transistor Tre is configured to receive a reset control signal Ctl, the input terminal of the reset transistor Tre is electrically connected with the second power supply terminal PVGH, and the output terminal of the reset transistor Tre is electrically connected with the first node Q1.

[0146] Optionally, when the display drive circuit Dc is applied in a display device, the reset module 80 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0147] Optionally, in some embodiments, the voltage corresponding to the third power supply end PVGL is less than the voltage corresponding to the second power supply end PVGH, and the voltage corresponding to the first power supply end NVGL is less than the voltage corresponding to the fourth power supply end NVGH.

[0148] Figures 9A-9B is a timing diagram of the corresponding gate drive circuit provided by the embodiment of the application, taking the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the second switch transistor Ts2, the third switch transistor Ts3, the fifth switch transistor Ts5, the first output transistor To1, the third output transistor To3~the fourth output transistor To4 and the first frequency division transistor Tf1~the fourth frequency division transistor Tf4 as P-type transistors, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first switch transistor Ts1, the fourth switch transistor Ts4, the second output transistor To2 as N-type transistors, X=1, the third clock line CKL3 transmits the corresponding first clock signal XCK to the pth gate drive circuit GA, the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the (p+1)th gate drive circuit GA, the first clock line CKL1 transmits the corresponding first clock signal XCK to the (p+2)th gate drive circuit GA, the second clock line CKL2 transmits the corresponding first clock signal XCK to the (p+3)th gate drive circuit GA, the first clock line CKL1 transmits the corresponding second clock signal CK to the pth gate drive circuit GA, the second clock line CKL2 transmits the corresponding second clock signal CK to the (p+1)th gate drive circuit GA, the third clock line CKL3 transmits the corresponding second clock signal CK to the (p+2)th gate drive circuit GA, and the fourth clock line CKL4 transmits the corresponding second clock signal CK to the (p+3)th gate drive circuit GA, for example, the working principle of the plurality of gate drive circuits GA is described. Wherein, p is an odd number.

[0149] In the first stage t1, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level state, the third clock signal CK3 transmitted by the third clock line CKL3 has a low level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level state. The second node Q2 of the (p-2)th gate drive circuit GA(p-2)~the second node Q2 of the (p-1)th gate drive circuit GA(p-1) has a high level. The first frequency division control signal NLF and the second frequency division control signal PLF have a low level.

[0150] In the pth stage gate drive circuit GA(p), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the second frequency dividing transistor Tf2, the fourth frequency dividing transistor Tf4, the first output transistor To1 are turned on, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, the first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the fourth switch transistor Ts4, the fifth switch transistor Ts5, the first frequency dividing transistor Tf1, the third frequency dividing transistor Tf3, the second output transistor To2 to the fourth output transistor To4 are turned off. The pth stage first gate control signal Nscan1(p) and the pth stage second gate control signal Pscan1(p) have high levels.

[0151] The third transistor T3 is turned off in the gate drive circuit GA which is located behind the pth stage gate drive circuit GA(p) and to which the first clock signal XCK does not correspond and is provided by the third clock line CKL3. The second transistor T2 and the third transistor T3 are turned on in the gate drive circuit GA which is located behind the pth stage gate drive circuit GA(p) and to which the first clock signal XCK corresponds and is provided by the third clock line CKL3. Therefore, the p+1th stage first gate control signal Nscan1(p+1) to the p+11th stage first gate control signal Nscan1(p+11) remain low, and the p+1th stage second gate control signal Pscan1(p+1) to the p+11th stage second gate control signal Pscan1(p+11) have high levels.

[0152] In the second stage t2, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a low level. The second node Q2 of the p-2th stage gate drive circuit GA(p-2) to the second node Q2 of the p-1th stage gate drive circuit GA(p-1) have high levels. The first frequency dividing control signal NLF and the second frequency dividing control signal PLF have low levels.

[0153] In the pth stage gate drive circuit GA(p), the third transistor T3 is turned off, and the pth stage first gate control signal Nscan1(p) and the pth stage second gate control signal Pscan1(p) have high levels.

[0154] The action performed by the (p+1)th gate drive circuit GA(p+1) in the second stage t2 is similar to the action performed by the pth gate drive circuit GA(p) in the first stage t1. The action performed by the (p+2)th gate drive circuit GA(p+2) in the second stage t2 is similar to the action performed by the (p+1)th gate drive circuit GA(p+1) in the first stage t1. By analogy, the steps performed by the (p+3)th gate drive circuit GA(p+3) to the (p+11)th gate drive circuit GA(p+11) in the second stage t2 are obtained. Thus, the (p+1)th first gate control signal Nscan1(p+1) has a high level, the (p+2)th first gate control signal Nscan1(p+2) to the (p+11)th first gate control signal Nscan1(p+11) have low levels, and the (p+1)th second gate control signal Pscan1(p+1) to the (p+11)th second gate control signal Pscan1(p+11) have high levels.

[0155] In the third stage t3, the first clock signal CK1 transmitted by the first clock line CKL1 has a low level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The second nodes Q2 of the (p-2)th gate drive circuit GA(p-2) to the (p-1)th gate drive circuit GA(p-1) have high levels. The first frequency division control signal NLF and the second frequency division control signal PLF have low levels.

[0156] In the pth gate drive circuit GA(p), the third transistor T3 is off, and the pth first gate control signal Nscan1(p) and the pth second gate control signal Pscan1(p) have high levels. Moreover, because the start signal STV corresponding to the (p+2)th gate drive circuit GA(p+2) is provided by the pth gate drive circuit GA(p), and because the action performed by the (p+2)th gate drive circuit GA(p+2) in the third stage t3 is similar to the action performed by the pth gate drive circuit GA(p) in the first stage t1, in the third stage t3, the first output terminal Nout of the (p+2)th gate drive circuit GA(p+2) is electrically connected to the fourth power supply terminal NVGH, so that the corresponding load on the fourth power supply terminal NVGH is increased, and then the pth first gate control signal Nscan1(p) appears a voltage drop.

[0157] The action performed by the (p+1)th gate drive circuit GA(p+1) in the third stage t3 is similar to the action performed by the pth gate drive circuit GA(p) in the second stage t2. The action performed by the (p+2)th gate drive circuit GA(p+2) in the third stage t3 is similar to the action performed by the (p+1)th gate drive circuit GA(p+1) in the second stage t2. By analogy, the steps performed by the (p+3)th gate drive circuit GA(p+3) to the (p+11)th gate drive circuit GA(p+11) in the third stage t3 are obtained. Thus, the (p+1)th first gate control signal Nscan1(p+1) to the (p+2)th first gate control signal Nscan1(p+2) have high levels. The (p+3)th first gate control signal Nscan1(p+3) to the (p+11)th first gate control signal Nscan1(p+11) have low levels, and the (p+1)th second gate control signal Pscan1(p+1) to the (p+11)th second gate control signal Pscan1(p+11) have high levels.

[0158] In the fourth stage t4, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a low level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The second node Q2 of the (p-2)th gate drive circuit GA(p-2) to the second node Q2 of the (p-1)th gate drive circuit GA(p-1) have high levels. The first frequency division control signal NLF and the second frequency division control signal PLF have low levels.

[0159] The action performed by the pth gate drive circuit GA(p) in the fourth stage t4 is similar to the action performed by the pth gate drive circuit GA(p) in the first stage t1. Since the start signal STV corresponding to the (p+4)th gate drive circuit GA(p+4) is provided by the (p+2)th gate drive circuit GA(p+2), and since the action performed by the (p+4)th gate drive circuit GA(p+4) in the fourth stage t4 is similar to the action performed by the pth gate drive circuit GA(p) in the first stage t1, in the fourth stage t4, the first output terminal Nout of the (p+4)th gate drive circuit GA(p+4) is electrically connected to the fourth power supply terminal NVGH, so that the corresponding load on the fourth power supply terminal NVGH is increased, and then the voltage drop of the pth first gate control signal Nscan1(p) occurs.

[0160] The third transistor T3 is turned off in the gate drive circuit GA not provided with the third clock line CKL3 corresponding to the first clock signal XCK behind the pth gate drive circuit GA(p). The second transistor T2 and the third transistor T3 are turned on in the gate drive circuit GA provided with the third clock line CKL3 corresponding to the first clock signal XCK behind the pth gate drive circuit GA(p). Therefore, the p+1th to p+4th first gate control signals Nscan1(p+1) to Nscan1(p+4) have high levels, the p+5th to p+11th first gate control signals Nscan1(p+5) to Nscan1(p+11) have low levels, and the p+1th to p+11th second gate control signals Pscan1(p+1) to Pscan1(p+11) have high levels.

[0161] In the fifth stage t5, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a low level. The second nodes Q2 of the p-2th to p-1th gate drive circuits GA(p-2) to GA(p-1) have high levels. The first and second frequency division control signals NLF and PLF have low levels.

[0162] In the pth gate drive circuit GA(p), the third transistor T3 is turned off, and the pth first and second gate control signals Nscan1(p) and Pscan1(p) have high levels.

[0163] The action performed by the (p+1)th gate drive circuit GA(p+1) at the fifth stage t5 is similar to the action performed by the pth gate drive circuit GA(p) at the fourth stage t4. The action performed by the (p+2)th gate drive circuit GA(p+2) at the fifth stage t5 is similar to the action performed by the (p+1)th gate drive circuit GA(p+1) at the fourth stage t4. By analogy, the steps performed by the (p+3)th gate drive circuit GA(p+3) to the (p+11)th gate drive circuit GA(p+11) at the fifth stage t5 are obtained. Thus, the (p+1)th first gate control signal Nscan1(p+1) to the (p+5)th first gate control signal Nscan1(p+5) have high levels. The (p+6)th first gate control signal Nscan1(p+6) to the (p+11)th first gate control signal Nscan1(p+11) have low levels, and the (p+1)th second gate control signal Pscan1(p+1) to the (p+11)th second gate control signal Pscan1(p+11) have high levels.

[0164] At the sixth stage t6, the first clock signal CK1 transmitted by the first clock line CKL1 has a low level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The second node Q2 of the (p-2)th gate drive circuit GA(p-2) has a low level, and the second node Q2 of the (p-1)th gate drive circuit GA(p-1) has a high level. The first frequency division control signal NLF and the second frequency division control signal PLF have low levels.

[0165] At the pth gate drive circuit GA(p), the second switch transistor Ts2 and the third output transistor To3 are turned on, the pth first gate control signal Nscan1(p) has a high level, and the pth second gate control signal Pscan1(p) has a low level. Moreover, because the start signal STV corresponding to the (p+6)th gate drive circuit GA(p+6) is provided by the (p+4)th gate drive circuit GA(p+4), and because the action performed by the (p+6)th gate drive circuit GA(p+6) at the sixth stage t6 is similar to the action performed by the pth gate drive circuit GA(p) at the first stage t1, at the sixth stage t6, the first output end Nout of the (p+6)th gate drive circuit GA(p+6) is electrically connected to the fourth power supply end NVGH, so that the corresponding load on the fourth power supply end NVGH is increased, and then the pth first gate control signal Nscan1(p) appears a voltage drop.

[0166] The action performed by the (p+1)th gate drive circuit GA(p+1) at the sixth stage t6 is similar to the action performed by the pth gate drive circuit GA(p) at the fifth stage t5. The action performed by the (p+2)th gate drive circuit GA(p+2) at the sixth stage t6 is similar to the action performed by the (p+1)th gate drive circuit GA(p+1) at the fifth stage t5. By analogy, the steps performed by the (p+3)th gate drive circuit GA(p+3) to the (p+11)th gate drive circuit GA(p+11) at the sixth stage t6 are obtained. Thus, the (p+1)th first gate control signal Nscan1(p+1) to the (p+6)th first gate control signal Nscan1(p+6) have high levels. The (p+7)th first gate control signal Nscan1(p+7) to the (p+11)th first gate control signal Nscan1(p+11) have low levels, and the (p+1)th second gate control signal Pscan1(p+1) to the (p+11)th second gate control signal Pscan1(p+11) have high levels.

[0167] At the seventh stage t7, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a low level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The second node Q2 of the (p-2)th gate drive circuit GA(p-2) and the second node Q2 of the (p-1)th gate drive circuit GA(p-1) have low levels. The first frequency division control signal NLF and the second frequency division control signal PLF have low levels.

[0168] In the pth gate drive circuit GA(p), the second transistor T2, the third transistor T3, the fourth transistor T4, the second switch transistor Ts2, the first to fourth frequency division transistors Tf1 to Tf4, the second and fourth output transistors To2 and To4 are turned on. The first transistor T1, the fifth to eighth transistors T5 to T8, the first to fourth switch transistors Ts1 to Ts4, the fifth switch transistor Ts5, the first and third output transistors To1 and To3 are turned off. The pth first gate control signal Nscan1(p) has a low level, and the pth second gate control signal Pscan1(p) has a high level.

[0169] The p+1th gate drive circuit GA(p+1) performs an action similar to that performed by the p+1th gate drive circuit GA(p+1) at the fourth stage t4. The p+2th gate drive circuit GA(p+2) performs an action similar to that performed by the p+2th gate drive circuit GA(p+2) at the fourth stage t4. By analogy, the steps performed by the p+3th gate drive circuit GA(p+3) to the p+11th gate drive circuit GA(p+11) at the seventh stage t7 are obtained. Thus, the p+1th first gate control signal Nscan1(p+1) to the p+8th first gate control signal Nscan1(p+8) have high levels. The p+9th first gate control signal Nscan1(p+9) to the p+11th first gate control signal Nscan1(p+11) have low levels, the p+1th second gate control signal Pscan1(p+1), the p+3th second gate control signal Pscan1(p+3) to the p+11th second gate control signal Pscan1(p+11) have high levels, and the p+2th second gate control signal Pscan1(p+2) has a low level.

[0170] Please continue to refer to Figure 9A At the eighth stage t8, the first clock signal CK1 transmitted by the first clock line CKL1 has a low level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The first frequency division control signal NLF has a high level, and the second frequency division control signal PLF has a low level.

[0171] The pth first gate control signal Nscan1(p) to the p+2th first gate control signal Nscan1(p+2) have low levels, the p+3th first gate control signal Nscan1(p+3) to the p+9th first gate control signal Nscan1(p+9) have high levels, the p+4th second gate control signal Pscan1(p+4) has a low level, the pth second gate control signal Pscan1(p) to the p+3th second gate control signal Pscan1(p+3) and the p+5th second gate control signal Pscan1(p+5) to the p+9th second gate control signal Pscan1(p+9) have high levels.

[0172] In the gate drive circuit GA of the p+10th stage, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the fourth frequency division transistor Tf4 are turned on, the second transistor T2, the fourth transistor T4, the eighth transistor T8, the first switch transistor Ts1, the fourth switch transistor Ts4, the second switch transistor Ts2, the third switch transistor Ts3, the fifth switch transistor Ts5, the first frequency division transistor Tf1, the second frequency division transistor Tf2, the third frequency division transistor Tf3, the first output transistor To1~the fourth output transistor To4 are turned off. The first gate control signal Nscan1(p+10) of the p+10th stage has a low level, and the second gate control signal Pscan1(p+10) of the p+10th stage has a high level.

[0173] In the gate drive circuit GA of the p+11th stage, the third transistor T3 is turned off, the first gate control signal Nscan1(p+11) of the p+11th stage has a low level, and the second gate control signal Pscan1(p+11) of the p+11th stage has a high level.

[0174] Please continue to refer to Figure 9A In the ninth stage t9, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level state, the second clock signal CK2 transmitted by the second clock line CKL2 has a low level state, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level state. The first frequency division control signal NLF has a high level, and the second frequency division control signal PLF has a low level.

[0175] The first gate control signal Nscan1(p)~the first gate control signal Nscan1(p+3) of the p+3th stage have a low level, the first gate control signal Nscan1(p+4)~the first gate control signal Nscan1(p+9) of the p+9th stage have a high level, the second gate control signal Pscan1(p+5) of the p+5th stage has a low level, and the second gate control signal Pscan1(p)~the second gate control signal Pscan1(p+4) of the p+4th stage and the second gate control signal Pscan1(p+6)~the second gate control signal Pscan1(p+9) of the p+9th stage have a high level.

[0176] In the gate drive circuit GA of the p+10th stage, the third transistor T3 is turned off, the first gate control signal Nscan1(p+10) of the p+10th stage has a low level, and the second gate control signal Pscan1(p+10) of the p+10th stage has a high level.

[0177] The gate drive circuit GA(p+ll) performs an operation at the ninth stage t9 similar to that of the gate drive circuit GA(p+10) at the eighth stage t8. Thus, the first gate control signal Nscanl(p+ll) of the p+llth stage has a low level, and the second gate control signal Pscanl(p+ll) of the p+llth stage has a high level.

[0178] Please continue to refer to Figure 9B At the eighth stage t8, the first clock signal CK1 transmitted by the first clock line CKL1 has a low level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The first frequency division control signal NLF has a low level, and the second frequency division control signal PLF has a high level.

[0179] The first gate control signal Nscanl(p) to the first gate control signal Nscanl(p+2) of the p+2th stage have low levels, the first gate control signal Nscanl(p+3) to the first gate control signal Nscanl(p+9) of the p+9th stage have high levels, the second gate control signal Pscanl(p+4) of the p+4th stage has a low level, and the second gate control signal Pscanl(p) to the second gate control signal Pscanl(p+3) of the p+3th stage and the second gate control signal Pscanl(p+5) to the second gate control signal Pscanl(p+9) of the p+9th stage have high levels.

[0180] In the gate drive circuit GA(p+10), the first transistor Tl, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the second frequency division transistor Tf2, and the first output transistor To1 are turned on, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, the first switch transistor Ts1, the fourth switch transistor Ts4, the second switch transistor Ts2, the third switch transistor Ts3, the fifth switch transistor Ts5, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth frequency division transistor Tf4, and the second output transistor To2 to the fourth output transistor To4 are turned off. The first gate control signal Nscanl(p+10) of the p+10th stage has a high level, and the second gate control signal Pscanl(p+10) of the p+10th stage has a high level.

[0181] In the gate drive circuit GA of the p+11th stage, the third transistor T3 is off, the first gate control signal Nscanl(p+11) of the p+11th stage has a low level, and the second gate control signal Pscanl(p+11) of the p+11th stage has a high level.

[0182] Please continue to refer to Figure 9B In the ninth stage t9, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a low level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a high level. The first frequency division control signal NLF has a low level, and the second frequency division control signal PLF has a high level.

[0183] The first gate control signal Nscanl(p) to the first gate control signal Nscanl(p+8) of the pth stage have low levels, the first gate control signal Nscanl(p+9) to the first gate control signal Nscanl(p+11) of the p+9th stage have high levels, and the second gate control signal Pscanl(p) to the second gate control signal Pscanl(p+4) of the pth stage and the second gate control signal Pscanl(p+11) of the p+11th stage have high levels.

[0184] In the gate drive circuit GA of the p+10th stage, the fourth frequency division transistor Tf4 is off, and the second gate control signal Pscanl(p+10) of the p+10th stage has a high level.

[0185] Please continue to refer to Figure 9B In the tenth stage t10, the first clock signal CK1 transmitted by the first clock line CKL1 has a high level, the second clock signal CK2 transmitted by the second clock line CKL2 has a high level, the third clock signal CK3 transmitted by the third clock line CKL3 has a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 has a low level. The first frequency division control signal NLF has a low level, and the second frequency division control signal PLF has a high level.

[0186] The first gate control signal Nscanl(p) to the first gate control signal Nscanl(p+9) of the pth stage have low levels, the first gate control signal Nscanl(p+10) to the first gate control signal Nscanl(p+11) of the p+10th stage have high levels, and the second gate control signal Pscanl(p) to the second gate control signal Pscanl(p+10) of the pth stage have high levels.

[0187] In the p+11th stage gate drive circuit GA, the fourth frequency dividing transistor Tf4 is turned off, and the p+11th stage second gate control signal Pscan1(p+11) has a high level.

[0188] Therefore, the level of the first frequency dividing control signal NLF can control the levels of the plurality of first gate control signals Nscan1, and the level of the second frequency dividing control signal PLF can control the levels of the plurality of second gate control signals Pscan1.

[0189] Similarly, the working principle of the multi-stage gate drive circuit GA when the first frequency dividing control signal NLF and the second frequency dividing control signal PLF jump from a high level to a low level can also be obtained.

[0190] Optionally, the time of the first frequency dividing control signal NLF and the second frequency dividing control signal PLF jumping between the high level and the low level can be the same or different.

[0191] Figure 10 is the timing diagram corresponding to the sub-pixel provided by the embodiment of the present application, taking the transistor Tc and the reset transistor Tr as N-type transistors, and the driving transistor Tdr, the first initial transistor Ti1, the second initial transistor Ti2, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 as P-type transistors as an example, the working principle of the sub-pixel Spi located in the mth row is described. The first gate control signal Nscan1 received by the control end of the compensation transistor Tc of the mth row sub-pixel Spi corresponds to the output of the first output end Nout of the p+1th stage gate drive circuit GA, and the second gate control signal Pscan1 received by the control end of the data transistor Tda of the mth row sub-pixel Spi corresponds to the output of the second output end Pout of the p+2th stage gate drive circuit GA. The third gate control signal Nscan2 received by the control end of the reset transistor Tr of the mth row sub-pixel Spi corresponds to the output of the first output end Nout of the p-2th stage gate drive circuit GA. The gate drive circuit GA corresponding to the reset transistor Tr and the gate drive circuit GA corresponding to the compensation transistor Tc can belong to different gate drive units, and the gate drive circuit GA corresponding to the data transistor Tda can belong to the same gate drive unit as the gate drive circuit GA corresponding to the compensation transistor Tc; and / or the gate drive circuit GA corresponding to the data transistor Tda can belong to the same gate drive unit as the gate drive circuit GA corresponding to the reset transistor Tr.

[0192] In the first reset stage Si1, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at high level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at low level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at low level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at high level, and the third gate control signal Nscan2 corresponding to the mth row of sub-pixels Spi is at low level. The first initial signal Vi1 transmitted by the first initial line is transmitted to the anode of the light emitting device Di, so as to reset the potential of the anode of the light emitting device Di; the second initial signal Vi2 transmitted by the second initial line is transmitted to the input terminal and the output terminal of the driving transistor Tdr, so as to reset the potential of the input terminal and the output terminal of the driving transistor Tdr.

[0193] In the second reset stage Si2, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at high level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at high level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at low level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at high level, and the third gate control signal Nscan2 corresponding to the mth row of sub-pixels Spi is at high level. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the driving transistor Tdr, so as to reset the potential of the control terminal of the driving transistor Tdr.

[0194] In the data writing stage Sw, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at high level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at high level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at high level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at low level, and the third gate control signal Nscan2 corresponding to the mth row of sub-pixels Spi is at low level. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tdr.

[0195] In the data writing stage Sw, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at high level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at high level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at high level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at low level, and the third gate control signal Nscan2 corresponding to the mth row of sub-pixels Spi is at low level. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tdr.

[0196] In the third reset stage Si3, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at high level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at low level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at low level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at high level, and the third gate control signal Nscan2 corresponding to the mth row of sub-pixels Spi is at low level. The first initial signal Vi1 is transmitted to the anode of the light emitting device Di, and the second initial signal Vi2 is transmitted to the input end and the output end of the driving transistor Tdr.

[0197] In the light emitting stage Sd, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at low level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at high level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at low level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at high level, and the third gate control signal Nscan2 corresponding to the mth row of sub-pixels Spi is at low level. The first light emitting control transistor Te1 and the second light emitting control transistor Te2 are turned on, and the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0198] In the fourth reset stage Si4 and the fifth reset stage Si5, the light emitting control signal EM corresponding to the mth row of sub-pixels Spi is at high level, the first scan signal Pscan2 corresponding to the mth row of sub-pixels Spi is at low level, the first gate control signal Nscan1 corresponding to the mth row of sub-pixels Spi is at low level, the second gate control signal Pscan1 corresponding to the mth row of sub-pixels Spi is at high level, and the third gate control signal Nscan2 of the p-2th stage is at low level. The first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input end and the output end of the driving transistor Tdr.

[0199] The write frame WF includes the first reset stage Si1, the second reset stage Si2, the data writing stage Sw, the third reset stage Si3, and the light emitting stage Sd, and the hold frame HF includes the fourth reset stage Si4, the fifth reset stage Si5, and the light emitting stage Sd.

[0200] Optionally, in some embodiments, the emission control signal EM has an inactive level pulse width of 60H, the first scan signal Pscan2 has an active level pulse width of 4H, the first gate control signal Nscanl and the third gate control signal Nscan2 have an active level pulse width of 24H, and the second gate control signal Pscanl has an active level pulse width of 1H. The phase difference between the time when the emission control signal EM starts to have an inactive level corresponding to the write frame WF and the time when the first reset stage Si1 starts is 8H, the phase difference between the first reset stage Si1 and the second reset stage Si2 is 8H, and the phase difference between the third gate control signal Nscan2 and the first gate control signal Nscanl is 3H. The phase difference between the time when the first gate control signal Nscanl jumps from an active level to an inactive level corresponding to the write frame WF and the time when the third reset stage Si3 starts is 2H, the phase difference between the time when the third gate control signal Nscan2 jumps from an active level to an inactive level and the time when the second gate control signal Pscanl starts to have an active level is 2H, the phase difference between the time when the second gate control signal Pscanl starts to have an active level and the time when the first gate control signal Nscanl jumps from an active level to an inactive level is 1H, and the phase difference between the time when the third reset stage Si3 ends and the time when the emission control signal EM jumps from an inactive level to an active level is 7H.

[0201] According to Figures 9A-9B and Figure 10 analysis, each sub-pixel Spi corresponding to the display refresh data is applied to the first gate control signal Nscanl, and the interval time difference of the voltage drop change occurs, so that the charging difference of the sub-pixel Spi at the frequency division position can be improved, thereby improving the display difference problem.

[0202] Figure 11 The high-frequency and low-frequency picture display principle diagram provided by the embodiment of the application is used to illustrate the write frame WF and the hold frame HF by taking the static picture display of the display panel DP as an example.

[0203] When the display panel DP displays at a high frequency (for example, 60Hz), the display panel DP needs to perform 60 times of display data refresh operations in 1 second, that is, 1 second contains 60 frames of pictures, and each frame of display performs display data refresh, and correspondingly, the sub-pixel Spi matches the write frame WF shown in FIG. 8. Figure 10

[0204] ​When the display panel DP displays at a low frequency (e.g., 1 Hz), the display panel DP also contains 60 frames of pictures within 1 second, but only the first frame of picture performs the refresh operation of the display data. Accordingly, the sub-pixel Spi only matches the first frame F1 of the timing of the write frame WF, and the 59 frames of pictures successively after the first frame F1 keep the picture data signal of the first frame, without performing the refresh operation of the display data. Accordingly, the sub-pixel Spi matches the 59 frames successively after the first frame F1 of the timing of the hold frame HF. Figure 10 The 59 frames successively after the first frame F1 of the timing of the hold frame HF are shown. Figure 10 The 59 frames successively after the first frame F1 of the timing of the hold frame HF are shown.

[0205] The frame in which the refresh of the display data is performed can be recorded as the write frame WF, and the frame in which the refresh of the display data is not performed can be recorded as the hold frame HF.

[0206] Thus, in the write frame WF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc, the third gate control signal Nscan2 corresponding to the reset transistor Tr, and the second gate control signal Pscan1 corresponding to the data transistor Tda all need to have the effective level, so that the original data signal stored in the control end of the driving transistor Tdr is covered by the newly written data signal, so that the sub-pixel Spi re-implements the display according to the newly written data signal in the write frame WF.

[0207] In the hold frame HF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the third gate control signal Nscan2 corresponding to the reset transistor Tr of part of the sub-pixel Spi keep the ineffective level, so that the compensation transistor Tc and the reset transistor Tr are cut off, so that the control end of the driving transistor Tdr does not store the new data signal. In the hold frame HF, the second gate control signal Pscan1 corresponding to the data transistor Tda can keep the same frequency as the write frame WF. Alternatively, in the hold frame HF, the second gate control signal Pscan1 corresponding to the data transistor Tda can keep the ineffective level, so that the second gate control signal Pscan1 corresponding to the data transistor Tda has a frequency lower than that in the write frame WF in the hold frame HF.

[0208] In combination with the analysis of Figures 9A-9B , Figure 10 and Figure 11 , the principle of implementing the frequency division display by the display panel DP using the display driving circuit Dc is described.

[0209] In the first frame F1 of a display period, in order to write the new data signal to the control end of the driving transistor Tdr of the plurality of sub-pixels Spi, the first frequency division control signal NLF and the second frequency division control signal PLF need to keep the effective level state, and the plurality of rows of sub-pixels Spi in the display panel DP all experience Figure 10The write frame WF stage is shown. One display period can include one frame or multiple frames. When one display period includes one frame, the frame corresponds to the write frame WF of the multiple rows of sub-pixels Spi. When one display period includes multiple frames, the first frame Fl corresponds to the write frame WF of the multiple rows of sub-pixels Spi.

[0210] In the second frame F2 of one display period, if the first L-1 rows of sub-pixels Spi of the display panel DP are displayed using high frequency and the Lth row of sub-pixels Spi and the following rows of sub-pixels Spi are displayed using low frequency, the first gate control signal Nscanl, the second gate control signal Pscanl and the third gate control signal Nscan2 applied to the first L-1 rows of sub-pixels Spi need to have effective pulses, so that the first L-1 rows of sub-pixels Spi all experience the write frame WF stage shown. Figure 10 The write frame WF stage is shown. One display period can include one frame or multiple frames. When one display period includes one frame, the frame corresponds to the write frame WF of the multiple rows of sub-pixels Spi. When one display period includes multiple frames, the first frame Fl corresponds to the write frame WF of the multiple rows of sub-pixels Spi. Figure 10 The write frame WF stage is shown. One display period can include one frame or multiple frames. When one display period includes one frame, the frame corresponds to the write frame WF of the multiple rows of sub-pixels Spi. When one display period includes multiple frames, the first frame Fl corresponds to the write frame WF of the multiple rows of sub-pixels Spi.

[0211] Thus, for the first L-1 rows of sub-pixels Spi, the second frame F2 is still the write frame WF, and for the Lth row of sub-pixels Spi and the following rows of sub-pixels Spi, the second frame F2 is the hold frame HF. Therefore, corresponding to the second frame F2, the control end of the driving transistor Tdr of the first L-1 rows of sub-pixels Spi has data signal writing, and the control end of the driving transistor Tdr of the Lth row of sub-pixels Spi and the following rows of sub-pixels Spi does not have data signal writing. The first L-1 rows of sub-pixels Spi and the Lth row of sub-pixels Spi and the following rows of sub-pixels Spi have a difference in refresh frequency corresponding to the second frame F2, so that the display panel DP realizes the frequency division display function.

[0212] Since the effective voltage of the second gate control signal Pscanl received by the data transistor Tda in each sub-pixel Spi corresponds to the interval time difference in which the first gate control signal Nscanl received by the compensation transistor Tc has a voltage drop change, the charging difference of the sub-pixels Spi in the part of the first L-1 rows of sub-pixels Spi close to the frequency division position can be improved, thereby improving the display difference problem.

[0213] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A display device, characterized by comprising: The display panel comprises a plurality of sub-pixels, each of which comprises a light-emitting device, a drive transistor configured to drive the light-emitting device to emit light, a data transistor and a compensation transistor configured to transmit a data signal to the control end of the drive transistor. The display driving circuit is electrically connected to the display panel and is configured to output a plurality of first gate control signals to the control end of the compensation transistor of a plurality of sub-pixels and a plurality of second gate control signals to the control end of the data transistor of a plurality of sub-pixels. The display driving circuit comprises a plurality of gate driving circuits and a plurality of frequency division control lines configured to transmit a frequency division control signal to a plurality of gate driving circuits to control the level of at least one of the plurality of first gate control signals. Each of the gate driving circuits is configured to generate the first gate control signal according to a corresponding start signal and a first clock signal. The phase difference between the two gate driving circuits in series is X gate driving circuits, and the phase difference between the two corresponding first clock signals is (X+1)H. In at least one of the sub-pixels, the effective level of the first gate control signal corresponding to the compensation transistor at least partially overlaps with the effective level of the second gate control signal corresponding to the data transistor. The effective level of the second gate control signal corresponding to the data transistor is located between the two first effective levels of the first clock signal applied by the gate driving circuit corresponding to the compensation transistor. The phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is greater than 0 and less than (X+1)H. X≥1, and H represents the unit time. X=1, the odd-numbered gate driving circuits are cascaded, and the even-numbered gate driving circuits are cascaded.

2. The display device according to claim 1, wherein The phase difference between the start signal corresponding to the nth gate driving circuit and the start signal corresponding to the (n+1)th gate driving circuit is 1H, and n is an odd number. The plurality of gate driving circuits are electrically connected to Y clock lines, and the Y clock lines are configured to transmit corresponding first clock signals to the plurality of gate driving circuits. Y=2(X+1).

3. The display device according to claim 1, wherein X=1, the Y clock lines include a first clock line, a second clock line, a third clock line and a fourth clock line.

4. The display device according to claim 3, wherein The first clock line transmits a corresponding first clock signal to the 4k+1th gate driving circuit, the second clock line transmits a corresponding first clock signal to the 4k+2th gate driving circuit, the third clock line transmits a corresponding first clock signal to the 4k+3th gate driving circuit, and the fourth clock line transmits a corresponding first clock signal to the 4k+4th gate driving circuit. k≥0. ​ 5. The display device according to any one of claims 1 to 4, characterized by Each of the gate drive circuits is configured to generate a plurality of the second gate control signals according to the corresponding start signal, the first clock signal and the second clock signal; Wherein, the first gate control signal and the second gate control signal corresponding to the same sub-pixel are generated by different levels of the gate drive circuit.

6. The display device according to claim 5, wherein Among the plurality of sub-pixels located in the mth row, the control end of the compensation transistor is electrically connected with the pth level of the gate drive circuit to receive the first gate control signal output by the pth level of the gate drive circuit; the control end of the data transistor is electrically connected with the p+1th level of the gate drive circuit to receive the second gate control signal output by the p+1th level of the gate drive circuit; wherein, m≥1, p≥1.

7. The display device according to claim 5, wherein The plurality of gate drive circuits are electrically connected with Z clock lines, and the Z clock lines are configured to transmit the corresponding second clock signals to the plurality of gate drive circuits; wherein, Z=2(X+1).

8. The display device according to claim 7, wherein X=1, the Z clock lines include a first clock line, a second clock line, a third clock line and a fourth clock line; Wherein, the third clock line transmits the corresponding second clock signal to the 4k+1th level of the gate drive circuit, the fourth clock line transmits the corresponding second clock signal to the 4k+2th level of the gate drive circuit, the first clock line transmits the corresponding second clock signal to the 4k+3th level of the gate drive circuit, and the second clock line transmits the corresponding second clock signal to the 4k+4th level of the gate drive circuit.

9. The display device according to claim 5, wherein Each of the gate drive circuits includes: A node control module electrically connected with a first node and a second node of the gate drive circuit of the current level, configured to control the signals transmitted to the first node and the second node according to the corresponding first clock signal and start signal; A first output module electrically connected with the first node, configured to output the first gate control signal according to the corresponding frequency division control signal and the signal of the first node; and A first frequency division module electrically connected with the first node, the second node and the first output module, configured to control the signal transmission between the first node and the first output module according to the corresponding frequency division control signal and the signal of the second node.

10. The display device according to claim 9, wherein At least one of the gate drive circuits includes: A second output module electrically connected with the first node and the second node, the second output module being configured to output the second gate control signal according to the corresponding second clock signal, the signals of the first node and the second node.

11. The display device according to claim 10, wherein The plurality of frequency division control lines are configured to transmit the frequency division control signals to the plurality of gate drive circuits to control the level of at least one of the plurality of second gate control signals; At least one of the gate drive circuits includes: A second frequency division module is electrically connected with the first node, the second node and the second output module, and is configured to control signal transmission between the first node and the corresponding second output module according to the corresponding frequency division control signal and the signal of the second node.

12. The display device of claim 11, wherein, The plurality of frequency division control lines include a first frequency division control line and a second frequency division control line. The first frequency division control line is electrically connected with the first frequency division module of the multi-stage gate drive circuit, and the second frequency division control line is electrically connected with the second frequency division module of the multi-stage gate drive circuit.

13. The display device of claim 1, wherein At least one of the sub-pixels includes a reset transistor, an input end of the reset transistor is electrically connected with a reset line, and an output end of the reset transistor is electrically connected with a control end of the driving transistor. In the same sub-pixel, an effective level of the first gate control signal received by the control end of the compensation transistor and an effective level of the third gate control signal received by the control end of the reset transistor partially coincide.

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