Semiconductor device

Abstract

A semiconductor device includes a substrate having a first surface, a first adhesive disposed on the first surface, and a first semiconductor chip disposed on the first adhesive. The semiconductor device further includes a first insulating member disposed on the first surface so as to be in contact with at least a portion of the first adhesive. An upper surface of the first insulating member is higher than or equal to an upper surface of the first adhesive in a first direction perpendicular to the first surface.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2024-070663, filed April 24, 2024, and U.S. Patent Application No. 18 / 820,120, filed August 29, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments described herein generally relate to a semiconductor device. BACKGROUND

[0004] Semiconductor packages in which semiconductor chips are disposed on a substrate using an adhesive are well known. However, occurrences of adhesive outflow from adhesive diffusion and adhesive bleed-out have been problematic. SUMMARY

[0005] Embodiments provide a semiconductor device capable of preventing adhesive bleed-out.

[0006] An embodiment provides,

[0007] A semiconductor device comprising:

[0008] a substrate having a first surface;

[0009] a first adhesive disposed on the first surface;

[0010] a first semiconductor chip disposed on the first adhesive;

[0011] a first insulating member disposed on the first surface so as to be in contact with at least a portion of the first adhesive, wherein

[0012] an upper surface of the first insulating member is higher than or equal to an upper surface of the first adhesive in a first direction perpendicular to the first surface.

[0013] An embodiment provides,

[0014] A semiconductor device comprising:

[0015] a substrate having a first surface and a second surface opposite to the first surface and including an opening on the first surface;

[0016] a first adhesive disposed in the opening such that at least a portion thereof is in contact with a side surface of the substrate in the opening; and

[0017] a first semiconductor chip disposed on the first adhesive, wherein

[0018] A depth of the opening in a first direction perpendicular to the first surface is equal to or greater than a thickness of the first adhesive in the first direction.

[0019] Further, an embodiment provides,

[0020] A semiconductor device includes:

[0021] a substrate having a first surface and a second surface opposite to the first surface;

[0022] a first adhesive disposed on the first surface;

[0023] a first semiconductor chip disposed on the first adhesive;

[0024] a first insulating member surrounding a periphery of the first adhesive and disposed on the first surface so as to be in contact with at least a portion of the first adhesive when viewed in a first direction perpendicular to the first surface;

[0025] a second adhesive in which the first semiconductor chip, the first adhesive, and the first insulating member are embedded;

[0026] a second semiconductor chip having a chip area greater than that of the first semiconductor chip and disposed on the first surface via the second adhesive; and

[0027] a second insulating member surrounding a periphery of the second adhesive and disposed on the first surface so as to be in contact with at least a portion of the second adhesive when viewed in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a cross-sectional view illustrating a configuration example of a semiconductor device according to a first embodiment.

[0029] Figure 2 is a plan view illustrating a configuration example of a semiconductor device according to the first embodiment.

[0030] Figure 3 is an enlarged cross-sectional view illustrating a vicinity of an insulating member of a semiconductor device according to the first embodiment.

[0031] Figure 4 is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0032] Figure 5 is a schematic cross-sectional view of a step in a method for manufacturing a semiconductor device according to the first embodiment.

[0033] Figure 6 is a schematic cross-sectional view of a step in a method for manufacturing a semiconductor device according to the first embodiment.

[0034] Figure 7 is a schematic cross-sectional view of a step in a method for manufacturing a semiconductor device according to the first embodiment.

[0035] Figure 8 is a schematic cross-sectional view of a step in a method for manufacturing a semiconductor device according to the first embodiment.

[0036] Figure 9 is a schematic cross-sectional view of a step in a method for manufacturing a semiconductor device according to the first embodiment.

[0037] Figure 10 is a schematic cross-sectional view of a step in a method for manufacturing a semiconductor device according to the first embodiment.

[0038] Figure 11 is a cross-sectional view illustrating a configuration example of a semiconductor device according to a first modification of the first embodiment.

[0039] Figure 12 is a cross-sectional view illustrating a configuration example of a semiconductor device according to a second modification of the first embodiment.

[0040] Figure 13 is a plan view illustrating a configuration example of a semiconductor device according to the second modification of the first embodiment.

[0041] Figure 14 is an enlarged cross-sectional view illustrating a vicinity of an insulating member of a semiconductor device according to the second modification of the first embodiment.

[0042] Figure 15 is a cross-sectional view illustrating a configuration example of a semiconductor device according to a third modification of the first embodiment.

[0043] Figure 16 is a plan view illustrating a configuration example of a semiconductor device according to the third modification of the first embodiment.

[0044] Figure 17 is an enlarged cross-sectional view illustrating a vicinity of an insulating member of a semiconductor device according to the third modification of the first embodiment.

[0045] Figure 18 is a cross-sectional view illustrating a configuration example of a semiconductor device according to the third modification of the first embodiment.

[0046] Figure 19is a plan view that illustrates a configuration example of a semiconductor device according to a third modification of the first embodiment.

[0047] Figure 20 is a cross-sectional view that illustrates a configuration example of a semiconductor device according to the second embodiment.

[0048] Figure 21 is a plan view that illustrates a configuration example of a semiconductor device according to the second embodiment.

[0049] Figure 22 is an enlarged cross-sectional view that illustrates a vicinity of a side surface inside an opening of a substrate according to the second embodiment.

[0050] Figure 23 is a cross-sectional view that illustrates a configuration example of a semiconductor device according to another modification.

[0051] Figure 24 is a cross-sectional view that illustrates a configuration example of a semiconductor device according to another modification. DETAILED DESCRIPTION

[0052] Embodiments provide a semiconductor device capable of preventing adhesive bleeding.

[0053] Generally, according to one embodiment, a semiconductor device includes a substrate having a first surface, a first adhesive disposed on the first surface, and a first semiconductor chip disposed on the first adhesive. The semiconductor device according to the embodiment further includes a first insulating member disposed on the first surface so as to be in contact with at least a portion of the first adhesive. An upper surface of the first insulating member is higher than or equal to an upper surface of the first adhesive in a first direction perpendicular to the first surface.

[0054] Hereinafter, embodiments will be described with reference to the drawings.

[0055] The drawings referred to hereinafter are schematic drawings, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like can differ from the actual situation. Furthermore, the drawings can include portions in which the dimensional relationship and the ratio differ from one another. In the following description, components having substantially the same function and configuration are given the same reference numerals. An alphabetical character or the like can be added to the reference numerals to distinguish elements having the same configuration from one another. In this specification, a step includes not only a single step but also a combination of a plurality of steps and a combination with other processes.

[0056] First, an X direction, a Y direction, and a Z direction are defined. The X direction and the Y direction are directions parallel to a first surface of a substrate, which will be described later. The Z direction is a direction intersecting (e.g., orthogonal to) the X direction and the Y direction. That is, the Z direction is a thickness direction of the adhesive and the insulating member, and is a direction perpendicular to the first surface of the substrate.

[0057] First embodiment

[0058] Figure 1 is a cross-sectional view illustrating a configuration example of the semiconductor device 100 according to the first embodiment. Figure 2 is a plan view illustrating a configuration example of the semiconductor device 100 according to the first embodiment. In Figure 2 , the illustration of the sealing resin 30 is omitted. As Figure 1 illustrated in

[0059] The substrate 10 includes the solder resist 11a and 11b, the core material 12, the wiring layers 13a and 13b, the vias 14, the pads 15, and the electrodes 18. The substrate 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a. The core material 12 has a third surface 12a and a fourth surface 12b opposite to the third surface 12a. For the core material 12, for example, an insulating material such as a glass epoxy resin is used. The substrate 10 can have a multilayer wiring structure formed by stacking a plurality of wiring layers and a plurality of insulating layers.

[0060] The solder resist 11a is disposed on the third surface 12a of the core material 12. The solder resist 11a covers the third surface 12a of the core material 12 except for a portion corresponding to the pads 15. The solder resist 11a is an example of a first insulating layer. The solder resist 11b is disposed on the fourth surface 12b. The solder resist 11b covers the fourth surface 12b of the core material 12 except for a portion corresponding to the electrodes 18. The solder resist 11b is an example of a second insulating layer. When it is not particularly necessary to distinguish the solder resists 11a and 11b, the solder resists 11a and 11b are described as a solder resist 11. The solder resist 11 is electrically insulating and protects the wiring layers 13a and 13b.

[0061] The wiring layer 13a is disposed on the third surface 12a. The wiring layer 13b is disposed on the fourth surface 12b. The wiring layers 13a and 13b are electrically connected by the vias 14. When it is not particularly necessary to distinguish the wiring layers 13a and 13b, the wiring layers 13a and 13b are described as a wiring layer 13.

[0062] A pad 15 is disposed on the third surface 12a of the core material 12. Each pad 15 is an example of a first electrode. The pad 15 contains an electrically conductive material, such as copper (Cu). The pad 15 can be part of the wiring layer 13a. A metal bump 40 is disposed on the second surface 10b of the substrate 10. The metal bump 40 is electrically connected to the wiring layer 13b through an electrode 18. The electrode 18 can be part of the wiring layer 13b. The metal bump 40 is made of an electrically conductive material, such as solder.

[0063] A semiconductor chip 21 is disposed on the first surface 10a with the adhesive 20 interposed therebetween. The semiconductor chip 21 is an example of a first semiconductor chip. The semiconductor chip 21 includes pads 22 on a peripheral edge portion of a front surface thereof. Each pad 22 is an example of a second electrode. The pad 15 is electrically connected with the pad 22 using an electrically conductive connection member 23, such as a wire bond. The pad 15 and the pad 22 are connected in a one-to-one manner. Each connection member 23 is an example of a first connection member.

[0064] The semiconductor chip 21 can be, for example, a semiconductor chip such as a NAND flash memory, but is not limited to the semiconductor chip. For example, any semiconductor chip can be used, such as a memory element (e.g., a dynamic random access memory (DRAM)), an operation element (e.g., a microprocessor), or a signal processing element. The number of semiconductor chips 21 can be one, or a plurality of semiconductor chips 21 can be stacked.

[0065] The adhesive 20 is a thermosetting resin. For example, the adhesive 20 is an epoxy resin, a polyimide resin, an acrylic resin, or a mixture thereof. For example, as the adhesive 20, a film adhesive is used, such as a die attach film (DAF), a film on wire (FOW) in which a connection member can be embedded, or a film on device (FOD) in which a semiconductor chip can be embedded. In the first embodiment, a case in which the adhesive 20 is a DAF will be described. The adhesive 20 is an example of a first adhesive.

[0066] When the semiconductor chip 21 is disposed on the first surface 10a, an outer edge of the adhesive 20 can be located outside an outer edge of the semiconductor chip 21. In other words, as illustrated in FIG. 1B, when viewed in the Z direction, the size of the outer shape of the adhesive 20 is larger than the size of the outer shape of the semiconductor chip 21. Figure 2 The ease of the bleeding tends to depend on the thickness and the modulus of elasticity of the adhesive.

[0067] Returning to Figure 1As described above, the sealing resin 30 seals the adhesive 20, the semiconductor chip 21, the connection member 23, the solder resist 50, and the first surface 10a of the substrate 10. As the sealing resin 30, a thermosetting resin such as an epoxy resin is used, for example.

[0068] The solder resist 50 is disposed on the first surface 10a of the substrate 10 so as to be in contact with at least a portion of the adhesive 20. The solder resist 50 is an example of a first insulating member. The solder resist 50 is disposed so as to form a gap G1 between the solder resist 50 and the semiconductor chip 21 in the X direction or the Y direction. Figure 1 and 2 , the solder resist 50 surrounds the entire periphery of the adhesive 20 when viewed in the Z direction. That is, the solder resist 50 is disposed so that gaps G1 are formed between the solder resist 50 and all four side surfaces of the semiconductor chip 21. However, the solder resist 50 may not be disposed so as to surround the entire periphery of the adhesive 20. Therefore, the solder resist 50 may be disposed in at least a portion of the periphery of the adhesive 20 when viewed in the Z direction.

[0069] Figure 3 is an enlarged cross-sectional view illustrating a portion adjacent to the solder resist 50 of the semiconductor device 100. The thickness T1 of the adhesive 20 in the Z direction is less than (eg Figure 3 ) or equal to the thickness T2 of the solder resist 50 in the Z direction. That is, the thickness T2 of the solder resist 50 in the Z direction is greater than (as shown in FIG. Figure 3 ) or equal to the thickness T1 of the adhesive 20 in the Z direction. In other words, the upper surface of the solder resist 50 is higher than (as shown in FIG. Figure 3 ) or equal to the upper surface of the adhesive 20.

[0070] Method for manufacturing a semiconductor device according to the first embodiment

[0071] Figure 4 is a flowchart for describing a manufacturing process of the semiconductor device 100 according to the first embodiment. Figures 5 to 10 Each of them is a cross-sectional view illustrating an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during manufacturing. Figure 4 An example of a manufacturing process of the semiconductor device 100 according to the first embodiment will be described.

[0072] Step S1: a step of preparing a substrate.

[0073] First, a through-hole is formed in the core material 12 using a drill or the like. Next, the via 14 is formed by embedding copper or the like on the inside of the through-hole. The via 14 can be formed by performing plating on the side surfaces of the through-hole with copper or the like. Next, the wiring layer 13, the pad 15, and the electrode 18 are formed by a known pattern forming method. Next, the solder resist is applied to each of the third surface 12a and the fourth surface 12b of the core material 12. Next, a mask is formed on the solder resist applied to each of the third surface 12a and the fourth surface 12b. The mask has openings at positions corresponding to the pad 15 and the electrode 18. Next, etching is performed using the mask to form the solder resists 11a and 11b. By this etching, the pad 15 and the electrode 18 are exposed to the outside. By the steps described above, the substrate 10 as Figure 5 illustrated in FIG. 1 is manufactured.

[0074] Step S2: A step of placing an insulating member on a substrate

[0075] As Figure 6 illustrated in FIG. 2, the solder resist 50 is disposed on the first surface 10a of the substrate 10 using, for example, a screen printing method. The solder resist 50 can be formed by first forming a mask at positions corresponding to the solder resist 50 after the solder resist 50 is applied to the third surface 12a of the core material 12, and then performing etching using the mask. In this case, the solder resist 50 is part of the solder resist 11a.

[0076] Step S3: A step of placing a semiconductor chip on a substrate

[0077] As Figure 7 illustrated in FIG. 3, the semiconductor chip 21 having the adhesive 20 attached to the back surface thereof is disposed on the first surface 10a of the substrate 10. The solder resist 50 is disposed so that a gap G1 is formed between the solder resist 50 and the semiconductor chip 21 in the X direction or the Y direction. In this case, when the semiconductor chip 21 is disposed on the first surface 10a, the adhesive 20 can ooze out due to stress. Although Figure 7 The case where the adhesive 20 and the solder resist 50 do not come into contact with each other is illustrated, but the adhesive 20 and the solder resist 50 can come into contact with each other due to oozing.

[0078] Step S4: A baking treatment step

[0079] As Figure 8 illustrated in FIG. 4, a baking treatment is performed to remove moisture and volatile organic substances attached to the substrate 10. The adhesive 20 can further ooze out due to the baking treatment. In Figure 8 , the solder resist 50 comes into contact with at least a part of the adhesive 20.

[0080] Step S5: a step of electrically connecting the semiconductor chip and the substrate

[0081] As Figure 9 illustrated in FIG. 1, the pad 15 formed on the third surface 12a of the core material 12 is electrically connected to the pad 22 formed on the outer peripheral portion of the front surface of the semiconductor chip 21 through the connection member 23.

[0082] Step S6: a sealing step

[0083] As Figure 10 illustrated in FIG. 2, the entire surface of the first surface 10a of the substrate 10 is covered with the sealing resin 30 so that the adhesive 20, the semiconductor chip 21, the connection member 23, and the solder resist 50 are all covered. The sealing resin 30 is cured by a known method such as a drying step, a heat curing step, or an ultraviolet curing step.

[0084] Step S7: a step of forming a metal bump on the substrate

[0085] First, the metal ball is mounted on the electrode 18 to which the solder flux is applied. Next, the metal ball is placed in a reflow furnace to be melted and joined to the electrode 18. Thereafter, cleaning is performed to remove the residue of the solder flux. In this way, the metal bump 40 is formed on the second surface 10b of the substrate 10. Through the above steps, the semiconductor device 100 according to the first embodiment as illustrated in FIG. 3 is manufactured. Figure 1

[0086] Effects of the first embodiment

[0087] In a temperature cycle test (TCT), stress is generated due to the difference in the coefficient of thermal expansion between the semiconductor chip 21 and the substrate 10. In this case, if the adhesive 20 is too thin, there is a concern that the semiconductor chip 21 can be detached from the substrate 10 because the adhesive 20 cannot sufficiently absorb the stress. According to the first embodiment, the solder resist 50 is disposed on the first surface 10a of the substrate 10 so as to be in contact with at least a portion of the adhesive 20. Therefore, the adhesive 20 can be prevented from becoming thin due to bleeding. Thus, the stress between the semiconductor chip 21 and the substrate 10 can be alleviated.

[0088] Further, according to the first embodiment, since the thickness of the solder resist 50 in the Z direction is greater than or equal to the thickness of the adhesive 20 in the Z direction, it is possible to prevent the adhesive 20 from bleeding over the solder resist 50. Further, according to the first embodiment, the solder resist 50 surrounds the entire periphery of the adhesive 20 when viewed in the Z direction, and it is possible to more reliably prevent the adhesive 20 from bleeding.

[0089] ​Furthermore, if flatness of the front surface of the semiconductor chip 21 on which the pad 22 is formed is damaged due to bleeding of the adhesive 20, wire bonding cannot be performed under optimal conditions, and thus, there is a concern that bonding strength between the pad 22 and the connection member 23 cannot be ensured. According to the first embodiment, since the thickness T1 of the adhesive 20 in the Z direction can be prevented from changing by preventing bleeding of the adhesive 20 with the solder resist 50, step S5 (wire bonding) can be performed under optimal conditions. Thus, bonding strength between the pad 22 and the connection member 23 can be improved.

[0090] First modification

[0091] Figure 11 is a cross-sectional view illustrating a configuration example of a semiconductor device 200 according to a first modification of the first embodiment. In the following, the same components as in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0092] The first modification differs from the first embodiment in a material of the insulating member. That is, the first modification differs from the first embodiment in that the first modification includes an epoxy ink 60. The epoxy ink 60 is an example of the insulating member. In the first modification, the epoxy ink 60 is distributed on the first surface 10a using, for example, a screen printing method. In this way, it is possible to prevent bleeding of the adhesive 20 even if the insulating member is made of a material different from the solder resist 11. The basic manufacturing method of the first modification is the same as that of the first embodiment, and according to the first modification, the same or similar effects as in the first embodiment described above can be obtained.

[0093] Second modification

[0094] Figure 12 is a cross-sectional view illustrating a configuration example of a semiconductor device 300 according to a second modification of the first embodiment. Figure 13 is a plan view illustrating a configuration example of the semiconductor device 300 according to the second modification of the first embodiment. In Figure 13 , the illustration of the adhesive 20, the semiconductor chip 21, the connection member 23, and the sealing resin 30 is omitted. In the following, the same components as in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0095] The second modification differs from the first embodiment in that the semiconductor device 300 further includes an adhesive 320, a semiconductor chip 321, a connection member 323, and a solder resist 350. In the first embodiment, the case where the adhesive 20 is a DAF is described, but in the second modification, the adhesive 20 is an FOD in which the semiconductor chip 321 is embedded. More specifically, the adhesive 20 covers the pads 315, the adhesive 320, the semiconductor chip 321, the connection member 323, and the solder resist 350.

[0096] The first surface 10a includes a first region 10a1 corresponding to the outer shape of the adhesive 20 and a second region 10a2 different from the first region 10a1 when viewed in the Z direction. The first region 10a1 is an example of a first region, and the second region 10a2 is an example of a second region.

[0097] The pads 315 are disposed in a region corresponding to the first region 10a1 of the third surface 12a. Each pad 315 is an example of a third electrode. The pads 315 contain an electrically conductive material, such as copper (Cu). The pads 315 can be part of the wiring layer 13a.

[0098] The semiconductor chip 321 is disposed on the first region 10a1 of the first surface 10a with the adhesive 320 interposed therebetween. The semiconductor chip 321 is a controller, for example. The semiconductor chip 321 has a chip area smaller than that of the semiconductor chip 21. That is, the semiconductor chip 21 has a chip area larger than that of the semiconductor chip 321. The semiconductor chip 321 is an example of a second semiconductor chip. The semiconductor chip 321 has pads 322 on a peripheral portion of a front surface thereof. Each pad 322 is an example of a fourth electrode. The pads 315 and the pads 322 are electrically connected using the connection member 323. Each connection member 323 is an example of a second connection member. The pads 315 and the pads 322 are connected in a one-to-one manner. The semiconductor chip 321 can be mounted on the first region 10a1 of the first surface 10a in a flip-chip manner.

[0099] The adhesive 320 as a DAF is thinner than the adhesive 20 as an FOD. That is, the thickness T1 of the adhesive 20 in the Z direction is greater than the thickness T3 of the adhesive 320 in the Z direction, which will be described later. The adhesive 320 is an example of a second adhesive. As Figure 13 As illustrated in FIG. 3B, the size of the outer shape of the adhesive 320 is greater than the size of the outer shape of the semiconductor chip 321 when viewed in the Z direction.

[0100] Returning to Figure 12For the sake of explanation, the solder resist 350 is disposed in the first region 10a1 so as to be in contact with at least a portion of the adhesive 320. The solder resist 350 is an example of a second insulating member. The solder resist 350 is disposed so that a gap G2 is formed between the solder resist 350 and the semiconductor chip 321 in the X direction or the Y direction. In Figure 12 and 13 In the example illustrated in

[0101] Figure 14 is an enlarged cross-sectional view illustrating a vicinity of the solder resist 350 of the semiconductor device 300. The thickness T3 of the adhesive 320 in the Z direction is smaller than (as illustrated in Figure 14 ) or equal to the thickness T4 of the solder resist 350 in the Z direction. That is, the thickness T4 of the solder resist 350 in the Z direction is larger than (as illustrated in Figure 14 ) or equal to the thickness T3 of the adhesive 320 in the Z direction. In other words, the upper surface of the solder resist 350 is higher than (as illustrated in Figure 14 ) or equal to the upper surface of the adhesive 320.

[0102] The basic manufacturing method of the second modification is the same as that of the first embodiment, and according to the second modification, the same or similar effects to those described above in the first embodiment can be obtained. Further, in the second modification, since the semiconductor chip 321 is embedded in the adhesive 20, it is possible to reduce the size of the semiconductor device 300 in the Z direction.

[0103] According to the second modification, the adhesive 20 having a thickness capable of embedding the semiconductor chip 321 can be bulged in the Z direction due to bleeding. This bulging of the adhesive 20 can create a hole when another semiconductor chip is stacked on the semiconductor chip 21. According to the second modification, the solder resist 50 is disposed on the first surface 10a of the substrate 10 so as to be in contact with at least a portion of the adhesive 20. Therefore, even if the adhesive 20 bleeds, it is possible to prevent the adhesive 20 from being bulged in the Z direction.

[0104] Third modification

[0105] Figure 15 is a cross-sectional view illustrating a configuration example of a semiconductor device 400 according to a third modification of the first embodiment. Figure 16is a plan view that illustrates a configuration example of a semiconductor device 400 according to a third modification of the first embodiment. In Figure 16 In the third modification, the illustration of the adhesives 20b and 20c, the semiconductor chips 21b and 21c, the connection members 23 and 423, and the sealing resin 30 is omitted. Hereinafter, the same components as in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0106] In the first embodiment, the case where one semiconductor chip 21 is disposed on the first surface 10a is described, but in the third modification, as illustrated in Figure 15 In the third modification, the case where one semiconductor chip 21 is disposed on the first surface 10a is described, but in the third modification, as illustrated in

[0107] The semiconductor chip 21a is disposed in the first region 10al of the first surface 10a with the adhesive 20a interposed therebetween. The semiconductor chip 21b is disposed on the semiconductor chip 21a with the adhesive 20b interposed therebetween so as not to cover the pad 22a, in which the semiconductor chip 21b is offset in the X direction with respect to the semiconductor chip 21a. The semiconductor chip 21c is disposed on the semiconductor chip 21b with the adhesive 20c interposed therebetween so as not to cover the pad 22b, in which the semiconductor chip 21c is offset in the X direction with respect to the semiconductor chip 21b.

[0108] In the first embodiment, the case where the adhesive 20 is a DAF is described, but in the third modification, the adhesive 20a is a FOW in which at least a part of the connection member 423 is embedded. More specifically, the adhesive 20a covers the pad 415 and at least a part of one connection member 423. The adhesives 20b and 20c are DAFs.

[0109] The third modification is further different from the first embodiment in that the semiconductor device 400 further includes an adhesive 420, a semiconductor chip 421, a connection member 423, and a solder resist 450.

[0110] The pad 415 is disposed in a region corresponding to the first region 10al of the third surface 12a. The pad 415 is an example of a third electrode. The pad 415 contains an electrically conductive material, such as copper (Cu). The pad 415 can be a part of the wiring layer 13a.

[0111] A semiconductor chip 421 is disposed in a second region 10a2 of the first surface 10a different from the first region 10a1 with the adhesive 420 interposed therebetween. The semiconductor chip 421 is, for example, a controller. The semiconductor chip 421 is an example of a second semiconductor chip. The semiconductor chip 421 has pads 422 on a peripheral edge portion of a front surface thereof. Each pad 422 is an example of a fourth electrode. The pads 15, 415 and the pads 422 are electrically connected with connection members 423. Each connection member 423 is an example of a second connection member. The pads 15, 415 and the pads 422 are connected in a one-to-one manner.

[0112] The adhesive 420 as the DAF is thinner than the adhesive 20a as the FOW. That is, a thickness T1 of the adhesive 20a in the Z direction is greater than a thickness T5 of the adhesive 420 in the Z direction, which will be described later. The adhesive 420 is an example of a second adhesive. As Figure 16 Illustrated in FIG. 6A, a size of an outer shape of the adhesive 420 is greater than a size of an outer shape of the semiconductor chip 421 when viewed in the Z direction.

[0113] Figure 17 is an enlarged cross-sectional view illustrating a vicinity of the solder resist 450 of the semiconductor device 400. A thickness T5 of the adhesive 420 in the Z direction is less than (as Figure 17 illustrated in FIG. 6A) or equal to a thickness T6 of the solder resist 450 in the Z direction. That is, the thickness T6 of the solder resist 450 in the Z direction is greater than (as Figure 17 illustrated in FIG. 6A) or equal to the thickness T5 of the adhesive 420 in the Z direction. In other words, an upper surface of the solder resist 450 is higher than (as Figure 17 illustrated in FIG. 6A) or equal to an upper surface of the adhesive 420.

[0114] Returning to the description of Figure 15 , the solder resist 450 is disposed in the second region 10a2 of the first surface 10a so as to be in contact with at least a portion of the adhesive 420. The solder resist 450 is an example of a second insulating member. The solder resist 450 is disposed so that a gap G3 is formed between the solder resist 450 and the semiconductor chip 421 in the X direction or the Y direction. In Figure 15 and 16 the example illustrated in FIG. 6A, the solder resist 450 surrounds the entire periphery of the adhesive 420 when viewed in the Z direction. That is, the solder resist 450 is disposed so that a gap G3 is formed between the solder resist 450 and all four side surfaces of the semiconductor chip 421. However, as Figure 18 and 19 illustrated in FIG. 6B, the solder resist 450 can not be disposed so as to surround the entire periphery of the adhesive 420. Thus, the solder resist 450 can be disposed in at least a portion of the periphery of the adhesive 420 when viewed in the Z direction. AsFigure 19 As illustrated in FIG. 14, the solder resist 450 is disposed in contact with one side of the frame-shaped solder resist 50. In this way, the entire periphery of the adhesive 420 can be surrounded by the solder resist 50 and 450.

[0115] The basic manufacturing method of the third modification is the same as that of the first embodiment, and according to the third modification, the same or similar effects to those described above in the first embodiment can be obtained.

[0116] According to the third modification, the semiconductor chip 421 is disposed in a second region 10a2 different from a first region 10a1 of the first surface 10a in which the adhesive 20a is disposed. In this case, since at least a part of one connection member 423 is embedded in the adhesive 20a, it is possible to reduce the size of the semiconductor device 400 in the X direction or the Y direction.

[0117] Second embodiment

[0118] Figure 20 FIG. 15 is a cross-sectional view illustrating a configuration example of a semiconductor device 500 according to a second embodiment. Figure 21 FIG. 16 is a plan view illustrating the configuration example of the semiconductor device 500 according to the second embodiment. In Figure 21 In FIG. 16, the illustration of the sealing resin 30 is omitted. Hereinafter, the same components as in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0119] The second embodiment differs from the first embodiment in that the substrate 10' has the opening 16 and no insulating member (e.g., the solder resist 50) is disposed on the first surface 10a of the substrate 10'.

[0120] The solder resist 11a has a first portion 11a1 disposed in the opening 16 and a second portion 11a2 disposed outside the opening 16. The shape of the solder resist 11a corresponds to the shape of the opening 16.

[0121] The semiconductor chip 21 is disposed in the opening 16 of the substrate 10', with the adhesive 20 interposed therebetween. The semiconductor chip 21 is disposed in the opening 16 with a gap G4 formed between the semiconductor chip 21 and the side surface 19 of the substrate 10' in the opening 16. At least a part of the adhesive 20 is in contact with the side surface 19 of the substrate 10' in the opening 16. As Figure 21 As illustrated in FIG. 16, the size of the outer shape of the opening 16 is larger than the size of the outer shape of the semiconductor chip 21 when viewed in the Z direction.

[0122] Figure 22 FIG. 17 is an enlarged cross-sectional view illustrating a vicinity of the side surface 19 of the substrate 10' in the opening 16.Figure 22 is also Figure 20 an enlarged view of the dashed box D in FIG. 13B. The second portion 11a2 of the solder resist 11a has a thickness T7 in the Z-direction that is greater than (as illustrated in FIG. 13B) or equal to the thickness T1 of the adhesive 20 in the Z-direction. That is, the depth of the opening 16 in the Z-direction is greater than (as illustrated in FIG. 13B) or equal to the thickness T1 of the adhesive 20 in the Z-direction. Figure 22 Figure 22

[0123] The basic manufacturing method of the second embodiment is the same as that of the first embodiment, and according to the second embodiment, the same or similar effects to those described above in the first embodiment can be obtained. In particular, since the second embodiment has a configuration in which no insulating member is provided, it is possible to reduce the cost related to the material of the insulating member.

[0124] Other modifications

[0125] The embodiments and modifications described above can be combined with each other as much as possible. For example, as illustrated in FIG. 13B, the first embodiment can be combined with the second embodiment. Furthermore, as illustrated in FIG. 13C, the first modification of the first embodiment can be combined with the second embodiment. Figure 23 Figure 24

[0126] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein can be made without departing from the spirit of the disclosure. The accompanying claims and therein equivalent are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.​​​​

Claims

1. A semiconductor device comprising: a substrate having a first surface; a first adhesive disposed on the first surface; a first semiconductor chip disposed on the first adhesive; a first insulating member disposed on the first surface so as to be in contact with at least a portion of the first adhesive, wherein an upper surface of the first insulating member is higher than or equal to an upper surface of the first adhesive in a first direction perpendicular to the first surface.

2. The semiconductor device according to claim 1, further comprising: a sealing resin disposed on the first surface and covering the first semiconductor chip, wherein the first insulating member is disposed so that a gap is formed between the first insulating member and the first semiconductor chip in a second direction parallel to the first surface, and the gap is filled with the sealing resin.

3. The semiconductor device according to claim 1, wherein the first insulating member surrounds an entire periphery of the first adhesive when viewed in the first direction.

4. The semiconductor device according to claim 1, wherein an outer shape of the first adhesive is larger in size than an outer shape of the first semiconductor chip when viewed in the first direction.

5. The semiconductor device according to claim 1, wherein the substrate includes a first electrode on the first surface, the first semiconductor chip includes a second electrode on an outer peripheral portion of a front surface thereof, and the semiconductor device further comprises a first connecting member electrically connecting the first electrode and the second electrode.

6. The semiconductor device according to claim 5, wherein the substrate includes a third electrode in a first region in which the first adhesive is disposed, the semiconductor device further comprises a second adhesive disposed in a second region different from the first region, a second semiconductor chip disposed on the second adhesive in the second region and including a fourth electrode on an outer peripheral portion of a front surface thereof, a second insulating member disposed in the second region so as to be in contact with at least a portion of the second adhesive, and a second connecting member electrically connecting the third electrode and the fourth electrode, and at least a portion of the second connecting member is embedded in the first adhesive.

7. The semiconductor device according to claim 1, further comprising: a second adhesive disposed on the first surface; a second semiconductor chip disposed on the second adhesive; and a second insulating member disposed on the first surface so as to be in contact with at least a portion of the second adhesive, wherein a thickness of the first adhesive in the first direction is greater than a thickness of the second adhesive in the first direction, and the first adhesive is embedded with the second semiconductor chip, the second adhesive, and the second insulating member.

8. The semiconductor device according to claim 7, wherein a thickness of the second insulating member in the first direction is greater than or equal to a thickness of the second adhesive in the first direction.

9. The semiconductor device according to claim 1, wherein ​ The substrate has a second surface opposite the first surface, and further includes a first insulating layer on the first surface and a second insulating layer on the second surface.

10. The semiconductor device according to claim 9, wherein The first insulating member is made of the same material as the first and second insulating layers.

11. The semiconductor device according to claim 9, wherein The first insulating member is made of a material different from that of the first and second insulating layers.

12. A semiconductor device comprising: a substrate having a first surface and a second surface opposite the first surface and including an opening on the first surface; a first adhesive disposed in the opening such that at least a portion thereof is in contact with a side surface of the substrate in the opening; and a first semiconductor chip disposed on the first adhesive, wherein a depth of the opening in a first direction perpendicular to the first surface is equal to or greater than a thickness of the first adhesive in the first direction.

13. The semiconductor device according to claim 12, wherein the substrate further includes a first insulating layer on the first surface and a second insulating layer on the second surface, and the first insulating layer further includes a first portion disposed in the opening and a second portion disposed outside the opening.

14. The semiconductor device according to claim 12, wherein an outer shape of the opening is larger in size than an outer shape of the first semiconductor chip when viewed in the first direction.

15. The semiconductor device according to claim 12, wherein the substrate includes a first electrode on the first surface, the first semiconductor chip includes a second electrode on a peripheral edge portion of a front surface thereof, and the semiconductor device further comprises a first connecting member electrically connecting the first electrode and the second electrode, and a sealing resin disposed on the first surface and covering the first semiconductor chip, the first adhesive, and the first connecting member.

16. A semiconductor device comprising: a substrate having a first surface and a second surface opposite the first surface; a first adhesive disposed on the first surface; a first semiconductor chip disposed on the first adhesive; a first insulating member surrounding a periphery of the first adhesive and disposed on the first surface so as to be in contact with at least a portion of the first adhesive when viewed in a first direction perpendicular to the first surface; a second adhesive in which the first semiconductor chip, the first adhesive, and the first insulating member are embedded; a second semiconductor chip having a chip area greater than that of the first semiconductor chip and disposed on the first surface via the second adhesive; and a second insulating member surrounding a periphery of the second adhesive and disposed on the first surface so as to be in contact with at least a portion of the second adhesive when viewed in the first direction.

17. The semiconductor device according to claim 16, wherein the first insulating member is disposed so that a gap is formed between the first insulating member and the first semiconductor chip in a second direction parallel to the first surface, and the second insulating member is disposed so that a gap is formed between the second insulating member and the second semiconductor chip in the second direction.

18. The semiconductor device according to claim 16, wherein the substrate further includes a first insulating layer on the first surface and a second insulating layer on the second surface, and the first and second insulating members are made of the same material as the first and second insulating layers.

19. The semiconductor device according to claim 16, wherein the substrate further includes a first insulating layer on the first surface and a second insulating layer on the second surface, and the first and second insulating members are made of a different material from that of the first and second insulating layers.

20. The semiconductor device according to claim 16, wherein an outer shape of the first adhesive is larger in size than an outer shape of the first semiconductor chip when viewed in the first direction, and an outer shape of the second adhesive is larger in size than an outer shape of the second semiconductor chip when viewed in the first direction.

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