A UART fractional correction circuit and correction method

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a UART decimal correction circuit and a correction method. The UART decimal correction circuit comprises a frequency division coefficient preloading circuit, an integer frequency division up counter, a decimal correction down counter, and a decimal correction algorithm circuit. The decimal correction algorithm circuit is used for inputting a count value cnt_i[9:0] and a count value cnt_f[3:0], determining a decimal correction sampling point through a shift, negation and comparison mode, and outputting a pulse signal reload to the integer frequency division up counter, the decimal correction down counter and a D flip-flop. When the pulse signal reload is valid, it is determined whether the integer frequency division up counter needs to be added by 1 and whether the decimal correction down counter needs to be subtracted by 1. The D flip-flop is used. The application determines the decimal correction sampling point through the shift, negation and comparison algorithm, so that a more accurate baud rate is realized with less logic.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a UART decimal correction circuit and a correction method. BACKGROUND

[0002] In the prior art, the generation of a UART baud rate usually divides 1 bit of data into 16 sampling points, and samples at the three middle sampling points of the 1 bit of data, i.e., 7, 8 and 9. Different baud rates may have decimal parts according to the baud rate generation formula. The occurrence of the decimal part will cause a relatively large baud rate error, and therefore the allocation of the decimal part is extremely important. A common method is to determine the sampling points to be allocated and the number of sampling points according to the value of the decimal part, and then allocate symmetrically from both sides to the middle. This method can effectively solve the baud rate error problem of both sides of communication. However, the patent with the publication number CN114138053A, a baud rate generator, only explains that the decimal frequency division value is allocated from two regions, one region starts from the maximum sampling bit, and the other region starts from the minimum sampling bit, and is symmetrically distributed to the middle, but does not explain how the allocated sampling points are determined. The patent with the publication number CN117792344A, a UART sampling pulse generation circuit and method with a decimal frequency division function, only uses a lookup table allocation method for decimal frequency division processing, which can determine the decimal frequency division value sampling points, but the introduction of the lookup table module also brings a large overhead to the circuit.

[0003] Therefore, in the implementation of the determination and allocation method of the decimal correction sampling points in the above two prior art patent solutions, a large amount of internal logic circuit is consumed. SUMMARY

[0004] The application aims to provide a UART decimal correction circuit and a correction method. The application proposes a shift, negation and comparison algorithm to generate a more accurate baud rate with fewer logic units.

[0005] To solve the above technical problems, the application provides a UART decimal correction circuit, which comprises:

[0006] A frequency division coefficient preloading circuit is configured to load an integer frequency division value UARTDBD[13:4] and a decimal frequency division value Fraction[3:0] of an output frequency division coefficient according to a write-in value of a baud rate register UARTBRR1-UARTBRR2;

[0007] An integer frequency division upward counter is configured to input the integer frequency division value UARTDBD[13:4] and output a count value cnt_i[9:0];

[0008] Fraction[3:0] and outputs count value cnt_f[3:0];

[0009] Fraction[3:0] and outputs count value cnt_f[3:0];

[0010] D flip-flop, which inputs pulse signal reload at D terminal, system clock fper at clock terminal and outputs the clock baud_clk generated by correction at Q terminal.

[0011] Preferably, the frequency division coefficient preloading circuit, the integer frequency division up counter and the fractional correction down counter further comprise high active system reset signal rst_h and system clock fper.

[0012] Preferably, the integer frequency division value UARTDBD[13:4] is composed of high 2-bit write value UARTBRR2[5:4] of baud rate register UARTBRR2 and full 8-bit write value UARTBRR1[7:0] of baud rate register UARTBRR1.

[0013] Preferably, the fractional frequency division value Fraction[3:0] is composed of low 4-bit write value UARTBRR2[3:0] of baud rate register UARTBRR2.

[0014] Preferably, the integer frequency division up counter is a 10-bit counter, which can realize integer frequency division by adding current value to full 1, i.e. 10’h3FF.

[0015] Preferably, the fractional correction down counter is a 4-bit counter, whose default value is 4’hF, which is reduced by 1 each time until it is 0, and which is corrected according to fractional frequency division value Fraction[3:0] each time, and the correction is performed for 16 times.

[0016] Preferably, when the fractional correction algorithm circuit corrects the fractional part, it includes the following correction methods: taking the way of average distribution from both sides to the middle, and making different judgments according to whether the fractional part is odd or even;

[0017] If the decimal part is even, the remainder in the baud rate register UARTBRR2 is right shifted by one bit to determine one of the modified sampling points, and the value is negated to get the other modified sampling point;

[0018] If the decimal part is odd, the remainder in the baud rate register UARTBRR2 is added by 1 to make it even, and then right shifted by one bit to determine one of the modified sampling points, and the value is negated and added by 1 to get the other modified sampling point;

[0019] If the decimal part is 0, no modification is needed for any sampling point;

[0020] If the decimal part is F, it is first complemented to get 4'h8, which is a sampling point that needs no modification, and all other values are sampling points that need modification.

[0021] Preferably, the clock baud_clk generated by the modification is the clock of the receiver; and the clock baud_clk generated by each modification is divided by 16 to get the sending clock.

[0022] Preferably, the baud rate generation formula is: ; wherein UARTDBD represents the integer division value, and Fraction represents the decimal division value.

[0023] The application also provides a UART decimal modification method, which uses the UART decimal modification circuit as described above, and comprises the following steps:

[0024] It is judged whether the remainder part of the division coefficient is 0; if the remainder part is 0, the integer division coefficient is loaded; if the remainder part is not 0, it is judged whether the remainder part is 4'hF;

[0025] If the remainder part is 4'hF, the value is negated and added by 1, and it is judged whether the value is equal to the decimal modification down counter; if the value is equal to the decimal modification down counter, the integer division coefficient is loaded; if the value is not equal to the decimal modification down counter, the integer division coefficient added by 1 is loaded;

[0026] If the remainder part is not 4'hF, it is judged whether the remainder part is odd; if the remainder part is odd, the value is added by 1 and right shifted by one bit, and it is judged whether the value is greater than the decimal modification down counter; if the value is greater than the decimal modification down counter, the integer division coefficient added by 1 is loaded; if the value is not greater than the decimal modification down counter, the value is negated and added by 1, and it is judged whether the value is less than the decimal modification down counter; if the value is less than the decimal modification down counter, the integer division coefficient is loaded; if the value is not less than the decimal modification down counter, the integer division coefficient is loaded;

[0027] If the remainder part is not an odd number, then right shift one bit, judge whether the value is greater than the decimal correction down counter, if the value is greater than the decimal correction down counter, then load the integer frequency division coefficient plus 1, if the value is not greater than the decimal correction down counter, then take the inverse, judge whether the value is less than the decimal correction down counter, if the value is less than the decimal correction down counter, then load the integer frequency division coefficient plus 1, if the value is not less than the decimal correction down counter, then load the integer frequency division coefficient.

[0028] Compared with the prior art, the present application has the following beneficial effects:

[0029] The application discloses a correction circuit and method for a decimal frequency division value in a UART baud rate generation process, and specifically comprises a frequency division coefficient preloading circuit, a 10bit integer frequency division up counter, a 4bit decimal frequency division down counter and a decimal correction algorithm circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a principle block diagram of a UART decimal correction circuit provided by the application.

[0031] Figure 2 is an algorithm flowchart of a 4'h8 correction sampling point provided by the application.

[0032] Figure 3 is an algorithm flowchart of a 4'hA correction sampling point provided by the application.

[0033] Figure 4 is an algorithm flowchart of a 4'h5 correction sampling point provided by the application.

[0034] Figure 5 is an algorithm flowchart of a 4'h9 correction sampling point provided by the application.

[0035] Figure 6 is an algorithm flowchart of a 4'hF correction sampling point provided by the application.

[0036] Figure 7 is a flowchart of a UART decimal correction method provided by the application.

[0037] Figure 8 is an odd number correction timing diagram provided by the application.

[0038] Figure 9 is an even number correction timing diagram provided by the application. DETAILED DESCRIPTION

[0039] The application will be described in further detail below with reference to the drawings and specific embodiments. The advantages and features of the application will be more apparent from the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of the application.

[0040] As shown in Figure 1 The embodiments of the application specifically provide a UART decimal correction circuit, comprising:

[0041] A frequency division coefficient preloading circuit, which loads integer frequency division value UARTDBD[13:4] and decimal frequency division value Fraction[3:0] of the output frequency division coefficient according to the write-in value of baud rate register UARTBRR1~UARTBRR2;

[0042] An integer frequency division up counter, which inputs the integer frequency division value UARTDBD[13:4] and outputs count value cnt_i[9:0];

[0043] A decimal correction down counter, which inputs the decimal frequency division value Fraction[3:0] and outputs count value cnt_f[3:0];

[0044] A decimal correction algorithm circuit, which inputs count value cnt_i[9:0] and count value cnt_f[3:0], determines the decimal correction sampling point by means of shifting, negating and comparing internally, and outputs pulse signal reload to the integer frequency division up counter, the decimal correction down counter and the D flip-flop; and when the pulse signal reload is valid, it determines whether the integer frequency division up counter needs to be added by 1 or not and whether the decimal correction down counter needs to be subtracted by 1 or not;

[0045] A D flip-flop, which inputs pulse signal reload at the D end, inputs system clock fper at the clock end, and outputs the corrected clock baud_clk at the Q end.

[0046] The frequency division coefficient preloading circuit, the integer frequency division up counter and the decimal correction down counter further comprise input high effective system reset signal rst_h and system clock fper.

[0047] The baud rate clock generated according to the value written in UARTBRR1 and UARTBRR2 registers is used for sending and receiving, the essence of which is frequency division of system clock fper, and the frequency division coefficient is controlled by UARTBRR1 and UARTBRR2. The frequency division coefficient is divided into integer part and decimal correction part.

[0048] Wherein, the integer part: UARTDBD = {UARTBRR2[5:4], UARTBRR1[7:0]} is composed. The fraction part: Fraction = UARTBRR2[3:0].

[0049] The integer division up counter is a 10-bit counter, which can realize integer division by adding from the current value to all 1s, i.e. 10'h3FF.

[0050] The fraction correction down counter is a 4-bit counter, and the default value is 4'hF. Each correction is reduced by 1 until it is reduced to 0, and each correction is corrected according to the fraction division value Fraction[3:0], and a total of 16 corrections are performed.

[0051] For the fraction correction part, since the fraction part is 4-bit, a 4-bit fraction correction down counter is internally provided, and the default value is 4'hF. Each correction is reduced by 1 until it is reduced to 0, so 16 corrections are performed. In the 16 corrections, the value of Fraction is corrected. For the correction method, the average distribution from both sides to the middle is adopted, and different judgments are made according to whether the fraction part is odd or even.

[0052] If the fraction part is even, the remainder buffer register is first right-shifted by one bit to determine the correction sampling point of one side, and the value is inverted to obtain the correction sampling point of the other side.

[0053] If the fraction part is odd, the remainder buffer register is first increased by 1 to become even, and then right-shifted by one bit to determine the correction sampling point of one side, and the value is inverted and added by 1 to obtain the correction sampling point of the other side.

[0054] If the fraction part is 0, no correction is needed for any sampling point; if the fraction part is F, the complement of F is first obtained, i.e. 4'h8, i.e. the sampling point that does not need to be corrected is obtained, and the other values are all sampling points that need to be corrected.

[0055] Therefore, the clock generated by the correction is the clock of the receiver; the clock generated by each correction is 16-divided to obtain the transmission clock.

[0056] The baud rate generation formula is: ; wherein UARTDBD represents the integer division value, and Fraction represents the fraction division value.

[0057] As a further elaboration of the embodiment of the application, taking the even fraction parts 4'h8 and 4'hA as examples. For 4'h8, as Figure 2As shown. First, shift it right by one bit to get 4'h4. Then, the data less than 4'h4 are 4'h0, 4'h1, 4'h2, and 4'h3; the data greater than 4'h4 (inverted, i.e., 4'hB) are 4'hC, 4'hD, 4'hE, and 4'hF. From this, we can obtain the sampling points that the decimal correction down-counter needs to correct during its decrement. At these sampling points, the integer frequency divider up-counter counts one more time, i.e., increments by 1. Since the decimal is 8, there are 8 points to correct, 4 from both sides towards the middle, and 4 from the highest to the lowest bit.

[0058] For 4'hA, the correction process is the same as for 4'h8, such as... Figure 3 As shown. The final correction results are 5 on each side. For other even numbers such as 4'h2, 4'h4, 4'h6, 4'hC, and 4'hE, the final correction results are 1, 2, 3, 6, and 7 on each side, respectively.

[0059] Take 4'h5 and 4'h9, where the decimal part is odd, as examples. For 4'h5, as... Figure 4 As shown. First, increment it by 1, then shift it right by one bit to get 4'h3. The data less than 4'h3 are 4'h0, 4'h1, and 4'h2; the data greater than 4'hD (i.e., inverted 4'h3 plus 1) are 4'hE and 4'hF. This gives us the sampling points that the decimal correction down-counter needs to correct during its decrement. At these sampling points, the integer frequency divider up-counter counts one more time, i.e., increments by 1. Since the decimal is 5, there are 5 points to correct, correcting from both sides towards the middle: 3 for the lower bits, 2 for the higher bits, and no correction for the other sampling points in the middle.

[0060] For 4'h9, such as Figure 5 As shown. The correction process is the same as for 4'h5, and the final correction results are 4 on the left and 5 on the right, respectively. For other odd numbers such as 4'h1, 4'h3, 4'h5, 4'hB, and 4'hD, the final correction results are: none on the left and 1 on the right, 1 on the left and 2 on the right, 2 on the left and 3 on the right, 5 on the left and 6 on the right, and 6 on the left and 7 on the right, respectively.

[0061] Special handling is required for 4'hF, such as... Figure 6 As shown. Because adding 1 causes data overflow, we directly invert and add 1, i.e., use its two's complement. Then, we swap the high and low bits of its two's complement to obtain the sampling point that does not need correction. That is, all other sampling points need correction. The final corrected result is 7 on the left and 8 on the right.

[0062] like Figure 7 As shown, this embodiment of the invention also provides a UART decimal correction method, including:

[0063] If the remainder part of the frequency division coefficient is 0, the integer frequency division coefficient is loaded; if not, it is judged whether the remainder part is 4'hF, if yes, after taking the inverse and adding 1, it is judged whether the value is equal to the decimal correction down counter; if yes, the integer frequency division coefficient is loaded; if not, the integer frequency division coefficient plus 1 is loaded.

[0064] If the remainder part is not 4'hF, it is judged whether the remainder part is odd, if yes, after adding 1 and right shifting one bit, it is judged whether the value is greater than the decimal correction down counter, if yes, the integer frequency division coefficient plus 1 is loaded; if not, after taking the inverse and adding 1, it is judged whether the value is less than the decimal correction down counter, if yes, the integer frequency division coefficient plus 1 is loaded; if not, the integer frequency division coefficient is loaded.

[0065] If the remainder part is not odd, after right shifting one bit, it is judged whether the value is greater than the decimal correction down counter, if yes, the integer frequency division coefficient plus 1 is loaded; if not, after taking the inverse, it is judged whether the value is less than the decimal correction down counter, if yes, the integer frequency division coefficient plus 1 is loaded; if not, the integer frequency division coefficient is loaded.

[0066] As a further elaboration of the embodiment of the present application, if the system clock operating frequency is 16M, and if 9600 baud rate is obtained, the register write-in value is: UARTBRR2 = 8'h33; UARTBRR1 = 8'h98, and the calculation method is as follows:

[0067] From the baud rate generation formula, 16000000 / 9600 / 16 = 104.17 can be obtained.

[0068] Then, UARTBD = 1024-104 = 920 = 10'h398.

[0069] Therefore, UARTBRR1 = 8'h98.

[0070] 9600 = 16000000 / (16*104+Fraction), then Fraction = 2.67≈3.

[0071] Therefore, UARTBRR2 = 8'h33.

[0072] From UARTBRR2[3:0], the decimal part is odd 3, so its 1 bit timing is as shown in Figure 8 The integer frequency division coefficient is 10'h398, and the remainder is 4'h3; therefore, the 10 bit integer frequency division counter starts counting from 10'h398, and since the remainder is 3, the correction point is 3, i.e. when the decimal correction counter is 4'hF, 4'h1 and 4'h0, the 10 bit integer frequency division counter will continue to add 1 after overflow.

[0073] As further elaboration of the embodiment of the application, if the system clock frequency is still 16M, if 57600 baud rate is obtained, the register write value is: UARTBRR2 = 8'h36; UARTBRR1 = 8'hEF, the calculation method is as follows:

[0074] From the baud rate generation formula: 16000000 / 57600 / 16 = 17.36;

[0075] Then UARTBD = 1024-17 = 1007 = 10'h3EF;

[0076] Therefore, UARTBRR1 = 8'hEF.

[0077] 57600 = 16000000 / (16*17+Fraction), then Fraction = 5.78≈6;

[0078] Therefore, UARTBRR2 = 8'h36.

[0079] From UARTBRR2[3:0], the fractional part is even 6, so its 1 bit timing is as shown in Figure 9 The integer frequency division coefficient is 10'h3EF, and the remainder is 4'h6; therefore, the 10-bit integer frequency division counter starts counting from 10'h3EF, and since the remainder is 6, the correction point is 6, that is, when the fractional correction counter is 4'hF, 4'hE, 4'hD, 4'h2, 4'h1, 4'h0, the 10-bit integer frequency division counter will continue to add 1 after overflow.

[0080] The above description is only a description of the preferred embodiment of the application, and is not any limitation on the scope of the application, any modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A UART fractional correction circuit, characterized in that, include: The frequency division coefficient preloading circuit loads the integer frequency division value UARTDBD[13:4] and the fractional frequency division value Fraction[3:0] of the output frequency division coefficient according to the written values ​​of the baud rate registers UARTBRR1~UARTBRR2. The integer divider up counter is used to input the integer divider value UARTDBD[13:4] and output the count value cnt_i[9:0]. The decimal correction down counter is used to input the decimal division value Friction[3:0] and output the count value cnt_f[3:0]. The decimal correction algorithm circuit is used to input the count values ​​cnt_i[9:0] and cnt_f[3:0]. Internally, it determines the decimal correction sampling point through shifting, inversion, and comparison, and outputs a pulse signal reload to the integer frequency divider up counter, the decimal correction down counter, and the D flip-flop. When the pulse signal reload is valid, it determines whether the integer frequency divider up counter needs to be incremented by 1 and whether the decimal correction down counter needs to be decremented by 1. A D flip-flop, with the D terminal inputting the pulse signal reload, the clock terminal inputting the system clock fper, and the Q terminal outputting the corrected clock baud_clk; When the decimal part is corrected, the decimal correction algorithm circuit includes the following correction methods: The method of distributing the fractions equally from both sides towards the middle is adopted, and different judgments are made based on whether the decimal part is odd or even. If the decimal part is even, first shift the remainder buffer baud rate register UARTBRR2 one bit to the right to determine the corrected sampling point on one side, and then invert the value to obtain the corrected sampling point on the other side. If the decimal part is odd, first increment the remainder buffer baud rate register UARTBRR2 by 1 to make it even, then shift it right by one bit to determine the corrected sampling point on one side, and invert the value and increment it by 1 to obtain the corrected sampling point on the other side. If the decimal part is 0, no correction is needed for any sampling points; If the fractional part is F, then first take its two's complement to get 4'h8, which gives the sampling point that does not need correction. Then all other values ​​are sampling points that need correction.

2. The UART fractional correction circuit as described in claim 1, characterized in that, The frequency division coefficient preloading circuit, the integer frequency division up counter, and the fractional correction down counter also include a highly active system reset signal rst_h and a system clock fper.

3. The UART fractional correction circuit as described in claim 1, characterized in that, The integer division value UARTDBD[13:4] is composed of the high 2 bits of the baud rate register UARTBRR2 written value UARTBRR2[5:4] and the full 8 bits of the baud rate register UARTBRR1 written value UARTBRR1[7:0].

4. A UART fractional correction circuit as described in claim 1, characterized in that, The fractional division value Friction[3:0] is composed of the lower 4 bits of the baud rate register UARTBRR2[3:0].

5. A UART fractional correction circuit as described in claim 1, characterized in that, The integer frequency divider up counter is a 10-bit counter. Integer frequency division can be achieved by incrementing from the current value to all 1s, i.e., 10'h3FF.

6. A UART fractional correction circuit as described in claim 1, characterized in that, The decimal correction down-counter is a 4-bit counter with a default value of 4'hF. It decrements by 1 with each correction until it reaches 0. Each correction is performed based on the decimal division value Friction[3:0], and a total of 16 corrections are performed.

7. A UART fractional correction circuit as described in claim 1, characterized in that, The clock baud_clk generated by the correction is the receiver clock; the transmit clock is obtained by dividing the clock baud_clk generated by each correction by 16.

8. A UART fractional correction circuit as described in claim 1, characterized in that, The formula for generating baud rate is: UARTDBD represents the integer frequency division value, and Fraction represents the fractional frequency division value.

9. A UART decimal correction method, employing a UART decimal correction circuit as described in any one of claims 1 to 8, characterized in that, include: Determine if the remainder of the frequency division coefficient is 0. If the remainder is 0, then load the integer frequency division coefficient. If the remainder is not 0, then determine whether the remainder is 4'hF; If the remainder is 4'hF, then invert it and add 1, then determine if the value is equal to the decimal correction down counter; if the value is equal to the decimal correction down counter, then load the integer frequency division coefficient. If the value is not equal to the decimal correction down counter, then the integer frequency division coefficient is incremented by 1; If the remainder is not 4'hF, then determine if the remainder is odd. If it is odd, increment by 1, shift one position to the right, and then determine if the value is greater than the decimal correction down counter. If the value is greater than the decimal correction down counter, then increment the integer frequency divider by 1. If the value is not greater than the decimal correction down counter, invert the value and increment by 1, then determine if the value is less than the decimal correction down counter. If the value is less than the decimal correction down counter, then increment the integer frequency divider by 1. If the value is not less than the decimal correction down counter, then increment the integer frequency divider by 1. If the remainder is not odd, shift it one position to the right and check if the value is greater than the decimal correction down counter. If the value is greater than the decimal correction down counter, increment the integer frequency divider by 1. If the value is not greater than the decimal correction down counter, invert the value and check if the value is less than the decimal correction down counter. If the value is less than the decimal correction down counter, increment the integer frequency divider by 1. If the value is not less than the decimal correction down counter, increment the integer frequency divider by 1.

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