Semiconductor device including decoupling capacitor

Abstract

The embodiment of the invention relates to a semiconductor device. The semiconductor device comprises a substrate; at least one lower interconnection layer disposed on the substrate; a first upper interconnection layer on the at least one lower interconnection layer; the second upper interconnection layer is located on the first upper interconnection layer; an external connection pad included in the second upper interconnect layer; and a metal oxide semiconductor (MOS) capacitor disposed on the substrate and vertically overlapping the external connection pad, in which the at least one lower interconnect layer includes: a main decoupling capacitor region vertically overlapping the MOS capacitor; and an additional decoupling capacitor region surrounding the main decoupling capacitor region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0052052 filed on April 18, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to semiconductor technology, and more particularly, to a semiconductor device including a decoupling capacitor. Background Art

[0004] As the integration density of semiconductor devices continues to increase, the demand for increased storage capacity and, simultaneously, for faster operating speeds, is growing. Read and write operations introduce transient noise into the power supply voltage, and as operating speeds increase, semiconductor devices become increasingly susceptible to this noise. To filter out this noise in the power supply voltage, semiconductor devices use decoupling capacitors connected between the power supply voltage and ground. Summary of the Invention

[0005] Embodiments of the present disclosure may provide a semiconductor device, comprising: a substrate; at least one lower interconnect layer disposed on the substrate; a first upper interconnect layer located on the at least one lower interconnect layer; a second upper interconnect layer located on the first upper interconnect layer; an external connection pad, the second upper interconnect layer including the external connection pad; and a metal oxide semiconductor (MOS) capacitor disposed on the substrate to vertically overlap with the external connection pad, wherein the at least one lower interconnect layer includes a main decoupling capacitor region and an additional decoupling capacitor region, the main decoupling capacitor region vertically overlapping the MOS capacitor, and the additional decoupling capacitor region surrounding the main decoupling capacitor region.

[0006] Embodiments of the present disclosure may provide a semiconductor device, comprising: a peripheral structure, the peripheral structure comprising a substrate, a circuit device and a lower interconnect layer, the substrate being defined with a first region and a second region, the circuit device being arranged on the substrate, and the lower interconnect layer being arranged on the circuit device; a cell structure, the cell structure comprising a memory cell array, a first upper interconnect layer, a second upper interconnect layer and an external connection pad, the memory cell array being arranged on the second region of the peripheral structure, the first upper interconnect layer being located on the memory cell array, the second upper interconnect layer being located on the first upper interconnect layer, the external connection pad being arranged in the first region, and the second upper interconnect layer including the external connection pad; a first vertical through-hole and a second vertical through-hole vertically overlapping with the external connection pad and extending vertically between the lower interconnect layer and the first upper interconnect layer; and a first decoupling capacitor comprising the first vertical through-hole, the second vertical through-hole and a dielectric layer between the first vertical through-hole and the second vertical through-hole.

[0007] Embodiments of the present disclosure can provide a semiconductor device, including: a peripheral structure including a substrate, a metal-oxide-semiconductor (MOS) capacitor, a lower dielectric layer, and a lower interconnect layer, the substrate having a first region and a second region defined thereon, the MOS capacitor disposed on the first region of the substrate, the lower dielectric layer covering the MOS capacitor, the lower interconnect layer disposed on the lower dielectric layer; a cell structure including a source plate, a gate lamination plate, a first upper dielectric layer, a second upper dielectric layer, a third upper dielectric layer, a first upper interconnect layer, a second upper interconnect layer, and an external connection pad, the source plate disposed on the second region of the peripheral structure, the gate lamination plate including a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked on the source plate, the first upper dielectric layer covering the source plate and the gate lamination plate, the second upper dielectric layer on the first upper dielectric layer, the first upper interconnect layer on the second upper dielectric layer, the third upper dielectric layer covering the first upper interconnect layer, the second upper interconnect layer on the third upper dielectric layer, the external connection pad disposed in the first region and the external connection pad included in the second upper interconnect layer; a first vertical via and a second vertical via vertically overlapping the external connection pad and vertically penetrating the first upper dielectric layer; and a first decoupling capacitor including the first vertical via, the second vertical via, and the first upper dielectric layer between the first vertical via and the second vertical via. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional view of a semiconductor device according to various embodiments of the present disclosure.

[0009] Figure 2 is a plan view of an embodiment of a main decoupling capacitor region and an additional decoupling capacitor region of a first lower interconnect layer of Figure 1

[0010] Figures 3 to 5 is a cross-sectional view of a semiconductor device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] In the following description of examples or embodiments of the present disclosure, reference is made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of example, and in which the same reference numbers and symbols can be used to denote the same or similar components even if they are shown in different drawings from each other. Also, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein can be omitted when it is determined that a detailed description of such functions and components can make the subject matter of some embodiments of the present disclosure less clear. The terms such as “include,” “have,” “contain,” “comprise,” “consist of,” and “consist of” used herein are generally intended to allow the addition of other components, unless the terms are used together with the term “only.” As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.​

[0012] Terms such as "first", "second", "A", "B", "(A)", or "(B)" can be used herein to describe elements of the disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0013] When it is mentioned that a first element is "connected or coupled", "in contact or overlap" with a second element, etc., it is understood that the first element can not only be "directly connected or coupled" or "directly in contact or overlap" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "in contact or overlap" with each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled", "in contact or overlap" with each other, etc. It will be understood that when one element or layer, etc. is referred to as "on" another element or layer, etc., it can be directly on the other element or layer, etc., or can be connected or coupled to the other element or layer, etc. with an intervening element or layer, etc. Conversely, when an element or layer, etc. is referred to as being "directly on", "connected" or "coupled" to another element or layer, etc., there is no intervening element or layer, etc. Identical reference numerals denote the same elements throughout.

[0014] When using temporal relative terms, such as "after", "subsequently", "next", "before", etc., to describe the process or operation of the elements or configuration, or the flow or step in the operation, process, manufacturing method, these terms can be used to describe non-continuous or non-sequential processes or operations, unless used with the term "directly" or "immediately".

[0015] In addition, when referring to any dimension, relative size, etc., it is considered that the numerical value or the corresponding information of the element or feature (e.g., level, range, etc.) includes a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if the relevant description is not specified. In addition, the term "may" fully covers all meanings of the term "can".

[0016] Various embodiments of the disclosure will be described in detail below with reference to the accompanying drawings.

[0017] Figure 1 is a cross-sectional view of a semiconductor device according to various embodiments of the disclosure.

[0018] Referring to Figure 1 A semiconductor device according to various embodiments of the disclosure can include a lower structure 100 and an upper structure 200 disposed on the lower structure 100.

[0019] The upper structure 200 may include a first external connection pad 26. The semiconductor device may include a first region R1 and a second region R2. The first external connection pad 26 may be disposed in the first region R1. In one embodiment, the first external connection pad 26 may be a power supply pad. In another embodiment, the first external connection pad 26 may be a ground pad. Although not shown, the upper structure 200 further includes a plurality of second external connection pads. The second external connection pads may include, for example, at least one of a data pad, an address pad, a command pad, and a control signal pad.

[0020] The lower structure 100 may include a MOS capacitor 12 vertically overlapping the first external connection pad 26. The lower structure 100 may include at least one lower interconnect layer. The at least one lower interconnect layer may include, for example, a first lower interconnect layer UM1, a second lower interconnect layer UM2, and a third lower interconnect layer UM3.

[0021] The first region R1 may include a main decoupling capacitor region MDR and an additional decoupling capacitor region ADR vertically overlapping the first external connection pad 26. The main decoupling capacitor region MDR may vertically overlap the MOS capacitor 12, and the additional decoupling capacitor region ADR may not vertically overlap the MOS capacitor 12 or may not vertically overlap the MOS capacitor 12. In an embodiment, as Figure 1 As shown, the main decoupling capacitor region MDR may vertically overlap with the MOS capacitor 12, and the additional decoupling capacitor region ADR may not vertically overlap with the MOS capacitor 12 or may not vertically overlap with the MOS capacitor 12. The main decoupling capacitor region MDR may vertically overlap with the center area of ​​the first external connection pad 26, and the additional decoupling capacitor region ADR may vertically overlap with the edge area of ​​the first external connection pad 26. In an embodiment, the main decoupling capacitor region MDR may vertically overlap with the center area of ​​the first external connection pad 26 without vertically overlapping with the edge area of ​​the first external connection pad 26, and the additional decoupling capacitor region ADR may vertically overlap with the edge area of ​​the first external connection pad 26 without vertically overlapping with the center area of ​​the first external connection pad 26.

[0022] In one embodiment, the upper structure 200 may include a memory cell array, and the lower structure 100 may include a peripheral circuit for controlling the operation of the memory cell array. In this case, the lower structure 100 may be defined as a peripheral structure, and the upper structure 200 may be defined as a cell structure.

[0023] For example, the lower structure 100 may include a substrate 10 , a circuit device 11 , a MOS capacitor 12 , lower dielectric layers 13 a , 13 b , 13 c , 13 d , and lower interconnect layers UM1 , UM2 , UM3 .

[0024] The substrate 10 can be bulk silicon or Silicon-On-Insulator (SOI). The substrate 100 can also be a silicon substrate. The substrate 10 can include, but is not limited to, silicon germanium, Silicon Germanium On Insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0025] The circuit device 11 can include a transistor. The transistor can include a first gate electrode 11a disposed on the substrate 10, a first gate insulating layer 11b between the substrate 10 and the first gate electrode 11a, and a source region 11c and a drain region 11d disposed in the substrate 10 on both sides of the first gate electrode 11a. The circuit device 11 can include a peripheral circuit for controlling the operation of the memory cell array. The peripheral circuit can include, for example, but is not limited to, a row decoder, a page buffer circuit, control logic, and a voltage generator.

[0026] The MOS capacitor 12 can include a second gate electrode 12a disposed on the substrate 10, an active region 12c of the substrate 10 overlapping the second gate electrode 12a, and a second gate insulating layer 12b between the active region 12c and the second gate electrode 12a. One of the second gate electrode 12a and the active region 12c can be connected to a power supply line, and the other can be connected to a ground line. In an embodiment, the MOS capacitor 12 can be used as a decoupling capacitor.

[0027] The lower dielectric layers 13a, 13b, 13c, 13d can include, for example, a first lower dielectric layer 13a, a second lower dielectric layer 13b, a third lower dielectric layer 13c, and a fourth lower dielectric layer 13d. The first lower dielectric layer 13a, the second lower dielectric layer 13b, the third lower dielectric layer 13c, and the fourth lower dielectric layer 13d can include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0028] The lower interconnection layers UM1, UM2, UM3, UM3 can include, for example, a first lower interconnection layer UM1, a second lower interconnection layer UM2, and a third lower interconnection layer UM3.

[0029] The first lower dielectric layer 13a can be disposed on the substrate 10 and can cover the circuit device 11 and the MOS capacitor 12. The first lower interconnection layer UM1 can be disposed on the first lower dielectric layer 13a.

[0030] The second lower dielectric layer 13b can be disposed on the first lower dielectric layer 13a and can cover the first lower interconnection layer UM1. The second lower interconnection layer UM2 can be disposed on the second lower dielectric layer 13b.

[0031] A third lower dielectric layer 13c can be disposed on the second lower dielectric layer 13b and can cover the second lower interconnection layer UM2. A third lower interconnection layer UM3 can be disposed on the third lower dielectric layer 13c.

[0032] A fourth lower dielectric layer 13d can be disposed on the third lower dielectric layer 13c and can cover the third lower interconnection layer UM3.

[0033] Although Figure 1 A case including three lower interconnection layers is illustrated, but it is not limited thereto. The semiconductor device according to various embodiments of the present disclosure can include at least one lower interconnection layer.

[0034] Each of the first lower interconnection layer UM1, the second lower interconnection layer UM2, and the third lower interconnection layer UM3 can include a main decoupling capacitor first electrode Pm and a main decoupling capacitor second electrode Gm disposed in a main decoupling capacitor region MDR. The main decoupling capacitor first electrode Pm can be connected to a power supply line, and the main decoupling capacitor second electrode Gm can be connected to a ground line.

[0035] On each of the first lower interconnection layer UM1, the second lower interconnection layer UM2, and the third lower interconnection layer UM3, the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm can be alternately disposed one by one.

[0036] The main decoupling capacitor first electrode Pm of the first lower interconnection layer UM1, the main decoupling capacitor second electrode Gm of the first lower interconnection layer UM1, and the second lower dielectric layer 13b therebetween can constitute a first main decoupling capacitor.

[0037] The main decoupling capacitor first electrode Pm of the second lower interconnection layer UM2, the main decoupling capacitor second electrode Gm of the second lower interconnection layer UM2, and the third lower dielectric layer 13c therebetween can constitute a second main decoupling capacitor.

[0038] The main decoupling capacitor first electrode Pm of the third lower interconnection layer UM3, the main decoupling capacitor second electrode Gm of the third lower interconnection layer UM3, and the fourth lower dielectric layer 13d therebetween can constitute a third main decoupling capacitor.

[0039] At least a portion of the main decoupling capacitor first electrode Pm of the first lower interconnection layer UM1 and at least a portion of the main decoupling capacitor second electrode Gm of the second lower interconnection layer UM2 can vertically overlap each other. At least a portion of the main decoupling capacitor second electrode Gm of the first lower interconnection layer UM1 and at least a portion of the main decoupling capacitor first electrode Pm of the second lower interconnection layer UM2 can vertically overlap each other.

[0040] At least a portion of the main decoupling capacitor first electrode Pm of the second lower interconnection layer UM2 and at least a portion of the main decoupling capacitor second electrode Gm of the third lower interconnection layer UM3 can vertically overlap each other. At least a portion of the main decoupling capacitor second electrode Gm of the second lower interconnection layer UM2 and at least a portion of the main decoupling capacitor first electrode Pm of the third lower interconnection layer UM3 can vertically overlap each other.

[0041] The main decoupling capacitor first electrode Pm of the first lower interconnection layer UM1, the main decoupling capacitor second electrode Gm of the second lower interconnection layer UM2, and the second lower dielectric layer 13b therebetween can constitute a fourth main decoupling capacitor.

[0042] The main decoupling capacitor second electrode Gm of the first lower interconnection layer UM1, the main decoupling capacitor first electrode Pm of the second lower interconnection layer UM2, and the second lower dielectric layer 13b therebetween can constitute a fifth main decoupling capacitor.

[0043] The main decoupling capacitor first electrode Pm of the second lower interconnection layer UM2, the main decoupling capacitor second electrode Gm of the third lower interconnection layer UM3, and the third lower dielectric layer 13c therebetween can constitute a sixth main decoupling capacitor.

[0044] The main decoupling capacitor second electrode Gm of the second lower interconnection layer UM2, the main decoupling capacitor first electrode Pm of the third lower interconnection layer UM3, and the third lower dielectric layer 13c therebetween can constitute a seventh main decoupling capacitor.

[0045] Each of the first lower interconnection layer UM1, the second lower interconnection layer UM2, and the third lower interconnection layer UM3 can include an additional decoupling capacitor first electrode Pa and an additional decoupling capacitor second electrode Ga disposed in an additional decoupling capacitor region ADR. The additional decoupling capacitor first electrode Pa can be connected to a power supply line, and the additional decoupling capacitor second electrode Ga can be connected to a ground line.

[0046] On each of the first lower interconnection layer UM1, the second lower interconnection layer UM2, and the third lower interconnection layer UM3, the additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga can be alternately disposed one by one.

[0047] The additional decoupling capacitor first electrode Pa of the first lower interconnection layer UM1, the additional decoupling capacitor second electrode Ga of the first lower interconnection layer UM1, and the second lower dielectric layer 13b therebetween can constitute a first additional decoupling capacitor.

[0048] The additional decoupling capacitor first electrode Pa of the second lower interconnection layer UM2, the additional decoupling capacitor second electrode Ga of the second lower interconnection layer UM2, and the third lower dielectric layer 13c therebetween can constitute a second additional decoupling capacitor.

[0049] The additional decoupling capacitor first electrode Pa of the third lower interconnect layer UM3, the additional decoupling capacitor second electrode Ga of the third lower interconnect layer UM3, and the fourth lower dielectric layer 13d therebetween can constitute a third additional decoupling capacitor.

[0050] At least a portion of the additional decoupling capacitor first electrode Pa of the first lower interconnect layer UM1 and at least a portion of the additional decoupling capacitor second electrode Ga of the second lower interconnect layer UM2 can vertically overlap each other. At least a portion of the additional decoupling capacitor second electrode Ga of the first lower interconnect layer UM1 and at least a portion of the additional decoupling capacitor first electrode Pa of the second lower interconnect layer UM2 can vertically overlap each other.

[0051] At least a portion of the additional decoupling capacitor first electrode Pa of the second lower interconnect layer UM2 and at least a portion of the additional decoupling capacitor second electrode Ga of the third lower interconnect layer UM3 can vertically overlap each other. At least a portion of the additional decoupling capacitor second electrode Ga of the second lower interconnect layer UM2 and at least a portion of the additional decoupling capacitor first electrode Pa of the third lower interconnect layer UM3 can vertically overlap each other.

[0052] The additional decoupling capacitor first electrode Pa of the first lower interconnect layer UM1, the additional decoupling capacitor second electrode Ga of the second lower interconnect layer UM2, and the second lower dielectric layer 13b therebetween can constitute a fourth additional decoupling capacitor.

[0053] The additional decoupling capacitor second electrode Ga of the first lower interconnect layer UM1, the additional decoupling capacitor first electrode Pa of the second lower interconnect layer UM2, and the second lower dielectric layer 13b therebetween can constitute a fifth additional decoupling capacitor.

[0054] The additional decoupling capacitor first electrode Pa of the second lower interconnect layer UM2, the additional decoupling capacitor second electrode Ga of the third lower interconnect layer UM3, and the third lower dielectric layer 13c therebetween can constitute a sixth additional decoupling capacitor.

[0055] The additional decoupling capacitor second electrode Ga of the second lower interconnect layer UM2, the additional decoupling capacitor first electrode Pa of the third lower interconnect layer UM3, and the third lower dielectric layer 13c therebetween can constitute a seventh additional decoupling capacitor.

[0056] The upper structure 200 can include a source plate 20, a gate laminate 21, a plurality of cell plugs 22, upper dielectric layers 23a, 23b, 23c, and upper interconnect layers M1, M2.

[0057] The source plate 20 can be disposed on the second region R2 of the lower structure 100. The source plate 20 can include a doped semiconductor.

[0058] The gate lamination plate 21 can include a plurality of interlayer insulation layers 21a and a plurality of gate electrode layers 21b alternately stacked on the source plate 20. The gate electrode layers 21b can include a conductive material. For example, the gate electrode layers 21b can include tungsten (W). The interlayer insulation layers 21a can include silicon oxide. The gate electrode layers 21b can include word lines. The gate electrode layers 21b can also include at least one source select line and at least one drain select line.

[0059] The cell plug 22 can vertically extend through the gate lamination plate 21 and extend to the source plate 20. Each cell plug 22 can include a passage layer 22a and a cell gate insulation layer 22b. The cell gate insulation layer 22b can have a tubular (straw) shell or a cylindrical shell shape that surrounds an outer wall of the passage layer 22a. The cell gate insulation layer 22b can include a tunnel insulation layer, a charge storage layer, and a blocking layer formed in order from the outer wall of the passage layer 22a. In some embodiments, the cell gate insulation layer 22b can have an oxide-nitride-oxide (ONO) lamination structure in which oxide layers, nitride layers, and oxide layers are laminated in order. Memory cells can be formed at positions where the word lines surround the cell plugs 22. Source select transistors can be formed at positions where the source select lines surround the cell plugs 22. Drain select transistors can be formed at positions where the drain select lines surround the cell plugs 22. The drain select transistors, the plurality of memory cells, and the source select transistors disposed along one cell plug 22 can form a cell string. A plurality of cell strings corresponding to the plurality of cell plugs 22 can be disposed in the second region R2 of the upper structure 200. The plurality of cell strings can form a memory cell array.

[0060] The upper dielectric layers 23a, 23b, 23c can include, for example, a first upper dielectric layer 23a, a second upper dielectric layer 23b, and a third upper dielectric layer 23c. The first upper dielectric layer 23a, the second upper dielectric layer 23b, and the third upper dielectric layer 23c can include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0061] The first upper dielectric layer 23a can be disposed on the fourth lower dielectric layer 13d of the lower structure 100 and can cover the top and side surfaces of the source plate 20, cover the top and side surfaces of the gate lamination plate 21, and cover the side surfaces of the cell plugs 22. The second upper dielectric layer 23b is disposed on the first upper dielectric layer 23a and can cover the top surfaces of the cell plugs 22.

[0062] The first upper interconnection layer M1 can be disposed on the second upper dielectric layer 23b. The first upper interconnection layer M1 can include a bit line BL and a third electrode 24a.

[0063] At the bottom of the bit line BL, a bit line contact 25 can be provided, which extends through the second upper dielectric layer 23b and to the cell plug 22. The bit line BL can be connected to the cell plug 22 through the bit line contact 25.

[0064] The third electrode 24a can be provided vertically overlapping the first external connection pad 26. Although Figure 1 Only one third electrode 24a is shown, but the first upper interconnect layer M1 can comprise a plurality of third electrodes 24a provided in an area vertically overlapping the first external connection pad 26.

[0065] A third upper dielectric layer 23c can be provided on the second upper dielectric layer 23b and covering the first upper interconnect layer M1. The bit line BL and the third electrode 24a can be covered by the third upper dielectric layer 23c. A second upper interconnect layer M2 can be provided on the third upper dielectric layer 23c. The second upper interconnect layer M2 can comprise the first external connection pad 26.

[0066] When the first external connection pad 26 is a power pad, the third electrode 24a can be connected with a ground line. Thus, a decoupling capacitor can be constituted comprising the third electrode 24a, the first external connection pad 26 and the third upper dielectric layer 23c therebetween.

[0067] On the other hand, when the first external connection pad 26 is a ground pad, the third electrode 24a can be connected with a power line. Thus, a decoupling capacitor can be constituted comprising the third electrode 24a, the first external connection pad 26 and the third upper dielectric layer 23c therebetween.

[0068] A protective layer 27 can be provided on the third upper dielectric layer 23c. The protective layer 27 can have an open area OP exposing the first external connection pad 26.

[0069] Figure 2 is a plan view showing Figure 1 a main decoupling capacitor area and an additional decoupling capacitor area of the first lower interconnect layer.

[0070] Referring to Figure 2 In the XY plane, the additional decoupling capacitor area ADR can surround the main decoupling capacitor area MDR. In the XY plane, the main decoupling capacitor area MDR can be located in an inner area surrounded by the additional decoupling capacitor area ADR.

[0071] The main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the first lower interconnect layer UM1 can have a finger structure. Specifically, the main decoupling capacitor first electrode Pm can include a plurality of first fingers Fl, and the main decoupling capacitor second electrode Gm can include a plurality of second fingers F2. In an embodiment, the first fingers Fl can provide an operating voltage VDD, and the second fingers F2 can provide a ground voltage VSS.

[0072] The first fingers Fl and the second fingers F2 can be alternately arranged in the XY plane and can be joined to each other. Since the first fingers Fl and the second fingers F2 are joined to each other, an overlapping area between the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm can increase. Accordingly, the embodiment can provide a high-capacity main decoupling capacitor.

[0073] Like the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the first lower interconnect layer UM1, the additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga of the first lower interconnect layer UM1 can also have a finger structure. Specifically, the additional decoupling capacitor first electrode Pa can include a plurality of third fingers F3, and the additional decoupling capacitor second electrode Ga can include a plurality of fourth fingers F4. In an embodiment, the third fingers F3 can provide an operating voltage VDD, and the fourth fingers F4 can provide a ground voltage VSS.

[0074] The third fingers F3 and the fourth fingers F4 can be alternately arranged in the XY plane and can be joined to each other. Since the third fingers F3 and the fourth fingers F4 are joined to each other, an overlapping area between the additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga can increase. Accordingly, the embodiment can provide a high-capacity additional decoupling capacitor.

[0075] Although not shown, the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the second lower interconnect layer (UM2) and the third lower interconnect layer (UM3) can have similar shapes to the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the first lower interconnect layer (UM1) shown in FIG. 1A. Figure 1 Figure 1 The main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the second lower interconnect layer (UM2) and the third lower interconnect layer (UM3) can have similar shapes to the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the first lower interconnect layer (UM1) shown in FIG. 1A. Figure 2 Figure 1 The main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the second lower interconnect layer (UM2) and the third lower interconnect layer (UM3) can have similar shapes to the main decoupling capacitor first electrode Pm and the main decoupling capacitor second electrode Gm of the first lower interconnect layer (UM1) shown in FIG. 1A.

[0076] The additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga of the second lower interconnect layer (UM2) and the third lower interconnect layer (UM3) can have similar shapes to the additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga of the first lower interconnect layer (UM1) shown in FIG. 1A. Figure 1 Figure 1 ​​​The additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga of the UM3) can have similar shapes to those of the Figure 2 The first lower interconnection layer (UM1) of the semiconductor device according to the embodiment of the disclosure can include a first lower interconnection layer (UM1) disposed between the first upper interconnection layer (M1) and the third lower interconnection layer (UM3). Figure 1 The additional decoupling capacitor first electrode Pa and the additional decoupling capacitor second electrode Ga of the UM1) can have similar shapes to those of the

[0077] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the disclosure.

[0078] Referring to Figure 3 The semiconductor device according to the embodiment of the disclosure can include a first vertical via 27a and a second vertical via 27b disposed between the first upper interconnection layer M1 and the third lower interconnection layer UM3.

[0079] The first vertical via 27a and the second vertical via 27b can vertically penetrate the first upper dielectric layer 23a in a region vertically overlapping the first external connection pad 26. The first vertical via 27a and the second vertical via 27b can be alternately disposed one after another.

[0080] The first vertical via 27a can be connected to a power supply voltage line, and the second vertical via 27b can be connected to a ground line.

[0081] For example, each first vertical via 27a can vertically penetrate the first upper dielectric layer 23a and the fourth lower dielectric layer 13d to be connected to one of the main decoupling capacitor first electrode Pm and the additional decoupling capacitor first electrode Pa, and can be connected to a power supply line through one of the main decoupling capacitor first electrode Pm and the additional decoupling capacitor first electrode Pa. Each second vertical via 27b can vertically penetrate the first upper dielectric layer 23a and the fourth lower dielectric layer 13d to be connected to one of the main decoupling capacitor second electrode Gm and the additional decoupling capacitor second electrode Ga, and can be connected to a ground line through one of the main decoupling capacitor second electrode Gm and the additional decoupling capacitor second electrode Ga.

[0082] The first vertical via 27a and the second vertical via 27b and the first upper dielectric layer 23a and the fourth lower dielectric layer 13d therebetween can constitute a decoupling capacitor. The first vertical via 27a constitutes a first electrode of the decoupling capacitor. The second vertical via 27b constitutes a second electrode of the decoupling capacitor. The first upper dielectric layer 23a and the fourth lower dielectric layer 13d between the first vertical via 27a and the second vertical via 27b constitute a dielectric layer of the decoupling capacitor.

[0083] In an embodiment, the thickness of the first upper dielectric layer 23a provided in the first region R1 increases by increasing the number of stacks of the gate electrode layer 21b to increase the integration level. According to various embodiments of the present disclosure, the capacity of the decoupling capacitor can be increased by forming the first vertical via 27a and the second vertical via 27b through the first upper dielectric layer 23a in the first region R1 and configuring the decoupling capacitor with the first vertical via 27a and the second vertical via 27b.

[0084] Figure 4 is a cross-sectional view illustrating a semiconductor device according to various embodiments of the present disclosure.

[0085] Referring to Figure 4 , the semiconductor device according to an embodiment of the present disclosure can include a first vertical contact 28a connecting the third electrode 24a of the first top interconnection layer M1 with the second vertical via 27b.

[0086] The first vertical contact 28a can be connected to the second vertical via 27b by vertically penetrating the second upper dielectric layer 23b from the bottom of the third electrode 24a. The third electrode 24a can be connected to the second vertical via 27b by the first vertical contact 28a.

[0087] Figure 4 The first external connection pad 26 is illustrated as a power pad in which the first vertical contact 28a connects the third electrode 24a with the second vertical via 27b, but is not limited thereto. If the first external connection pad 26 is a ground pad, the first vertical contact 28a can connect the third electrode 24a with the first vertical via 27a.

[0088] Figure 5 is a cross-sectional view illustrating a semiconductor device according to various embodiments of the present disclosure.

[0089] Referring to Figure 5 , the semiconductor device according to various embodiments of the present disclosure can include a second vertical contact 28b connecting the third electrode 24b to the first vertical via 27a, and a third vertical contact 29 connecting the first external connection pad 26 to the third electrode 24b.

[0090] The second vertical contact 28b can be connected to the first vertical via 27a by vertically penetrating the second upper dielectric layer 23b from the bottom of the third electrode 24b. The third vertical contact 29 can be connected to the third electrode 24b by penetrating the third upper dielectric layer 23c from the bottom of the first external connection pad 26. The first vertical via 27a can be connected to the first external connection pad 26 by the second vertical contact 28b, the third electrode 24b, and the third vertical contact 29.

[0091] In an embodiment, the second vertical contact 28b, the third electrode 24b, and the third vertical contact 29 can be vertically aligned with each other. In an embodiment, since the second vertical contact 28b, the third electrode 24b, and the third vertical contact 29 connecting the first vertical via 27a and the first external connection pad 26 are vertically aligned, a length of an electrical path connecting the first vertical via 27a and the first external connection pad 26 can correspond to a straight-line distance between the first vertical via 27a and the first external connection pad 26. Accordingly, in an embodiment, by minimizing the length of the electrical path between the decoupling capacitor including the first vertical via 27a and the first external connection pad 26, the noise cancellation effect of the decoupling capacitor can be enhanced.

[0092] The above description is merely illustrative of the technical idea of the present disclosure, and various modifications and changes are apparent to those skilled in the art to which the present disclosure pertains without departing from the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to illustrate, not to limit, the technical idea of the present disclosure, and the scope of the technical idea of the present disclosure is not limited to the embodiments.

Claims

1. A semiconductor device comprising: a substrate; at least one lower interconnect layer disposed on the substrate; a first upper interconnect layer on the at least one lower interconnect layer; a second upper interconnect layer on the first upper interconnect layer; an external connection pad, the second upper interconnect layer including the external connection pad; and a metal-oxide-semiconductor (MOS) capacitor disposed on the substrate vertically overlapping the external connection pad, wherein the at least one lower interconnect layer includes: a main decoupling capacitor region vertically overlapping the MOS capacitor; and an additional decoupling capacitor region surrounding the main decoupling capacitor region.

2. The semiconductor device of claim 1, the at least one lower interconnect layer including: wherein a main decoupling capacitor first electrode disposed in the main decoupling capacitor region; a main decoupling capacitor second electrode disposed in the main decoupling capacitor region; an additional decoupling capacitor first electrode disposed in the additional decoupling capacitor region; and an additional decoupling capacitor second electrode disposed in the additional decoupling capacitor region, wherein the main decoupling capacitor first electrode and the additional decoupling capacitor first electrode are connected to a power supply line, and the main decoupling capacitor second electrode and the additional decoupling capacitor second electrode are connected to a ground line.

3. The semiconductor device of claim 2, wherein: each of the additional decoupling capacitor first electrode and the additional decoupling capacitor second electrode includes a plurality of fingers, the at least one lower interconnect layer includes a first lower interconnect layer, and the fingers of the additional decoupling capacitor first electrode and the additional decoupling capacitor second electrode are alternately disposed in the first lower interconnect layer and engage each other.

4. The semiconductor device of claim 2, wherein: the at least one lower interconnect layer includes a first lower interconnect layer and a second lower interconnect layer on the first lower interconnect layer, at least a portion of the additional decoupling capacitor first electrode of the first lower interconnect layer and at least a portion of the additional decoupling capacitor second electrode of the second lower interconnect layer vertically overlap each other, and at least a portion of the additional decoupling capacitor second electrode of the first lower interconnect layer and at least a portion of the additional decoupling capacitor first electrode of the second lower interconnect layer vertically overlap each other.

5. The semiconductor device of claim 2, further comprising: a third electrode disposed on the first upper interconnect layer and vertically overlapping the external connection pad; and a decoupling capacitor including the external connection pad, the third electrode, and a dielectric layer between the external connection pad and the third electrode. the external connection pad is a power supply pad, and the third electrode is connected to a ground line. the external connection pad is a ground pad, and the third electrode is connected to a power supply line.

6. The semiconductor device according to claim 5, wherein the additional decoupling capacitor region vertically overlaps the external connection pad and does not vertically overlap the MOS capacitor.

7. The semiconductor device according to claim 5, wherein the additional decoupling capacitor region surrounds a periphery of the main decoupling capacitor region.

8. The semiconductor device according to claim 1, wherein 10. A semiconductor device comprising:

9. The semiconductor device according to claim 1, wherein ​ ​ a peripheral structure including a substrate, a circuitry device, and a lower interconnect layer, the substrate having a first region and a second region defined thereon, the circuitry device disposed on the substrate, the lower interconnect layer disposed on the circuitry device; a cell structure including a memory cell array, a first upper interconnect layer, a second upper interconnect layer, and an external connection pad, the memory cell array disposed on the second region of the peripheral structure, the first upper interconnect layer on the memory cell array, the second upper interconnect layer on the first upper interconnect layer, and the external connection pad disposed in the first region, the second upper interconnect layer including the external connection pad; a first vertical via and a second vertical via vertically overlapping the external connection pad and vertically extending between the lower interconnect layer and the first upper interconnect layer; and a first decoupling capacitor including the first vertical via, the second vertical via, and a dielectric layer between the first vertical via and the second vertical via.

11. The semiconductor device according to claim 10, wherein the first vertical via is connected to a power line, and the second vertical via is connected to a ground line.

12. The semiconductor device according to claim 10, wherein the lower interconnect layer includes: a main decoupling capacitor region vertically overlapping a central region of the external connection pad; and an additional decoupling capacitor region vertically overlapping an edge region of the external connection pad.

13. The semiconductor device according to claim 12, wherein the lower interconnect layer includes: a main decoupling capacitor first electrode disposed in the main decoupling capacitor region and connected to a power line; a main decoupling capacitor second electrode disposed in the main decoupling capacitor region and connected to a ground line; an additional decoupling capacitor first electrode disposed in the additional decoupling capacitor region and connected to a power line; an additional decoupling capacitor second electrode disposed in the additional decoupling capacitor region and connected to a ground line.

14. The semiconductor device of claim 13, wherein the first vertical via is connected to one of the main decoupling capacitor first electrode and the additional decoupling capacitor first electrode, and the second vertical via is connected to one of the main decoupling capacitor second electrode and the additional decoupling capacitor second electrode.

15. A semiconductor device comprising: a peripheral structure including a substrate, a metal-oxide-semiconductor capacitor (MOS capacitor), a lower dielectric layer, and a lower interconnect layer, the substrate having a first region and a second region defined thereon, the MOS capacitor disposed on the first region of the substrate, the lower dielectric layer covering the MOS capacitor, the lower interconnect layer disposed on the lower dielectric layer; a unit structure including a source plate, a gate laminate, a first upper dielectric layer, a second upper dielectric layer, a third upper dielectric layer, a first upper interconnect layer, a second upper interconnect layer, and an external connection pad, the source plate disposed on a second region of the peripheral structure, the gate laminate including a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked on the source plate, the first upper dielectric layer covering the source plate and the gate laminate, the second upper dielectric layer on the first upper dielectric layer, the first upper interconnect layer on the second upper dielectric layer, the third upper dielectric layer covering the first upper interconnect layer, the second upper interconnect layer on the third upper dielectric layer, the external connection pad disposed in the first region, the external connection pad included in the second upper interconnect layer; a first vertical via and a second vertical via vertically overlapping the external connection pad and vertically penetrating the first upper dielectric layer; and a first decoupling capacitor including the first vertical via, the second vertical via, and the first upper dielectric layer between the first vertical via and the second vertical via.

16. The semiconductor device according to claim 15, wherein the lower interconnect layer includes: a main decoupling capacitor first electrode disposed in a main decoupling capacitor region vertically overlapping the MOS capacitor; a main decoupling capacitor second electrode disposed in the main decoupling capacitor region; an additional decoupling capacitor first electrode disposed in an additional decoupling capacitor region surrounding the main decoupling capacitor region; and an additional decoupling capacitor second electrode disposed in the additional decoupling capacitor region, and wherein the main decoupling capacitor first electrode and the additional decoupling capacitor first electrode are connected to a power line, and the main decoupling capacitor second electrode and the additional decoupling capacitor second electrode are connected to a ground line.

17. The semiconductor device of claim 15, further comprising: a third electrode disposed on the first upper interconnect layer and vertically overlapping the external connection pad; a second decoupling capacitor including the external connection pad, the third electrode, and a third upper dielectric layer between the external connection pad and the third electrode.

18. The semiconductor device of claim 17, further comprising a vertical contact penetrating the second upper dielectric layer and connecting one of the first vertical via and the second vertical via to the third electrode.

19. The semiconductor device of claim 17, further comprising: a first vertical contact vertically penetrating the second upper dielectric layer and connecting one of the first vertical via and the second vertical via to the third electrode; and a second vertical contact vertically penetrating the third upper dielectric layer and connecting the third electrode to the external connection pad. the first vertical contact, the third electrode, and the second vertical contact vertically aligned with each other.

20. The semiconductor device according to claim 19, wherein ​

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