Display device and mobile electronic device including the same

Abstract

A display device and a mobile electronic device including the same are provided. A display device includes a substrate and a display element layer on the substrate, in which the display element layer includes: a pixel defining film defining a plurality of sub-pixels; a first electrode of each of the plurality of sub-pixels in the opening of the pixel defining film; a first wiring on the pixel defining film between adjacent sub-pixels; a light emitting stack on the first electrode and the pixel defining film on which the first wiring is disposed, and broken around the first wiring; and a second electrode on the light emitting stack, in which a top surface of the pixel defining film around the first wiring is uneven and has a cross-sectional shape of the first pattern, and a top surface of the first wiring is uneven and has a cross-sectional shape of the second pattern.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0050741, filed on April 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a display device and a mobile electronic device including the same. BACKGROUND

[0003] Wearable devices that form a focal point at a distance close to a user's eyes in the form of glasses or a helmet have been developed. For example, the wearable device can be a head-mounted display (HMD) and / or augmented reality (AR) glasses. The wearable device provides a user with an augmented reality (hereinafter, referred to as "AR") image or a virtual reality (hereinafter, referred to as "VR") image.

[0004] A wearable device such as an HMD and / or AR glasses requires a display specification of at least 2000 PPI (pixels per inch) so that a user can use it for a long time without dizziness. For this purpose, an organic light emitting diode on silicon (OLEDoS) technology, which is a high-resolution small organic light emitting display device, is on the rise. The organic light emitting diode on silicon (OLEDoS) is a technology for disposing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed.

[0005] In a display panel to which the OLEDoS technology is applied, as the distance between adjacent sub-pixels decreases, unintended leakage current can occur between the adjacent sub-pixels. The leakage current can occur through some conductive layers disposed in an emission stack between a pixel electrode (e.g., an anode electrode) and a common electrode (e.g., a cathode electrode), and is considered to be a cause of color crosstalk between adjacent sub-pixels. SUMMARY

[0006] Aspects and features of embodiments of the present disclosure provide a display device capable of reducing and / or preventing leakage current and color crosstalk by breaking the emission stack between adjacent sub-pixels, and also provide a mobile electronic device including the same.

[0007] According to one or more embodiments of the disclosure, a display device includes a substrate and a display element layer on the substrate, wherein the display element layer includes: a pixel defining film defining a plurality of sub-pixels; a first electrode of each of the plurality of sub-pixels located in an opening of the pixel defining film; a first wiring on the pixel defining film between adjacent sub-pixels; a light emitting stack on the first electrode and the pixel defining film on which the first wiring is disposed, and broken around the first wiring; and a second electrode on the light emitting stack, wherein a top surface of the pixel defining film around the first wiring is not flat and has a cross-sectional shape of a first pattern, and a top surface of the first wiring is not flat and has a cross-sectional shape of a second pattern.

[0008] In one or more embodiments, the first pattern of the pixel defining film includes a trench in which the first wiring is positioned.

[0009] In one or more embodiments, the second pattern of the first wiring has a cross-sectional structure of a positive taper shape.

[0010] In one or more embodiments, the second pattern of the first wiring has a triangular shape having a width that gradually narrows from a bottom surface of the trench to a top surface of the trench.

[0011] In one or more embodiments, the second pattern of the first wiring includes at least one groove at a top surface of the first wiring.

[0012] In one or more embodiments, a bottom surface of the at least one groove at the top surface of the first wiring is flat.

[0013] In one or more embodiments, a bottom surface of the at least one groove at the top surface of the first wiring is recessed.

[0014] In one or more embodiments, the second pattern of the first wiring includes a plurality of circular protrusions on a top surface of the first wiring.

[0015] In one or more embodiments, the second pattern of the first wiring includes a plurality of triangular protrusions on a top surface of the first wiring.

[0016] In one or more embodiments, the second pattern of the first wiring further includes a groove between adjacent triangular protrusions.

[0017] In one or more embodiments, the second pattern of the first wiring includes a plurality of triangular protrusions on a side surface and a top surface of the first wiring.

[0018] In one or more embodiments, the trench in the pixel defining film has a recessed bottom surface.

[0019] In one or more embodiments, the first pattern of the pixel-defining film includes a trench having a lower height than a height of the first wiring, surrounding the first wiring, and having a recessed bottom surface.

[0020] In one or more embodiments, the first pattern of the pixel-defining film includes a convex top surface of the pixel-defining film.

[0021] In one or more embodiments, the first pattern of the pixel-defining film includes a plurality of circular protrusions on a top surface of the pixel-defining film, and the first wiring is between adjacent circular protrusions.

[0022] According to one or more embodiments of the disclosure, a mobile electronic device includes a display panel including a substrate and a display element layer on the substrate, wherein the display element layer includes: a pixel-defining film defining a plurality of sub-pixels; a first electrode of each of the plurality of sub-pixels in an opening of the pixel-defining film; a first wiring on the pixel-defining film between adjacent sub-pixels; a light emitting stack on the first electrode and the pixel-defining film having the first wiring disposed thereon, and broken around the first wiring; and a second electrode on the light emitting stack, wherein a top surface of the pixel-defining film around the first wiring is not flat and has a cross-sectional shape of a first pattern, and a top surface of the first wiring is not flat and has a cross-sectional shape of a second pattern.

[0023] In one or more embodiments, the first pattern of the pixel-defining film includes a trench in which the first wiring is positioned.

[0024] In one or more embodiments, the second pattern of the first wiring has a cross-sectional structure of a positive taper shape.

[0025] In one or more embodiments, the second pattern of the first wiring has a triangular shape having a width that gradually narrows from a bottom surface of the trench to a top of the trench.

[0026] In one or more embodiments, the second pattern of the first wiring includes at least one groove at a top surface of the first wiring.

[0027] In the display device according to one or more embodiments and the mobile electronic device including the same, it is possible to reduce or prevent a leakage current and color cross-talk by breaking the light emitting stack between adjacent sub-pixels.

[0028] Effects, aspects, and features of embodiments of the disclosure are not limited to what has been described above and are apparent from the following description, and other effects, aspects, and features not described herein will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate example embodiments of the present disclosure by way of example: Figure 1 is an exploded perspective view illustrating a display device according to one or more embodiments; Figure 2 is a block diagram illustrating a display device according to one or more embodiments; Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments; Figure 4 is a layout view illustrating an example of a display panel according to one or more embodiments; Figure 5 and Figure 6 is a layout view illustrating an example of a display area of Figure 4 ; Figure 7 is a cross-sectional view illustrating an example of a display panel taken along a line I1-I1' of Figure 5 ; Figure 8 is a perspective view illustrating a head-mounted display according to one or more embodiments; Figure 9 is an exploded perspective view illustrating an example of a head-mounted display of Figure 8 ; Figure 10 is a perspective view illustrating a head-mounted display according to one or more embodiments; Figure 11 is a cross-sectional view schematically illustrating a display element layer of a display panel according to one or more embodiments; Figure 12 is a flowchart illustrating a method of manufacturing a display panel according to one or more embodiments; Figures 13 to 16 is a cross-sectional view illustrating a method of manufacturing a display element layer of a display panel according to one or more embodiments; Figure 17 is a cross-sectional view schematically illustrating a first wiring and a light emitting stack of a display panel according to a comparative example; Figure 18 and Figure 19 are cross-sectional views schematically illustrating a pixel definition film and a first wiring according to one or more embodiments; Figure 20 and Figure 21 are conceptual views illustrating a method of forming a first wiring according to one or more embodiments; and Figures 22 to 30 are cross-sectional views schematically illustrating a pixel definition film and a first wiring according to one or more embodiments. DETAILED DESCRIPTION

[0030] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0031] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0032] For the purposes of this disclosure, when expressions such as “at least one of,” “one of,” or “selected from,” when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, XZ, and YZ for example), or any variation thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. In addition, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”

[0033] Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first element discussed below may be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," etc. may also be used herein to distinguish between elements of different categories or groups. For the sake of simplicity, the terms "first," "second," etc. may respectively represent "first category (or first group)," "second category (or second group)," etc.

[0034] As used herein, the terms “substantially,” “approximately,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account measurement uncertainty and the limitations of measuring a particular quantity. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of a stated value. Further, the use of “may” in describing embodiments of the present disclosure indicates “one or more embodiments of the present disclosure.”

[0035] Further, any numerical ranges recited in this disclosure are intended to include all sub-ranges of the same whole number recited, as implicitly disclaimed. For example, a range of 1.0 to 10.0 should be read to include a range of 2.4 to 7.6, and so on. Any maximum numerical limitation recited in this specification is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range including any minimum or maximum numerical limitation disclosed herein. All such ranges are intended to be inherently described in this specification, such that amending to expressly recite any such sub-ranges would comply with the requirements of 35 U.S.C. § 112, first paragraph, and 35 U.S.C. § 132(a).

[0036] Features of various embodiments of the present disclosure can be combined, in part or in whole. As will be apparent to those of ordinary skill in the art, various interchanges and modifications of the technology are possible. Various embodiments can be practiced individually or in combination.

[0037] Those of ordinary skill in the art will appreciate that, in light of the overall disclosure, each suitable feature of various embodiments of the present disclosure can be combined in whole or part, or combined in various suitable ways, and can be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment can be implemented independently of each other or in combination with each other in any suitable way.

[0038] In the following, specific example embodiments will be described with reference to the accompanying drawings.

[0039] Figure 1is an exploded perspective view illustrating a display apparatus according to one or more embodiments. Figure 2 is a block diagram illustrating a display apparatus according to one or more embodiments.

[0040] Referring to Figure 1 and Figure 2 , a display apparatus 10 according to one or more embodiments is an apparatus for displaying moving images and / or still images. The display apparatus 10 according to one or more embodiments can be applied to a portable electronic apparatus such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, and / or an ultra mobile PC (UMPC), etc. For example, the display apparatus 10 according to one or more embodiments can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) terminal. Alternatively, the display apparatus 10 according to one or more embodiments can be applied to a smart watch, a watch phone, and / or a head-mounted display (HMD) for implementing virtual reality and augmented reality, etc.

[0041] The display apparatus 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply circuit (i.e., a power supply unit) 500.

[0042] The display panel 100 can have a planar shape similar to a quadrilateral shape. For example, the display panel 100 can have a planar shape similar to a quadrilateral shape having a short side in a first direction DR1 and a long side in a second direction DR2 crossing the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be a right angle or rounded with a suitable curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to the quadrilateral shape, and can be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display apparatus 10 can follow the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0043] As shown in Figure 2 , the display panel 100 includes a display area DAA for displaying an image and a non-display area NDA not displaying an image.

[0044] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0045] The plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0046] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0047] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. 4 can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, a plurality of pixel transistors of the data driver 700 may be formed of a complementary metal oxide semiconductor (CMOS).

[0048] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to one write scan line GWL among a plurality of write scan lines GWL, one control scan line GCL among a plurality of control scan lines GCL, one bias scan line GBL among a plurality of bias scan lines GBL, one first emission control line EL1 among a plurality of first emission control lines EL1, one second emission control line EL2 among a plurality of second emission control lines EL2, and one data line DL among a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0049] The non-display area NDA includes a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0050] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed on a semiconductor substrate SSUB (see FIG. Figure 7 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors can be formed by CMOS. Although Figure 2It is shown in FIG. 6 that the scan driver 610 is disposed at the left side of the display area DAA and the emission driver 620 is disposed at the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 can be disposed at both the left and right sides of the display area DAA.

[0051] The scan driver 610 can include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 can generate write scan signals according to the scan timing control signal SCS from the timing controller 400 and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 can generate control scan signals in response to the scan timing control signal SCS and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 can generate bias scan signals according to the scan timing control signal SCS and sequentially output them to the bias scan lines GBL.

[0052] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing controller 400. The first emission control driver 621 can generate first emission control signals according to the emission timing control signal ECS from the timing controller 400 and sequentially output them to the first emission control lines EL1. The second emission control driver 622 can generate second emission control signals according to the emission timing control signal ECS from the timing controller 400 and sequentially output them to the second emission control lines EL2.

[0053] The data driver 700 can include a plurality of data transistors, which can be formed on a semiconductor substrate SSUB (see FIG. 6) by a semiconductor process. Figure 7 For example, the plurality of data transistors can be formed of CMOS.

[0054] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data lines DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signals of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0055] The heat dissipation layer 200 can be stacked with the display panel 100 in a third direction DR3 that is a thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on one surface of the display panel 100 (e.g., on a rear surface thereof). The heat dissipation layer 200 functions to dissipate heat generated from the display panel 100. The heat dissipation layer 200 can include a graphite or metal layer (such as silver (Ag), copper (Cu), and / or aluminum (Al)) having high thermal conductivity.

[0056] The circuit board 300 can be electrically connected to a plurality of first pads PD1 (see Figure 4 ) of the first pad portion PDA1 (see Figure 4 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be a flexible printed circuit board (FPCB) having a flexible material or a flexible film. Although the circuit board 300 is shown as being unfolded in Figure 1 , the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be disposed on a rear surface of the display panel 100 and / or a rear surface of the heat dissipation layer 200. The one end of the circuit board 300 can be an opposite end of the plurality of first pads PD1 (see Figure 4 ) of the first pad portion PDA1 (see Figure 4 ) of the display panel 100 connected to the other end by using the conductive adhesive member.

[0057] The timing controller 400 can receive digital video data DATA and a timing signal inputted from the outside. The timing controller 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing controller 400 can output the scan timing control signal SCS to the scan driver 610 and output the emission timing control signal ECS to the emission driver 620. The timing controller 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0058] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 can generate a reference voltage VREF, a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later in connection with Figure 3 .

[0059] Each of the timing controller 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller 400 can be supplied to the display panel 100 through the circuit board 300. Further, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0060] Alternatively, each of the timing controller 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similar to the scan driver 610, the emission driver 620, and the data driver 700. In this case, the timing controller 400 can include a plurality of timing transistors, and each power supply circuit 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed on a semiconductor substrate SSUB (see FIG. 1) by a semiconductor process. For example, the plurality of timing transistors and the plurality of power transistors can be formed by CMOS. Each of the timing controller 400 and the power supply circuit 500 can be disposed between the data driver 700 and the first pad portion PDA1 (see FIG. 1). Figure 7 Figure 4

[0061] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments.

[0062] Referring to Figure 3 , the first sub-pixel SP1 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line EL1, a second emission control line EL2, and a data line DL. Further, the first sub-pixel SP1 can be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0063] The first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.​​

[0064] The light emitting element LE emits light in response to a drive current flowing through a channel of the first transistor T1. An emission amount of the light emitting element LE can be proportional to the drive current. The light emitting element LE can be provided between the fourth transistor T4 (or the third node N3) and the first drive voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode thereof can be connected to the first drive voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode (OLED) including a first electrode, a second electrode, and an organic light emitting layer provided between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor provided between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0065] The first transistor T1 can be a drive transistor that controls a source-drain current (e.g., a drive current) flowing between a source electrode and a drain electrode thereof according to a voltage applied to a gate electrode thereof. The first transistor T1 includes the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0066] The second transistor T2 can be provided between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 includes the gate electrode connected to the write scan line GWL, the source electrode connected to the data line DL, and the drain electrode connected to the one electrode of the first capacitor CP1.

[0067] The third transistor T3 can be provided between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, because the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes the gate electrode connected to the control scan line GCL, the source electrode connected to the second node N2, and the drain electrode connected to the first node N1.

[0068] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0069] The fifth transistor T5 can be provided between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0070] The sixth transistor T6 can be provided between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0071] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0072] The second capacitor CP2 is formed between the gate electrode (or the first node N1) of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode (or the first node N1) of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0073] The first node N1 is a node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and the one electrode of the second capacitor CP2. The second node N2 is a node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0074] Each of the first transistor T1 to the sixth transistor T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, and each of the remaining transistors can be an N-type MOSFET.

[0075] Although the first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors CP1 and CP2 in Figure 3 , it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the equivalent circuit diagram shown in Figure 3 . For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to the numbers shown in Figure 3 .

[0076] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in connection with Figure 3 . Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 is not repeated in the present disclosure.

[0077] Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments.

[0078] Referring to Figure 4 , the display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0079] The scan driver 610 can be disposed at a first side of the display area DAA, and the emission driver 620 can be disposed at a second side of the display area DAA. For example, the scan driver 610 can be disposed at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be disposed at the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed at the left side of the display area DAA, and the emission driver 620 can be disposed at the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 can be disposed at both the first side and the second side of the display area DAA.

[0080] The first pad portion PDA1 can include a plurality of first pads PD1 connected to the pads or bumps of the circuit board 300 through conductive adhesive members. The first pad portion PDA1 can be disposed at a third side of the display area DAA. For example, the first pad portion PDA1 can be disposed at one side of the display area DAA in the second direction DR2.

[0081] The first pad portion PDA1 can be disposed outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 can be disposed closer to the edge of the display panel 100 than the data driver 700.

[0082] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to check pads for checking whether the display panel 100 operates normally. The plurality of second pads PD2 can be connected to a jig or a probe in a checking process, or can be connected to a circuit board for checking. The circuit board for checking can be a printed circuit board (PCB) made of a rigid material or a flexible printed circuit board (FPCB) made of a flexible material.

[0083] The first distribution circuit 710 distributes data voltages applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute data voltages applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 can be disposed at the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed at one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed at the lower side of the display area DAA.

[0084] The second distribution circuit 720 distributes a signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed at another side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed at an upper side of the display area DAA.

[0085] Figure 5 and Figure 6 is a layout diagram illustrating an embodiment of the display area of Figure 4

[0086] Referring to Figure 5 and Figure 6 , each of the pixels PX includes a first emission area EA1 that is an emission area of the first sub-pixel SP1, a second emission area EA2 that is an emission area of the second sub-pixel SP2, and a third emission area EA3 that is an emission area of the third sub-pixel SP3.

[0087] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in a plan view.

[0088] A maximum length of the third emission area EA3 in the first direction DR1 can be less than a maximum length of the first emission area EA1 in the first direction DR1 and a maximum length of the second emission area EA2 in the first direction DR1. The maximum length of the first emission area EA1 in the first direction DR1 and the maximum length of the second emission area EA2 in the first direction DR1 can be substantially the same.

[0089] A maximum length of the third emission area EA3 in the second direction DR2 can be greater than a maximum length of the first emission area EA1 in the second direction DR2 and a maximum length of the second emission area EA2 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be greater than the maximum length of the second emission area EA2 in the second direction DR2.

[0090] The first emission area EA1, the second emission area EA2, and the third emission area EA3 can have shapes as illustrated in Figure 6 ​The first, second, and third emission areas EA1, EA2, and EA3 may have polygonal, circular, elliptical, and / or irregular shapes other than a hexagonal shape in a plan view.

[0091] like Figure 5 As shown in FIG, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different.

[0092] Alternatively, as Figure 6 As shown in FIG, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2. The second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0093] The first emission area EA1 can emit light of a first color, the second emission area EA2 can emit light of a second color, and the third emission area EA3 can emit light of a third color. Here, the first color light can be light in a blue wavelength band, the second color light can be light in a green wavelength band, and the third color light can be light in a red wavelength band. For example, the blue wavelength band can be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band can be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band can be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0094] exist Figure 5 and Figure 6 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0095] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to Figure 5 andFigure 6 The emission regions of the plurality of pixels PX can be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, a PENTILE structure in which the emission regions are arranged in a diamond shape, or a hexagonal structure in which the emission regions have a hexagonal shape in a plan view, as illustrated in FIGS. 1A to 1C. ® The emission regions of the plurality of pixels PX can be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, a PENTILE structure in which the emission regions are arranged in a diamond shape, or a hexagonal structure in which the emission regions have a hexagonal shape in a plan view, as illustrated in FIGS. 1A to 1C. Figure 6 The emission regions of the plurality of pixels PX can be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, a PENTILE structure in which the emission regions are arranged in a diamond shape, or a hexagonal structure in which the emission regions have a hexagonal shape in a plan view, as illustrated in FIGS. 1A to 1C. ® PENTILE is a registered trademark of Samsung Display Co., Ltd.

[0096] Figure 7 is a cross-sectional view illustrating an example of the display panel taken along a line I1-I1' of Figure 5

[0097] Referring to Figure 7 , the display panel 100 includes a semiconductor backplane SBP, an emission element backplane EBP, a display element layer EML, a sealing layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0098] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the first to sixth transistors T1 to T6 described with reference to Figure 3

[0099] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. A plurality of well regions WA can be disposed on a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0100] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode thereof, and a channel region CH disposed between the source region SA and the drain region DA.

[0101] A bottom insulating film BINS can be disposed between the gate electrode GE and the well region WA. A side insulating film SINS can be disposed on a side surface of the gate electrode GE. The side insulating film SINS can be disposed on the bottom insulating film BINS.

[0102] ​​Each of the source region SA and the drain region DA can be a region doped with a first type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be provided on one side of the gate electrode GE, and the drain region DA can be provided on the other side of the gate electrode GE.

[0103] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 provided between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 provided between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. A distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, a length of the channel region CH of each of the pixel transistors PTR can be increased, so that a punch-through phenomenon and a hot carrier phenomenon that can be caused by a short channel can be reduced or prevented.

[0104] The first semiconductor insulating film SINS1 can be provided on the semiconductor substrate SSUB and the gate electrode GE of the pixel transistor PTR. The first semiconductor insulating film SINS1 can be formed of a silicon carbon nitride (SiCN) and / or a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0105] The second semiconductor insulating film SINS2 can be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0106] The plurality of contact terminals CTE can be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole that penetrates the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), or an alloy including one or more of them.

[0107] A third semiconductor insulating film SINS3 can be provided on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0108] The semiconductor substrate SSUB can be replaced with a glass substrate and / or a polymer resin substrate such as polyimide. In this case, thin film transistors can be provided on the glass substrate and / or the polymer resin substrate. The glass substrate can be a non-flexible rigid substrate, and the polymer resin substrate can be a flexible substrate that can be bent and / or folded.

[0109] The light emitting element backplane EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. In the light emitting element backplane EBP, the plurality of insulating films INS1 to INS9 can be provided between the first conductive layer ML1 and the eighth conductive layer ML8.

[0110] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect the plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing the circuit of the first sub-pixel SP1 shown in FIG. 1B. For example, the first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection of the first transistor T1 to the sixth transistor T6 to the first capacitor C1 and the second capacitor C2 is realized through the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE is also realized through the first conductive layer ML1 to the eighth conductive layer ML8. Figure 3 The first insulating film INS1 can be provided on the semiconductor backplane SBP. Each of the first vias VA1 can penetrate the first insulating film INS1 and be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 can be provided on the first insulating film INS1 and can be connected to the first via VA1.

[0111] The second insulating film INS2 can be provided on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and can be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be provided on the second insulating film INS2 and can be connected to the second via VA2.

[0112]

[0113] ​A third insulating film INS3 can be provided over the second insulating film INS2 and the second conductive layer ML2. Each of third vias VA3 can penetrate the third insulating film INS3 and can be connected to the exposed second conductive layer ML2. Each of third conductive layers ML3 can be provided over the third insulating film INS3 and can be connected to the third via VA3.

[0114] A fourth insulating film INS4 can be provided over the third insulating film INS3 and the third conductive layer ML3. Each of fourth vias VA4 can penetrate the fourth insulating film INS4 and can be connected to the exposed third conductive layer ML3. Each of fourth conductive layers ML4 can be provided over the fourth insulating film INS4 and can be connected to the fourth via VA4.

[0115] A fifth insulating film INS5 can be provided over the fourth insulating film INS4 and the fourth conductive layer ML4. Each of fifth vias VA5 can penetrate the fifth insulating film INS5 and can be connected to the exposed fourth conductive layer ML4. Each of fifth conductive layers ML5 can be provided over the fifth insulating film INS5 and can be connected to the fifth via VA5.

[0116] A sixth insulating film INS6 can be provided over the fifth insulating film INS5 and the fifth conductive layer ML5. Each of sixth vias VA6 can penetrate the sixth insulating film INS6 and can be connected to the exposed fifth conductive layer ML5. Each of sixth conductive layers ML6 can be provided over the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0117] A seventh insulating film INS7 can be provided over the sixth insulating film INS6 and the sixth conductive layer ML6. Each of seventh vias VA7 can penetrate the seventh insulating film INS7 and can be connected to the exposed sixth conductive layer ML6. Each of seventh conductive layers ML7 can be provided over the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0118] An eighth insulating film INS8 can be provided over the seventh insulating film INS7 and the seventh conductive layer ML7. Each of eighth vias VA8 can penetrate the eighth insulating film INS8 and can be connected to the exposed seventh conductive layer ML7. Each of eighth conductive layers ML8 can be provided over the eighth insulating film INS8 and can be connected to the eighth via VA8.

[0119] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more of them. The first to eighth vias VA1 to VA8 can be made of substantially the same material. The first to eighth insulating films INS1 to INS8 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0120] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 1360 A. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 1440 A. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately 1150 A.

[0121] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 9000 A. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 6000 A.

[0122] The ninth insulating film INS9 can be provided on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed of a silicon oxide (SiO x ) -based inorganic film, but the present disclosure is not limited thereto.

[0123] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and can be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. The thickness of the ninth via VA9 can be approximately 16500 A.

[0124] The display element layer EML can be provided on the light emitting element backplane EBP. The display element layer EML can include: a plurality of light emitting elements LE each including a first electrode AND, a light emitting stack IL, and a second electrode CAT; a reflective electrode layer RL; a tenth insulating film INS10 and an eleventh insulating film INS11; a tenth via VA10; a pixel definition film PDL; and a plurality of trenches TRC.

[0125] The reflective electrode layer RL can be provided on the ninth insulating film INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as shown in FIG. 1B, the reflective electrode layer RL can include first to fourth reflective electrodes RL1, RL2, RL3, and RL4. Figure 7

[0126] ​Each of the first reflective electrodes RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrodes RL1 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy or a compound including one or more of them. For example, the first reflective electrodes RL1 can include titanium nitride (TiN).

[0127] Each of the second reflective electrodes RL2 can be disposed on the first reflective electrodes RL1. The second reflective electrodes RL2 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more of them. For example, the second reflective electrodes RL2 can include aluminum (Al).

[0128] Each of the third reflective electrodes RL3 can be disposed on the second reflective electrodes RL2. The third reflective electrodes RL3 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy or a compound including one or more of them. For example, the third reflective electrodes RL3 can include titanium nitride (TiN).

[0129] Each of the fourth reflective electrodes RL4 can be disposed on the third reflective electrodes RL3. The fourth reflective electrodes RL4 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more of them. For example, the fourth reflective electrodes RL4 can include titanium (Ti).

[0130] Since the second reflective electrodes RL2 are electrodes that substantially reflect light from the light emitting elements LE, the thickness of the second reflective electrodes RL2 can be greater than the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4. For example, the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4 can be approximately 100 Å, and the thickness of the second reflective electrodes RL2 can be approximately 850 Å. However, in one or more embodiments, the thickness of the second reflective electrodes RL2 can be substantially the same as the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4.

[0131] The tenth insulating film INS10 can be provided on the ninth insulating film INS9. The tenth insulating film INS10 can be provided between the reflective electrode layers RL adjacent to each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). The tenth insulating film INS10 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0132] The eleventh insulating film INS11 can be provided on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be an optical auxiliary layer through which light reflected by the reflective electrode layer RL among light emitted from the light emitting element LE passes.

[0133] In one or more embodiments, the tenth insulating film INS10 can be provided on the reflective electrode layer RL. In order to match a resonance distance of light emitted from the light emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating film INS10 or the eleventh insulating film INS11 can not be provided under the first electrode AND. For example, in one or more embodiments, the first electrode AND of the first sub-pixel SP1 can be directly provided on the reflective electrode layer RL. The eleventh insulating film INS11 can be provided under the first electrode AND of the second sub-pixel SP2. In one or more embodiments, the tenth insulating film INS10 and the eleventh insulating film INS11 can be provided under the first electrode AND of the third sub-pixel SP3. However, in one or more embodiments, in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the eleventh insulating film INS11 can be provided under the first electrode AND, and a thickness of the eleventh insulating film INS11 in the third direction DR3 can be different in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0134] In summary, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first, second, and third subpixels SP1, SP2, and SP3. That is, to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first, second, and third subpixels SP1, SP2, and SP3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 may be set in each of the first, second, and third subpixels SP1, SP2, and SP3, or the thickness of the eleventh insulating film INS11 may be adjusted in each of the first, second, and third subpixels SP1, SP2, and SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1. The present disclosure is not limited to the above examples.

[0135] In addition, although the tenth insulating film INS10 and the eleventh insulating film INS11 are shown in the present disclosure, a twelfth insulating film disposed under the first electrode AND of the first sub-pixel SP1 may be added. In this case, the eleventh insulating film INS11 and the twelfth insulating film may be disposed under the first electrode AND of the second sub-pixel SP2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be disposed under the first electrode AND of the third sub-pixel SP3.

[0136] Each of the tenth via holes VA10 may penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the first, second, and third sub-pixels SP1, SP2, and SP3, and may be connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. The thickness of the tenth via hole VA10 in the second sub-pixel SP2 may be thinner than that of the tenth via hole VA10 in the third sub-pixel SP3, and the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be thinner than that of the tenth via hole VA10 in the second sub-pixel SP2.

[0137] The first electrode AND of each of the light emitting elements LE can be provided on the eleventh insulating film INS11 and connected to the tenth via hole VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via holes VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy or a compound including one or more of them. For example, the first electrode AND of each of the light emitting elements LE can be titanium nitride (TiN).

[0138] The pixel defining film PDL can be provided on a part of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL can cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL can be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0139] The first emission area EA1 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0140] The pixel defining film PDL can include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 can be provided on an edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining film PDL2 can be provided on the first pixel defining film PDL1, and the third pixel defining film PDL3 can be provided on the second pixel defining film PDL2. The first to third pixel defining films PDL1, PDL2, and PDL3 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto. The first to third pixel defining films PDL1, PDL2, and PDL3 can each have a thickness of about 500 Å.

[0141] When the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are formed as one pixel definition film, the height of the one pixel definition film increases, so that the first encapsulation inorganic film TFE1 can be cut off due to a step coverage. The step coverage refers to a ratio of a degree of coating a thin film on an inclined portion to a degree of coating a thin film on a flat portion. The lower the step coverage, the more likely the thin film will be cut off at the inclined portion.

[0142] Therefore, in order to reduce or prevent the possibility that the first encapsulation inorganic film TFE1 is cut off due to the step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure having a step portion. For example, the width of the first pixel definition film PDL1 can be greater than the width of the second pixel definition film PDL2 and the width of the third pixel definition film PDL3, and the width of the second pixel definition film PDL2 can be greater than the width of the third pixel definition film PDL3. The width of the first pixel definition film PDL1 refers to a horizontal length of the first pixel definition film PDL1 defined in the first direction DR1 and the second direction DR2.

[0143] Each of the plurality of trenches TRC can penetrate the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. In addition, each of the plurality of trenches TRC can also penetrate the eleventh insulating film INS11. In one or more embodiments, the tenth insulating film INS10 can be partially recessed at each of the plurality of trenches TRC.

[0144] At least one trench TRC can be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Although two trenches TRC are shown to be disposed between adjacent sub-pixels SP1, SP2, and SP3, the present disclosure is not limited thereto.

[0145] The light emitting stack IL can include a plurality of intermediate layers. Figure 7 Although the light emitting stack IL is shown to have a triple series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3, the present disclosure is not limited thereto. For example, the light emitting stack IL can have a double series structure including two intermediate layers.

[0146] In the triple series structure, the light emitting stack IL can have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different light. For example, the light emitting stack IL can include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a second color, and a third stack layer IL3 that emits light of a third color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be sequentially stacked.

[0147] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0148] A first charge generation layer for supplying holes to the second stack layer IL2 and supplying electrons to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer supplying electrons to the first stack layer IL1 and a P-type charge generation layer supplying holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metallic material.

[0149] A second charge generation layer for supplying holes to the third stack layer IL3 and supplying electrons to the second stack layer IL2 can be disposed between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer supplying electrons to the second stack layer IL2 and a P-type charge generation layer supplying holes to the third stack layer IL3.

[0150] The first stack layer IL1 can be disposed on the first electrode AND and the pixel definition film PDL, and can be disposed on a bottom surface of each of the trenches TRC. The first stack layer IL1 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The second stack layer IL2 can be disposed on the first stack layer IL1. The second stack layer IL2 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The cavity ESS or empty space can be disposed between the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 can be disposed on the second stack layer IL2. The third stack layer IL3 is not cut by the trenches TRC, and can be disposed to cover the second stack layer IL2 in each of the trenches TRC. That is, in the triple tandem structure, each of the plurality of trenches TRC can be a structure for cutting the first stack layer IL1 and the second stack layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3. In addition, in the double tandem structure, each of the trenches TRC can be a structure for cutting the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0151] To stably cut the first and second stacked layers IL1 and IL2 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trenches TRC can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To cut the first and second stacked layers IL1 and IL2 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, there can be another structure instead of the trenches TRC. For example, instead of the trenches TRC, an inverted taper-shaped partition wall can be provided on the pixel defining film PDL.

[0152] The number of the stacked layers IL1, IL2, and IL3 that emit different light is not limited to the number shown in Figure 7 FIG. 1. For example, the light emitting stack IL can include two intermediate layers. In this case, one of the two intermediate layers can be substantially the same as the first stacked layer IL1, and the other can include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer can be provided between the two intermediate layers.

[0153] In addition, Figure 7 It is shown that the first to third stacked layers IL1, IL2, and IL3 are all provided in the first, second, and third emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. For example, the first stacked layer IL1 can be provided in the first emission area EA1, and can be omitted from the second and third emission areas EA2 and EA3. Also, the second stacked layer IL2 can be provided in the second emission area EA2, and can be omitted from the first and third emission areas EA1 and EA3. Also, the third stacked layer IL3 can be provided in the third emission area EA3, and can be omitted from the first and second emission areas EA1 and EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0154] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmitting transparent conductive material (TCO) such as ITO and / or IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0155] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen and / or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0156] The first encapsulation inorganic film TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic film TFE1 may be formed of a material selected from silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ) are alternately stacked. The first encapsulation inorganic film TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0157] The second encapsulation inorganic film TFE2 may be provided on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 may be made of titanium oxide (TiO x ) and / or aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The second encapsulation inorganic film TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 may be less than the thickness of the first encapsulation inorganic film TFE1.

[0158] The organic film APL may be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0159] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filler layer FIL. The plurality of color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the organic film APL.

[0160] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color (i.e., light in the blue wavelength band). The blue wavelength band may be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0161] The second color filter CF2 may overlap the second emission area EA2 of the second subpixel SP2. The second color filter CF2 may transmit light of the second color (i.e., light in the green wavelength band). The green wavelength band may be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0162] The third color filter CF3 may overlap the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit light of a third color (i.e., light in a red wavelength band). The red wavelength band may be approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0163] A plurality of lenses LNS may be provided on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction (e.g., a third direction DR3).

[0164] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0165] The cover layer CVL can be disposed on the filling layer FIL. The cover layer CVL can be a glass substrate and / or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filling layer FIL. In this case, the filling layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can serve as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filling layer FIL.

[0166] A polarizing plate POL can be disposed on one surface of the cover layer CVL. The polarizing plate POL can be a structure for reducing or preventing visibility deterioration caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and / or a phase retardation film. For example, the phase retardation film can be a λ / 4 wave plate (e.g., a quarter wave plate), but the present disclosure is not limited thereto. However, when visibility deterioration caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizing plate can be omitted.

[0167] Figure 8 is a perspective view illustrating a head-mounted display according to one or more embodiments. Figure 9 is an exploded perspective view illustrating an example of the head-mounted display of Figure 8

[0168] Referring to Figure 8 and Figure 9 , the head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600. In Figure 8 and Figure 9 , the X direction, the Y direction, and the Z direction can be similar to the aforementioned first direction DR1, the second direction DR2, and the third direction DR3, respectively, and detailed descriptions thereof will be omitted.

[0169] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Since each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in connection with Figure 1 and Figure 2 , descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0170] The first optical member 1510 can be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0171] ​The middle frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0172] The control circuit board 1600 can be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA (see Figure 2 ) to the first display device 10_1 and the second display device 10_2 through the connectors.

[0173] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1 and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0174] The display device housing 1100 serves to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is disposed to cover one open surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 at which the left eye of the user is positioned and a second eyepiece 1220 at which the right eye of the user is positioned. Figure 8 and Figure 9 It is illustrated that the first eyepiece 1210 and the second eyepiece 1220 are separately disposed, but the disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0175] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210 and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0176] The head-mounted band 1300 serves to fix the display device housing 1100 to the head of a user so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively held to be positioned on the left eye and the right eye of the user. When the display device housing 1100 is implemented to be light and compact, the head-mounted display 1000 can be provided with a spectacle frame as shown in FIG. 1B instead of the head-mounted band 1300. Figure 10

[0177] In addition, the head-mounted display 1000 can further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port for receiving an image source and a wireless communication module. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0178] Figure 10 FIG. 1A is a perspective view illustrating a head-mounted display according to one or more embodiments.

[0179] Referring to Figure 10 , the head-mounted display 1000_1 according to one or more embodiments can be a spectacle-type display device in which the display device housing 1200_1 is implemented in a light and compact manner. The head-mounted display 1000_1 according to one or more embodiments can include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temple pieces 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0180] The display device housing 1200_1 can accommodate the display device 10_3, the optical member 1060, and the optical path changing member 1070. An image displayed on the display device 10_3 can be enlarged by the optical member 1060 and can be provided to the right eye of the user through the right eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image seen through the right eye lens 1020 are combined through the right eye.

[0181] Figure 10 ​The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030. In this case, the image of the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030. In this case, the user can view the image displayed on the display device 10_3 with both the left and right eyes.

[0182] In the display panel 100 (see Figure 4 ), as the distance between the sub-pixels SP1, SP2, and SP3 decreases, it is possible that adjacent sub-pixels SP1, SP2, and SP3 (see Figure 7 ) between the sub-pixels SP1, SP2 and SP3. Figure 7 ) and the second electrode CAT (see Figure 7 ) between the light emitting stack IL (see Figure 7 ) generates leakage current in some conductive layers. It is known that leakage current is the cause of color crosstalk between adjacent sub-pixels SP1, SP2, and SP3.

[0183] exist Figure 7 In the embodiment of the present invention, a through pixel definition film PDL (see FIG. Figure 7 ) of multiple groove TRC (see Figure 7 ), the light emitting stack IL is disconnected at the plurality of trenches TRC during a deposition process of the light emitting stack IL. Due to the plurality of trenches TRC, the light emitting stack IL is disconnected around the plurality of trenches TRC according to a step coverage characteristic.

[0184] Refer to below Figures 11 to 30 In various embodiments of the present disclosure, Figure 7 Unlike the embodiment, a first wiring 1720 is formed between adjacent sub-pixels SP1, SP2 and SP3 (see FIG. Figure 11 ), and after the light-emitting stack IL is entirely deposited, a suitable voltage (e.g., a preset voltage) is applied to the first wiring 1720 to disconnect the light-emitting stack IL. When the voltage is applied to the first wiring 1720, the first wiring 1720 is heated, and the heated first wiring 1720 disconnects the light-emitting stack IL deposited therearound. This method of disconnecting the light-emitting stack IL using the first wiring 1720 that emits heat can be referred to as a "Joule heating method."

[0185] In the disclosure, the first wiring 1720 can be replaced by terms such as "heating wiring", "dummy wiring", and / or "Joule heating wiring", and the disclosure is not limited to the terms of the first wiring 1720.

[0186] Hereinafter, a display device 10 (see Figure 1 ) in which a light emitting stack IL is disconnected between adjacent sub-pixels SP1, SP2, and SP3 by using a Joule heating method according to one or more embodiments and a manufacturing method thereof will be described.

[0187] Figure 11 is a cross-sectional view schematically showing a display element layer of a display panel according to one or more embodiments. For example, Figure 11 At least a portion of the display element layer EML shown in Figure 7 may be similar to at least a portion of the display element layer EML of the display panel 100 shown in Figure 11 . Other layers (e.g., structures above the display element layer EML and structures below the display element layer EML) other than the display element layer EML shown in Figure 7 may be substantially the same as the structure of the display panel 100 shown in Figure 11 . Therefore, the description of other layers (e.g., structures above the display element layer EML and structures below the display element layer EML) other than the display element layer EML shown in Figure 7 will be replaced by the description with reference to

[0188] With reference to Figure 11 , unlike the embodiments of Figure 7 , the display element layer EML according to one or more embodiments includes the first wiring 1720 that emits heat when a suitable voltage (e.g., a preset voltage) is applied thereto, but does not include a trench TRC (see Figure 7 ).

[0189] The display element layer EML includes a reflective electrode layer RL disposed on a ninth insulating film INS9 of a light emitting element back plate EBP, a differential film 1710 covering the reflective electrode layer RL, first electrodes AND1, AND2, and AND3 and a pixel definition film PDL disposed on the differential film 1710, a first wiring 1720 disposed on the pixel definition film PDL between adjacent sub-pixels SP1, SP2, and SP3, a light emitting stack IL deposited on the pixel definition film PDL on which the first wiring 1720 is disposed and disconnected around the first wiring 1720, and a second electrode CAT deposited on the light emitting stack IL and the first wiring 1720.

[0190] The reflective electrode layer RL can include, for example, a first reflective electrode RL1, a second reflective electrode RL2, and a third reflective electrode RL3, which are sequentially stacked.

[0191] The first reflective electrode RL1 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more of them.

[0192] The second reflective electrode RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more of them.

[0193] The third reflective electrode RL3 can be disposed on the second reflective electrode RL2. The third reflective electrode RL3 can include a metal having high reflectivity to facilitate reflection of light. The third reflective electrode RL3 can be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, which is an alloy of silver (Ag), palladium (Pd), and copper (Cu), and / or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the disclosure is not limited thereto.

[0194] The differential film 1710 can be disposed on and around the reflective electrode layer RL. The differential film 1710 can include a first differential film 1711 and a second differential film 1712 disposed on the first differential film 1711. The differential film 1710 can be commonly stacked in the first sub-pixel SP1 and the second sub-pixel SP2, but can not be stacked in the third sub-pixel SP3. The differential film 1710 serves to change a distance between the first electrode AND and the reflective electrode layer RL for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0195] In the first sub-pixel SP1, the first differential film 1711, the second differential film 1712, and the first electrode AND1 of the first sub-pixel SP1 can be sequentially stacked on the reflective electrode layer RL.

[0196] In the second sub-pixel SP2, the second differential film 1712 and the first electrode AND2 of the second sub-pixel SP2 can be sequentially stacked on the reflective electrode layer RL.

[0197] In the third sub-pixel SP3, the first electrode AND3 of the third sub-pixel SP3 can be disposed on the reflective electrode layer RL.

[0198] The distance between the first electrode AND and the reflective electrode layer RL can be different for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL can be longest in the first sub-pixel SP1 and shortest in the third sub-pixel SP3 due to the thickness difference of the differential film 1710.

[0199] According to one or more embodiments, a pixel defining film PDL that bounds the sub-pixels SP1, SP2, and SP3 is disposed on the first electrodes AND1, AND2, and AND3 and the differential film 1710. The pixel defining film PDL is disposed to cover both ends of the first electrodes AND1, AND2, and AND3 of the respective sub-pixels SP1, SP2, and SP3. In an opening OP of the pixel defining film PDL, each of the first electrodes AND1, AND2, and AND3 is disposed to be partially exposed during a process.

[0200] The first wiring 1720 is disposed on the pixel defining film PDL between adjacent sub-pixels SP1, SP2, and SP3. The first wiring 1720 can be disposed around (e.g., surrounding) the first electrodes AND1, AND2, and AND3 of the respective sub-pixels SP1, SP2, and SP3. The first wiring 1720 can receive a suitable voltage (e.g., a preset voltage) through a pad disposed in a non-display area NDA of the display panel 100. Figure 4 The suitable voltage (e.g., the preset voltage) is applied to the first wiring 1720 when the light emitting stack IL is deposited on the first electrodes AND1, AND2, and AND3, the first wiring 1720, and the pixel defining film PDL.

[0201] The light emitting stack IL can include at least one conductive layer that is broken on and around the first wiring 1720. Here, the broken conductive layer of the light emitting stack IL includes at least one of a hole injection layer (e.g., HIL), a hole transport layer (e.g., HTL), an electron transport layer (e.g., ETL), a charge generation layer (e.g., CGL), and a P-doped layer (e.g., PHIL).

[0202] The light emitting stack IL can include at least one conductive layer that is broken on and around the first wiring 1720. Here, the broken conductive layer of the light emitting stack IL includes at least one of a hole injection layer (e.g., HIL), a hole transport layer (e.g., HTL), an electron transport layer (e.g., ETL), a charge generation layer (e.g., CGL), and a P-doped layer (e.g., PHIL).

[0203] In one or more embodiments of the present disclosure, in order to facilitate the disconnection of the light emitting stack IL when a voltage is applied to the first wiring 1720 to disconnect the light emitting stack IL, the pixel definition film PDL is designed to have a cross-sectional shape of a suitable first pattern (e.g., a predetermined first pattern) around the first wiring 1720, and the first wiring 1720 is designed to have a cross-sectional shape of a suitable second pattern (e.g., a predetermined second pattern). Details of the first pattern of the pixel definition film PDL and the second pattern of the first wiring 1720 will be described later with reference to Figures 18 to 30 The first pattern of the pixel definition film PDL and the second pattern of the first wiring 1720 are described in detail.

[0204] Figure 12 is a flowchart illustrating a method of manufacturing a display panel according to one or more embodiments. Figures 13 to 16 is a cross-sectional view illustrating a method of manufacturing a display element layer of a display panel according to one or more embodiments.

[0205] Hereinafter, a method of manufacturing a display element layer EML of a display panel 100 according to one or more embodiments will be described with reference to Figures 12 to 16

[0206] Referring to Figure 12 , in operation 1810, first electrodes AND (see Figure 7 ) of subpixels SP1, SP2, and SP3 (see Figure 7 ) and a pixel definition film PDL defining the subpixels SP1, SP2, and SP3 are formed. For example, the pixel definition film PDL (see Figure 11 ) defining the subpixels SP1, SP2, and SP3 (see Figure 11 ) is disposed on the first electrodes AND1, AND2, and AND3 (see Figure 11 ) and the differential film 1710 (see Figure 11 ). The pixel definition film PDL is disposed to cover both ends of the first electrodes AND1, AND2, and AND3 of the subpixels SP1, SP2, and SP3, and portions of the first electrodes AND1, AND2, and AND3 are disposed in openings OP (see Figure 11 ) of the pixel definition film PDL to be exposed during a process.

[0207] Referring to Figure 12 and Figure 13 , in operation 1820, the first wiring 1720 is formed on the pixel definition film PDL. The first wiring 1720 has a cross-sectional shape of a suitable second pattern (e.g., a predetermined second pattern).

[0208] Referring to Figure 12 and Figure 14 ​In operation 1830, a light emitting stack IL is deposited on the pixel definition layer PDL on which the first wiring 1720 is disposed. For example, the light emitting stack IL is deposited on the entire surface of the semiconductor substrate Ssub (see Figure 7 ). Thus, the light emitting stack IL is deposited on the first electrodes AND1, AND2, and AND3, the first wiring 1720, and the pixel definition layer PDL.

[0209] Referring to Figure 12 and Figure 15 , in operation 1840, the light emitting stack IL disposed between the adjacent sub-pixels SP1, SP2, and SP3 is removed by applying a suitable voltage (e.g., a preset voltage) to the first wiring 1720. The suitable voltage (e.g., the preset voltage) can be, for example, about 10 V to about 3000 V, but the present disclosure is not limited thereto. The temperature of the first wiring 1720 to which the suitable voltage (e.g., the preset voltage) is applied can increase to about 550 ℃. As indicated by reference numeral 1901 in Figure 15 , the first wiring 1720 whose temperature has been raised as described above can cause the light emitting stack IL deposited around it to be disconnected.

[0210] According to one or more embodiments of the present disclosure, in order to facilitate the disconnection of the light emitting stack IL when a voltage is applied to the first wiring 1720 to cause the light emitting stack IL to be disconnected, the pixel definition layer PDL is designed to have a suitable first pattern (e.g., a predetermined first pattern) of a cross-sectional shape around the first wiring 1720, and the first wiring 1720 is designed to have a suitable second pattern (e.g., a predetermined second pattern) of a cross-sectional shape. The first pattern of the pixel definition layer PDL and the second pattern of the first wiring 1720 will be described in detail later with reference to Figures 18 to 30 .

[0211] Referring to Figure 12 and Figure 16 , in operation 1850, a second electrode CAT is deposited. The second electrode CAT is commonly disposed in the plurality of sub-pixels SP1, SP2, and SP3. The second electrode CAT can be a common layer to which the plurality of sub-pixels SP1, SP2, and SP3 are connected to each other in the area between them. The second electrode CAT continuously extends while covering the light emitting stack IL in the opening OP of the pixel definition layer PDL and covering the first wiring 1720 and the light emitting stack IL between the adjacent sub-pixels SP1, SP2, and SP3.

[0212] As described above with reference to Figure 7 , the encapsulation layer TFE, the organic film APL, the optical layer OPL, the cover layer CVL, and the polarizing plate POL can be stacked on the second electrode CAT.

[0213] Figure 17 is a cross-sectional view schematically illustrating a first wire and a light emitting stack of a display panel according to a comparative example.

[0214] Referring to Figure 17 , the first wire 1720 according to the comparative example has a rectangular cross-sectional structure and includes a flat top surface. In the joule heating method according to the comparative example, heat generated from the first wire 1720 can not be concentrated in an upward direction of the first wire 1720, and thus, as indicated by reference numeral 2001 in Figure 17 , a defect in which the light emitting stack IL is not disconnected can occur. If the light emitting stack IL is not disconnected, a leakage current and color cross-talk that need to be addressed can occur.

[0215] Figure 18 and Figure 19 is a cross-sectional view schematically illustrating a pixel defining film and a first wire according to one or more embodiments.

[0216] Referring to Figure 18 and Figure 19 , the display panel 100 includes the first wire 1720 disposed on the pixel defining film PDL between the adjacent sub-pixels SP1, SP2, and SP3.

[0217] A top surface of the pixel defining film PDL around the first wire 1720 is not flat and has a cross-sectional shape of a suitable first pattern (e.g., a predetermined first pattern). In addition, a top surface of the first wire 1720 is also not flat and has a cross-sectional shape of a suitable second pattern (e.g., a predetermined second pattern).

[0218] The first pattern of the pixel defining film PDL includes a trench PDL_T in which the first wire 1720 is deposited. The trench PDL_T of the pixel defining film PDL disconnects the light emitting stack IL when the light emitting stack IL is deposited on the pixel defining film PDL due to a step coverage characteristic.

[0219] The second pattern of the first wire 1720 has a cross-sectional structure of a positive taper shape. For example, the first wire 1720 has a cross-sectional structure in which a width decreases as it goes from a bottom surface of the trench PDL_T toward a top thereof.

[0220] The second pattern of the first wire 1720 includes a triangular shape in which a width narrows as it goes from the bottom surface of the trench PDL_T toward the top thereof. Accordingly, the first wire 1720 has a sharp protruding portion 2002. When a suitable voltage (e.g., a preset voltage) is applied to the first wire 1720 to disconnect the light emitting stack IL, a temperature of the protruding portion 2002 of the first wire 1720 can be higher than a temperature of other portions of the first wire 1720. Accordingly, compared to Figure 17Compared to the embodiment of FIG. 1 , the portion 2003 of the light emitting stack IL deposited on the first wiring 1720 can be more easily disconnected.

[0221] In addition, if Figure 19 As shown in FIG, the first wiring 1720 includes a tapered side surface (ie, an inclined surface 2004). The inclined surface 2004 of the first wiring 1720 can increase the contact area between the first wiring 1720 and the deposition surface of the light emitting stack IL. Figure 17 Compared to the embodiment of FIG. 1 , the portion 2003 of the light emitting stack IL deposited on and around the first wiring 1720 can be more easily disconnected.

[0222] As described above, in the display panel 100 of the present disclosure, the pixel definition film PDL includes a cross-sectional structure of the first pattern, and the first wiring 1720 includes a cross-sectional structure of the second pattern. With this configuration, the appropriate voltage (e.g., preset voltage) for driving the first wiring 1720 can be reduced. In addition, even if the appropriate voltage (e.g., preset voltage) for driving the first wiring 1720 is fixed, the voltage is not affected by the voltage according to the embodiment of the present invention. Figure 17 The light emitting stack IL can also be disconnected more easily and stably compared to the Joule heating method of the comparative example shown in .

[0223] Figure 20 and Figure 21 is a conceptual diagram illustrating a method of forming a first wiring according to one or more embodiments.

[0224] Reference Figure 20 , the method of forming the first wiring 1720 may include a sputtering process. For example, the deposition substrate 2130 (eg, Figure 4 The display panel 100 in FIG. 2 is aligned to face the deposition source 2110. On the deposition substrate 2130 (eg, Figure 4 A deposition mask 2120 is provided between the display panel 100 in FIG. 1 and the deposition source 2110. The deposition mask 2120 may include an opening through which the deposition material emitted from the deposition source 2110 passes, and the opening may have a pointed structure. Thus, the first wiring 1720 has a tapered side surface (ie, an inclined surface 2004 ( Figure 19 ))'s cross-sectional structure has a positive conical shape.

[0225] Reference Figure 21The grooves 1721 and 1722 can be formed on the top surface of the first wiring 1720 by a dry etching process and / or a wet etching process after the first wiring 1720 is deposited on the pixel definition film PDL. For example, as indicated by reference numeral 2210, the first wiring 1720 can be deposited by performing a sputtering process on the pixel definition film PDL. Subsequently, as indicated by reference numeral 2220, a photoresist pattern 2221 including an opening 2222 can be formed on the first wiring 1720. The opening 2222 of the photoresist pattern 2221 can be formed to overlap the middle of the top surface of the first wiring 1720.

[0226] Subsequently, a dry etching process 2231 can be performed by using the photoresist pattern 2221 as a mask to form the groove 1721 on the top surface of the first wiring 1720, and the photoresist pattern 2221 is removed. Accordingly, the second pattern of the first wiring 1720 includes at least one groove 1721 formed on the top surface of the first wiring 1720. At this time, the bottom surface of the at least one groove 1721 formed on the top surface of the first wiring 1720 is flat.

[0227] Alternatively, a wet etching process 2232 can be performed by using the photoresist pattern 2221 as a mask to form the groove 1722 on the top surface of the first wiring 1720, and the photoresist pattern 2221 is removed. Accordingly, the second pattern of the first wiring 1720 includes at least one groove 1722 formed on the top surface of the first wiring 1720. The bottom surface of the at least one groove 1722 formed on the top surface of the first wiring 1720 is recessed.

[0228] Figures 22 to 30 FIG. 22 is a cross-sectional view schematically illustrating a pixel definition film and a first wiring according to various embodiments.

[0229] In the embodiment shown in Figure 22 , unlike the embodiment shown in Figure 18 , the second pattern of the first wiring 1720 includes a plurality of circular protrusions 1723 formed on the top surface of the first wiring 1720.

[0230] Referring to Figure 22 , the plurality of circular protrusions 1723 are formed on the top surface of the first wiring 1720. The circular protrusions 1723 of the first wiring 1720 increase the surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720. In the embodiment described above Figure 22 , since the surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720 is increased, the disconnection of the light emitting stack IL on and around the first wiring 1720 is facilitated.

[0231] In the embodiment shown in Figure 23 , unlike the embodiment shown in Figure 18 , the second pattern of the first wiring 1720 includes a plurality of triangular protrusions 1724 formed on a top surface of the first wiring 1720.

[0232] Referring to Figure 23 , the plurality of triangular protrusions 1724 are formed on the top surface of the first wiring 1720. The triangular protrusions 1724 can be referred to as "spikes." The triangular protrusions 1724 of the first wiring 1720 increase a surface area between the first wiring 1720 and a deposition surface of the light emitting stack IL deposited on the first wiring 1720. In the embodiment described above Figure 23 , due to the increased surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720, disconnection of the light emitting stack IL on and around the first wiring 1720 is facilitated.

[0233] In the embodiment shown in Figure 24 , unlike the embodiment shown in Figure 18 , the second pattern of the first wiring 1720 includes at least one groove 1721 or 1722 formed on a top surface of the first wiring 1720. A bottom surface of the at least one groove 1721 or 1722 formed on the top surface of the first wiring 1720 can be concave or flat.

[0234] Referring to Figure 24 , the at least one groove 1721 or 1722 is formed on the top surface of the first wiring 1720. As described with reference to Figure 21 , the groove 1721 or 1722 of the first wiring 1720 can be formed by a dry etching process 2231 or a wet etching process 2232. In the embodiment described above Figure 24 , due to the increased surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720, disconnection of the light emitting stack IL on and around the first wiring 1720 is facilitated.

[0235] In the embodiment shown in Figure 25 , unlike the embodiment shown in Figure 18 , the second pattern of the first wiring 1720 includes a plurality of triangular protrusions 1724 formed on a top surface of the first wiring 1720, and a groove 1721 is formed between adjacent triangular protrusions 1724.

[0236] Referring to Figure 25, the triangular protrusions 1724 can be referred to as "pegs." The triangular protrusions 1724 of the first wiring 1720 increase the surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720. As described with reference to Figure 21 , the grooves 1721 formed between adjacent triangular protrusions 1724 can be formed by a dry etching process 2231 or a wet etching process 2232. In Figure 25 , embodiments where the first wiring 1720 includes the second pattern, the surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720 is increased, facilitating the disconnection of the light emitting stack IL on and around the first wiring 1720.

[0237] In the embodiments shown in Figure 26 , unlike the embodiments shown in Figure 18 , the second pattern of the first wiring 1720 includes a plurality of triangular protrusions 1725 formed on the top surface and the side surface of the first wiring 1720.

[0238] Referring to Figure 26 , the triangular protrusions 1725 can be referred to as "pegs." The plurality of triangular protrusions 1725 formed on the top surface and the side surface of the first wiring 1720 increase the surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720. In Figure 26 , embodiments where the first wiring 1720 includes the second pattern, the surface area between the first wiring 1720 and the deposition surface of the light emitting stack IL deposited on the first wiring 1720 is increased, facilitating the disconnection of the light emitting stack IL on and around the first wiring 1720.

[0239] In the embodiments shown in Figure 27 , unlike the embodiments shown in Figure 18 , the trench formed in the pixel definition layer PDL includes a recessed bottom surface PDL_H. In Figure 27 , this embodiment, the light emitting stack IL can be disconnected due to a step coverage characteristic during a deposition process of the light emitting stack IL. In Figure 27 , embodiments, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to a step coverage characteristic of the pixel definition layer PDL. Thus, the disconnection of the light emitting stack IL around the first wiring 1720 is facilitated.

[0240] In the embodiments shown in Figure 28 , unlike the embodiments shown in Figure 18In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 28 In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 28 In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated.

[0241] In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 29 In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 18 In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated.

[0242] In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 30 In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 18 In the embodiment shown in FIG. 17, the first pattern of the pixel definition layer PDL includes a trench having a height lower than a height of the first wiring 1720, around (e.g., surrounding) the first wiring 1720, and having a recessed bottom surface PDL_H. In this embodiment, during a deposition process of the light emitting stack IL, the light emitting stack IL can be broken due to a step coverage characteristic of the pixel definition layer PDL. In the embodiment of FIG. 17, the thickness of the light emitting stack IL around the first wiring 1720 is relatively small according to the step coverage characteristic of the pixel definition layer PDL. Thus, the breaking of the light emitting stack IL around the first wiring 1720 is facilitated. Figure 30 Figure 30

[0243] It will be understood by those of ordinary skill in the art to which the present disclosure belongs that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it will be understood that the above-described embodiments are illustrative, not limiting. It will be understood that the scope of the present disclosure is defined by the claims and their equivalents, not the above detailed description, and all modifications and variations derived from the claims and their equivalents fall within the scope of the present disclosure.​​

Claims

1. A display device comprising: a substrate; and a display element layer over the substrate, wherein the display element layer includes: a pixel-defining film defining a plurality of sub-pixels; a first electrode of each of the plurality of sub-pixels in an opening of the pixel-defining film; a first wiring on the pixel-defining film between adjacent sub-pixels; a light-emitting stack on the first electrode and the pixel-defining film on which the first wiring is provided, and broken around the first wiring; and a second electrode on the light-emitting stack, wherein a top surface of the pixel-defining film around the first wiring is not flat and has a cross-sectional shape of a first pattern, and wherein a top surface of the first wiring is not flat and has a cross-sectional shape of a second pattern.

2. The display device according to claim 1, wherein The first pattern of the pixel-defining film includes a trench in which the first wiring is positioned.

3. The display device according to claim 2, wherein The second pattern of the first wiring has a cross-sectional structure of a positive taper shape.

4. The display device according to claim 3, wherein The second pattern of the first wiring has a triangular shape having a width that gradually narrows from a bottom surface of the trench to a top surface of the trench.

5. The display device according to claim 2, wherein The second pattern of the first wiring includes at least one groove at the top surface of the first wiring.

6. The display device of claim 5, wherein, A bottom surface of the at least one groove at the top surface of the first wiring is flat.

7. The display device according to claim 5, wherein A bottom surface of the at least one groove at the top surface of the first wiring is recessed.

8. The display device according to claim 2, wherein The second pattern of the first wiring includes a plurality of circular protrusions on the top surface of the first wiring.

9. The display device according to claim 2, wherein The second pattern of the first wiring includes a plurality of triangular protrusions on the top surface of the first wiring.

10. The display device of claim 9, wherein, The second pattern of the first wiring further includes a groove between adjacent triangular protrusions.

11. The display device according to claim 2, wherein The second pattern of the first wiring includes a plurality of triangular protrusions on a side surface and the top surface of the first wiring.

12. The display device according to claim 2, wherein The trench in the pixel-defining film has a recessed bottom surface.

13. The display device of claim 1, wherein, The first pattern of the pixel-defining film includes a trench having a height lower than a height of the first wiring, surrounding the first wiring, and having a recessed bottom surface.

14. The display device of claim 1, wherein, The first pattern of the pixel-defining film includes a convex top surface of the pixel-defining film.

15. The display device according to claim 1, wherein The first pattern of the pixel-defining film includes a plurality of circular protrusions on the top surface of the pixel-defining film, and wherein the first wiring is between adjacent circular protrusions.

16. A mobile electronic device comprising: a display panel including a substrate and a display element layer over the substrate, wherein the display element layer includes: a pixel-defining film defining a plurality of sub-pixels; a first electrode of each of the plurality of sub-pixels in an opening of the pixel-defining film; a first wiring on the pixel-defining film between adjacent sub-pixels; a light-emitting stack on the first electrode and the pixel-defining film on which the first wiring is provided, and broken around the first wiring; and a second electrode on the light-emitting stack, wherein a top surface of the pixel-defining film around the first wiring is not flat and has a cross-sectional shape of a first pattern, and a top surface of the first wiring is not flat and has a cross-sectional shape of a second pattern.

17. The mobile electronic device of claim 16, wherein, the first pattern of the pixel-defining film includes a trench in which the first wiring is positioned.

18. The mobile electronic device of claim 17, wherein, the second pattern of the first wiring has a cross-sectional structure of a positive taper shape.

19. The mobile electronic device of claim 18, wherein, the second pattern of the first wiring has a triangular shape having a width that gradually narrows from a bottom surface of the trench to a top surface of the trench.

20. The mobile electronic device of claim 17, wherein, the second pattern of the first wiring includes at least one groove at the top surface of the first wiring.

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