Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. In general, according to an embodiment, a display device includes: a first insulating layer; a first lower electrode on the first insulating layer and having a first peripheral portion; the second insulating layer is positioned on the first insulating layer; a second lower electrode on the second insulating layer and having a second peripheral portion; the third insulating layer is positioned on the second insulating layer; a third lower electrode on the third insulating layer and having a third peripheral portion; a rib layer that overlaps the first peripheral portion, the second peripheral portion, and the third peripheral portion and is formed of an inorganic material; a first organic layer on the first lower electrode; a second organic layer on the second lower electrode; a third organic layer on the third lower electrode; a first upper electrode on the first organic layer; a second upper electrode on the second organic layer; and a third upper electrode over the third organic layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-065970 filed on April 16, 2024, and incorporates by reference the entire disclosure of that Japanese Patent Application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a display device and a manufacturing method of a display device. BACKGROUND

[0004] In recent years, a display device to which an organic light emitting diode (OLED) is applied as a display element has been put into practical use. The display element has a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer emits light in response to a potential difference between the lower electrode and the upper electrode.

[0005] In order to realize a display device with a high aperture ratio, it is necessary to narrow the interval of the lower electrodes of adjacent display elements. However, it is difficult to sufficiently narrow the interval of the lower electrodes due to constraints in processing technology and the like. SUMMARY

[0006] Generally, according to an embodiment, a display device has a first insulating layer, a first lower electrode located above the first insulating layer and having a first peripheral portion, a second insulating layer located above the first insulating layer, a second lower electrode located above the second insulating layer and having a second peripheral portion, a third insulating layer located above the second insulating layer, a third lower electrode located above the third insulating layer and having a third peripheral portion, a rib layer overlapping the first peripheral portion, the second peripheral portion, and the third peripheral portion and formed of an inorganic material, a first organic layer located above the first lower electrode, a second organic layer located above the second lower electrode, a third organic layer located above the third lower electrode, a first upper electrode located above the first organic layer, a second upper electrode located above the second organic layer, and a third upper electrode located above the third organic layer.

[0007] Generally, according to the embodiment, in the manufacturing method of the display device, a first insulating layer is formed, a first lower electrode is formed over the first insulating layer, a second insulating layer is formed over the first insulating layer, a second lower electrode is formed over the second insulating layer, a third insulating layer is formed over the second insulating layer, a third lower electrode is formed over the third insulating layer, a rib layer overlapping a first peripheral portion of the first lower electrode, a second peripheral portion of the second lower electrode, and a third peripheral portion of the third lower electrode is formed, a first organic layer and a first upper electrode overlapping the first lower electrode, a second organic layer and a second upper electrode overlapping the second lower electrode, and a third organic layer and a third upper electrode overlapping the third lower electrode are formed.

[0008] According to the embodiment, a display device capable of achieving high aperture ratio and a manufacturing method of the display device can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a view showing a configuration example of a display device according to the first embodiment.

[0010] Figure 2 is a schematic top view showing an example of a layout of a sub-pixel.

[0011] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2 .

[0012] Figure 4 is a view showing an example of a layer structure applicable to a display element.

[0013] Figure 5 is a schematic cross-sectional view of the display device along the line V-V in Figure 2 .

[0014] Figure 6 is a schematic cross-sectional view of the display device along the line VI-VI in Figure 2 .

[0015] Figure 7 is a schematic cross-sectional view of the display device along the line VII-VII in Figure 2 .

[0016] Figure 8 is a schematic cross-sectional view showing a part of a manufacturing method of a display device according to the first embodiment.

[0017] Figure 9 is a schematic cross-sectional view showing a manufacturing step subsequent to Figure 8 .

[0018] Figure 10 is a schematic cross-sectional view showing a manufacturing step subsequent to Figure 9Fig. 1 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0019] Figure 11 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 10 Fig. 2 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0020] Figure 12 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 11 Fig. 3 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0021] Figure 13 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 12 Fig. 4 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0022] Figure 14 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 13 Fig. 5 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0023] Figure 15 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 14 Fig. 6 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0024] Figure 16 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 15 Fig. 7 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0025] Figure 17 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 16 Fig. 8 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0026] Figure 18 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 17 Fig. 9 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0027] Figure 19 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 18 Fig. 10 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0028] Figure 20 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 19 Fig. 11 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0029] Figure 21 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 20 Fig. 12 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0030] Figure 22 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 21 Fig. 13 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0031] Figure 23 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 22 Fig. 14 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0032] Figure 24 is a schematic cross-sectional view of a manufacturing process of a semiconductor device. Figure 23 Fig. 15 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.

[0033] Figure 25 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 24

[0034] Figure 26 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 25

[0035] Figure 27 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 26

[0036] Figure 28 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 27

[0037] Figure 29 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 28

[0038] Figure 30 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 29

[0039] Figure 31 is a schematic cross-sectional view showing a display device according to the second embodiment.

[0040] Figure 32 is a schematic cross-sectional view showing a display device according to the third embodiment.

[0041] Figure 33 is a schematic cross-sectional view showing a part of a manufacturing method of the display device according to the third embodiment.

[0042] Figure 34 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 33

[0043] Figure 35 is a schematic cross-sectional view showing a manufacturing process of the display device. Figure 34

[0044] Figure 36 is a schematic cross-sectional view showing a display device according to the fourth embodiment.

[0045] Figure 37 is a diagram showing an example of a layer structure applicable to the display element according to the fourth embodiment.

[0046] Figure 38 is a schematic cross-sectional view showing a display device according to the fifth embodiment.

[0047] Figure 39 is a schematic cross-sectional view showing a part of a manufacturing method of the display device according to the fifth embodiment. ​​​​​​​​DETAILED DESCRIPTION

[0048] A number of embodiments will be described with reference to the drawings.

[0049] The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the application are naturally included in the scope of the application. In addition, in the drawings, in order to make the explanation more clear, the width, thickness, shape, and the like of each portion are sometimes schematically represented compared to the actual ones, but this is merely an example and does not limit the explanation of the application. In addition, in the present specification and the drawings, a reference sign is attached to a constituent element that has the same or similar function as that of a constituent element described with respect to a drawing already appearing, and sometimes the repeated detailed explanation is appropriately omitted.

[0050] Note that, in the drawings, an X axis, a Y axis, and a Z axis orthogonal to each other are described as needed for the understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. In addition, the manner of observing various elements in parallel with the Z direction is referred to as plan view observation.

[0051] The display device related to each embodiment is an organic electroluminescent display device provided with an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, a car-mounted device, a tablet terminal, a smartphone, a portable telephone terminal, and a wearable terminal.

[0052] [First Embodiment]

[0053] Figure 1 is a view showing a configuration example of a display device DSP related to an embodiment. The display device DSP is provided with a substrate 10 that is insulating. The substrate 10 has a display region DA for displaying an image and a peripheral region SA around the display region DA. The substrate 10 can be glass or a resin film having flexibility.

[0054] In the present embodiment, the shape of the substrate 10 in plan view observation is rectangular. However, the shape of the substrate 10 in plan view observation is not limited to a rectangle, and can be a square, a circle, or another shape such as an ellipse.

[0055] The display region DA is provided with a plurality of pixels PX arranged in a matrix shape along the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP for displaying different colors. In the present embodiment, a case is assumed in which the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. However, the pixel PX can include a sub-pixel SP of another color such as white, together with or instead of any one of the sub-pixels SP1, SP2, SP3.

[0056] The sub-pixel SP has a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 has a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are, for example, switching elements constituted by thin film transistors.

[0057] In the display region DA, a plurality of scan lines GL that supply a scan signal to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines SL that supply an image signal to the pixel circuit 1 of each sub-pixel SP, and a plurality of power supply lines PL are arranged. In the display region DA, the plurality of sub-pixels SP are arranged in a matrix form. Figure 1 In the example shown in FIG. 1, the scan lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0058] The gate electrode of the pixel switch 2 is connected to the scan line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power supply line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0059] Note that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 can have more thin film transistors and capacitors.

[0060] Figure 2 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, and SP3. In the example shown in FIG. 2, the sub-pixels SP1 and SP2 are arranged in the X direction, and the sub-pixel SP3 is arranged in the Y direction. Figure 2 In the example shown in FIG. 1, the scan lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0061] In the case where the sub-pixels SP1, SP2, and SP3 are arranged in this manner, in the display region DA, a column in which the sub-pixels SP1 and SP2 are alternately arranged in the Y direction, and a column in which a plurality of sub-pixels SP3 are repeatedly arranged in the Y direction are formed. These columns are alternately arranged in the X direction. Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example shown in FIG. 2. Figure 2

[0062] In the display region DA, a rib layer 5 is arranged. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example shown in FIG. 3, the pixel openings AP1 and AP2 are arranged in the X direction, and the pixel opening AP3 is arranged in the Y direction. Figure 2 ​In the example, pixel opening AP3 is larger than pixel opening AP2, and pixel opening AP2 is larger than pixel opening AP1. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP3 has the largest aperture ratio, while sub-pixel SP1 has the smallest aperture ratio. It should be noted that the sizes of pixel openings AP1, AP2, and AP3 are not limited to this example. For example, pixel openings AP1 and AP2 may also have the same size.

[0063] Subpixel SP1 includes a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer), which overlap with pixel opening AP1. Subpixel SP2 includes a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer), which overlap with pixel opening AP2. Subpixel SP3 includes a lower electrode LE3 (third lower electrode), an upper electrode UE3 (third upper electrode), and an organic layer OR3 (third organic layer), which overlap with pixel opening AP3.

[0064] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of sub-pixel SP3. The display elements DE1, DE2, and DE3 may also include a cover layer, which will be described later. The rib layer 5 surrounds each of the aforementioned display elements DE1, DE2, and DE3.

[0065] The pixel circuit 1 of the sub-pixels SP1, SP2, and SP3 (see Figure 1 ) are respectively disposed below the lower electrodes LE1, LE2, and LE3. The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 via the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 via the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 via the contact hole CH3.

[0066] The partition wall 6 is arranged in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 as a whole. Figure 2In the example shown in FIG, the partition wall 6 has the same top-view shape as the rib layer 5. That is, the partition wall 6 has openings in each of the sub-pixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition wall 6 form a grid pattern when viewed from above, surrounding each of the display elements DE1, DE2, and DE3. Specifically, the rib layer 5 and the partition wall 6 surround the lower electrodes LE1, LE2, and LE3, the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3, respectively. The partition wall 6 serves as wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0067] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The pixel circuit 1, scanning lines GL, signal lines SL, power supply lines PL and other various circuits and wirings are shown.

[0068] The display device DSP includes insulating layers IL1, IL2, and IL3. The circuit layer 11 is covered by the insulating layer IL1 (first insulating layer). The insulating layer IL1 functions as a planarizing film that flattens the unevenness generated by the circuit layer 11. The lower electrode LE1 and the insulating layer IL2 (second insulating layer) are located on the insulating layer IL1. Figure 3 In the example shown, the lower electrode LE1 is separated from the insulating layer IL2. The lower electrode LE2 and the insulating layer IL3 (third insulating layer) are located on the insulating layer IL2. Figure 3 In the example shown, the lower electrode LE2 is separated from the insulating layer IL3. The lower electrode LE3 is located on the insulating layer IL3.

[0069] The lower electrode LE1 has a peripheral edge portion E1 (first peripheral edge portion), the lower electrode LE2 has a peripheral edge portion E2 (second peripheral edge portion), and the lower electrode LE3 has a peripheral edge portion E3 (third peripheral edge portion). Peripheral edge portion E1 overlaps with the insulating layer IL1 in the Z direction. Peripheral edge portion E2 overlaps with the insulating layers IL1 and IL2 in the Z direction. Peripheral edge portion E3 overlaps with the insulating layers IL1, IL2, and IL3 in the Z direction.

[0070] The rib layer 5 overlaps with the peripheral edges E1, E2, and E3. Figure 3 In the example shown, the rib layer 5 directly covers the peripheral portions E1, E2, and E3. Furthermore, the rib layer 5 covers the ends of the insulating layers IL2 and IL3. Furthermore, the rib layer 5 is in contact with the insulating layer IL1 between the lower electrodes LE1 and LE2, and between the lower electrodes LE2 and LE3.

[0071] The partition wall 6 includes a lower portion 61 having conductivity disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. Thus, both end portions of the upper portion 62 protrude from the side surfaces of the lower portion 61. The shape of such a partition wall 6 is called a cantilever shape. The peripheral edge portions E1, E2, E3 are located directly below the partition wall 6.

[0072] In Figure 3 In the example shown in FIG. 1, the lower portion 61 has a base layer 63 and a shaft layer 64. The base layer 63 is disposed on the rib layer 5 and is formed to be thinner than the shaft layer 64. The shaft layer 64 is disposed on the base layer 63. In addition, in the example shown in FIG. 1, both end portions of the base layer 63 protrude from the side surfaces of the shaft layer 64. Furthermore, the end portions of the base layer 63 are located between the end portions of the upper portion 62 and the side surfaces of the shaft layer 64 in plan view. The upper portion 62 is disposed on the shaft layer 64. Figure 3

[0073] The organic layer OR1 is disposed on the lower electrode LE1, and the upper electrode UE1 is disposed on the organic layer OR1. The organic layer OR1 covers the lower electrode LE1 through the pixel opening API. The upper electrode UE1 covers the organic layer OR1 and opposes the lower electrode LE1.

[0074] The organic layer OR2 is disposed on the lower electrode LE2, and the upper electrode UE2 is disposed on the organic layer OR2. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and opposes the lower electrode LE2.

[0075] The organic layer OR3 is disposed on the lower electrode LE3, and the upper electrode UE3 is disposed on the organic layer OR3. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and opposes the lower electrode LE3. In the example shown in FIG. 1, the organic layers OR1, OR2, OR3 are configured to emit light in different colors from each other. The upper electrodes UE1, UE2, UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6. Figure 3

[0076] The display element DE1 includes a cover layer CPI that covers the upper electrode UE1. The display element DE2 includes a cover layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cover layer CP3 that covers the upper electrode UE3. The cover layers CPI, CP2, CP3 each have a function as an optical adjustment layer that improves the extraction efficiency of light emitted by the organic layers OR1, OR2, OR3.

[0077] In the following description, a multilayer body including the organic layer OR1, the upper electrode UE1, and the cover layer CPI is referred to as a laminated film FL1, a multilayer body including the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is referred to as a laminated film FL2, and a multilayer body including the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is referred to as a laminated film FL3.​​

[0078] A portion of the layered film FL1 is positioned on the upper portion 62. This portion is separated from the portion in the layered film FL1 positioned around the barrier wall 6 (the portion constituting the display element DE1). Similarly, a portion of the layered film FL2 is positioned on the upper portion 62, and this portion is separated from the portion in the layered film FL2 positioned around the barrier wall 6 (the portion constituting the display element DE2). Further, a portion of the layered film FL3 is positioned on the upper portion 62, and this portion is separated from the portion in the layered film FL3 positioned around the barrier wall 6 (the portion constituting the display element DE3).

[0079] The sealing layers SE11, SE12, SE13 are provided in the sub-pixels SP1, SP2, SP3 so as to cover the layered films FL1, FL2, FL3, respectively. Specifically, the sealing layer SE11 continuously covers the cover layer CP1, the barrier wall 6 around the sub-pixel SP1. The sealing layer SE12 continuously covers the cover layer CP2, the barrier wall 6 around the sub-pixel SP2. The sealing layer SE13 continuously covers the cover layer CP3, the barrier wall 6 around the sub-pixel SP3.

[0080] In the example of Fig. 1, the layered film FL1 and the sealing layer SE11 on the barrier wall 6 between the sub-pixels SP1, SP2 are separated from the layered film FL2 and the sealing layer SE12 on the barrier wall 6. Further, the layered film FL1 and the sealing layer SE11 on the barrier wall 6 between the sub-pixels SP1, SP3 are separated from the layered film FL3 and the sealing layer SE13 on the barrier wall 6. Figure 3

[0081] The sealing layers SE11, SE12, SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2 and the sealing layer SE2 are at least continuously provided in the entire display region DA, and a portion thereof reaches the surrounding region SA.

[0082] A cover member such as a polarizing plate, a protective film, or a cover glass can also be provided on the resin layer RS2. Such a cover member can be adhered to the resin layer RS2 via an adhesive layer such as an OCA (Optical Clear Adhesive).

[0083] ​The insulating layer IL1 is formed of an organic insulating material such as polyimide. The insulating layers IL2, IL3, the rib layer 5, and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the insulating layers IL2, IL3, the rib layer 5 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin, acrylic resin, or the like, for example.

[0084] The lower electrodes LE1, LE2, LE3 have a reflective layer and a pair of conductive oxide layers covering the upper surface and the lower surface of the reflective layer, respectively. The reflective layer can be formed of a metal material excellent in light reflectivity such as silver. Each of the conductive oxide layers can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide), for example.

[0085] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), for example. The lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes, for example.

[0086] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material, for example. As the metal material of the bottom layer 63, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb) can be used, for example. As the metal material of the shaft layer 64, aluminum (Al), an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi) can be used, for example. Note that at least one of the bottom layer 63 and the shaft layer 64 can have a stacked structure of a plurality of layers. In addition, the shaft layer 64 can include a layer formed of an insulating material.

[0087] The upper portion 62 of the partition wall 6 has a stacked structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide, for example. As the metal material forming the lower layer, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used, for example. As the conductive oxide forming the upper layer, ITO or IZO can be used, for example. Note that the upper portion 62 can have a single-layer structure of a metal material. In addition, the upper portion 62 can include a layer formed of an insulating material.

[0088] A common voltage is supplied to the barrier ribs 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the side surface of the lower portion 61, respectively. The pixel voltages corresponding to the image signals of the signal lines SL are supplied to the lower electrodes LE1, LE2, LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, SP3, respectively.

[0089] Figure 4 is a view showing an example of a layer structure applicable to the display elements DE1, DE2, DE3. Note that here, a case where the lower electrodes LE1, LE2, LE3 correspond to anodes and the upper electrodes UE1, UE2, UE3 correspond to cathodes is described as an example.

[0090] The organic layer OR1 includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light emitting layer EM1, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL is positioned over the lower electrode LE1, the hole transport layer HTL is positioned over the hole injection layer HIL, the electron blocking layer EBL is positioned over the hole transport layer HTL, the light emitting layer EM1 is positioned over the electron blocking layer EBL, the hole blocking layer HBL is positioned over the light emitting layer EM1, the electron transport layer ETL is positioned over the hole blocking layer HBL, the electron injection layer EIL is positioned over the electron transport layer ETL, and the upper electrode UE1 is positioned over the electron injection layer EIL. The light emitting layer EM1 is formed of a material that emits light in a red wavelength region.

[0091] Note that the organic layer OR1 can include other functional layers such as a carrier-generating layer, in addition to the above-described functional layers, as necessary, and at least one of the above-described functional layers can be omitted.

[0092] The display element DE2 is formed in the same manner as the display element DE1, except that the organic layer OR2 between the lower electrode LE2 and the upper electrode UE2 includes a light emitting layer EM2 instead of the light emitting layer EM1. The display element DE3 is formed in the same manner as the display element DE1, except that the organic layer OR3 between the lower electrode LE3 and the upper electrode UE3 includes a light emitting layer EM3 instead of the light emitting layer EM1. The light emitting layer EM2 is formed of a material that emits light in a green wavelength region. The light emitting layer EM3 is formed of a material that emits light in a blue wavelength region.

[0093] Figure 5 is a cross-sectional view of the display device DSP along the line V-V in Figure 2 . In Figure 5 to Figure 7 , the substrate 10, the resin layers RS1 and RS2, and the sealing layer SE2 shown in Figure 3 are omitted.

[0094] The insulating layer IL1 has a contact hole CH1 (first contact hole) that overlaps with the lower electrode LE1 in the Z direction. The contact hole CH1 penetrates the insulating layer IL1. The lower electrode LE1 contacts the conductive layer CL included in the circuit layer 11 through the contact hole CH1. The conductive layer CL corresponds to, for example Figure 1 The source electrode or drain electrode of the driving transistor 3 is shown.

[0095] Figure 6 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line VI-VI in FIG. The insulating layer IL1 includes a contact hole CH21 (second contact hole) that overlaps with the lower electrode LE2 in the Z direction. The contact hole CH21 penetrates the insulating layer IL1. The insulating layer IL2 includes a contact hole CH22 (fourth contact hole) that overlaps with the contact hole CH21 in the Z direction. The contact hole CH22 penetrates the insulating layer IL2. The contact hole CH2 is composed of the contact holes CH21 and CH22. The lower electrode LE2 contacts the conductive layer CL through the contact hole CH2.

[0096] Figure 7 It is along Figure 2 Schematic cross-sectional view of the display device DSP taken along line VII-VII in FIG. The insulating layer IL1 includes a contact hole CH31 (third contact hole) that overlaps with the lower electrode LE3 in the Z direction. The contact hole CH31 penetrates the insulating layer IL1. The insulating layer IL2 includes a contact hole CH32 (fifth contact hole) that overlaps with the contact hole CH31 in the Z direction. The contact hole CH32 penetrates the insulating layer IL2. The insulating layer IL3 includes a contact hole CH33 (sixth contact hole) that overlaps with the contact holes CH31 and CH32 in the Z direction. The contact hole CH33 penetrates the insulating layer IL3. The contact hole CH3 is composed of the contact holes CH31, CH32, and CH33. The lower electrode LE3 contacts the conductive layer CL through the contact hole CH3.

[0097] Next, an example of a method for manufacturing the display device DSP will be described.

[0098] Figure 8 to Figure 30 1 is a schematic cross-sectional view showing a portion of a method for manufacturing the display device DSP according to the first embodiment. Figure 3 The substrate 10 is shown.

[0099] After forming the circuit layer 11 including the conductive layer CL on the substrate 10, as shown in FIG. Figure 8 As shown in FIG. 1 , an insulating layer IL1 is formed on the circuit layer 11. Figure 9 As shown in FIG. 1 , a resist R1 is disposed on the insulating layer IL1. The resist R1 covers a portion of the insulating layer IL1. Then, the portion of the insulating layer IL1 exposed from the resist R1 is removed by etching using the resist R1 as a mask.Figure 10 As shown, contact holes CH1, CH21, CH31 are formed in the insulating layer IL1. Thereafter, as shown, Figure 11 As shown, a lower electrode LE1 is formed so as to overlap the contact hole CH1. The lower electrode LE1 is in contact with the conductive layer CL through the contact hole CH1.

[0100] Next, as shown, Figure 12 As shown, an insulating layer IL2 is formed on the insulating layer IL1 and the lower electrode LE1. Thereafter, as shown, Figure 13 As shown, a resist R2 is disposed on the insulating layer IL2. The resist R2 covers a part of the insulating layer IL2. Thereafter, a part of the insulating layer IL2 exposed from the resist R2 is removed by etching with the resist R2 as a mask. Thus, as shown, Figure 14 As shown, contact holes CH22, CH32 are formed in the insulating layer IL2. The contact hole CH2 is constituted by the contact hole CH21 formed in the insulating layer IL1 and the contact hole CH22 formed in the insulating layer IL2. In addition, a part of the insulating layer IL1 is exposed from the insulating layer IL2 by this etching. Thereafter, as shown, Figure 15 As shown, a lower electrode LE2 is formed on the insulating layer IL2 so as to overlap the contact hole CH2. The lower electrode LE2 is in contact with the conductive layer CL through the contact hole CH2.

[0101] Next, as shown, Figure 16 As shown, an insulating layer IL3 is formed on the insulating layer IL2 and the lower electrode LE2. Thereafter, as shown, Figure 17 As shown, a resist R3 is disposed on the insulating layer IL3. The resist R3 covers a part of the insulating layer IL3. Thereafter, a part of the insulating layer IL3 exposed from the resist R3 is removed by etching with the resist R3 as a mask. Thus, as shown, Figure 18 As shown, a contact hole CH33 is formed in the insulating layer IL3. The contact hole CH3 is constituted by the contact hole CH31 formed in the insulating layer IL1, the contact hole CH32 formed in the insulating layer IL2, and the contact hole CH33 formed in the insulating layer IL3. In addition, a part of the insulating layer IL1 is exposed from the insulating layer IL3 by this etching. Thereafter, as shown, Figure 19 As shown, a lower electrode LE3 is formed on the insulating layer IL3 so as to overlap the contact hole CH3. The lower electrode LE3 is in contact with the conductive layer CL through the contact hole CH3.

[0102] Next, as shown, Figure 20 As shown, a resist R4 is disposed so as to cover the lower electrode LE3. Thereafter, the insulating layers IL2, IL3 located above the lower electrode LE1 and the insulating layer IL3 located above the lower electrode LE2 are removed by etching with the resist R4 as a mask. Thus, as shown, Figure 21 As shown, the lower electrodes LE1, LE2 are exposed.

[0103] Next, as shown in Figure 22 the ribs layer 5 covering the lower electrodes LE1, LE2, LE3 is formed. The ribs layer 5 covers the end portions of the insulating layers IL2, IL3. The ribs layer 5 is in contact with the insulating layer IL1 between the lower electrodes LE1, LE2, LE3.

[0104] Next, as shown in Figure 23 the resist R5 is disposed on the ribs layer 5. The resist R5 covers a portion of the ribs layer 5. Thereafter, the portion of the ribs layer 5 exposed from the resist R5 is removed by etching with the resist R5 as a mask. Thus, as shown in Figure 24 the pixel openings AP1 overlapping with the lower electrode LE1, the pixel openings AP2 overlapping with the lower electrode LE2, and the pixel openings AP3 overlapping with the lower electrode LE3 are formed in the ribs layer 5.

[0105] Next, as shown in Figure 25 the partition wall 6 is formed on the ribs layer 5. In the process of forming the partition wall 6, the lower portion 61 having conductivity is formed on the ribs layer 5. The lower portion 61 includes the bottom layer 63 formed on the ribs layer 5 and the shaft layer 64 formed on the bottom layer 63. Thereafter, the upper portion 62 protruding from the side surface of the lower portion is formed on the shaft layer 64 (the lower portion 61). Note that the process of forming the partition wall 6 is not limited to the above process. In one example, the upper portion 62, the shaft layer 64, and the bottom layer 63 can be formed in this order by etching after the layer for processing into the bottom layer 63, the layer for processing into the shaft layer 64, and the layer for processing into the upper portion 62 are sequentially stacked on the ribs layer 5. In this embodiment, the partition wall 6 is formed after the pixel openings AP1, AP2, AP3 are formed, but the partition wall 6 can be formed before the pixel openings AP1, AP2, AP3 are formed.

[0106] After the ribs layer 5 and the partition wall 6 are formed, the process for forming the display elements DE1, DE2, DE3 is performed. In this embodiment, the case where the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed is assumed. However, the order of formation of the display elements DE1, DE2, DE3 is not limited to this example.

[0107] When the display element DE1 is formed, first, as shown in Figure 26As shown, a stacked film FL1 and a sealing layer SE11 are formed. The stacked film FL1 includes an organic layer OR1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1 is formed on and covers the lower electrode LE1. The organic layer OR1 contacts the lower electrode LE1 through a pixel opening AP1. The upper electrode UE1 is formed on and covers the organic layer OR1. The cap layer CP1 is formed on and covers the upper electrode UE1. The sealing layer SE11 is formed on and covers the cap layer CP1.

[0108] The organic layer OR1, upper electrode UE1, and cap layer CP1 are formed by vapor deposition. Seal layer SE11 is also formed by CVD (Chemical Vapor Deposition). The laminate film FL1 is divided into multiple sections by cantilevered partition walls 6. Seal layer SE11 continuously covers each of the partitioned sections of the laminate film FL1 and the partition walls 6.

[0109] After forming the laminate film FL1 and the sealing layer SE11, as shown in FIG. Figure 27 As shown in FIG. 1 , a resist R6 is disposed on the sealing layer SE11. The resist R6 covers the sub-pixel SP1 and a portion of the partition wall 6 surrounding it. Subsequently, the portion of the laminated film FL1 and the sealing layer SE11 exposed from the resist R6 is removed by etching using the resist R2 as a mask. Figure 28 As shown, a display element DE1 is formed in the sub-pixel SP1. For example, the etching includes wet etching and dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1 and the organic layer OR1. After the above etching, the resist R6 is removed.

[0110] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, Figure 29 As shown, a stacked film FL2 and a sealing layer SE12 are formed. The stacked film FL2 includes an organic layer OR2, an upper electrode UE2, and a cap layer CP2. The organic layer OR2 is formed on and covers the lower electrode LE2. The organic layer OR2 contacts the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 is formed on and covers the organic layer OR2. The cap layer CP2 is formed on and covers the upper electrode UE2. The sealing layer SE12 is formed on and covers the cap layer CP2.

[0111] The organic layer OR2, upper electrode UE2, and cap layer CP2 are formed by vapor deposition. Seal layer SE12 is also formed by CVD. The laminate film FL2 is partitioned into multiple sections by cantilevered partition walls 6. Seal layer SE12 continuously covers each partitioned section of the laminate film FL2 and the partition walls 6.

[0112] The display element DE3 is formed in the same steps as the display elements DE1 and DE2. That is, as shown in Figure 30 the laminated film FL3 and the sealing layer SE13 are formed. The laminated film FL3 includes the organic layer OR3, the upper electrode UE3, and the cover layer CP3. The organic layer OR3 is formed on and covers the lower electrode LE3. The organic layer OR3 is in contact with the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 is formed on and covers the organic layer OR3. The cover layer CP3 is formed on and covers the upper electrode UE3. The sealing layer SE13 is formed on and covers the cover layer CP3.

[0113] The organic layer OR3, the upper electrode UE3, and the cover layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD. The laminated film FL3 is partitioned into a plurality of portions by the cantilever-like partition wall 6. The sealing layer SE13 continuously covers the partitioned portions of the laminated film FL3 and the partition wall 6.

[0114] After the display elements DE1, DE2, and DE3 are formed, as shown in Figure 5 the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are formed in this order. Through such a process, the display device DSP is completed.

[0115] In the display device DSP according to the present embodiment, the lower electrode LE1 is located on the insulating layer IL1, the lower electrode LE2 is located on the insulating layer IL2, and the lower electrode LE3 is located on the insulating layer IL3. With such a configuration, even if the distance between the lower electrodes LE1, LE2, and LE3 is narrowed, the short circuit between the lower electrodes LE1, LE2, and LE3 can be suppressed. As a result, since the interval between the lower electrodes LE1, LE2, and LE3 can be reduced, the high aperture ratio of the display device DSP can be achieved.

[0116] [Second Embodiment]

[0117] Next, the second embodiment will be described. Note that the configuration not particularly mentioned is the same as that of the first embodiment.

[0118] Figure 31 is a schematic cross-sectional view of a display device DSP according to the second embodiment. In the present embodiment, the lower electrode LE1 is located on the insulating layer IL1, the lower electrode LE2 is located on the insulating layer IL2, and the lower electrode LE3 is located on the insulating layer IL2. With such a configuration, the distance between the lower electrode LE2 and the lower electrode LE3 and the distance between the lower electrode LE1 and the lower electrode LE3 can be reduced, and the same effects as the above can be obtained.

[0119] It should be noted that the lower electrode LE1 may be located on the insulating layer IL1, and the lower electrodes LE2 and LE3 may be located on the insulating layer IL2. In other words, at least one of the lower electrodes LE1, LE2, and LE3 may be located on the insulating layer IL1, and at least one of the lower electrodes LE1, LE2, and LE3 may be located on the insulating layer IL2. Even with this configuration, the same effects as described above can be achieved.

[0120] [Third embodiment]

[0121] Next, a third embodiment will be described. It should be noted that the configuration not specifically mentioned is the same as that of the above-described embodiment.

[0122] Figure 32 This is a schematic cross-sectional view of a display device DSP according to a third embodiment. In this embodiment, the insulating layer IL2 directly covers the peripheral portion E1 of the lower electrode LE1, and the insulating layer IL3 directly covers the peripheral portion E2 of the lower electrode LE2. Furthermore, the rib layer 5 is located on the insulating layer IL3 and directly covers the peripheral portion E3 of the lower electrode LE3. The peripheral portions E1, E2, and E3 overlap when viewed from above.

[0123] Next, an example of a method for manufacturing the display device DSP according to the third embodiment will be described.

[0124] Figure 33 to Figure 35 1 and 2 are schematic cross-sectional views showing a portion of a method for manufacturing a display device DSP according to a third embodiment. Figure 2 The contact holes CH1, CH2, CH3, Figure 32 The substrate 10 and the circuit layer 11 are shown.

[0125] The insulating layer IL1 and the lower electrode LE1 are connected to the Figure 8 to Figure 11 After forming the lower electrode LE1, as shown in FIG. Figure 33 As shown, the insulating layer IL2 covering the lower electrode LE1 is formed on the insulating layer IL1 and the lower electrode LE1. Thereafter, the lower electrode LE2 is formed on the insulating layer IL2. The peripheral portion E2 of the lower electrode LE2 overlaps with the peripheral portion E1 of the lower electrode LE1 in the Z direction. Thereafter, the insulating layer IL3 covering the lower electrode LE2 is formed on the insulating layer IL2 and the lower electrode LE2. Thereafter, the lower electrode LE3 is formed on the insulating layer IL3. The peripheral portion E3 of the lower electrode LE3 overlaps with the peripheral portion E2 of the lower electrode LE2 in the Z direction. In addition, although not shown in the figure, the peripheral portion E3 of the lower electrode LE3 overlaps with the peripheral portion E1 of the lower electrode LE1 in the Z direction. Thereafter, the rib layer 5 covering the lower electrode LE3 is formed on the insulating layer IL3 and the lower electrode LE3.

[0126] It should be noted that, although not shown in the figure, after the step of forming the insulating layer IL2, the insulating layer IL2 is formed by using Figure 13 、 Figure 14 Contact holes CH22 and CH32 are formed in the insulating layer IL2 by the same process as described above. Figure 17 、 Figure 18 The contact hole CH33 is formed in the insulating layer IL3 through the same process as described above.

[0127] Then, if Figure 34 As shown, a resist R11 is disposed on the rib layer 5. The resist R11 covers a portion of the rib layer 5. Thereafter, the portions of the rib layer 5 and the insulating layers IL2 and IL3 exposed from the resist R11 are removed by etching using the resist R11 as a mask. Figure 35 As shown in FIG, pixel openings AP1, AP2, and AP3 are formed. Then, the display device DSP is completed through the same steps as the above steps.

[0128] In this embodiment, the peripheral edges E1, E2, and E3 of the lower electrodes LE1, LE2, and LE3 overlap each other in a plan view. This configuration can improve the aperture ratio of the pixel openings AP1, AP2, and AP3 compared to the display device DSP according to the first and second embodiments.

[0129] [Fourth embodiment]

[0130] Next, a fourth embodiment will be described. It should be noted that the configuration not specifically mentioned is the same as that of the above-described embodiment.

[0131] Figure 36 This is a schematic cross-sectional view of a display device DSP according to a fourth embodiment. In this embodiment, the organic layers OR1, OR2, and OR3 are configured to emit white light. The laminated films FL1, FL2, and FL3 entirely cover the upper surface of the partition wall 6 (the upper surface of the upper portion 62).

[0132] The display device DSP further includes a color filter layer CF. The color filter layer CF is located above the lower electrodes LE1, LE2, and LE3 (display elements DE1, DE2, and DE3). Figure 36 In the example shown, the color filter layer CF is located on the sealing layer SE2 and is covered by the resin layer RS2. It should be noted that the position of the color filter layer CF is not limited to this position.

[0133] The color filter layer CF includes color filters CF1, CF2, CF3. In one example, the color filter CF1 is formed of a resin material colored red, the color filter CF2 is formed of a resin material colored green, and the color filter CF3 is formed of a resin material colored blue. The color filter CF1 is positioned directly above the lower electrode LE1 (display element DE1). The color filter CF2 is positioned directly above the lower electrode LE2 (display element DE2). The color filter CF3 is positioned directly above the lower electrode LE3 (display element DE3).

[0134] An optical black film BM is provided between the color filter layer CF and the sealing layer SE2. In one example, the optical black film BM is formed in a lattice shape and overlaps the rib layer 5 and the partition wall 6 in plan view.

[0135] Figure 37 is a view showing one example of a layer structure applicable to the display elements DE1, DE2, DE3 involved in the fourth embodiment. Figure 37 The display elements DE1, DE2, DE3 shown are formed similarly to the display elements DE1, DE2, DE3 shown in Figure 4 The display elements DE1, DE2, DE3 shown are formed similarly to the display elements DE1, DE2, DE3 shown in

[0136] The light emitting layer EM1 included in the organic layer OR1 includes a light emitting layer EM11 (first light emitting layer) that emits red light, a light emitting layer EM12 (second light emitting layer) that emits green light, and a light emitting layer EM13 (third light emitting layer) that emits blue light. The light emitting layers EM11, EM12, EM13 are stacked. Specifically, the light emitting layer EM11 is positioned above the electron blocking layer EBL, the light emitting layer EM12 is positioned above the light emitting layer EM11, and the light emitting layer EM13 is positioned above the light emitting layer EM12. Note that the stacking order of the light emitting layers EM11, EM12, EM13 is not limited to this example. In addition, the organic layer OR1 can include a light emitting layer that emits light in a color other than the above colors.

[0137] The light emitting layer EM2 included in the organic layer OR2 includes a light emitting layer EM21 (first light emitting layer) that emits red light, a light emitting layer EM22 (second light emitting layer) that emits green light, and a light emitting layer EM23 (third light emitting layer) that emits blue light. The light emitting layers EM21, EM22, EM23 are stacked. Specifically, the light emitting layer EM21 is positioned above the electron blocking layer EBL, the light emitting layer EM22 is positioned above the light emitting layer EM21, and the light emitting layer EM23 is positioned above the light emitting layer EM22. Note that the stacking order of the light emitting layers EM21, EM22, EM23 is not limited to this example. In addition, the organic layer OR2 can include a light emitting layer that emits light in a color other than the above colors.

[0138] The light-emitting layer EM3 included in the organic layer OR3 includes a light-emitting layer EM31 (first light-emitting layer) that emits red light, a light-emitting layer EM32 (second light-emitting layer) that emits green light, and a light-emitting layer EM33 (third light-emitting layer) that emits blue light. The light-emitting layers EM31, EM32, EM33 are stacked. Specifically, the light-emitting layer EM31 is positioned on the electron-blocking layer EBL, the light-emitting layer EM32 is positioned on the light-emitting layer EM31, and the light-emitting layer EM33 is positioned on the light-emitting layer EM32. Note that the order of stacking of the light-emitting layers EM31, EM32, EM33 is not limited to this example. In addition, the organic layer OR3 can include a light-emitting layer that emits light of a color other than the above colors.

[0139] In such a configuration, the same effects as described above can be obtained.

[0140] [5th Embodiment]

[0141] Next, the 5th embodiment will be described. Note that the configuration not specifically mentioned is the same as in the above embodiments.

[0142] Figure 38 is a schematic cross-sectional view of a display device DSP according to the 5th embodiment. The display device DSP according to the 5th embodiment is different from the other embodiments in that it does not have the partition wall 6. In addition, the organic layers OR1, OR2, OR3 are integrally formed as a common layer. Similarly, the upper electrodes UE1, UE2, UE3 are integrally formed as a common electrode, the cover layers CP1, CP2, CP3 are integrally formed as a common layer, and the sealing layers SE11, SE12, SE13 are integrally formed as a common layer. In Figure 38 In this example, the display elements DE1, DE2, DE3 are formed of the same layers as the display elements DE1, DE2, DE3 shown in Figure 37 . That is, the organic layers OR1, OR2, OR3 are configured to emit white light.

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib layer 5 is formed, the organic layers OR1, OR2, OR3 are integrally formed on the lower electrodes LE1, LE2, LE3, as shown in Figure 8 to Figure 24 . The organic layers OR1, OR2, OR3 respectively cover the lower electrodes LE1, LE2, LE3 through the pixel openings AP1, AP2, AP3. Figure 39

[0143] Next, an example of a method for manufacturing the display device DSP according to the 5th embodiment will be described.

[0144] Figure 39 is a schematic cross-sectional view showing a part of a method for manufacturing the display device DSP according to the 5th embodiment.

[0145] The steps up to the formation of the rib layer 5 are the same as those described in the method for manufacturing the display device DSP according to the 4th embodiment. After the rib

[0146] After that, the upper electrode UE1, UE2, UE3 is integrally formed on the organic layer OR1, OR2, OR3. After that, the cover layer CP1, CP2, CP3 is formed on the upper electrode UE1, UE2, UE3. After that, the cover layer CP1, CP2, CP3 is formed on the sealing layer SE11, SE12, SE13. After that, the display device DSP is completed via the same procedure as the above-described procedure.

[0147] In such a configuration, the same effects as the above-described effects can also be obtained.

[0148] All of the display devices and the manufacturing methods of the display devices which can be implemented by the person skilled in the art based on the display devices and the manufacturing methods of the display devices described above as the embodiments of the present application with appropriate design changes are also within the scope of the present application as long as the gist of the present application is included.

[0149] Various modifications can be conceived by the person skilled in the art within the scope of the idea of the present application, and these modifications should also be understood as being within the scope of the present application. For example, a solution obtained by the person skilled in the art with appropriate addition, deletion, or design change of the configuration elements to the above-described embodiments, or a solution obtained by the person skilled in the art with appropriate addition, omission, or condition change of the procedures as long as the gist of the present application is included should also be included within the scope of the present application.

[0150] In addition, other action effects brought about by the solutions described in the above-described embodiments should of course be understood as being action effects brought about by the present application as long as the action effects are clear from the description of the present specification or can be appropriately conceived by the person skilled in the art.

Claims

1. A display device comprising: a first insulating layer; a first lower electrode over the first insulating layer, having a first peripheral portion; a second insulating layer over the first insulating layer; a second lower electrode over the second insulating layer, having a second peripheral portion; a third insulating layer over the second insulating layer; a third lower electrode over the third insulating layer, having a third peripheral portion; a rib layer overlapping the first, second, and third peripheral portions and formed of an inorganic material; a first organic layer over the first lower electrode; a second organic layer over the second lower electrode; a third organic layer over the third lower electrode; a first upper electrode over the first organic layer; a second upper electrode over the second organic layer; and a third upper electrode over the third organic layer. The rib layer directly covers the first, second, and third peripheral portions.

2. The display device according to claim 1, wherein The rib layer is in contact with the first insulating layer.

3. The display device of claim 2, wherein, The second insulating layer directly covers the first peripheral portion, 4. The display device according to claim 1, wherein The third insulating layer directly covers the second peripheral portion, The rib layer is over the third insulating layer and directly covers the third peripheral portion. At least two of the first, second, and third peripheral portions overlap each other when viewed from above.

5. The display device according to claim 1, wherein The first, second, and third peripheral portions overlap each other when viewed from above.

6. The display device according to claim 1, wherein 7. The display device according to claim 1, further comprising a barrier wall including a lower portion provided over the rib layer and having conductivity, and an upper portion provided over the lower portion and protruding from a side surface of the lower portion, the barrier wall surrounds the first, second, and third organic layers, the first, second, and third upper electrodes, respectively, the first, second, and third upper electrodes are in contact with the lower portion. The first, second, and third peripheral portions are directly below the barrier wall.

8. The display device of claim 7, wherein, The first, second, and third organic layers are configured to emit light in different colors from each other.

9. The display device of claim 7, wherein, The first, second, and third organic layers are a common layer formed integrally, 10. The display device according to claim 1, wherein The first, second, and third upper electrodes are a common electrode formed integrally. The first, second, and third organic layers are configured to emit white light.

11. The display device according to claim 7 or 10, wherein Each of the first, second, and third organic layers includes:

12. The display device of claim 11, wherein, a first light-emitting layer configured to emit red light; a second light-emitting layer configured to emit green light; and a third light-emitting layer configured to emit blue light, the first, second, and third light-emitting layers are stacked.

13. The display device according to claim 1, further comprising a color filter layer over the first, second, and third lower electrodes. The second and third insulating layers are formed of an inorganic material.

14. The display device of claim 1, wherein, ​ 15. The display device of claim 1, wherein, The first insulating layer has a first contact hole overlapping the first lower electrode, a second contact hole overlapping the second lower electrode, and a third contact hole overlapping the third lower electrode, The second insulating layer has a fourth contact hole overlapping the second contact hole and a fifth contact hole overlapping the third contact hole, The third insulating layer has a sixth contact hole overlapping the fifth contact hole.

16. A method for manufacturing a display device, wherein forming a first insulating layer, forming a first lower electrode over the first insulating layer, forming a second insulating layer over the first insulating layer, forming a second lower electrode over the second insulating layer, forming a third insulating layer over the second insulating layer, forming a third lower electrode over the third insulating layer, forming a rib layer overlapping a first peripheral portion of the first lower electrode, a second peripheral portion of the second lower electrode, and a third peripheral portion of the third lower electrode, forming a first organic layer and a first upper electrode overlapping the first lower electrode, a second organic layer and a second upper electrode overlapping the second lower electrode, and a third organic layer and a third upper electrode overlapping the third lower electrode.

17. The method for manufacturing a display device according to claim 16, wherein after the rib layer is formed, forming a partition wall over the rib layer, in the process of forming the partition wall, forming a lower portion having conductivity over the rib layer, forming an upper portion protruding from a side surface of the lower portion over the lower portion.

18. The method for manufacturing a display device according to claim 17, wherein in the process of forming the first organic layer, the first upper electrode, the second organic layer, the second upper electrode, the third organic layer, and the third upper electrode, forming the first organic layer over the first lower electrode, forming the first upper electrode over the first organic layer, forming the second organic layer over the second lower electrode, forming the second upper electrode over the second organic layer, forming the third organic layer over the third lower electrode, forming the third upper electrode over the third organic layer.

19. The method for manufacturing a display device according to claim 18, wherein after the first upper electrode is formed and before the second organic layer is formed, forming a cap layer over the first upper electrode, forming a sealing layer over the cap layer.

20. The method for manufacturing a display device according to claim 16, wherein in the process of forming the first organic layer, the first upper electrode, the second organic layer, the second upper electrode, the third organic layer, and the third upper electrode, integrally forming the first organic layer, the second organic layer, and the third organic layer over the first lower electrode, the second lower electrode, and the third lower electrode, integrally forming the first upper electrode, the second upper electrode, and the third upper electrode over the first organic layer, the second organic layer, and the third organic layer.

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