Display device, method of manufacturing the same, and electronic device including the same

Abstract

A display device, a method of manufacturing the same, and an electronic device including the same are provided. The display device includes a sub-pixel including a first sub-pixel and a second sub-pixel adjacent to each other. The display device includes: a pixel circuit layer; and a light-emitting element layer. The light-emitting element layer includes: a planarization layer; an anode electrode; a pixel defining layer; a trench; a light-emitting structure including a first light-emitting structure and a second light-emitting structure; an intermediate light-emitting structure disposed within the trench in a boundary region between the first sub-pixel and the second sub-pixel, and including the same material as the light-emitting structure; an intermediate connection layer disposed in a boundary region between the first sub-pixel and the second sub-pixel and connecting the first light-emitting structure and the second light-emitting structure; and a cathode electrode disposed across the first sub-pixel and the second sub-pixel, at least a portion of the cathode electrode being disposed on the intermediate connection layer. The intermediate light emitting structure and the intermediate connection layer are physically separated from each other.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device, a manufacturing method of a display device, and an electronic device including the display device. BACKGROUND

[0002] As recent interest in information display has increased, research and development of display devices has continued.

[0003] A display device can include sub-pixels each including an organic light emitting diode (OLED). The organic light emitting diode, as an active light emitting type display element, has the advantages of not only a wide field of view and excellent contrast, but also low voltage driving, fast response speed, and light weight and thinness.

[0004] The organic light emitting diode can be included in each of the sub-pixels, and can include a hole transport part, an electron transport part, and a light emitting layer between the hole transport part and the electron transport part. Holes provided from the hole transport part and electrons provided from the electron transport part can recombine in the light emitting layer to generate excitons. The generated excitons can change from an excited state to a ground state and generate light.

[0005] The organic light emitting diode, in order to emit light, can include a cathode electrode configured to provide electrons. The cathode electrode can be constituted by a common electrode of each of different sub-pixels. The cathode electrode needs to be appropriately patterned in the entire area where the sub-pixels are formed in order to supply a cathode signal suitable for each organic light emitting diode.

[0006] There is a need for division of an electrical signal supplied to each of sub-pixels adjacent to each other. For example, there can be a risk of electrical signal mixing due to lateral leakage occurring between the sub-pixels. Thus, there is a demand for a display device that can reduce the risk of leakage current and the like. SUMMARY

[0007] An aspect of the disclosure provides a display device, a manufacturing method of a display device, and an electronic device including the display device, which can reduce the risk of leakage current and the like.

[0008] An aspect of the disclosure provides a display device, a manufacturing method of a display device, and an electronic device including the display device, which can have excellent display quality with high resolution.

[0009] An aspect of the disclosure provides a display device, a manufacturing method of a display device, and an electronic device including the display device, which can secure a process margin.

[0010] According to embodiments of the disclosure, a display device can include subpixels including a first subpixel and a second subpixel adjacent to each other, wherein the display device includes a pixel circuit layer including a pixel circuit on a substrate, and a light emitting element layer disposed on the pixel circuit layer. The light emitting element layer can include a planarization layer, an anode electrode disposed on the planarization layer, a pixel defining layer at least a portion of which is disposed on the anode electrode, a trench passing through the pixel defining layer and at least a portion of the planarization layer, a light emitting structure disposed across the first subpixel and the second subpixel and at least a portion of which is disposed on the anode electrode exposed through the pixel defining layer, the light emitting structure including a first light emitting structure forming the first subpixel and a second light emitting structure forming the second subpixel, an intermediate light emitting structure disposed in the trench in a boundary region between the first subpixel and the second subpixel and including the same material as the light emitting structure, an intermediate connection layer disposed in the boundary region between the first subpixel and the second subpixel and connecting the first light emitting structure and the second light emitting structure, and a cathode electrode disposed across the first subpixel and the second subpixel and at least a portion of which is disposed on the intermediate connection layer. The intermediate light emitting structure and the intermediate connection layer can be physically separated from each other.

[0011] According to embodiments, a void can be formed between the intermediate light emitting structure and the intermediate connection layer.

[0012] According to embodiments, the intermediate light emitting structure can include a plurality of intermediate light emitting structures. The trench can include a plurality of trenches. The number of the plurality of intermediate light emitting structures and the number of the plurality of trenches can be the same as each other.

[0013] According to embodiments, the intermediate connection layer can include a plurality of intermediate connection layers. The plurality of intermediate connection layers can be disposed apart from each other at edges of the subpixels.

[0014] According to embodiments, each of the subpixels can have a polygonal shape. The plurality of intermediate connection layers can be disposed at each of vertex portions of the polygonal shape.

[0015] According to embodiments, a width of the pixel defining layer can be 0.5 µm to 3.5 µm.

[0016] According to embodiments, the light emitting structure can include a common layer, each of the first subpixel and the second subpixel including the common layer in common. The common layer can be broken by the trench.

[0017] According to an embodiment, the height of the trench can be greater than half the thickness of the light emitting structure. The width of the trench can be greater than 1 / 4 of the thickness of the light emitting structure.

[0018] According to an embodiment, the side surface of the trench can form an included angle of 60 degrees to 90 degrees with respect to a plane in which the substrate is disposed.

[0019] According to an embodiment, the display device can further include a cover layer disposed across the first sub-pixel and the second sub-pixel and on the cathode electrode, and an encapsulation layer disposed on the cover layer. The cover layer and the encapsulation layer can overlap the intermediate connection layer and the intermediate light emitting structure when viewed in a plane.

[0020] According to an embodiment, the cover layer and the intermediate connection layer can be directly adjacent to each other.

[0021] According to an embodiment, the intermediate connection layer can include an organic material having an electron transport property.

[0022] According to an embodiment, the substrate can include a silicon substrate.

[0023] According to an embodiment of the disclosure, there is provided a method of manufacturing a display device including sub-pixels including a first sub-pixel and a second sub-pixel adjacent to each other. The method can include forming a pixel circuit layer including a pixel circuit on a substrate, and forming a light emitting element layer on the pixel circuit layer. Forming the light emitting element layer can include forming a planarization layer, forming an anode electrode on the planarization layer, forming a pixel defining layer covering at least a portion of the anode electrode, forming a trench passing through the pixel defining layer and at least a portion of the planarization layer, forming a light emitting structure across the first sub-pixel and the second sub-pixel, forming an intermediate connection layer disposed in a boundary region between the first sub-pixel and the second sub-pixel, and forming a cathode electrode across the first sub-pixel and the second sub-pixel. Forming the intermediate connection layer can include patterning the intermediate connection layer using a fine silicon mask.

[0024] According to an embodiment, forming the light emitting structure can include a step in which at least a portion of the light emitting structure is disconnected by the trench.

[0025] According to an embodiment, forming the light emitting structure can include a step of forming an intermediate light emitting structure disposed in the trench.

[0026] According to embodiments, it can be that the light emitting structure includes a first light emitting structure forming the first sub-pixel and a second light emitting structure forming the second sub-pixel. It can be that the step of forming the intermediate connection layer includes a step of patterning the intermediate connection layer to overlap the intermediate light emitting structure when viewed in a plane; and a step of the intermediate connection layer connecting the first light emitting structure and the second light emitting structure.

[0027] According to embodiments, it can be that the fine silicon mask includes an evaporation opening portion. It can be that a width of the evaporation opening portion is 0.2 μm to 0.8 μm.

[0028] According to embodiments, it can be that the step of patterning the intermediate connection layer includes a step of patterning a plurality of intermediate connection layers. It can be that the plurality of intermediate connection layers are patterned simultaneously.

[0029] According to embodiments, it can be that the step of patterning the intermediate connection layer includes a step of patterning a plurality of intermediate connection layers. It can be that a portion of the plurality of intermediate connection layers is patterned in a first time interval, and another portion of the plurality of intermediate connection layers is patterned in a second time interval after the first time interval.

[0030] According to an embodiment of the present disclosure, an electronic device may include: a processor that provides input image data; a display device that displays an image based on the input image data and includes a subpixel region; and a power supply that supplies power to the display device. Alternatively, the display device may include: subpixels that form the subpixel region and include a first subpixel and a second subpixel that are adjacent to each other; a pixel circuit layer that includes pixel circuits on a substrate; and a light-emitting element layer that is disposed on the pixel circuit layer. The light-emitting element layer may include: a planarization layer; an anode electrode disposed on the planarization layer; a pixel defining layer, at least a portion of which is disposed on the anode electrode; a trench penetrating the pixel defining layer and at least a portion of the planarization layer; a light-emitting structure disposed across the first sub-pixel and the second sub-pixel, at least a portion of which is disposed on the anode electrode exposed by the pixel defining layer, the light-emitting structure including a first light-emitting structure forming the first sub-pixel and a second light-emitting structure forming the second sub-pixel; an intermediate light-emitting structure disposed within the trench in a boundary region between the first sub-pixel and the second sub-pixel and comprising the same material as the light-emitting structure; an intermediate connecting layer disposed in a boundary region between the first sub-pixel and the second sub-pixel and connecting the first light-emitting structure and the second light-emitting structure; and a cathode electrode disposed across the first sub-pixel and the second sub-pixel, at least a portion of which is disposed on the intermediate connecting layer. The intermediate light-emitting structure and the intermediate connecting layer may be physically separated from each other.

[0031] According to the embodiments of the present invention, a display device capable of reducing risks such as leakage current, a method for manufacturing the display device, and an electronic device including the display device can be provided.

[0032] An aspect of the present disclosure may provide a display device that may have excellent display quality with high resolution, a method of manufacturing the display device, and an electronic device including the display device.

[0033] An aspect of the present disclosure may provide a display device that can ensure a process margin, a method of manufacturing the display device, and an electronic device including the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0035] Figure 2 It shows Figure 1 A simplified exploded perspective view of a portion of a display panel.

[0036] Figure 3 is a schematic plan view showing a pixel according to the embodiment.

[0037] Figure 4 and Figure 5 is a schematic plan view showing a pixel according to an embodiment.

[0038] Figure 6 is a schematic plan view showing a pixel according to an embodiment.

[0039] Figure 7 is a schematic plan view showing a pixel according to an embodiment.

[0040] Figure 8 is a schematic cross-sectional view showing a display device according to an embodiment.

[0041] Figure 9 is a schematic cross-sectional view showing sub-pixels adjacent to each other.

[0042] Figure 10 and Figure 11 is a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0043] Figure 12 is a schematic sequential view showing a manufacturing method of a display device according to an embodiment.

[0044] Figure 13 is a schematic sequential view showing a step of forming a light-emitting element layer over a pixel circuit layer according to an embodiment.

[0045] Figures 14 to 20 is a schematic view showing a manufacturing method of a display device according to an embodiment by process steps.

[0046] Figure 21 is a block diagram showing an embodiment of an electronic device.

[0047] Figure 22 is a perspective view showing an applicable example of the electronic device of Figure 21

[0048] Figure 23 is a diagram showing a head-mounted display device worn on a user of Figure 22

[0049] (Explanation of Reference Numerals)

[0050] 100: display device

[0051] SP: sub-pixel

[0052] PXL: pixel

[0053] DA, NDA: display region, non-display region

[0054] SUB: substrate

[0055] PD: pad​​

[0056] MCL: middle connection layer

[0057] TRCH: trench

[0058] EMA: emission area

[0059] NEA: non-emission area

[0060] AE: anode electrode

[0061] EMS: emission structure

[0062] EMS_M: middle emission structure

[0063] CE: cathode electrode

[0064] CPL: cover layer

[0065] TFE: encapsulation layer DETAILED DESCRIPTION

[0066] The present disclosure can be applied various modifications, and can have various forms, a specific embodiment is exemplified in the accompanying drawings and described in detail herein. However, this is not to limit the present disclosure to a specific disclosed form, and it is understood to include all modifications, equivalents, and substitutes contained in the concept and technical scope of the present disclosure.

[0067] The first, second, and the like terms can be used to describe various constituent elements, but the above-described constituent elements are not limited by the above-described terms. The above-described terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, a first constituent element can be named a second constituent element, and similarly the second constituent element can also be named the first constituent element, without departing from the scope of the present disclosure. The singular representation includes the plural representation unless it is specifically different in the context.

[0068] In the present disclosure, the terms "include" or "have" or the like are understood to specify the presence of features, numbers, steps, operations, constituent elements, parts, or combinations thereof described in the specification, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, constituent elements, parts, or combinations thereof. In addition, when it is said that a layer, a film, a region, a plate, and the like are "on" another part, this includes not only the case of being "directly on" the other part, but also the case of having another part therebetween. In addition, in the present specification, when it is said that any layer, film, region, plate, and the like are formed "on" another part, the direction of formation is not limited to the upward direction, but includes formation in the lateral or downward direction. Conversely, when it is said that a layer, a film, a region, a plate, and the like are "under" another part, this includes not only the case of being "directly under" the other part, but also the case of having another part therebetween.

[0069] The present disclosure relates to a display device, a manufacturing method of a display device, and an electronic device including the display device. Hereinafter, a display device according to an embodiment will be described with reference to the accompanying drawings.

[0070] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0071] Referring to Figure 1 , a display device 100 according to an embodiment is configured to emit light.

[0072] The display device 100 can include a display area DA and a non-display area NDA. The display device 100 displays an image through the display area DA. The non-display area NDA is disposed at a periphery of the display area DA.

[0073] The display device 100 can include a substrate SUB, a sub-pixel SP, and a pad PD.

[0074] The display device 100 can be applied to various fields. For example, the display device 100 can be used as a display screen for a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device, etc. In this case, the display device 100 can be disposed very close to the user's eyes, thereby requiring a relatively high integration of the sub-pixel SP. To improve the integration of the sub-pixel SP, the substrate SUB can be provided as a silicon substrate. The sub-pixel SP and / or the display device 100 can be formed on the substrate SUB of the silicon substrate. The display device 100 formed on the substrate SUB of the silicon substrate can be referred to as an OLEDoS (OLED on Silicon) display device.

[0075] The sub-pixel SP is disposed (or formed) on the substrate SUB in the display area DA. The sub-pixels SP can be arranged in a matrix form along a first direction DR1 and a second direction DR2 different from (e.g., intersecting) the first direction DR1. However, embodiments are not limited thereto. For example, the sub-pixels SP can be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP can be arranged in a PENTILE TM form. It can be that the first direction DR1 is a row direction and the second direction DR2 is a column direction.

[0076] Each of the sub-pixels SP can include at least one light emitting element LD configured to generate light (refer to Figure 8). Thus, each of the sub-pixels SP can generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP can constitute one pixel PXL. For example, as shown in FIG. 1, three sub-pixels SP can form one pixel PXL. Figure 1

[0077] Hereinafter, an embodiment in which the sub-pixels SP include a first sub-pixel SP1 (see FIG. 2) that provides light of a first color (e.g., red), a second sub-pixel SP2 (see FIG. 3) that provides light of a second color (e.g., green), and a third sub-pixel SP3 (see FIG. 4) that provides light of a third color (e.g., blue) will be described as a reference. Figure 2 Figure 2 Figure 2

[0078] According to the embodiment, the first sub-pixel SP1, as a red pixel, can provide light of a wavelength band of 600 nm to 750 nm. The second sub-pixel SP2, as a green pixel, can provide light of a wavelength band of 480 nm to 560 nm. The third sub-pixel SP3, as a blue pixel, can provide light of a wavelength band of 370 nm to 460 nm.

[0079] The non-display area NDA on the substrate SUB can be configured with components for controlling the sub-pixels SP. For example, wirings (e.g., gate lines and data lines for driving the sub-pixels SP, etc.) connected to the sub-pixels SP can be configured in the non-display area NDA. In addition, a gate driver, a data driver, a voltage generator, a controller, a temperature sensor, etc. for obtaining driving signals supplied to the sub-pixels SP can be integrated in the non-display area NDA of the display device 100. However, the disclosure is not limited thereto.

[0080] The non-display area NDA on the substrate SUB is configured with a pad PD. The pad PD can be electrically connected to the sub-pixels SP through a wiring. For example, the pad PD can be connected to the sub-pixels SP through a data line.

[0081] The pad PD can join components in the display area DA and the non-display area NDA to other components of the display device 100. In the embodiment, a voltage and a signal required for the operation of the components included in the display device 100 can be supplied from a driving integrated circuit through the pad PD. For example, a data line can be electrically connected to the driving integrated circuit through the pad PD. For example, a power voltage for driving the sub-pixels SP can be received from the driving integrated circuit through the pad PD. For example, a gate control signal for controlling the gate driver can be transmitted from the driving integrated circuit to the gate driver through the pad PD. ​​​​

[0082] In the embodiment, the circuit board can be electrically connected to the pad PD with a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board can be a flexible circuit board (FPCB) or a flexible film having a flexible material. The drive integrated circuit can be mounted on the circuit board to be electrically connected to the pad PD.

[0083] In the embodiment, the display area DA can have various shapes. The display area DA can have a closed loop shape including sides of straight lines and / or curves. For example, the display area DA can have a polygonal shape, a circular shape, a semicircular shape, an elliptical shape, or the like.

[0084] In the embodiment, the display device 100 can have a flat display surface. In other embodiments, the display device 100 can have a display surface that is at least partially round. In the embodiment, the display device 100 can be bendable, or foldable, or rollable. In this case, the display device 100 and / or the substrate SUB can include a substance having a flexible property.

[0085] Figure 2 is a simplified exploded perspective view showing a portion of the display panel of Figure 1 In Figure 2 , for clear and concise explanation, a portion of the display panel DP corresponding to two pixels PXL1, PXL2 of the pixels PXL of Figure 1 is simply shown. The portion of the display panel DP corresponding to the remaining pixels can also be identically configured.

[0086] Referring to Figure 1 and Figure 2 , each of the first and second pixels PXL1, PXL2 can include first to third sub-pixels SP1-SP3. However, the embodiment is not limited thereto. For example, each of the first and second pixels PXL1, PXL2 can include four sub-pixels SP, or two sub-pixels SP.

[0087] In Figure 2 , when viewed in a third direction DR3 crossing the first and second directions DR1, DR2, the first to third sub-pixels SP1-SP3 are shown to have a quadrilateral shape having the same size as each other. However, the embodiment is not limited thereto. The first to third sub-pixels SP1-SP3 can be deformed to have various shapes.

[0088] The display panel DP can include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a cover layer CPL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0089] In an embodiment, the substrate SUB can include a silicon wafer substrate formed by a semiconductor process. The substrate SUB can include a semiconductor substance suitable for forming circuit elements. For example, the semiconductor substance can include silicon, germanium, and / or silicon-germanium. The substrate SUB can also be provided from a bulk wafer, an epitaxial layer, an SOI (Silicon On Insulator) layer, or a SeOI (Semiconductor On Insulator) layer, etc. In another embodiment, the substrate SUB can include a glass substrate. In yet another embodiment, the substrate SUB can include a PI (Polyimide) substrate.

[0090] The pixel circuit layer PCL is configured on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL can include insulating layers and conductive patterns configured between the insulating layers. The conductive patterns of the pixel circuit layer PCL can function as at least a part of circuit elements, wirings, etc. The conductive patterns can include copper, but embodiments are not limited thereto.

[0091] The circuit elements can include a sub-pixel circuit of each of the first to third sub-pixels SP1-SP3. The sub-pixel circuit can include a transistor and one or more capacitors. Each transistor can include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion is included in the substrate SUB, and the gate electrode is included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. Each capacitor can include electrodes separated from each other. For example, each capacitor can include electrodes separated from each other on a plane defined by the first and second directions DR1, DR2. For example, each capacitor can include electrodes separated from each other in the third direction DR3 through an insulating layer.

[0092] A plane defined in the specification as a plane extending in the first direction DR1 and the second direction DR2 can be defined with reference to a plane on which the substrate SUB is disposed. According to an embodiment, the third direction DR3 can be a thickness direction of the substrate SUB, and the third direction DR3 can also be a light emission direction of the display device 100.

[0093] The wirings of the pixel circuit layer PCL can include signal lines connected to each of the first to third sub-pixels SP1-SP3, such as gate lines, light emission control lines, and data lines, etc.

[0094] The light emitting element layer LDL can include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0095] The anode electrode AE can be disposed on the pixel circuit layer PCL. The anode electrode AE can be electrically connected with the circuit elements of the pixel circuit layer PCL.

[0096] The pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL can include openings OP exposing a portion of each of the anode electrodes AE. The openings OP of the pixel defining layer PDL can be understood as light emitting regions corresponding to the first to third sub-pixels SP1-SP3, respectively.

[0097] At least a portion of the emission structure EMS can be disposed on the anode electrode AE exposed through the openings OP of the pixel defining layer PDL. The emission structure EMS can include a light emitting layer configured to generate light, an electron transport portion configured to transport electrons, and a hole transport portion configured to transport holes, etc.

[0098] In an embodiment, the emission structure EMS can fill the openings OP of the pixel defining layer PDL and be disposed entirely above the pixel defining layer PDL. In other words, the emission structure EMS can extend across the first to third sub-pixels SP1-SP3. In this case, at least a portion of the layers within the emission structure EMS can be disconnected or bent at the boundaries between the first to third sub-pixels SP1-SP3. However, embodiments are not limited thereto. For example, portions of the emission structure EMS corresponding to the first to third sub-pixels SP1-SP3 can be separated from each other, each of which is disposed within the openings OP of the pixel defining layer PDL.

[0099] The cathode electrode CE can be disposed on the emission structure EMS. The cathode electrode CE can extend across the first to third sub-pixels SP1-SP3. As such, the cathode electrode CE can be provided as a common electrode for the first to third sub-pixels SP1-SP3.

[0100] The cathode electrode CE can be a thin metal layer having a thickness to a degree that light emitted from the emission structure EMS can be transmitted. The cathode electrode CE can be formed of a metal material or formed of a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE can include at least one of various transparent conductive materials such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In another embodiment, the cathode electrode CE can include at least one of silver (Ag) magnesium (Mg) and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0101] It can be understood that any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping therewith, and the portion of the cathode electrode CE overlapping therewith constitute one light emitting element LD (see Figure 8 In other words, each of the light-emitting elements of the first to third subpixels SP1-SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS that overlaps with the anode electrode AE, and a portion of the cathode electrode CE that overlaps with the cathode electrode CE. In each of the first to third subpixels SP1-SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the light-emitting layer of the light-emitting structure EMS to form excitons. When the excitons transition from an excited state to a ground state, light is generated. The brightness of the light can be determined by the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined by the structure of the light-emitting layer.

[0102] A cover layer CPL is disposed on the cathode electrode CE. The cover layer CPL can passivate the light emitting element layer LDL and / or the pixel circuit layer PCL.

[0103] An encapsulation layer TFE is disposed on the cover layer CPL. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ) etc. For example, the organic film may include an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenyleneether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). However, the materials of the organic film and the inorganic film of the encapsulation layer TFE are not limited thereto.

[0104] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO x The thin film including aluminum oxide may be located on the encapsulation layer TFE facing the optical function layer OFL and / or on the underside of the encapsulation layer TFE facing the light emitting element layer LDL.

[0105] The thin film including aluminum oxide can be formed by an Atomic Layer Deposition (ALD) method. However, embodiments are not limited thereto. The encapsulation layer TFE can further include a thin film formed of at least one of various substances suitable for improvement of encapsulation efficiency.

[0106] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL can include a color filter layer CFL and a lens array LA.

[0107] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter light emitted from the light emitting structure EMS and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL can include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of such color filters CF passes light of a wavelength range corresponding to the corresponding sub-pixel. For example, a color filter corresponding to the first sub-pixel SP1 can pass red light, a color filter corresponding to the second sub-pixel SP2 can pass green light, and a color filter corresponding to the third sub-pixel SP3 can pass blue light. At least a portion of the color filters CF can be omitted according to light emitted from the light emitting structure EMS of each sub-pixel.

[0108] The lens array LA is disposed on the color filter layer CFL. The lens array LA can include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS can improve light emission efficiency by outputting light emitted from the light emitting structure EMS in an intended path. The lens array LA can have a relatively high refractive index. For example, the lens array LA can have a refractive index higher than that of the overcoat layer OC. In embodiments, the lenses LS can include an organic substance. In embodiments, the lenses LS can include an acrylic substance. However, the substance of the lenses LS is not limited thereto.

[0109] The overcoat layer OC can be disposed on the lens array LA. The overcoat layer OC can cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC can include various substances suitable for protecting the underlying layers thereunder from foreign substances such as dust, moisture, etc. For example, the overcoat layer OC can include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OC can include an epoxy, but embodiments are not limited thereto. The overcoat layer OC can have a refractive index lower than that of the lens array LA.

[0110] A cover window CW can be disposed on the outer coating OC. The cover window CW is configured to protect the layer thereunder. The cover window CW can have a higher refractive index than the outer coating OC. The cover window CW can include glass, but embodiments are not limited thereto. For example, the cover window CW can be an encapsulation glass configured to protect the constituent elements disposed thereunder. In another embodiment, the cover window CW can be omitted.

[0111] According to an embodiment, the display device 100 can further include an intermediate connection layer MCL between the light emitting structure EMS and the cathode electrode CE (refer to Figure 3 ).

[0112] Hereinafter, with reference to Figures 3 to 11 , a display device 100 according to an embodiment including an intermediate connection layer MCL will be described.

[0113] First, with reference to Figures 3 to 7 , a planar structure of the display device 100 (refer to Figure 1 ) according to an embodiment will be described.

[0114] Figure 3 is a schematic plan view illustrating a pixel according to an embodiment.

[0115] With reference to Figure 3 , the pixel PXL can include sub-pixels SP arranged in a first direction DR1. The sub-pixels SP can include first sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3 arranged in the first direction DR1.

[0116] The sub-pixels SP can include light emitting areas EMA. For example, the light emitting areas EMA can include first light emitting areas EMA1, second light emitting areas EMA2, and third light emitting areas EMA3. The first sub-pixels SP1 can include the first light emitting areas EMA1 and non-light emitting areas NEA around the first light emitting areas EMA1. The second sub-pixels SP2 can include the second light emitting areas EMA2 and non-light emitting areas NEA around the second light emitting areas EMA2. The third sub-pixels SP3 can include the third light emitting areas EMA3 and non-light emitting areas NEA around the third light emitting areas EMA3.

[0117] The first light emitting areas EMA1 can be from the light emitting structure EMS (refer to Figure 2The second light emitting area EMA2 can be an area from which light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third light emitting area EMA3 can be an area from which light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. As previously described, each light emitting area EMA can be understood as a pixel defining layer PDL (cf. Fig. 1) corresponding to each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. As previously described, each light emitting area EMA can be understood as a pixel defining layer PDL (cf. Fig. 1) corresponding to each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. Figure 2 The second light emitting area EMA2 can be an area from which light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third light emitting area EMA3 can be an area from which light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. As previously described, each light emitting area EMA can be understood as a pixel defining layer PDL (cf. Fig. 1) corresponding to each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. As previously described, each light emitting area EMA can be understood as a pixel defining layer PDL (cf. Fig. 1) corresponding to each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. Figure 2

[0118] According to embodiments, the pixel PXL (or the display device 100 (cf. Fig. 1)) can further comprise a trench TRCH and an intermediate connection layer MCL. Figure 1

[0119] The trench TRCH can form a separation structure between adjacent sub-pixels SP. For example, the trench TRCH can cause at least a portion of the light emitting structure EMS to be broken. The trench TRCH can cause at least a portion of the light emitting structure EMS to be discontinuously formed.

[0120] The trench TRCH can cause at least a portion of the light emitting structure EMS continuously configured between adjacent sub-pixels SP to be cut off, whereby the risk of a leakage current occurring between adjacent sub-pixels SP can be reduced.

[0121] The trench TRCH can be formed at a periphery of the light emitting area EMA of each of the sub-pixels SP. The trench TRCH can overlap the non-light emitting area NEA.

[0122] The trench TRCH can be formed singularly, but according to embodiments, it can also be formed in plurality between adjacent sub-pixels SP. However, the present disclosure is not limited thereto, and the following description is based on an embodiment in which the trench TRCH is formed singularly between adjacent sub-pixels SP for ease of explanation.

[0123] When viewed in plan, the intermediate connection layer MCL can overlap the trench TRCH. The intermediate connection layer MCL can be configured within the non-light emitting area NEA. The intermediate connection layer MCL can be configured at a periphery of the light emitting area EMA.

[0124] According to embodiments, the intermediate connection layer MCL can comprise a plurality of intermediate connection layers MCL. The plurality of intermediate connection layers MCL can be spaced apart from each other. The plurality of intermediate connection layers MCL can be formed at edges of each of the sub-pixels SP.

[0125] According to embodiments, when the sub-pixel SP has a polygonal shape, each of the plurality of intermediate connection layers MCL can be configured at each of vertex portions of the polygonal shape defined by the sub-pixel SP. For example, as previously described, the sub-pixel SP can have a polygonal shape (cf. Fig. 1). Figure 3 ​​When the sub-pixel SP has a substantially quadrangular shape, a plurality of intermediate connection layers MCL can be disposed at each of the four vertex portions of each of the sub-pixels SP.

[0126] According to an embodiment, the display device 100 can include the trench TRCH to reduce the risk of a leakage current or the like, and can include the intermediate connection layer MCL to form a careful cathode connection structure. Details regarding this will be described later with reference to Figure 8 The later drawings are described later.

[0127] Figure 4 and Figure 5 is a schematic plan view illustrating a pixel according to an embodiment.

[0128] Referring to Figure 4 and Figure 5 , the pixel PXL according to an embodiment is different from the pixel PXL described with reference to Figure 3 in that the first to third sub-pixels SP1 to SP3 are arranged in a diamond form.

[0129] According to an embodiment, the pixel PXL can include one first sub-pixel SP1, two second sub-pixels SP2, and one third sub-pixel SP3. The first sub-pixel SP1 and the third sub-pixel SP3 can be adjacent in a first direction DR1, and the second sub-pixels SP2 can be adjacent in a second direction DR2. According to an embodiment, the first and third sub-pixels SP1, SP3 can have an area greater than that of the second sub-pixels SP2.

[0130] According to an embodiment, the trench TRCH can be disposed at a periphery of each of the light emitting areas EMA. The intermediate connection layer MCL can be disposed at each of the vertex portions of each of the sub-pixels SP.

[0131] On the other hand, in conjunction with Figure 5 , the pixel defining layer PDL according to an embodiment can be disposed at a peripheral portion of the light emitting area EMA. At least a portion of the pixel defining layer PDL can be removed to form the trench TRCH.

[0132] The intermediate connection layer MCL can not be formed integrally between adjacent sub-pixels SP, and can be selectively disposed at a portion of an area between the adjacent sub-pixels SP.

[0133] According to the intermediate connection layer MCL being formed at the vertex portion of each of the sub-pixels SP, the cathode electrode CE (see Figure 2 ) in the sub-pixel SP within the display area DA can be carefully formed, and the risk of a voltage drop or the like can be reduced.

[0134] Figure 6 is a schematic plan view illustrating a pixel according to an embodiment.

[0135] Referring to Figure 6 The pixel PXL can include first to third sub-pixels SP1 to SP3 having at least a part of different areas. According to an embodiment, the third sub-pixel SP3 can have an area greater than that of the first sub-pixel SP1. The third sub-pixel SP3 can have an area greater than that of the second sub-pixel SP2. According to an embodiment, the second sub-pixel SP2 can have an area greater than that of the first sub-pixel SP1, or have the same area as each other. According to an embodiment, the first and second sub-pixels SP1, SP2 can be adjacent to each other in the second direction DR2. The third sub-pixel SP3 can be adjacent to the first sub-pixel SP1 along the first direction DR1, and can be adjacent to the second sub-pixel SP2 along the first direction DR1.

[0136] Figure 7 is a brief plan view showing a pixel according to an embodiment.

[0137] Referring to Figure 7 The first to third sub-pixels SP1 to SP3 can have a polygonal shape. For example, the shapes of the first to third sub-pixels SP1 to SP3 can be hexagonal. The first and third sub-pixels SP1, SP3 can be arranged in the first direction DR1. The second sub-pixel SP2 can be disposed in a direction (or diagonal direction) inclined at an acute angle with respect to the first sub-pixel SP1 on the basis of the second direction DR2.

[0138] However, the structure in which the sub-pixels SP, the light emitting areas EMA, and the intermediate connection layers MCL are arranged is not necessarily limited to the aforementioned example.

[0139] Next, referring to Figures 8 to 11 , a cross-sectional structure of the display device 100 according to an embodiment is described.

[0140] Figure 8 is a brief cross-sectional view showing a display device according to an embodiment. Figure 9 is a brief cross-sectional view showing sub-pixels adjacent to each other.

[0141] Figure 8 and Figure 9 A cross-sectional structure of the display device 100 in the display area DA is briefly shown. For convenience of description, Figure 8 First to third sub-pixels SP1 to SP3 are briefly shown, Figure 9 A light emitting element LD (see Figure 8 ) and a structure adjacent thereto are briefly shown.

[0142] Figure 10 and Figure 11 is a brief cross-sectional view showing a light emitting element according to an embodiment. Figure 10 A light emitting element LD including a series structure is briefly shown. Figure 11A light emitting element LD that emits light of one color is briefly shown from each sub-pixel SP (refer to Figure 8

[0143] According to an embodiment, there is provided a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0144] The substrate SUB can include a silicon wafer substrate formed by a semiconductor process. For example, the substrate SUB can include silicon, germanium, and / or silicon-germanium.

[0145] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include circuit elements of each of the first to third sub-pixels SP1-SP3. For example, the substrate SUB and the pixel circuit layer PCL can include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. It can be that the transistor T_SP1 of the first sub-pixel SP1 is any one of transistors included in a sub-pixel circuit of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2 is any one of transistors included in a sub-pixel circuit of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 is any one of transistors included in a sub-pixel circuit of the third sub-pixel SP3. In Figure 8 In the drawings, for the sake of clear and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0146] The transistor T_SP1 of the first sub-pixel SP1 can include a source region SRA, a drain region DRA, and a gate electrode GE.

[0147] The source region SRA and the drain region DRA can be disposed within the substrate SUB. It can be that a well WL formed by an ion implantation process is disposed within the substrate SUB, and the source region SRA and the drain region DRA are disposed apart from each other within the well WL. A region between the source region SRA and the drain region DRA within the well WL can be defined as a channel region.

[0148] The gate electrode GE can overlap the channel region between the source region SRA and the drain region DRA, and be disposed on the pixel circuit layer PCL. The gate electrode GE can be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE can include an electrically conductive substance.

[0149] ​The plurality of layers included in the pixel circuit layer PCL can include insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns can include the first and second conductive patterns CP1, CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA through a drain connection portion DRC that penetrates one or more of the insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA through a source connection portion SRC that penetrates one or more of the insulating layers.

[0150] The transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1, depending on the connection of the gate electrode GE and the first and second conductive patterns CP1, CP2 with other circuit elements and / or wiring.

[0151] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be configured in the same manner as the transistor T_SP1 of the first sub-pixel SP1.

[0152] In this way, the substrate SUB and the pixel circuit layer PCL can include the circuit elements of each of the first to third sub-pixels SP1-SP3.

[0153] The light emitting element layer LDL is disposed on the pixel circuit layer PCL. The light emitting element layer LDL can include a planarization layer PLNL, an anode electrode AE, a pixel definition layer PDL, a light emitting structure EMS, and a cathode electrode CE. A cover layer CPL and a sealing layer TFE can be disposed on the light emitting element layer LDL.

[0154] The planarization layer PLNL can cover the pixel circuit layer PCL and have a planar surface as a whole. The planarization layer PLNL can include an organic material. According to an embodiment, the planarization layer PLNL can be a via layer.

[0155] The anode electrode AE can be disposed on the planarization layer PLNL. The anode electrode AE can include a first anode electrode AE1 forming a first light emitting element LD1 in the first sub-pixel SP1, a second anode electrode AE2 forming a second light emitting element LD2 in the second sub-pixel SP2, and a third anode electrode AE3 forming a third light emitting element LD3 in the third sub-pixel SP3.

[0156] The first anode electrode AE1 can be electrically connected with the transistor T_SP1 of the first sub-pixel SP1 through a first contact portion CNT1 that penetrates the planarization layer PLNL. The first contact portion CNT1 can also penetrate at least a portion of the pixel circuit layer PCL. The second anode electrode AE2 can be electrically connected with the transistor T_SP2 of the second sub-pixel SP2 through a second contact portion CNT2 that penetrates the planarization layer PLNL. The second contact portion CNT2 can also penetrate at least a portion of the pixel circuit layer PCL. The third anode electrode AE3 can be electrically connected with the transistor T_SP3 of the third sub-pixel SP3 through a third contact portion CNT3 that penetrates the planarization layer PLNL. The third contact portion CNT3 can also penetrate at least a portion of the pixel circuit layer PCL.

[0157] The anode electrode AE can include various conductive materials. The anode electrode AE can be supplied with an anode signal (e.g., a voltage) for the light emitting element LD to emit light, and can form a light recycling structure (e.g., a resonance structure) for improving the light emission efficiency of the light emitting element LD.

[0158] For example (see Figure 10 , Figure 11 ), the anode electrode AE can include a first anode transparent portion AE_T1, an anode reflective portion AE_M, a second anode transparent portion AE_T2, and a third anode transparent portion AE_T3. According to an embodiment, the second anode transparent portion AE_T2 and the third anode transparent portion AE_T3 can be electrically connected to each other in the first to third sub-pixels SP1 to SP3.

[0159] The first to third anode transparent portions AE_T1 to AE_T3 can include at least one of a transparent conductive substance such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO). The anode reflective portion AE_M can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more selected from them. However, the disclosure is not limited thereto.

[0160] According to an embodiment (see Figure 10), the first anode electrode AE1 can further include a first anode buffer part BUF1. The second anode electrode AE2 can further include a second anode buffer part BUF2. The first and second anode buffer parts BUF1, BUF2 can adjust the height of the upper surface of the first and second anode electrodes AE1, AE2 in the first and second sub-pixels SP1, SP2. Thereby, the distance between the anode electrode AE and the cathode electrode CE can be adjusted according to the sub-pixel SP (refer to Figure 8 ).

[0161] The pixel defining layer PDL can be disposed on the anode electrode AE and the planarization layer PLNL. The pixel defining layer PDL can include an opening OP exposing a portion of each of the first to third anode electrodes AE1-AE3. The opening OP of the pixel defining layer PDL can define a light emitting area EMA1-EMA3 of each of the first to third sub-pixels SP1-SP3 (refer to Figure 3 ).

[0162] In an embodiment, the pixel defining layer PDL can include a plurality of inorganic insulating layers. For example, the pixel defining layer PDL can include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3, each of the first to third pixel defining layers PDL1-PDL3 can include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the first pixel defining layer PDL1 can include silicon nitride, the second pixel defining layer PDL2 can include silicon oxide, and the third pixel defining layer PDL3 can include silicon nitride. However, embodiments are not limited thereto. The first to third pixel defining layers PDL1-PDL3 can have a stepped cross-section in a region adjacent to the opening OP.

[0163] According to an embodiment, the width PGAP of the pixel defining layer PDL can be 9 μm or less. For example, the width PGAP of the pixel defining layer PDL can be 0.5 μm to 3.5 μm. For example, the width PGAP of the pixel defining layer PDL defined between the sub-pixels SP adjacent to each other can be about 2 μm.

[0164] Thereby, the size of the non-light emitting area NEA (refer to Figure 3 ) formed by the pixel defining layer PDL can be reduced, and thereby a display device 100 having a high resolution characteristic can be provided. According to an embodiment, the width PGAP of the pixel defining layer PDL can be reduced as the intermediate connection layer MCL according to an embodiment is formed. Details regarding this will be described later.

[0165] As described above, the trench TRCH can be formed in the boundary region BDA between the sub-pixels SP adjacent to each other. The trench TRCH can be formed within the pixel defining layer PDL and the planarization layer PLNL. For example, the trench TRCH can entirely penetrate the pixel defining layer PDL, and can penetrate (e.g., partially penetrate) the planarization layer PLNL.

[0166] The trench TRCH can have a trench height TRCH_H with reference to a thickness direction of the substrate SUB, and can have a trench width TRCH_W with reference to a direction in which the sub-pixels SP are spaced apart from each other. According to an embodiment, the trench height TRCH_H can be greater than half of a thickness of the light emitting structure EMS. In addition, the trench width TRCH_W can be greater than 1 / 4 of the thickness of the light emitting structure EMS. In this case, a common layer (e.g., the first and second charge generation layers CGL1, CGL2, etc.) of the light emitting structure EMS can be suitably disconnected.

[0167] According to an embodiment, a side surface of the trench TRCH can form an included angle of 60 degrees to 90 degrees with respect to a plane in which the substrate SUB is disposed. However, the disclosure is not limited thereto.

[0168] The trench TRCH can cause a discontinuity to be formed in the light emitting structure EMS in the boundary region BDA. For example, the light emitting structure EMS can be disconnected or bent in the boundary region BDA by the trench TRCH. The charge generation layers CGL1, CGL2 included in the light emitting structure EMS can be disconnected by the trench TRCH. For example, in connection with Figure 10 , the first light emitting unit EU1, the first charge generation layer CGL1, the third light emitting unit EU3, and the second charge generation layer CGL2 can be cut off by the trench TRCH. Thus, portions of the light emitting structure EMS included in the first to third sub-pixels SP1-SP3 can be at least partially separated.

[0169] Thus, according to an embodiment, according to the formation of the trench TRCH while the light emitting structure EMS is disposed across the sub-pixels SP, a leakage current between adjacent sub-pixels SP (e.g., in a horizontal direction) can be reduced, a current direction for forming light in each sub-pixel SP can be defined as a substantially vertical direction (i.e., a direction from the anode electrode AE toward the cathode electrode CE), and the reliability of the light emitting element LD can be improved.

[0170] The light emitting structure EMS can be disposed on the anode electrode AE exposed through the opening OP of the pixel defining layer PDL. The light emitting structure EMS can fill the opening OP of the pixel defining layer PDL and be entirely disposed across the first to third sub-pixels SP1-SP3.

[0171] The light emitting structure EMS can include a first light emitting structure EMS1 forming a first light emitting element LD1 in the first sub-pixel SP1, a second light emitting structure EMS2 forming a second light emitting element LD2 in the second sub-pixel SP2, a third light emitting structure EMS3 forming a third light emitting element LD3 in the third sub-pixel SP3, and an intermediate organic structure EMS_M provided in the boundary area BDA.

[0172] According to an embodiment (with reference to FIG. 1), Figure 10 ), each of the light emitting structures EMS (e.g., the first to third light emitting structures EMS1-EMS3) can have a tandem structure. For example, the light emitting structure EMS can include a first light emitting unit EU1 emitting light of a first color, a second light emitting unit EU2 emitting light of a second color, a third light emitting unit EU3 emitting light of a third color, and charge generation layers CGL1, CGL2.

[0173] According to an embodiment, in the light emitting structure EMS, a first light emitting unit EU1, a first charge generation layer CGL1, a third light emitting unit EU3, a second charge generation layer CGL2, and a second light emitting unit EU2 can be sequentially arranged. However, the disclosure is not limited thereto.

[0174] Each of the light emitting units EU1-EU3 can include a hole transport unit HTU1-HTU3, a light emitting layer EML1-EML3, and an electron transport unit ETU1-ETU3.

[0175] The hole transport units HTU1-HTU3 can include a multi-layer structure having a plurality of layers each including a different material from each other. As an example, the hole transport units HTU1-HTU3 can include at least one of a hole injection layer and a hole transport layer, and can further include a light emitting auxiliary layer, an electron blocking layer, and the like according to an embodiment. For example, the hole transport unit can have a multi-layer structure of a hole injection layer / hole transport layer, a hole injection layer / hole transport layer / light emitting auxiliary layer, a hole injection layer / light emitting auxiliary layer, a hole transport layer / light emitting auxiliary layer, an electron blocking layer / hole injection layer / hole transport layer, a hole transport layer or a hole injection layer / hole transport layer / electron blocking layer sequentially arranged and including different materials from each other, or the like. However, the disclosure is not limited to a particular example.

[0176] The light-emitting layers EML1 to EML3 can include a material that can emit light of one color. The light-emitting layers EML1 to EML3 can include a host and a dopant. The host of the light-emitting layers EML1 to EML3, as a light-emitting substance that can trap carriers (electrons and holes) used to generate light, can induce the formation of excitons to be effective. The dopant can include a phosphorescent dopant or a fluorescent dopant. According to an embodiment, examples of the dopant are not particularly limited. According to an embodiment, the dopant can include an organic material, and can also include a metal complex, etc.

[0177] The electron transport portions ETU1 to ETU3 can include a multi-layer structure having a plurality of layers each including a material different from each other. The electron transport portions ETU1 to ETU3 can include at least one of an electron injection layer and an electron transport layer, and according to an embodiment, can further include an electron buffer layer, a hole blocking layer, etc. For example, the electron transport portions ETU1 to ETU3 can have a multi-layer structure of an electron transport layer / electron injection layer, a hole blocking layer / electron transport layer / electron injection layer, an electron regulating layer / electron transport layer / electron injection layer, or a buffer layer / electron transport layer / electron injection layer, etc. However, the present disclosure is not limited to the particular examples.

[0178] However, the present disclosure is not limited thereto. In another embodiment (refer to Figure 11 ), the light-emitting structure EMS can also include different light-emitting layers EML1 to EML3 according to the first to third sub-pixels SP1 to SP3. In this case, the first light-emitting unit EU1 can be configured in the first sub-pixel SP1, the second light-emitting unit EU2 can be configured in the second sub-pixel SP2, and the third light-emitting unit EU3 can be configured in the third sub-pixel SP3. In an embodiment, the hole transport portion HTU and the electron transport portion ETU can be a common layer to the first to third sub-pixels SP1 to SP3. In an embodiment, a first anode buffer portion BUF1 for forming a step can be configured between the first light-emitting layer EML1 and the hole transport portion HTU within the first sub-pixel SP1. A second anode buffer portion BUF2 for forming a step can be configured between the second light-emitting layer EML2 and the hole transport portion HTU within the second sub-pixel SP2. A third anode buffer portion BUF3 for forming a step can be configured between the third light-emitting layer EML3 and the hole transport portion HTU within the third sub-pixel SP3. In this case, at least a portion of the light-emitting structure EMS broken by the trench TRCH (refer to Figure 8 ) can be the hole transport portion HTU that is a common layer between the first to third sub-pixels SP1 to SP3.

[0179] The intermediate light-emitting structure EMS_M can be formed within the same process as the first to third light-emitting structures EMS1 to EMS3, and can include the same materials as each other.

[0180] The intermediate light emitting structure EMS M can be configured between the sub-pixels SP adjacent to each other. The intermediate light emitting structure EMS M can be configured within the trench TRCH in the boundary area BDA. The intermediate light emitting structure EMS M can not overlap with the anode electrode AE when viewed in a plan view. The intermediate light emitting structure EMS M can not overlap with the pixel defining layer PDL when viewed in a plan view.

[0181] The intermediate light emitting structure EMS M can overlap with the intermediate connection layer MCL when viewed in a plan view. For example, the intermediate light emitting structure EMS M can be physically separated from the intermediate connection layer MCL, the intermediate light emitting structure EMS M can be covered by the intermediate connection layer MCL when viewed in a plan view. The intermediate light emitting structure EMS M can be non-contact with the intermediate connection layer MCL. According to an embodiment, a void can be formed between the intermediate light emitting structure EMS M and the intermediate connection layer MCL. For example, the pixel defining layer PDL, the planarization layer PLNL, the intermediate light emitting structure EMS M, and the intermediate connection layer MCL can surround a space, whereby a void can be defined. For example, a first portion of the void can be directly adjacent to the pixel defining layer PDL, a second portion of the void can be directly adjacent to the planarization layer PLNL, a third portion of the void can be directly adjacent to the intermediate light emitting structure EMS M, and a fourth portion of the void can be directly adjacent to the intermediate connection layer MCL. At least a portion of the void can also be filled with air. According to an embodiment, the void defined between the intermediate light emitting structure EMS M and the intermediate connection layer MCL can be referred to as a cavity structure.

[0182] The intermediate light emitting structure EMS M can be formed in an evaporation process for forming the light emitting structure EMS, and can be manufactured through the trench TRCH. Thus, the intermediate light emitting structure EMS M can include a plurality of intermediate light emitting structures EMS M in the display area DA, the trench TRCH can include a plurality of trenches TRCH, and the number of the plurality of intermediate light emitting structures EMS M can be the same as the number of the trenches TRCH.

[0183] The intermediate connection layer MCL can be configured between the sub-pixels SP adjacent to each other. The intermediate connection layer MCL can overlap with the trench TRCH when viewed in a plan view. The intermediate connection layer MCL can relieve a step formed by the trench TRCH.

[0184] The intermediate connection layer MCL can be configured in the boundary area BDA. The intermediate connection layer MCL can be configured on the light emitting structure EMS in the boundary area BDA. For example, the intermediate connection layer MCL can connect the first light emitting structure EMS1 and the second light emitting structure EMS2.

[0185] The intermediate connection layer MCL can be covered by a portion of the cathode electrode CE (e.g., a bridge cathode electrode CE_BR) in the boundary area BDA. The intermediate connection layer MCL can form a bridge in the boundary area BDA to make the cathode electrical path formed across the first to third light emitting elements LD1 to LD3 unbroken.

[0186] For example, the intermediate connection layer MCL can be physically connected with each of the light emitting structures EMS adjacent to each other across the trench TRCH. The intermediate connection layer MCL can be covered by the bridge cathode electrode CE_BR. Thereby, the cathode electrode CE can reduce the risk of being broken by the trench TRCH, and the common electrode can be formed intricately within the display area DA.

[0187] According to an embodiment, the intermediate connection layer MCL can include various materials.

[0188] For example, the intermediate connection layer MCL can include an organic material having an electron transport property. For example, the intermediate connection layer MCL can include an organic material forming an electron transport layer.

[0189] However, the disclosure is not limited thereto. For example, the intermediate connection layer MCL can include a conductive material. Or according to an embodiment, the intermediate connection layer MCL can also include an inorganic material, and in another example, the intermediate connection layer MCL can also include other organic materials.

[0190] The cathode electrode CE can be disposed on the light emitting structure EMS. The cathode electrode CE can be commonly provided to the first to third sub-pixels SP1 to SP3. The cathode electrode CE can function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0191] At least a portion of the cathode electrode CE can be disposed on the intermediate connection layer MCL. The cathode electrode CE can include a base cathode electrode CE_BS and a bridge cathode electrode CE_BR. The base cathode electrode CE_BS can be included in the light emitting element LD and can overlap the light emitting area EMA when viewed in a plan view. The bridge cathode electrode CE_BR can be disposed in the boundary area BDA and can overlap the intermediate light emitting structure EMS_M and the intermediate connection layer MCL when viewed in a plan view. For example, the bridge cathode electrode CE_BR can be in contact with the intermediate connection layer MCL.

[0192] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping the first anode electrode AE1, and a portion of the cathode electrode CE overlapping the first anode electrode AE1 can constitute a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping the second anode electrode AE2, and a portion of the cathode electrode CE overlapping the second anode electrode AE2 can constitute a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping the third anode electrode AE3, and a portion of the cathode electrode CE overlapping the third anode electrode AE3 can constitute a third light emitting element LD3.

[0193] A cover layer CPL is disposed on the cathode electrode CE. The cover layer CPL can cover the light emitting elements LD. According to an embodiment, the cover layer CPL can be directly adjacent to the intermediate connection layer MCL in the boundary area BDA. According to an embodiment, the cover layer CPL can include an inorganic material or an organic material. The cover layer CPL can have a relatively high refractive index, whereby light extraction efficiency of the light emitting elements LD can be improved. However, the disclosure is not limited thereto.

[0194] When viewed in plan, the cover layer CPL can overlap the intermediate light emitting structure EMS_M and the intermediate connection layer MCL.

[0195] An encapsulation layer TFE is disposed on the cover layer CPL. The encapsulation layer TFE can prevent oxygen and / or moisture and the like from permeating to the light emitting element layer LDL.

[0196] An optical function layer OFL is disposed on the encapsulation layer TFE. In an embodiment, the optical function layer OFL can be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL can be separately manufactured and attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform a function of protecting the layers below including the encapsulation layer TFE.

[0197] When viewed in plan, the encapsulation layer TFE can overlap the intermediate light emitting structure EMS_M and the intermediate connection layer MCL.

[0198] The optical function layer OFL can include a color filter layer CFL and a lens array LA. The color filter layer CFL can include first to third color filters CFL to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CFL to CF3 can pass light of mutually different wavelength ranges. For example, the first to third color filters CFL to CF3 can pass red, green, and blue light, respectively.

[0199] In an embodiment, the first to third color filters CF1 to CF3 can be partially overlapped in the boundary area BDA. In another embodiment, it can be that the first to third color filters CF1 to CF3 are spaced apart from each other, providing a black matrix between the first to third color filters CF1 to CF3.

[0200] The lens array LA is configured on the color filter layer CFL. The lens array LA can include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 can improve light extraction efficiency by outputting light respectively emitted from the first to third light emitting elements LD1 to LD3 in an intended path.

[0201] Referring to Figures 12 to 20 , a manufacturing method of the display device 100 according to an embodiment will be described with reference to FIGS. 10A to 10E. Repetitive explanations of the foregoing contents can be omitted or not repeated. Figure 8

[0202] Figure 12 is a brief sequence diagram illustrating a manufacturing method of a display device according to an embodiment. Figure 13 is a brief sequence diagram illustrating a step of forming a light emitting element layer on a pixel circuit layer according to an embodiment. Figures 14 to 20 is a brief diagram illustrating a manufacturing method of a display device according to an embodiment by process steps. For convenience of explanation, Figures 14 to 17 and Figure 20 are cross-sectional diagrams illustrating a manufacturing method of a display device 100 according to an embodiment by process steps, with reference to the cross-sectional structure illustrated in FIG. 1. Figure 9 and Figure 18 are plan diagrams illustrating a manufacturing method of a display device 100 according to an embodiment by process steps, with reference to the plan structure illustrated in FIG. 2. Hereinafter, for convenience of explanation, for explanation of the sub-pixels SP, with reference to the first and second sub-pixels SP1, SP2 formed adjacent to each other, a manufacturing method of the display device 100 will be described. Figure 19 Figure 4 Figure 5

[0203] Referring to Figure 12 , the manufacturing method of the display device 100 can include a step of forming a pixel circuit layer on a substrate (S100), a step of forming a light emitting element layer on the pixel circuit layer (S200), a step of forming a cover layer and an encapsulation layer on the light emitting element layer (S300), and a step of forming an optical functional layer on the encapsulation layer (S400).

[0204] Referring to Figure 13 ​​​​The step of forming the light emitting element layer on the pixel circuit layer (S200) can include a step of forming a planarization layer (S220), a step of forming an anode electrode (S230), a step of forming a pixel defining layer (S240), a step of forming a trench (S250), a step of forming a light emitting structure (S260), a step of forming an intermediate connection layer (S270), and a step of forming a cathode electrode (S280).

[0205] In combination Figure 8 With reference to Figure 12 In the step of forming the pixel circuit layer on the substrate (S100), the transistor can be patterned on the substrate SUB to form the pixel circuit layer PCL.

[0206] According to embodiments, the conductive layer and the insulating layer on the substrate SUB can be formed based on a general process for manufacturing a semiconductor device. For example, the conductive layer or the insulating layer on the substrate SUB can be formed by a photolithography process, and can be etched by various manners (wet etching, dry etching, etc.), and can be evaporated by various manners (sputtering, chemical vapor deposition, etc.). The present disclosure is not necessarily limited to the specific examples.

[0207] With reference to Figures 12 to 14 In the step of forming the light emitting element layer on the pixel circuit layer (S200), the step of forming the planarization layer (S220) can be performed.

[0208] In this step (S220), the planarization layer PLNL can offset the step by the layer formed below.

[0209] With reference to Figures 12 to 14 In the step of forming the light emitting element layer on the pixel circuit layer (S200), the step of forming the anode electrode (S230) can be performed.

[0210] In this step (S230), the first and second anode electrodes AE1, AE2 for forming the first and second sub-pixels SP1, SP2 can be patterned. In addition, the first and second contact portions CNT1, CNT2 that penetrate the planarization layer PLNL can be formed, and the first and second anode electrodes AE1, AE2 can be electrically connected with the circuit elements of the pixel circuit layer.

[0211] With reference to Figures 12 to 14 In the step of forming the light emitting element layer on the pixel circuit layer (S200), the step of forming the pixel defining layer (S240) can be performed.

[0212] In this step (S240), the pixel defining layer PDL can be patterned to cover between the first and second anode electrodes AE1, AE2. According to embodiments, the pixel defining layer PDL can be patterned to have a relatively narrow width PGAP. At least a portion of the pixel defining layer PDL can be disposed on the planarization layer PLNL.

[0213] Referring to Figure 12 , Figure 13 and Figure 15 , in the step (S200) of forming the light emitting element layer on the pixel circuit layer, a step (S250) of forming a trench can be performed.

[0214] In this step (S250), at least a portion of each of the pixel defining layer PDL and the planarization layer PLNL within the boundary area BDA can be removed, and a trench TRCH can be formed.

[0215] Referring to Figure 12 , Figure 13 and Figure 16 , in the step (S200) of forming the light emitting element layer on the pixel circuit layer, a step (S260) of forming a light emitting structure can be performed.

[0216] In this step (S260), a light emitting structure EMS (see Figure 8 ) can be formed (e.g., evaporated), and at least a portion of the light emitting structure EMS can be broken or bent by the trench TRCH. In addition, at least a portion of the light emitting structure EMS can be provided within the trench TRCH, and an intermediate light emitting structure EMS_M can be formed.

[0217] Referring to Figure 12 , Figure 13 and Figure 17 , in the step (S200) of forming the light emitting element layer on the pixel circuit layer, a step (S270) of forming an intermediate connection layer can be performed.

[0218] In this step (S270), the intermediate connection layer MCL can be patterned to overlap the intermediate light emitting structure EMS_M within the boundary area BDA. Thus, the intermediate connection layer MCL can connect the first light emitting structure EMS1 of the first sub-pixel SP1 and the second light emitting structure EMS2 of the second sub-pixel SP2.

[0219] In this step (S270), the intermediate connection layer MCL can be patterned with a fine silicon mask MAS including silicon. When the intermediate connection layer MCL is patterned with the fine silicon mask MAS, a material can be evaporated at a relatively high incident angle. For example, in an evaporation process with the fine silicon mask MAS, the incident angle of material evaporation can be 80 degrees or more (e.g., 80 degrees to 90 degrees), in which case the range of evaporation shadow can be reduced. In addition, the size of the evaporation opening DOP formed in the fine silicon mask MAS can be substantially finely defined, and a portion of the pixel defining layer PDL having a relatively narrow width PGAP can finely pattern the intermediate connection layer MCL. According to an embodiment, the width OWD of the evaporation opening DOP can be 0.2 μm to 0.8 μm. For example, the width OWD of the evaporation opening DOP can be about 0.5 μm. That is, as the intermediate connection layer MCL according to an embodiment is manufactured with a fine silicon mask, the width PGAP of the pixel defining layer PDL can be reduced, and a display device 100 having a high resolution characteristic can be provided.

[0220] However, the present disclosure is not necessarily limited thereto. For example, the intermediate connection layer MCL can also be patterned with a fine metal mask or other types of masks.

[0221] According to an embodiment, an evaporation process for forming the intermediate connection layer MCL can be performed with evaporation material provided from an evaporation source. According to an embodiment, the evaporation source can be implemented in various ways. For example, the evaporation source can be a point-type source fixed at a specific position to sequentially provide evaporation material to an evaporation target substrate. Or the evaporation source can be a line-type evaporation source moved in a scanning manner and sequentially providing evaporation material to a line-type range of an evaporation target substrate. According to an embodiment, when the evaporation source is a point-type source, a more finely designed sub-pixel can be possible, and a process margin for a process for forming the intermediate connection layer MCL and the pixel defining layer PDL can be more ensured.

[0222] According to an embodiment, a plurality of intermediate connection layers MCL can be formed within a display area DA (refer to Figure 8 ). According to an embodiment, the intermediate connection layers MCL can be patterned within the same process (e.g., simultaneously). Or according to an embodiment, the intermediate connection layers MCL can also be formed separately in a process performed a plurality of times. For example, referring to Figure 18 and Figure 19 , after a portion of the intermediate connection layer MCL is patterned at a first position with a fine silicon mask MAS in a first time interval, other intermediate connection layers MCL are patterned with the fine silicon mask MAS moved (or, shifted) from the first position to a second position in a second time interval after the first time interval.

[0223] Referring to Figure 12 , Figure 13 and Figure 20 , in the step (S200) of forming the light emitting element layer on the pixel circuit layer, the step (S280) of forming the cathode can be performed.

[0224] In this step (S280), the cathode electrode CE (refer to Figure 8 ) can be vapor-deposited throughout the display area DA (refer to Figure 8 ). The cathode electrode CE can cover the light emitting structure EMS (refer to Figure 8 ), and can cover the intermediate connection layer MCL. The intermediate connection layer MCL offsets the step below, so the cathode electrode CE can be appropriately patterned without being broken in the boundary area BDA.

[0225] Referring to Figure 12 and Figure 20 , in the step (S300) of forming the cover layer and the encapsulation layer on the light emitting element layer, the cover layer CPL and the encapsulation layer TFE can be formed on the cathode electrode CE (refer to Figure 8 ) and the intermediate connection layer MCL.

[0226] In this step (S300), the cover layer CPL and the encapsulation layer TFE can be configured, and the light emitting element layer LDL can be appropriately passivated.

[0227] In conjunction with Figure 8 , referring to Figure 12 , in the step (S400) of forming the optical function layer on the encapsulation layer, the optical function layer OFL including the color filters CF1 to CF3 and the lens array LA can be formed.

[0228] After that, according to the embodiment, the overcoat layer OC and the cover window CW, etc. can be provided, and the display device 100 according to the embodiment can be provided.

[0229] Figure 21 is a block diagram illustrating an embodiment of an electronic device.

[0230] Referring to Figure 21 , the electronic device 1000 can include a processor 1100 and one or more display devices 1210, 1220. The electronic device 1000 can implement a display system.

[0231] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 can include an application processor, a graphic processor, a microprocessor, a central processing device (CPU), etc. The processor 1100 can be connected to other constituent elements of the electronic device 1000 through a bus system and control them.

[0232] According to an embodiment, the processor 1100 can provide input image data to the display devices 1210, 1220, which can display images based on the input image data provided to the processor 1100.

[0233] In Figure 21 an embodiment, the electronic device 1000 is shown to include first and second display devices 1210, 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1 and to the second display device 1220 through a second channel CH2.

[0234] Through the first channel CH1, the processor 1100 can transmit first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 can display images based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be constructed identically to the display device 100 described with reference to Figure 1

[0235] Through the second channel CH2, the processor 1100 can transmit second image data IMG2 and a second control signal CTRL2 to the second display device 1220. The second display device 1220 can display images based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be constructed identically to the display device 100 described with reference to Figure 1

[0236] ​​The electronic device 1000 can include a portable computer, a mobile phone, a smart phone, a tablet personal computer, and a smart watch, a watch phone, a PMP (portable multimedia player), a navigation, a UMPC (ultra mobile personal computer), and the like, which provide an image display function. In addition, the electronic device 1000 can include at least one of a head-mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0237] According to an embodiment, the electronic device 1000 can further include a memory device, a storage device, an input / output device, and a power supply device.

[0238] The memory device can store data required to perform the operation of the electronic device 1000. The memory device can operate as a work memory and / or a buffer memory for the processor 1100. For example, the memory device can include one or more volatile memory devices such as a DRAM device, a SRAM device, or a mobile DRAM device.

[0239] The storage device can store data according to a control signal or data from the processor 1100. The storage device can include one or more non-volatile storage devices that can maintain data even if the power of the electronic device 1000 is turned off. In some embodiments, the storage device can include a SSD (solid state drive), an HDD (hard disk drive), a CD-ROM (compact disc read-only memory), or the like.

[0240] The input / output device can include an input device such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, and an output device such as a speaker, a printer. In an embodiment, the display device 1210, 1220 can be included in the input / output device.

[0241] The power supply device can supply power required to operate the electronic device 1000. For example, the power supply device can be a power management integrated circuit (PMIC). In one embodiment, the power supply device can supply power to the display devices 1210 and 1220.

[0242] Figure 22 It shows Figure 21 A perspective view of an application example of an electronic device.

[0243] Reference Figure 22 , Figure 21 The electronic device 1000 may be applicable to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on a user's head.

[0244] The head-mounted display device 2000 may include a headband 2100 and a display device storage box 2200. The headband 2100 may be connected to the display device storage box 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may wrap around the sides of the user's head, while the vertical strap wraps around the top of the user's head. However, the embodiment is not limited thereto. For example, the headband 2100 may also be implemented in the form of eyeglass frames, a helmet, or the like.

[0245] The display device storage box 2200 can store Figure 21 The first and second display devices 1210, 1220. The display device storage box 2200 can also store Figure 21 Processor 1100.

[0246] Figure 23 It shows Figure 22 Figure 1 shows a head-mounted display device worn by a user.

[0247] Reference Figure 23 In the head mounted display device 2000, a first display device 1210 (see Figure 21 ) of the first display panel DP1 and the second display device 1220 (refer to Figure 21 ) of the second display panel DP2. The head mounted display device 2000 may further include one or more lenses LLNS, RLNS.

[0248] In the display device receiving box 2200 , the right-eye lens RLNS may be disposed between the first display panel DP1 and the user's right eye. In the display device receiving box 2200 , the left-eye lens LLNS may be disposed between the second display panel DP2 and the user's left eye.

[0249] An image output from the first display panel DP1 can be displayed to the right eye of the user through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 toward the right eye of the user. The right eye lens RLNS can perform an optical function for adjusting a viewing distance between the first display panel DP1 and the right eye of the user.

[0250] An image output from the second display panel DP2 can be displayed to the left eye of the user through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 toward the left eye of the user. The left eye lens LLNS can perform an optical function for adjusting a viewing distance between the second display panel DP2 and the left eye of the user.

[0251] In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS can include an optical lens having a cross section of a pancake shape. In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS can include a multi-channel lens including sub-areas having different optical characteristics from each other. In this case, it can be that each display panel outputs an image corresponding to the respective sub-areas of the multi-channel lens, and the output images are displayed to the user through the respective sub-areas.

[0252] As observed above, the preferred embodiments with reference to the present disclosure have been described, but it should be understood by those skilled in the art or those having ordinary knowledge in the art that various modifications and changes can be made to the present disclosure within the scope of the concept and technical field of the present disclosure recited in the appended claims, without departing from the scope of the present disclosure.

[0253] Therefore, the technical scope of the present disclosure is not limited by the contents recited in the detailed description of the specification, and should be determined only by the claims.

Claims

1. A display device comprising sub-pixels, the sub-pixels comprising a first sub-pixel and a second sub-pixel adjacent to each other, wherein, The display device includes: a pixel circuit layer including a pixel circuit on a substrate; and a light emitting element layer disposed on the pixel circuit layer, The light emitting element layer includes: a planarization layer; an anode electrode disposed on the planarization layer; a pixel defining layer at least a part of which is disposed on the anode electrode; a trench passing through the pixel defining layer and at least a part of the planarization layer; a light emitting structure disposed across the first sub-pixel and the second sub-pixel and at least a part of which is disposed on the anode electrode exposed through the pixel defining layer, the light emitting structure including a first light emitting structure forming the first sub-pixel and a second light emitting structure forming the second sub-pixel; an intermediate light emitting structure disposed in the trench in a boundary region between the first sub-pixel and the second sub-pixel and including the same material as the light emitting structure; an intermediate connection layer disposed in a boundary region between the first sub-pixel and the second sub-pixel and connecting the first light emitting structure and the second light emitting structure; and a cathode electrode disposed across the first sub-pixel and the second sub-pixel and at least a part of which is disposed on the intermediate connection layer, The intermediate light emitting structure and the intermediate connection layer are physically separated from each other.

2. The display device according to claim 1, wherein a gap is formed between the intermediate light emitting structure and the intermediate connection layer.

3. The display device according to claim 1, wherein the intermediate light emitting structure includes a plurality of intermediate light emitting structures, the trench includes a plurality of trenches, the number of the plurality of intermediate light emitting structures and the number of the plurality of trenches are the same as each other.

4. The display device according to claim 1, wherein the intermediate connection layer includes a plurality of intermediate connection layers, the plurality of intermediate connection layers are disposed apart from each other at edges of the sub-pixels.

5. The display device according to claim 4, wherein each of the sub-pixels has a polygonal shape, the plurality of intermediate connection layers are disposed at each of vertex portions of the polygonal shape.

6. The display device according to claim 1, wherein a width of the pixel defining layer is 0.5 μm to 3.5 μm.

7. The display device according to claim 1, wherein the light emitting structure includes a common layer, each of the first sub-pixel and the second sub-pixel commonly including the common layer, the common layer is broken by the trench.

8. The display device according to claim 7, wherein a height of the trench is greater than half a thickness of the light emitting structure, a width of the trench is greater than 1 / 4 of the thickness of the light emitting structure.

9. The display device according to claim 7, wherein a side surface of the trench forms an included angle of 60 degrees to 90 degrees with respect to a plane on which the substrate is disposed.

10. The display device according to claim 1, wherein the display device further includes: a cover layer disposed across the first sub-pixel and the second sub-pixel and on the cathode electrode; and an encapsulation layer disposed on the cover layer, When viewed in a planar manner, the cover layer and the encapsulation layer overlap with the intermediate connection layer and the intermediate light emitting structure.

11. The display device according to claim 10, wherein: The cover layer and the intermediate connecting layer are directly adjacent to each other.

12. The display device according to claim 1, wherein The intermediate connection layer includes an organic material having electron transport properties.

13. The display device according to claim 1, wherein The substrate includes a silicon substrate.

14. A method for manufacturing a display device, the display device comprising sub-pixels, the sub-pixels comprising a first sub-pixel and a second sub-pixel adjacent to each other, wherein, The manufacturing method of the display device includes: forming a pixel circuit layer including a pixel circuit on a substrate; and forming a light emitting element layer on the pixel circuit layer; The step of forming the light emitting element layer includes: forming a planarization layer; forming an anode electrode on the planarization layer; forming a pixel defining layer covering at least a portion of the anode electrode; forming a trench that penetrates the pixel definition layer and at least partially penetrates the planarization layer; forming a light-emitting structure across the first sub-pixel and the second sub-pixel; forming an intermediate connection layer disposed in a boundary region between the first sub-pixel and the second sub-pixel; and forming a cathode electrode across the first sub-pixel and the second sub-pixel, The step of forming the intermediate connection layer includes the step of patterning the intermediate connection layer using a fine silicon mask.

15. The method for manufacturing a display device according to claim 14, wherein: The step of forming the light emitting structure includes the step of disconnecting at least a portion of the light emitting structure by the groove.

16. The method for manufacturing a display device according to claim 14, wherein: The step of forming the light emitting structure includes the step of forming an intermediate light emitting structure disposed in the trench.

17. The method for manufacturing a display device according to claim 16, wherein: The light-emitting structure includes a first light-emitting structure forming the first sub-pixel and a second light-emitting structure forming the second sub-pixel. The step of forming the intermediate connection layer includes: patterning the intermediate connection layer to overlap the intermediate light emitting structure when viewed in a planar manner; and connecting the first light emitting structure and the second light emitting structure through the intermediate connection layer.

18. The method for manufacturing a display device according to claim 14, wherein: The fine silicon mask includes an evaporation opening portion, The width of the vapor deposition opening is 0.2 μm to 0.8 μm.

19. The method for manufacturing a display device according to claim 14, wherein: The step of patterning the intermediate connection layer includes the step of patterning a plurality of intermediate connection layers, The plurality of intermediate connection layers are patterned simultaneously.

20. The method for manufacturing a display device according to claim 14, wherein: The step of patterning the intermediate connection layer includes the step of patterning a plurality of intermediate connection layers, A portion of the plurality of intermediate connection layers is patterned in a first time interval, and another portion of the plurality of intermediate connection layers is patterned in a second time interval after the first time interval.

21. An electronic device comprising: A processor provides input image data; A display device displays an image based on the input image data and includes a sub-pixel region; and A power supply supplies power to the display device, The display device includes: a sub-pixel forming the sub-pixel region and including a first sub-pixel and a second sub-pixel adjacent to each other; a pixel circuit layer including a pixel circuit on a substrate; and a light emitting element layer disposed on the pixel circuit layer, The light emitting element layer includes: a planarization layer; an anode electrode disposed on the planarization layer; a pixel definition layer at least a portion of which is disposed on the anode electrode; a trench passing through the pixel definition layer and at least a portion of the planarization layer; a light emitting structure disposed across the first sub-pixel and the second sub-pixel and at least a portion of which is disposed on the anode electrode exposed through the pixel definition layer, the light emitting structure including a first light emitting structure forming the first sub-pixel and a second light emitting structure forming the second sub-pixel; an intermediate light emitting structure disposed within the trench in a boundary region between the first sub-pixel and the second sub-pixel and including the same material as the light emitting structure; an intermediate connection layer disposed in a boundary region between the first sub-pixel and the second sub-pixel and connecting the first light emitting structure and the second light emitting structure; and a cathode electrode disposed across the first sub-pixel and the second sub-pixel and at least a portion of which is disposed on the intermediate connection layer, The intermediate light emitting structure and the intermediate connection layer are physically separated from each other.

Images