Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate; a pixel circuit layer over the substrate; a first anode, a second anode, and a third anode spaced apart above the pixel circuit layer; a pixel defining layer over the pixel circuit layer and overlapping a portion of the first anode, a portion of the second anode, and a portion of the third anode; first, second, and third emission structures over the first, second, and third anodes, respectively, and including curved edges, respectively; and a common layer over the first emission structure, the second emission structure, the third emission structure, and the pixel defining layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0051297, filed on April 17, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. BACKGROUND

[0004] With the development of information technology, the importance of a display device, which is a medium of connection between a user and information, is emphasized. Due to the importance of the display device, the use of various types of display devices, such as liquid crystal display devices and organic light emitting display devices, has increased.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore it can not necessarily be construed as existing technology that is already known to those skilled in the art. SUMMARY

[0006] Aspects of some embodiments of the present disclosure include a method of manufacturing a display device through an indirect patterning process and a display device manufactured through the method.

[0007] According to some embodiments of the present disclosure, a display device includes a substrate, a pixel circuit layer above the substrate, first, second, and third anodes spaced apart above the pixel circuit layer, a pixel definition layer above the pixel circuit layer and overlapping a portion of the first anode, a portion of the second anode, and a portion of the third anode, first, second, and third emission structures above the first, second, and third anodes, respectively, and including curved edges, respectively, and a common layer above the first, second, third emission structures, and the pixel definition layer.

[0008] The edges of the first, second, and third emission structures can have a slope on the pixel definition layer.

[0009] The first, second, and third emission structures can have an inverted conical shape.

[0010] The widths of the first, second, and third emission structures can increase in a thickness direction.

[0011] Each of the first, second, and third emission structures can include a hole injection layer, a hole transport layer above the hole injection layer, an emission layer above the hole transport layer, and a buffer layer above the emission layer.

[0012] The common layer may include: an electron transport layer over the first emission structure, the second emission structure, the third emission structure, and the pixel defining layer; an electron injection layer over the electron transport layer; and a cathode over the electron injection layer.

[0013] The common layer may further include: an auxiliary electrode above the cathode.

[0014] The cathode and the auxiliary electrode may comprise different materials.

[0015] The cathode may include a semi-transparent conductive material, wherein the auxiliary electrode includes a transparent conductive material.

[0016] Each of the first emission structure, the second emission structure and the third emission structure may include: a hole injection layer; a hole transport layer, above the hole injection layer; an emission layer, above the hole transport layer; a buffer layer, above the emission layer; an electron transport layer, above the buffer layer; and an electron injection layer, above the electron transport layer.

[0017] The common layer may include a cathode over the first emission structure, the second emission structure, the third emission structure, and the pixel defining layer.

[0018] The display device may further include: an encapsulation layer above the common layer.

[0019] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: forming a first anode, a second anode, a third anode and a pixel defining layer above a pixel circuit layer above a substrate; forming a covering layer above a portion of the pixel defining layer; forming a first emission structure above the first anode, the second anode, the third anode, the pixel defining layer and the covering layer; forming a first sacrificial layer above the first emission structure; forming a first photoresist over a portion of the first sacrificial layer; removing the first emission structure and the first sacrificial layer above the second anode, the third anode and the covering layer; and removing the first photoresist.

[0020] The cover layer may include: a first layer having a first thickness; and a second layer over the first layer and having a second thickness smaller than the first thickness.

[0021] The width of the second layer may be greater than the width of the first layer.

[0022] The second layer may overlap edges of the first anode, the second anode, and the third anode.

[0023] The method can further include forming a second emissive structure over the first sacrificial layer, the second anode, the third anode, the pixel-defining layer, and the capping layer; forming a second sacrificial layer over the second emissive structure; forming a second photoresist over a portion of the second sacrificial layer; removing the second emissive structure and the second sacrificial layer over the first sacrificial layer, the third anode, and the capping layer; and removing the second photoresist.

[0024] The method can further include forming a third emissive structure over the first sacrificial layer, the second sacrificial layer, the third anode, the pixel-defining layer, and the capping layer; forming a third sacrificial layer over the third emissive structure; forming a third photoresist over a portion of the third sacrificial layer; removing the third emissive structure and the third sacrificial layer over the first sacrificial layer, the second sacrificial layer, and the capping layer; and removing the third photoresist.

[0025] The method can further include removing the first sacrificial layer through the third sacrificial layer and the capping layer.

[0026] The method can further include forming a common layer over the first emissive structure, the second emissive structure, the third emissive structure, and the pixel-defining layer; and forming an encapsulation layer over the common layer. BRIEF DESCRIPTION OF DRAWINGS

[0027] Aspects of some embodiments of the present disclosure are further described in detail by reference to the drawings, in which:

[0028] Figure 1 FIG. 1 is a block diagram illustrating a display apparatus according to one or more embodiments.

[0029] Figure 2 FIG. 2 is a block diagram illustrating a sub-pixel according to one or more embodiments.

[0030] Figure 3 FIG. 3 is a plan view illustrating a display panel according to one or more embodiments.

[0031] Figure 4 FIG. 4 is a cross-sectional view illustrating a display panel according to one or more embodiments.

[0032] Figure 5 FIG. 5 is a cross-sectional view illustrating a display panel according to one or more embodiments.

[0033] Figure 6 FIG. 6 is a plan view illustrating a pixel according to one or more embodiments.

[0034] Figure 7 FIG. 7 is a cross-sectional view taken along line I-I’ of FIG. 6 according to one or more embodiments. Figure 6

[0035] FIG. 7 is a cross-sectional view taken along line I-I’ of FIG. 6 according to one or more embodiments.Figure 8 According to one or more embodiments Figure 6 A cross-sectional view taken along line II'.

[0036] Figure 9 According to one or more embodiments Figure 6 A cross-sectional view taken along line II'.

[0037] Figure 10 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments.

[0038] Figures 11 to 27 is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment.

[0039] Figure 28 is a block diagram illustrating a display system according to one or more embodiments.

[0040] Figures 29 to 32 It is an icon Figure 28 A perspective view showing an application example of the display system. DETAILED DESCRIPTION

[0041] By referring to the detailed description and the accompanying drawings of the embodiments, the aspects of some embodiments of the present disclosure and the methods for realizing the same can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand aspects of the present disclosure can be omitted. Unless otherwise noted, throughout the drawings and written description, the same reference numerals, characters or combinations thereof refer to the same elements, and therefore their repeated descriptions can be omitted.

[0042] The described embodiments may have various modifications, may be embodied in different forms, and should not be construed as limited to the embodiments illustrated herein. When describing embodiments, the use of "may," "might," or "may not" corresponds to one or more embodiments of the present disclosure.

[0043] In view of the entire content of this disclosure, those skilled in the art will understand that each appropriate feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, may be technically interlocked and operated in various appropriate manners, and each embodiment may be implemented independently of each other or in combination with each other in any appropriate manner, unless otherwise stated or implied.

[0044] In the drawings, the relative sizes and positions of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, because the dimensions and thicknesses of elements, as depicted in the drawings, are arbitrary, the present disclosure should not be limited to the precise illustrations given. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of the elements depicted therein. As a result, unless otherwise indicated, the presence of cross-hatching or shading in a drawing generally does not indicate or imply any particular material, material property, dimension, ratio, commonality between illustrated elements, and / or any other characteristic, property, quality, or attribute of an element, either actual or to be given.

[0045] Various embodiments are described herein with reference to cross-sectional illustrations of schematic illustrations of embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Further, the particular shapes of the structures disclosed herein are not intended to limit the embodiments of the present disclosure, and are instead provided as illustrative examples of structures that can be implemented to implement embodiments of the present disclosure. Thus, embodiments disclosed herein should not be construed as limited to the particular shapes of elements as illustrated, but rather, are to include deviations in shapes that result from, for example, manufacturing.

[0046] For example, an implant region illustrated as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can cause some implantation in the region between the buried region and the surface through which implantation occurs.

[0047] For ease of explanation, spatial relative terms such as "below," "under," "beneath," "lower," "below," "above," "upper," "on," "higher," "top," "side" (e.g., as in "sidewall"), and the like, can be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below," "under," or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both orientations. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it indicates that the first part is disposed on the upper side or lower side of the second part, without regard to the gravity direction of the second part.

[0048] Furthermore, the phrase "in plan view" means when viewing the object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-sectional illustration of the object portion from the side through a vertical cut. The term "overlapping" or "overlapped" means that a first object can be above or below or to the side of a second object, and vice versa. Furthermore, the term "overlapping" can include stacking, facing or facing towards, extending across, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The expression "not overlapping" can include such as "spaced apart" or "separated" or "offset" as well as any other suitable equivalent meaning as would be appreciated and understood by one of ordinary skill in the art. The terms "facing" and "facing towards" can mean that a first object can be directly or indirectly opposite a second object. In case a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although still facing each other.

[0049] It will be understood that when an element, layer, region or component is referred to as being "on" or "connected to" or "(operably or communicatively) coupled to" another element, layer, region or component, it can be directly on, directly connected to, or directly coupled to the other element, layer, region or component, or intervening elements, layers, regions or components can be present. In addition, it will be understood that when a layer, region or component is referred to as being "formed on" or "formed over" or "connected to" or "coupled to" another layer, region or component, it can be directly formed on, directly formed over, directly connected to, or directly coupled to the other layer, region or component, or intervening layers, regions or components can be present. Further, this can be referred to collectively as direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component can be directly electrically connected or electrically coupled to the other layer, region or component, or one or more intervening layers, regions or components can be present. The one or more intervening components can include switches, resistors, and / or capacitors, etc. In describing embodiments, expressions referring to connection indicate electrical connection, unless expressly described as direct connection, and "directly connected / directly coupled" or "directly on" refers to a component directly connected or coupled to another component or directly on another component, without intervening components.

[0050] Also, in this specification, when a portion of a layer, film, region, or plate, etc. is formed on another portion, the direction of formation is not limited to the upward direction, but includes formation of the portion on a side surface or in a downward direction. Conversely, when a portion of a layer, film, region, or plate, etc. is formed "under" another portion, this includes not only the case where the portion is "directly under" the other portion, but also the case where there is yet another portion between the portion and the other portion. At the same time, other expressions of relationship between components such as "between," "directly between," "adjacent," and "directly adjacent" can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0051] For purposes of the present disclosure, expressions such as "at least one of... " or "any of... " or "one or more of... " when following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one of a group consisting of X, Y, and Z" can be interpreted as X alone, Y alone, Z alone, or any combination or subset of X, Y, and Z such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" means "and / or" and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of... ", "one or more of", "one of", and other similar phrases when used after a list of elements, modify the entire list of elements and do not modify the individual elements of the list. When the statement "C to D" is made, this means C and above and D and below, unless otherwise indicated.

[0052] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. An element described as“first” need not necessarily be present before or before another element or other elements. The terms“first,”“second,” etc. can also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms“first,”“second,” etc. can be used herein to designate the“first category (or first group)” the“second category (or second group)” etc.

[0053] In examples, the x-axis, the y-axis and / or the z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, the y-axis and the z-axis can be perpendicular to each other or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0054] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises” and“comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0055] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described consecutively can be performed substantially simultaneously, or can be performed in an order opposite to the described order.

[0056] As used herein, the terms“substantially,”“approximately,”“about,” and like terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured values and calculated values that would be recognized by those of ordinary skill in the art. For example,“substantially” can include a range of + / - 5% of a recited value. Considering the measurements in question and the errors associated with measuring a particular quantity (i.e., limitations of the measurement system),“about” or“approximately,” as used herein, includes the recited value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example,“about” can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the recited value. Further, when describing embodiments of the disclosure, the use of“may” indicates that“one or more embodiments of the disclosure.”

[0057] In some embodiments, well-known structures and devices can be described in the form of one or more functional blocks (e.g., block diagrams), units, and / or modules in the accompanying drawings to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will appreciate that the blocks, units, and / or modules are functional logical groupings of hardware, software, and / or firmware that physically reside in a memory element, a processor, an electrical circuit, a hardware component, a software component, or a combination thereof. This can be formed using semiconductor-based manufacturing techniques or other technologies. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware can be programmed using software and controlled using firmware and / or software. Furthermore, each block, unit, and / or module can be implemented by dedicated hardware, or a combination of dedicated hardware and a processor (e.g., one or more programmed microprocessors and associated circuitry) that executes software and / or firmware that performs the functions of the dedicated hardware. Moreover, in some embodiments, blocks, units, and / or modules can be physically combined into fewer blocks, units, and / or modules, or physically separated into additional blocks, units, and / or modules, without departing from the scope of the disclosure.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0059] Figure 1 is a block diagram illustrating a display device DD according to one or more embodiments.

[0060] Referring to Figure 1 , the display apparatus DD can include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0061] The display panel DP can include sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP can be connected to the data driver 130 through first to n-th data lines DL1 to DLn. Wherein m and n are integers equal to or greater than 1.

[0062] The sub-pixels SP can generate light of two or more colors. For example, each of the sub-pixels SP can generate light of a color such as red, green, blue, cyan, magenta, or yellow.

[0063] Two or more of the sub-pixels SP can form one pixel PXL. For example, as illustrated in Figure 1 , the pixel PXL can include three sub-pixels SP. Accordingly, the pixel PXL can emit light of various colors and various brightnesses depending on a combination of light emitted from the sub-pixels SP included in the pixel PXL.

[0064] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS can include a horizontal synchronization signal and a start signal indicating the start of each frame, etc.

[0065] The gate driver 120 can be located at one side of the display panel DP. However, embodiments are not limited to the above-described example. For example, the gate driver 120 can be divided into two or more drivers that are physically and / or logically distinguished from each other. These drivers can be located at a first side of the display panel DP and a second side of the display panel DP opposite the first side. Accordingly, the gate driver 120 can be located around the display panel DP in various forms depending on embodiments.

[0066] The data driver 130 can be connected to the sub-pixels SP arranged in a column direction through the first to n-th data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS can include a source start signal, a source shift clock, and a source output enable signal, etc.

[0067] The data driver 130 can receive a voltage from the voltage generator 140. The data driver 130 can apply a data signal having a gray voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn using the received voltage. When a gate signal is applied to each of the first to mth gate lines GL1 to GLm, a data signal corresponding to the image data DATA can be applied to the first to nth data lines DL1 to DLn. Accordingly, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0068] In an embodiment, the gate driver 120 and the data driver 130 can include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0069] The voltage generator 140 can operate in response to a voltage control signal VCS provided from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages, and provide the generated voltages to components of the display apparatus DD, such as the gate driver 120, the data driver 130, and the controller 150. The voltage generator 140 can receive an input voltage from an external apparatus of the display apparatus DD, and can generate a plurality of voltages by adjusting the received voltage.

[0070] The voltage generator 140 can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixel SP through the power line PL. In other embodiments, at least one of the first and second power voltages can be provided to the display apparatus DD from an external apparatus.

[0071] Further, the voltage generator 140 can provide various voltages and / or signals. For example, the voltage generator 140 can provide one or more initialization voltages to be applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light emitting element of the sub-pixel SP, a specific reference voltage can be applied to each of the first to nth data lines DL1 to DLn. The voltage generator 140 can generate the reference voltage, and can transmit the reference voltage to the data driver 130. For example, during a display operation for displaying an image on the display panel DP, a common pixel control signal can be applied to the sub-pixel SP, and the voltage generator 140 can generate the pixel control signal. In an embodiment, the voltage generator 140 can provide the pixel control signal to the sub-pixel SP through a pixel control line PXCL. Although in the above-described embodiment, the voltage generator 140 is described as being provided in the display apparatus DD, the voltage generator 140 can be provided in an external apparatus of the display apparatus DD. Figure 1The pixel control line PXCL is connected between the voltage generator 140 and the display panel DP in the middle illustration, but embodiments are not limited thereto. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0072] The controller 150 can control the overall operation of the display apparatus DD. The controller 150 can receive input image data IMG and a control signal CTRL corresponding thereto from an external apparatus. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0073] The controller 150 can convert the input image data IMG to be suitable for the display apparatus DD or the display panel DP, and then can output image data DATA. In an embodiment, the controller 150 can arrange the input image data IMG on a line basis to be suitable for the sub-pixel SP, and then output the image data DATA.

[0074] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 can be mounted on a single integrated circuit. As Figure 1 In the middle illustration, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 can be functionally separated components in the single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 can be provided as a component separate from the driver integrated circuit DIC.

[0075] Figure 2 is a block diagram illustrating a sub-pixel SPij according to one or more embodiments. In Figure 2 In the middle illustration, Figure 1 a sub-pixel SPij among the sub-pixels SP of FIG. 1, which is located on an i-th row (where i is an integer equal to or greater than 1 and equal to or less than m) and a j-th column (where j is an integer equal to or greater than 1 and equal to or less than n).

[0076] Referring to Figure 2 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light emitting element LD.

[0077] The light emitting element LD is connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can be connected to Figure 1one of power lines PL of the display panel DP to receive a first power voltage. The second power voltage node VSSN can be connected to Figure 1 another one of the power lines PL of the display panel DP to receive a second power voltage. The first power voltage can have a voltage level higher than a voltage level of the second power voltage.

[0078] The light emitting element LD can include an anode AE and a cathode CE. The anode AE can be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. For example, the anode AE can be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC. The cathode CE can be connected to the second power voltage node VSSN. The light emitting element LD is configured to emit light based on a current flowing from the anode AE to the cathode CE.

[0079] The sub-pixel circuit SPC can be connected to Figure 1 an i-th gate line GLi among the first to m-th gate lines GL1 to GLm of the display panel DP, and Figure 1 a j-th data line DLj among the first to n-th data lines DL1 to DLn of the display panel DP. In response to a gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC can control the light emitting element LD to emit light based on a data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can be further connected to Figure 1 a pixel control line PXCL of the display panel DP. In this case, the sub-pixel circuit SPC can further control the light emitting element LD in response to a pixel control signal received through the pixel control line PXCL.

[0080] For the above operations, the sub-pixel circuit SPC can include circuit elements, such as transistors and one or more capacitors.

[0081] The transistors of the sub-pixel circuit SPC can include P-type transistors and / or N-type transistors. In an embodiment, the transistors of the sub-pixel circuit SPC can include metal oxide silicon field effect transistors (MOSFETs). In an embodiment, the transistors of the sub-pixel circuit SPC can include amorphous silicon semiconductors, single crystal silicon semiconductors, polycrystalline silicon semiconductors, or oxide semiconductors, etc.

[0082] Figure 3 is a plan view illustrating a display panel DP according to one or more embodiments.

[0083] Referring to Figure 3 , the display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be located around the display area DA.

[0084] The display panel DP includes sub-pixels SP in the display area DA. The sub-pixels SP can be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP can be arranged in a matrix form in the first direction DR1 and the second direction DR2. As another example, the sub-pixels SP can be arranged in a zigzag form in the first direction DR1 and the second direction DR2. The arrangement of the sub-pixels SP can vary depending on embodiments. The first direction DR1 can refer to a row direction, and the second direction DR2 can refer to a column direction.

[0085] Two or more of the sub-pixels SP among the sub-pixels SP can form one pixel PXL. Although Figure 3 The illustrated pixel PXL includes three sub-pixels SP1 to SP3, but embodiments are not limited thereto. For example, the pixel PXL can include two sub-pixels SP. Hereinafter, for convenience of explanation, it is assumed that the pixel PXL includes first to third sub-pixels SP1 to SP3.

[0086] Each of the first to third sub-pixels SP1 to SP3 can generate light of one color among various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for a clear and brief description, it is assumed that the first sub-pixel SP1 is configured to generate light of red, the second color pixel SP2 is configured to generate light of green, and the third sub-pixel SP3 is configured to generate light of blue.

[0087] Each of the first to third sub-pixels SP1 to SP3 can include at least one light emitting element configured to generate light. In embodiments, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of the same color. For example, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of blue. In other embodiments, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of different colors. For example, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of red, green, and blue, respectively.

[0088] As the display panel DP, a self-emissive display panel such as an LED display panel using a micro- or nano-scale light emitting diode as a light emitting element and an organic light emitting display panel (OLED panel) using an organic light emitting diode as a light emitting element can be used.

[0089] A component for controlling the sub-pixels SP can be located in the non-display area NDA. A line (for example, a gate line GL, a data line DL, a power line PL, and a pixel control line PXCL) connected to the sub-pixels SP can be located in the non-display area NDA. Figure 1 The first to m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power line PL, and the pixel control line PXCL of the display panel DP can be located in the non-display area NDA.

[0090] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 of the display panel DP may be located in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 may be located in the non-display area NDA. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be implemented as a separate device from the display panel DP. Figure 1 The driver integrated circuit DIC may be connected to the lines located in the non-display area NDA. In other embodiments, the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 may be implemented as a single integrated circuit separate from the display panel DP.

[0091] In embodiments, the display area DA may have various shapes. The display area DA may have a closed loop shape including linear edges and / or curved edges. For example, the display area DA may have shapes such as polygonal, circular, semicircular, and elliptical.

[0092] In an embodiment, the display panel DP may have a planar display surface. In an embodiment, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In the above cases, the display panel DP and / or the substrate of the display panel DP may include a material having flexible properties.

[0093] Figure 4 is a cross-sectional view illustrating a display panel DP according to one or more embodiments.

[0094] refer to Figure 4 The display panel DP may include a substrate SUB, and a pixel circuit layer PCL, a display element layer DPL, and a light function layer LFL sequentially stacked on the substrate SUB in a third direction DR3 crossing the first direction DR1 and the second direction DR2.

[0095] The substrate SUB may be made of an insulating material such as glass or resin. For example, the substrate SUB may include a glass substrate. As another example, the substrate SUB may include a polyimide (PI) substrate. As another example, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process.

[0096] In an embodiment, the substrate SUB can be made of a material having flexibility so as to be bendable or foldable, and can have a single-layer structure or a multi-layer structure. For example, the material having flexibility can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, embodiments are not limited thereto.

[0097] The pixel circuit layer PCL can be located on the substrate SUB. The pixel circuit layer PCL can include insulating layers and semiconductor patterns and conductive patterns between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as circuit elements or lines, etc.

[0098] The circuit elements of the pixel circuit layer PCL can include Figure 3 respective sub-pixel circuits SPC of the sub-pixels SP (refer to Figure 2 ). In other words, the circuit elements of the pixel circuit layer PCL can be provided as transistors of the sub-pixel circuits SPC and one or more capacitors.

[0099] The lines of the pixel circuit layer PCL can include lines connected to the sub-pixels SP. The lines of the pixel circuit layer PCL can include various signal lines and / or voltage lines suitable for driving the display element layer DPL.

[0100] The display element layer DPL can be located on the pixel circuit layer PCL. The display element layer DPL can include light emitting elements of the sub-pixels SP.

[0101] The light function layer LFL can be located on the display element layer DPL. The light function layer LFL can include a light conversion pattern having color conversion particles and / or scattering particles. For example, the color conversion particles can include quantum dots. The quantum dots can convert a wavelength (or a color) of light emitted from the display element layer DPL. The light function layer LFL can further include a light scattering pattern having scattering particles. In an embodiment, the light conversion pattern and the light scattering pattern can be omitted.

[0102] The light function layer LFL can further include a color filter layer including color filters. Each of the color filters can selectively transmit light of a respective wavelength (or a respective color). In an embodiment, the color filter layer can be omitted.

[0103] The display panel DP can further include a window (not shown). The window can be provided on the light functional layer LFL to protect an exposed surface (or upper surface) of the display panel DP. The window can protect the display panel DP from external impact. The window can be connected to the light functional layer LFL by an optically transparent adhesive (or bonding agent). The window can have a multi-layer structure including layers selected from among a glass substrate, a plastic film, and a plastic substrate. The multi-layer structure can be formed by a continuous process or a bonding process using an adhesive layer. All or part of the window can have flexibility.

[0104] Figure 5 is a cross-sectional view illustrating a display panel DP’ according to one or more embodiments.

[0105] Referring to Figure 5 , the display panel DP’ can include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light functional layer LFL. The substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL can be configured in the same manner as the substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL described with reference to Figure 4 In the following, repeated explanations will be omitted.

[0106] The input sensing layer ISL can sense a user input on an upper surface (or display surface) of the display panel DP’. The input sensing layer ISL can include a component suitable for sensing an external object such as a user’s hand or a pen, etc. For example, the input sensing layer ISL can include a touch electrode.

[0107] Figure 6 is a plan view illustrating a pixel PXL according to one or more embodiments.

[0108] Referring to Figure 6 , the pixel PXL can include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0109] The first sub-pixel SP1 can include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1. The second sub-pixel SP2 can include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2. The third sub-pixel SP3 can include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3.

[0110] The first emission area EMA1 can be an area in which light is emitted from a portion of a first emission structure EMS1 (refer to Figure 7 ) corresponding to the first sub-pixel SP1. The second emission area EMA2 can be an area in which light is emitted from a portion of a second emission structure EMS2 (refer toFigure 7 ) corresponding to the third sub-pixel SP3. The third emission area EMA3 can be an area in which light is emitted from a part of the third emission structure EMS3 (refer to Figure 7 ) corresponding to the third sub-pixel SP3.

[0111] Figure 7 is a cross-sectional view taken along the line I-I’ of Figure 6 in accordance with one or more embodiments.

[0112] Referring to Figure 7 , the pixel circuit layer PCL can be located on the substrate SUB. The pixel circuit layer PCL can include insulating layers, semiconductor patterns, and conductive patterns stacked on the substrate SUB. The insulating layers can include a buffer layer, one or more interlayer insulating layers, and one or more passivation layers. The semiconductor patterns and the conductive patterns can be placed between the insulating layers. The conductive patterns can be used as at least some of circuit elements and lines, etc. The conductive patterns can include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag), but embodiments are not limited thereto.

[0113] The circuit elements can include respective sub-pixel circuits SPC (refer to Figure 6 ) of the first to third sub-pixels SP1, SP2, and SP3 (refer to Figure 2 ). The sub-pixel circuits SPC can include transistors and one or more capacitors. Each transistor can include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, in a case where the substrate SUB is formed of a silicon substrate, the semiconductor portion can be included in the substrate SUB, and the gate electrode can be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In one or more embodiments, in a case where the substrate SUB is formed of a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. Each capacitor can include electrodes spaced apart from each other. For example, each capacitor can include electrodes spaced apart from each other in the third direction DR3, with an insulating layer interposed between the electrodes spaced apart from each other in the third direction DR3.

[0114] The lines of the pixel circuit layer PCL can include signal lines, such as gate lines, emission control lines, and / or data lines, connected to each of the first to third sub-pixels SP1 to SP3. The lines can further include a line connected to the first power voltage node VDDN of Figure 2 . Further, the lines can further include a line connected to the second power voltage node VSSN of Figure 2 .

[0115] In an embodiment, a via layer can be located on the pixel circuit layer PCL. The via layer can cover the pixel circuit layer PCL and can have an overall planar surface. The via layer can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbon nitride (SiCN), but embodiments are not limited thereto.

[0116] The display element layer DPL can be located on the pixel circuit layer PCL. The display element layer DPL can include the first to third anodes AE1 to AE3, the pixel definition layer PDL, the first to third emission structures EMS1 to EMS3, and the common layer CML.

[0117] The first to third anodes AE1 to AE3 can be located on the pixel circuit layer PCL. The first to third anodes AE1 to AE3 can be spaced apart from each other. For example, the first to third anodes AE1 to AE3 can be located in the first to third sub-pixels SP1 to SP3 (refer to FIG. 1), respectively. The first anode AE1 can be provided as an anode AE (refer to FIG. 1) included in a sub-pixel circuit SPC (refer to FIG. 1) of the first sub-pixel SP1. The second anode AE2 can be provided as an anode AE included in a sub-pixel circuit SPC of the second sub-pixel SP2. The third anode AE3 can be provided as an anode AE included in a sub-pixel circuit SPC of the third sub-pixel SP3. Figure 6 Figure 2 Figure 2

[0118] The first to third anodes AE1 to AE3 can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). However, embodiments are not limited to the above examples. For example, the first to third anodes AE1 to AE3 can include titanium nitride (TiN).

[0119] The pixel definition layer PDL can be located on the pixel circuit layer PCL. The pixel definition layer PDL can overlap a portion of the first to third anodes AE1 to AE3. For example, the pixel definition layer PDL can be located directly on a portion of the first to third anodes AE1 to AE3. The pixel definition layer PDL can include openings through which respective portions of the first to third anodes AE1 to AE3 are exposed. The openings in the pixel definition layer PDL can define respective emission areas of the first to third sub-pixels SP1 to SP3. In other words, the pixel definition layer PDL can be placed in a non-emission area NEA (refer to FIG. 1) and can define first to third emission areas EMA1 to EMA3 (refer to FIG. 1). Figure 6 Figure 6

[0120] ​​​​​The pixel definition layer PDL can include a plurality of inorganic insulating layers. Each of the inorganic insulating layers can include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel definition layer PDL can include first to third inorganic insulating layers which are continuously stacked. The first to third inorganic insulating layers can include silicon nitride, silicon oxide, and silicon nitride, respectively. However, embodiments are not limited thereto.

[0121] The first to third emission structures EMS1 to EMS3 can be respectively located on the first to third anodes AE1 to AE3. For example, the first to third emission structures EMS1 to EMS3 can be respectively located on the first to third anodes AE1 to AE3 which are exposed through the openings of the pixel definition layer PDL. The first to third emission structures EMS1 to EMS3 can overlap a portion of the pixel definition layer PDL. For example, the first to third emission structures EMS1 to EMS3 can be directly located on a portion of the pixel definition layer PDL.

[0122] An edge of each of the first to third emission structures EMS1 to EMS3 can be gently curved. For example, the edge of each of the first to third emission structures EMS1 to EMS3 can not have a steep step. For example, the edge of each of the first to third emission structures EMS1 to EMS3 can have a gentle slope on the pixel definition layer PDL. For example, the edge of each of the first to third emission structures EMS1 to EMS3 can have an inverted taper structure (or shape). In this case, the width (or diameter) of each of the first to third emission structures EMS1 to EMS3 can increase in the third direction DR3 (or the thickness direction).

[0123] If the edge of each of the first to third emission structures EMS1 to EMS3 has a steep (e.g., almost vertical) step, a structure located on the first to third emission structures EMS1 to EMS3 can be disconnected. For example, the cathode CE can be disconnected due to the steep step, thereby destabilizing a contact structure. A separate structure such as a spacer can be introduced to remove the steep step, but the manufacturing process can be more complicated and the manufacturing cost can increase. If the edge of each of the first to third emission structures EMS1 to EMS3 is gently curved, the possibility of the cathode CE being disconnected can be reduced or easily prevented, and a stable contact structure can be ensured.

[0124] The first emission structure EMS1 can include a hole injection layer HIL, a hole transport layer HTL, a first emission layer EML1, and a buffer layer BFL. The hole injection layer HIL of the first emission structure EMS1 can be located on the first anode AE1. The hole transport layer HTL of the first emission structure EMS1 can be located on the hole injection layer HIL of the first emission structure EMS1. The first emission layer EML1 can be located on the hole transport layer HTL of the first emission structure EMS1. In an embodiment, the first emission layer EML1 can emit red light. The buffer layer BFL of the first emission structure EMS1 can be located on the first emission layer EML1. The buffer layer BFL of the first emission structure EMS1 can protect the first emission layer EML1. For example, the buffer layer BFL of the first emission structure EMS1 can reduce or prevent penetration of foreign substances such as oxygen or water into the first emission layer EML1. The buffer layer BFL can include an inorganic material such as silicon carbon nitride, but embodiments are not limited thereto.

[0125] The second emission structure EMS2 can include a hole injection layer HIL, a hole transport layer HTL, a second emission layer EML2, and a buffer layer BFL. The hole injection layer HIL of the second emission structure EMS2 can be located on the second anode AE2. The hole transport layer HTL of the second emission structure EMS2 can be located on the hole injection layer HIL of the second emission structure EMS2. The second emission layer EML2 can be located on the hole transport layer HTL of the second emission structure EMS2. In an embodiment, the second emission layer EML2 can emit green light. The buffer layer BFL of the second emission structure EMS2 can be located on the second emission layer EML2. The buffer layer BFL of the second emission structure EMS2 can protect the second emission layer EML2. For example, the buffer layer BFL of the second emission structure EMS2 can reduce or prevent penetration of foreign substances such as oxygen or water into the second emission layer EML2.

[0126] The third emission structure EMS3 can include a hole injection layer HIL, a hole transport layer HTL, a third emission layer EML3, and a buffer layer BFL. The hole injection layer HIL of the third emission structure EMS3 can be located on the third anode AE3. The hole transport layer HTL of the third emission structure EMS3 can be located on the hole injection layer HIL of the third emission structure EMS3. The third emission layer EML3 can be located on the hole transport layer HTL of the third emission structure EMS3. In an embodiment, the third emission layer EML3 can emit blue light. The buffer layer BFL of the third emission structure EMS3 can be located on the third emission layer EML3. The buffer layer BFL of the third emission structure EMS3 can protect the third emission layer EML3. For example, the buffer layer BFL of the third emission structure EMS3 can reduce or prevent penetration of foreign substances such as oxygen or water into the third emission layer EML3.

[0127] The first to third emission layers EML1 to EML3 may each include an organic light emitting material, but the embodiment is not limited thereto. For example, the first to third emission layers EML1 to EML3 may each include an inorganic light emitting material, quantum dots, quantum rods, etc.

[0128] In an embodiment, the first to third emission structures EMS1 to EMS3 may each include a material that is resistant to water or etchants. For example, the first to third emission structures EMS1 to EMS3 may each include a material that substantially maintains the display device DD (refer to FIG. 1 ) even after exposure to water (or air). Figure 1 ) such as driving voltage, emission efficiency, color coordinates, and lifespan. For example, the first to third emission structures EMS1 to EMS3 may include a material that substantially maintains the original shapes of the first to third emission structures EMS1 to EMS3 and the above-mentioned characteristics of the display device DD even after being exposed to an etchant including phosphoric acid, nitric acid, and acetic acid.

[0129] The common layer CML may continuously extend over the first to third sub-pixels SP1 to SP3 (refer to Figure 6 ) is provided. For example, the common layer CML may be located on the first to third emission structures EMS1 to EMS3 and the pixel defining layer PDL. In one or more embodiments, the common layer CML may include an electron transport layer ETL, an electron injection layer EIL and a cathode CE. The electron transport layer ETL may be located on the first to third emission structures EMS1 to EMS3 and the pixel defining layer PDL. The electron injection layer EIL may be located on the electron transport layer ETL. The cathode CE may be located on the electron injection layer EIL. As described above, the cathode CE may be continuously located on the electron injection layer EIL without being disconnected. The common layer CML may include an electron transport layer ETL and an electron injection layer EIL divided into separate layers, but the embodiment is not limited thereto. For example, the electron transport layer ETL and the electron injection layer EIL may be integrated into a single layer. The single layer may include a composite material in which the material of the electron transport layer ETL and the material of the electron injection layer EIL are mixed.

[0130] The encapsulation layer TFE may be located on the display element layer DPL. For example, the encapsulation layer TFE may be located on the cathode CE. The encapsulation layer TFE may reduce or prevent oxygen or water from penetrating into the display element layer DPL. The encapsulation layer TFE may include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y). For example, the organic layer can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB), etc. However, embodiments are not limited to the above examples. For example, the encapsulation layer TFE can include aluminum oxide (AlO x ).

[0131] Figure 8 is a cross-sectional view taken along line I-I’ of Figure 6 , the explanation of the contents repeated with the contents of Figure 8 , is simplified or omitted. Figure 7

[0132] Referring to Figure 8 , the common layer CML’ can further include an auxiliary electrode AXE. The auxiliary electrode AXE can be located between the cathode CE and the encapsulation layer TFE. The auxiliary electrode AXE can help form a stable contact structure together with the cathode CE. The auxiliary electrode AXE can include a material different from that of the cathode CE. For example, the auxiliary electrode AXE can include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode CE can include a semi-transparent conductive material such as silver (Ag) or a silver alloy (Ag alloy). In this case, the cathode CE can partially reflect and amplify light emitted from the first to third emission layers EML1 to EML3. The amplified light can be output through the cathode CE and the auxiliary electrode AXE.

[0133] Figure 9 is a cross-sectional view taken along line I-I’ of Figure 6 , the explanation of the contents repeated with the contents of Figure 9 , is simplified or omitted. Figure 7

[0134] Referring to Figure 9 , the first to third emission structures EMS1’ to EMS3’ can each further include an electron transport layer ETL and an electron injection layer EIL. The electron transport layer ETL can be located on the buffer layer BFL. The electron injection layer EIL can be located on the electron transport layer ETL. In this case, the common layer CML” can be substantially the same as the cathode CE.

[0135] Figure 10 is a block diagram illustrating a method of manufacturing a display apparatus according to one or more embodiments. Figures 11 to 27 is a cross-sectional view schematically illustrating a method of manufacturing a display apparatus according to an embodiment. Hereinafter, a method of manufacturing a display apparatus using an indirect patterning process will be described with reference to Figures 10 to 27 .

[0136] Referring to​​Figure 10 and Figure 11 The process S100 of forming anodes and a pixel defining layer can be performed. First to third anodes AE1 to AE3 spaced apart from each other can be formed on the pixel circuit layer PCL on the substrate SUB. For example, the first anode AE1 can be patterned at a position corresponding to the first emission area EMA1 (refer to Figure 6 ). The second anode AE2 can be patterned at a position corresponding to the second emission area EMA2 (refer to Figure 6 ). The third anode AE3 can be patterned at a position corresponding to the third emission area EMA3 (refer to Figure 6 ). For example, the pixel defining layer PDL can be formed on a portion of the first to third anodes AE1 to AE3 and the pixel circuit layer PCL. For example, after the pixel defining layer PDL is formed completely across the first to third anodes AE1 to AE3 and the pixel circuit layer PCL, the pixel defining layer PDL can be etched to form openings through which the first to third anodes AE1 to AE3 are exposed.

[0137] Referring to Figure 10 , the process S200 of forming a cover layer can be performed. Figure 12 The process S200 of forming a cover layer according to one or more embodiments is illustrated. Referring to Figure 10 and Figure 12 , the cover layer CL can be formed on the pixel defining layer PDL through an etching process. For example, the cover layer CL having a multi-layer structure can be formed on the pixel defining layer PDL. The cover layer CL can include a first layer L1 and a second layer L2. The first layer L1 can be located on the pixel defining layer PDL. The second layer L2 can be located on the first layer L1.

[0138] In one or more embodiments, a thickness t1 of the first layer L1 and a thickness t2 of the second layer L2 can be different from each other. The term "thickness" can refer to a length measured in the third direction DR3. For example, the thickness t1 of the first layer L1 can be greater than the thickness t2 of the second layer L2. For example, the thickness t1 of the first layer L1 can be about 2000 angstroms and the thickness t2 of the second layer L2 can be about In one or more embodiments, the first layer L1 and the second layer L2 can be formed of different materials. For example, the first layer L1 can include a nickel-aluminum alloy (AlNi alloy) and the second layer L2 can include aluminum (Al), but embodiments are not limited thereto.

[0139] The capping layer CL can be formed in an undercut structure. For example, the width of the second layer L2 can be greater than the width of the first layer L1. The term "width" can refer to a length measured in a direction (or longitudinal direction) perpendicular to the third direction DR3. During an etching process, the capping layer CL having the undercut structure can be formed by adjusting the selectivity with respect to the first and second layers L1 and L2. For example, the etching rate of the first layer L1 can be higher than the etching rate of the second layer L2. The capping layer CL can overlap at least a portion of the edges of each of the first to third anodes AE1 to AE3. For example, the second layer L2 of the capping layer CL can overlap at least a portion of the edges of each of the first to third anodes AE1 to AE3. The capping layer CL having the undercut structure can help to form the edges of each of the first to third emission structures EMS1 to EMS3 (refer to FIG. 1) in a gently curved shape. Figure 7 ) can be formed in a gently curved shape.

[0140] Figure 13 A process S200 of forming a capping layer is illustrated according to one or more other embodiments. Referring to Figure 10 and Figure 13 , the capping layer CL' can be formed on the pixel definition layer PDL through an etching process. For example, the capping layer CL' having a single layer structure can be formed on the pixel definition layer PDL. The capping layer CL' can have titanium (Ti), but embodiments are not limited thereto. The capping layer CL' can be formed in an undercut structure. In the case where the capping layer CL' having the undercut structure is formed, the number of masks used during a manufacturing process can be reduced.

[0141] Referring to Figure 10 and Figures 14 to 17 , a process S300 of patterning the first emission structure can be performed. Referring to Figure 14 , the first emission structure EMS1 can be formed on the first to third anodes AE1 to AE3, the pixel definition layer PDL, and the capping layer CL (or the second layer L2). The first emission structure EMS1 on the capping layer CL can be formed to have a steep (e.g., almost vertical) step. On the other hand, the first emission structure EMS1 on the first to third anodes AE1 to AE3 and the pixel definition layer PDL can be formed to be gently curved. For example, during a process of depositing the first emission structure EMS1, the capping layer CL having the undercut structure shields or interferes with the deposition material, whereby the edges of the first emission structure EMS1 can be formed in a gently curved shape. Thereafter, the first sacrificial layer SCL1 can be formed on the first emission structure EMS1. Due to the capping layer CL having the undercut structure, the first sacrificial layer SCL1 can be partially formed on the pixel definition layer PDL. The first sacrificial layer SCL1 can include aluminum (Al) or silver (Ag), etc., but embodiments are not limited thereto.

[0142] Referring toFigure 15 , a first photoresist PR1 may be formed on the first sacrificial layer SCL1. The first photoresist PR1 may be formed to cover a structure on the first anode AE1. The first photoresist PR1 may be formed through an exposure process and a development process.

[0143] refer to Figure 16 , the first emission structure EMS1 and the first sacrificial layer SCL1 may be partially removed. For example, the second anode AE2 and the third anode AE3, as well as the first emission structure EMS1 and the first sacrificial layer SCL1 on the cover layer CL, may be removed by an etching process. The etching process may be performed as a wet etch or a dry etch. As a result, the first emission structure EMS1 and the first sacrificial layer SCL1 on the first anode AE1 may remain.

[0144] refer to Figure 17 , the first photoresist PR1 may be removed. For example, the first photoresist PR1 may be removed by an ashing process. Thus, the first emission structure EMS1 may be patterned at a position corresponding to the first anode AE1. A first sacrificial layer SCL1 may be placed on the first emission structure EMS1.

[0145] refer to Figure 10 as well as Figures 18 to 21 , a process of patterning the second emission structure S400 may be performed. Figure 18 , the second emission structure EMS2 can be formed on the second anode AE2 and the third anode AE3, the first sacrificial layer SCL1, the pixel defining layer PDL and the cover layer CL (or the second layer L2). The second emission structure EMS2 on the cover layer CL can be formed to have a steep (for example, almost vertical) step. On the other hand, the second emission structure EMS2 on the second anode AE2 and the third anode AE3, the first sacrificial layer SCL1 and the pixel defining layer PDL can be formed to be gently curved. For example, during the process of depositing the second emission structure EMS2, the cover layer CL having an undercut structure shields the deposited material, whereby the edge of the second emission structure EMS2 can be formed in a gently curved shape. Thereafter, the second sacrificial layer SCL2 can be formed on the second emission structure EMS2. Due to the cover layer CL having an undercut structure, the second sacrificial layer SCL2 can be partially formed on the pixel defining layer PDL. The second sacrificial layer SCL2 can include the same material as the first sacrificial layer SCL1, but the embodiment is not limited thereto.

[0146] refer to Figure 19 The second photoresist PR2 may be formed on the second sacrificial layer SCL2. The second photoresist PR2 may be formed to cover the structure on the second anode AE2. The second photoresist PR2 may be formed through an exposure process and a development process.

[0147] refer to Figure 20 , the second emission structure EMS2 and the second sacrificial layer SCL2 may be partially removed. For example, the second emission structure EMS2 and the second sacrificial layer SCL2 on the first sacrificial layer SCL1, the third anode AE3, and the cover layer CL may be removed by an etching process. The etching process may be performed as a wet etching or a dry etching process. As a result, the second emission structure EMS2 and the second sacrificial layer SCL2 on the second anode AE2 may remain.

[0148] refer to Figure 21 , the second photoresist PR2 can be removed. For example, the second photoresist PR2 can be removed by an ashing process. Therefore, the second emission structure EMS2 can be patterned at a position corresponding to the second anode AE2. The second sacrificial layer SCL2 can be placed on the second emission structure EMS2.

[0149] refer to Figure 10 as well as Figures 22 to 25 , a process S500 of patterning the third emission structure may be performed. Figure 22 , the third emission structure EMS3 can be formed on the third anode AE3, the first sacrificial layer SCL1 and the second sacrificial layer SCL2, the pixel defining layer PDL and the cover layer CL (or the second layer L2). The third emission structure EMS3 on the cover layer CL can be formed to have a steep (for example, almost vertical) step. On the other hand, the third emission structure EMS3 on the third anode AE3, the first sacrificial layer SCL1 and the second sacrificial layer SCL2 and the pixel defining layer PDL can be formed to be gently curved. For example, during the process of depositing the third emission structure EMS3, the cover layer CL having an undercut structure shields the deposited material, whereby the edge of the third emission structure EMS3 can be formed in a gently curved shape. Thereafter, the third sacrificial layer SCL3 can be formed on the third emission structure EMS3. Due to the cover layer CL having an undercut structure, the third sacrificial layer SCL3 can be partially formed on the pixel defining layer PDL. The third sacrificial layer SCL3 can include the same material as the first sacrificial layer SCL1, but the embodiment is not limited thereto.

[0150] refer to Figure 23 A third photoresist PR3 may be formed on the third sacrificial layer SCL3. The third photoresist PR3 may be formed to cover the third anode AE3. The third photoresist PR3 may be formed through an exposure process and a development process.

[0151] refer to Figure 24The third emission structure EMS3 and the third sacrificial layer SCL3 can be partially removed. For example, the first and second sacrificial layers SCL1 and SCL2 and the third emission structure EMS3 and the third sacrificial layer SCL3 on the capping layer CL can be removed by an etching process. The etching process can be performed as a wet etching or a dry etching. Accordingly, the third emission structure EMS3 and the third sacrificial layer SCL3 on the third anode AE3 can be left.

[0152] Referring to Figure 25 The third photoresist PR3 can be removed. For example, the third photoresist PR3 can be removed by an ashing process. Accordingly, the third emission structure EMS3 can be patterned at a position corresponding to the third anode AE3. The third sacrificial layer SCL3 can be disposed on the third emission structure EMS3.

[0153] Referring to Figure 10 and Figure 26 A process S600 of removing the capping layer and the sacrificial layers can be performed. The capping layer CL (refer to Figure 25 ) and the first to third sacrificial layers SCL1 to SCL3 (refer to Figure 25 ) can be removed by an etching process. The etching process can be performed as a wet etching. Accordingly, upper surfaces of the first to third emission structures EMS1 to EMS3 can be exposed. After the process S600 of removing the sacrificial layers, a drying process can be performed to remove moisture. For example, the drying process can be performed at a temperature of about 90°C under a vacuum condition.

[0154] Referring to Figure 10 and Figure 27 A process S700 of forming a common layer and an encapsulation layer can be performed. First, a common layer CML can be formed. For example, an electron transport layer ETL can be formed on the first to third emission structures EMS1 to EMS3 and a pixel definition layer PDL. An electron injection layer EIL can be formed on the electron transport layer ETL. Thereafter, a cathode CE can be formed on the electron injection layer EIL. In one or more embodiments, an auxiliary electrode AXE (refer to Figure 8 ) can be formed on the cathode CE. Thereafter, an encapsulation layer TFE can be formed on the common layer CML.

[0155] As illustrated in Figure 27 , because edges of each of the first to third emission structures EMS1 to EMS3 are patterned in a gently curved shape, the common layer CML (e.g., the cathode CE) can be continuously formed on the first to third emission structures EMS1 to EMS3 without being broken, and an additional structure such as a spacer is not needed.

[0156] Figure 28is a block diagram illustrating a display system 1000 according to one or more embodiments.

[0157] Referring to Figure 28 , the display system 1000 can include a processor 1100 and a display device 1200.

[0158] The processor 1100 can perform various tasks and operations. In an embodiment, the processor 1100 can include an application processor, a graphic processor, a microprocessor, and a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system to control the components.

[0159] The processor 1100 can transmit input image data IMG and a control signal CTRL to the display device 1200. The display device 1200 can display an image based on the input image data IMG and the control signal CTRL. The display device 1200 can be configured in the same manner as the display device DD described with reference to Figure 1 . In this case, the input image data IMG and the control signal CTRL can be provided as the input image data IMG and the control signal CTRL of Figure 1 , respectively.

[0160] The display system 1000 can include a computing system providing an image display function such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer (tablet PC), a watch phone, a car display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra-mobile personal computer (UMPC), a television (TV), and / or a monitor. Further, the display system 1000 can include at least one of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0161] Figures 29 to 32 is a perspective view illustrating an application example of the display system 1000 of Figure 28 .

[0162] Referring to Figure 29 , Figure 28 , the display system 1000 of

[0163] The smart watch 2000 can be a wearable electronic device. For example, the smart watch 2000 can have a structure in which the watch band 2200 can be mounted on a wrist of a user. Here, the display system 1000 (with reference to Figure 28 ) and / or the display device 1200 (with reference to Figure 28) can be applied to the display part 2100, so that image data including time information can be provided to the user.

[0164] refer to Figure 30 , Figure 28 The display system 1000 may be applied to a car display system 3000. Here, the car display system 3000 may include a computing system provided inside and / or outside a vehicle to provide image data.

[0165] For example, the display system 1000 (refer to Figure 28 ) and / or display device 1200 (reference Figure 28 ) can be applied to at least one of an infotainment panel 3100, an instrument panel 3200, a co-pilot display 3300, a head-up display 3400, a rearview mirror display 3500, and a rear seat display 3600 that may be provided in a vehicle.

[0166] refer to Figure 31 , Figure 28 The display system 1000 can be applied to smart glasses 4000. Smart glasses 4000 can be wearable electronic devices that can be worn on the user's head. For example, smart glasses 4000 can be wearable devices for augmented reality.

[0167] Smart glasses 4000 may include a frame 4100 and a lens assembly 4200. The frame 4100 may include a housing 4110 that supports the lens assembly 4200 and leg members 4120 that enable a user to wear the smart glasses 4000. The leg members 4120 may be connected to the housing 4110 by a hinge and thus may be folded or unfolded relative to the housing 4110.

[0168] The frame 4100 may be equipped with a battery, a touch panel, a microphone, a camera, etc. In addition, the frame 4100 may be equipped with a projector configured to output light and a processor configured to control a light signal, etc.

[0169] The lens component 4200 may include an optical component configured to transmit light or reflect light. For example, the lens component 4200 may include glass, a transparent synthetic resin, or the like.

[0170] In order to enable the user's eyes to perceive visual information, the lens component 4200 can reflect an image based on the light signal transmitted from the projector of the frame 4100 through the rear surface of the lens component 4200 (e.g., the surface facing the user's eyes). For example, the user can perceive visual information such as time and date displayed on the lens component 4200. Here, the projector and / or the lens component 4200 can be a type of display device. The display device 1200 (refer to Figure 28 ) can be applied to the projector and / or lens component 4200.

[0171] refer to Figure 32 , Figure 28 The display system 1000 can be applied to a head-mounted display device 5000.

[0172] The head-mounted display device 5000 may be a wearable electronic device that can be worn on the user's head. For example, the head-mounted display device 5000 may be a wearable device for virtual reality or mixed reality.

[0173] The head-mounted display device 5000 may include a headband 5100 and a display device receiving housing 5200. The headband 5100 may be connected to the display device receiving housing 5200. The headband 5100 may include horizontal and / or vertical straps to secure the head-mounted display device 5000 to the user's head. The horizontal straps may wrap around the sides of the user's head, and the vertical straps may wrap around the top of the user's head. However, embodiments are not limited to the above examples. For example, the headband 5100 may be implemented in the form of eyeglass frames, helmets, and the like.

[0174] The display device receiving housing 5200 can receive the display system 1000 (refer to Figure 28 ) and / or display device 1200 (reference Figure 28 ).

[0175] The embodiments described in detail above are provided to explain the present disclosure, but it should be noted that the embodiments are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that various changes, substitutions and modifications can be made herein without departing from the scope of the present disclosure defined by the claims.

[0176] According to some embodiments, a display device can be easily manufactured through an indirect patterning process. For example, since the edge of the emission structure is formed in a gently curved shape, the possibility of cathode disconnection can be reduced or easily prevented without introducing a separate structure for step removal.

[0177] However, the aspects and features of the present disclosure are not limited to the above-described aspects and features, and a person of ordinary skill in the art will understand various other aspects and features within the spirit and scope of the present disclosure.

[0178] The embodiments described in detail above are provided to explain the present disclosure, but these embodiments are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that various changes, substitutions and modifications can be made in the present disclosure without departing from the scope of the present disclosure defined by the claims and their equivalents.

[0179] The scope of embodiments according to the present disclosure is not to be limited by the detailed description set forth in the specification, but is instead defined by the claims and their equivalents. Furthermore, all changes or modifications that come within the meaning and range of equivalents of the claims and their equivalents are to be embraced by the scope of embodiments according to the present disclosure. Embodiments can be combined to form additional embodiments.

Claims

1. A display device comprising: a substrate; a pixel circuit layer over the substrate; a first anode, a second anode, and a third anode spaced apart over the pixel circuit layer; a pixel-defining layer over the pixel circuit layer and overlapping a portion of the first anode, a portion of the second anode, and a portion of the third anode; a first emission structure, a second emission structure, and a third emission structure over the first anode, the second anode, and the third anode, respectively, and each comprising a curved edge; and a common layer over the first emission structure, the second emission structure, the third emission structure, and the pixel-defining layer. The edges of the first emission structure, the second emission structure, and the third emission structure have a slope over the pixel-defining layer.

2. The display device according to claim 1, wherein The first emission structure, the second emission structure, and the third emission structure have an inverted conical shape.

3. The display device according to claim 1, wherein The width of the first emission structure, the second emission structure, and the third emission structure increases in a thickness direction.

4. The display device according to claim 3, wherein Each of the first emission structure, the second emission structure, and the third emission structure comprises:

5. The display device according to any one of claims 1 to 4, wherein a hole injection layer; a hole transport layer over the hole injection layer; an emission layer over the hole transport layer; and a buffer layer over the emission layer. The common layer comprises:

6. The display device of claim 5, wherein, an electron transport layer over the first emission structure, the second emission structure, the third emission structure, and the pixel-defining layer; an electron injection layer over the electron transport layer; and a cathode over the electron injection layer. The common layer further comprises:

7. The display device of claim 6, wherein, an auxiliary electrode over the cathode. The cathode and the auxiliary electrode comprise different materials.

8. The display device of claim 7, wherein, The cathode comprises a semi-transparent conductive material, and 9. The display device of claim 8, wherein, wherein the auxiliary electrode comprises a transparent conductive material. Each of the first emission structure, the second emission structure, and the third emission structure comprises:

10. The display device according to any one of claims 1 to 4, wherein, a hole injection layer; a hole transport layer over the hole injection layer; an emission layer over the hole transport layer; a buffer layer over the emission layer; an electron transport layer over the buffer layer; and an electron injection layer over the electron transport layer. The common layer comprises:

11. The display device of claim 10, wherein, a cathode over the first emission structure, the second emission structure, the third emission structure, and the pixel-defining layer.

12. The display device of claim 1, further comprising: an encapsulation layer over the common layer.

13. A method of manufacturing a display device, the method comprising: forming a first anode, a second anode, a third anode, and a pixel-defining layer over a pixel circuit layer over a substrate; forming a cover layer over a portion of the pixel-defining layer; forming a first emission structure over the first anode, the second anode, the third anode, the pixel-defining layer, and the cover layer; forming a first sacrificial layer over the first emission structure; forming a first photoresist over a portion of the first sacrificial layer; removing the first emission structure and the first sacrificial layer over the second anode, the third anode, and the cover layer; and ​ ​ removing the first photoresist.

14. The method of claim 13, wherein, The cap layer includes: a first layer having a first thickness; and a second layer over the first layer and having a second thickness less than the first thickness.

15. The method of claim 14, wherein, The second layer has a width greater than a width of the first layer.

16. The method of claim 15, wherein, The second layer overlaps edges of the first anode, the second anode, and the third anode.

17. The method of any of claims 13-16, further comprising: forming a second emissive structure over the first sacrificial layer, the second anode, the third anode, the pixel-defining layer, and the cap layer; forming a second sacrificial layer over the second emissive structure; forming a second photoresist over a portion of the second sacrificial layer; removing the second emissive structure and the second sacrificial layer over the first sacrificial layer, the third anode, and the cap layer; and removing the second photoresist.

18. The method of claim 17, further comprising: forming a third emissive structure over the first sacrificial layer, the second sacrificial layer, the third anode, the pixel-defining layer, and the cap layer; forming a third sacrificial layer over the third emissive structure; forming a third photoresist over a portion of the third sacrificial layer; removing the third emissive structure and the third sacrificial layer over the first sacrificial layer, the second sacrificial layer, and the cap layer; and removing the third photoresist.

19. The method of claim 18, further comprising: removing the first sacrificial layer through the third sacrificial layer and the cap layer.

20. The method of claim 19, further comprising: forming a common layer over the first emissive structure, the second emissive structure, the third emissive structure, and the pixel-defining layer; and forming an encapsulation layer over the common layer.

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