Display device

Abstract

Disclosed is a display device including: a display panel; a first conductive pattern over the display panel; a second conductive pattern over the first conductive pattern; an insulating layer over the second conductive pattern; and a cover layer over the insulating layer, where an edge of the insulating layer and an edge of the cover layer are aligned and spaced apart from an edge of the display panel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0053528, filed on April 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device and a mother panel. Background Art

[0004] Generally speaking, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying images. The display device generates images and provides the generated images to the user via a display screen. The display device includes a display panel that displays the images and an input sensor located on the display panel to sense external inputs.

[0005] Display devices can be susceptible to external impact. When a display device is dropped, the impact can be applied to the side surfaces of the display device, potentially damaging them. For example, the side surfaces of some components of the input sensing unit may become delaminated. Technological development is needed to reduce or prevent damage to the side surfaces of display devices. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device and a mother panel for reducing or preventing damage to a side surface of the display device.

[0007] According to one or more embodiments, a display device includes: a display panel; a first conductive pattern above the display panel; a second conductive pattern above the first conductive pattern; an insulating layer above the second conductive pattern; and a covering layer above the insulating layer, wherein an edge of the insulating layer and an edge of the covering layer are aligned and spaced apart from an edge of the display panel.

[0008] The display device may further include: an adhesive layer over the cover layer and the display panel to cover the edge of the insulating layer and the edge of the cover layer; and a reflection reducing layer over the adhesive layer.

[0009] The display panel may include: a substrate; and pixels over the substrate, and wherein the adhesion layer is in direct contact with a portion of an upper surface of the substrate adjacent to an edge of the substrate.

[0010] An upper side, a left side, and a right side of the display panel and an upper side, a left side, and a right side of the insulating layer may define a stepped portion.

[0011] The display device can further include a dummy insulating layer over the display panel and between the insulating layer and a lower side of the display panel in a plan view, wherein a trench is defined between the dummy insulating layer and the insulating layer.

[0012] The dummy insulating layer and the insulating layer can include a same material.

[0013] The stepped portion and the trench can have a closed ring shape and can surround a display area of the display panel in a plan view.

[0014] The display device can further include a first dam layer over the display panel and between the edge of the display panel and the insulating layer in a plan view, wherein a first trench is defined between the first dam layer and the insulating layer.

[0015] The display device can further include a first dam layer over the display panel and between the edge of the display panel and the insulating layer in a plan view, and a second dam layer over the display panel and between the edge of the display panel and the first dam layer in a plan view, wherein a first trench is defined between the first dam layer and the insulating layer, and wherein a second trench is defined between the second dam layer and the first dam layer.

[0016] The insulating layer, the first dam layer, and the second dam layer can include a same material.

[0017] The first dam layer and the second dam layer can surround a display area of the display panel in a plan view.

[0018] The display device can further include a dummy dam layer over the display panel and spaced apart from the insulating layer, wherein an edge of the dummy dam layer is aligned with the edge of the display panel, and wherein a dummy trench is defined between the dummy dam layer and the insulating layer.

[0019] The display device can further include a dummy dam layer over the display panel and spaced apart from the insulating layer, and a first dummy dam layer over the display panel and between the dummy dam layer and the insulating layer, wherein a first dummy trench is defined between the first dummy dam layer and the insulating layer, and wherein a second dummy trench is defined between the dummy dam layer and the first dummy dam layer.

[0020] The display device can further include a dummy dam layer between a lower side of the display panel and the insulating layer in a plan view.

[0021] The dummy dam layer can be arranged in a zigzag form in a direction substantially parallel to the lower side of the display panel.

[0022] The dummy dam layer can be arranged in a zigzag form in a direction substantially parallel to the lower side of the display panel.

[0023] According to one or more embodiments, a display device includes a display panel including a substrate and pixels over the substrate; a first conductive pattern over the display panel; a second conductive pattern over the first conductive pattern; an insulating layer over the second conductive pattern; and a cover layer over the insulating layer, wherein an edge of the insulating layer is spaced apart from an edge of the substrate, and wherein the cover layer covers the edge of the insulating layer and is in direct contact with a portion of an upper surface of the substrate adjacent to the edge of the substrate.

[0024] The display device can further include a first dam layer over the display panel and between the edge of the display panel and the insulating layer in a plan view; and a second dam layer over the display panel and between the edge of the display panel and the first dam layer in a plan view, wherein a first slot is defined between the first dam layer and the insulating layer, wherein a second slot is defined between the second dam layer and the first dam layer, and wherein the cover layer is over the first dam layer and the second dam layer and fills the first slot and the second slot.

[0025] The display device can further include a dummy dam layer over the display panel and spaced apart from the insulating layer; and a first dummy dam layer over the display panel and between the dummy dam layer and the insulating layer, wherein a first dummy slot is defined between the first dummy dam layer and the insulating layer, wherein a second dummy slot is defined between the dummy dam layer and the first dummy dam layer, and wherein the cover layer is over the first dummy dam layer and the second dummy dam layer and fills the first dummy slot and the second dummy slot.

[0026] According to one or more embodiments, a mother panel includes a unit panel; a first conductive pattern over the unit panel; a second conductive pattern over the first conductive pattern; an insulating layer over the second conductive pattern; a cover layer over the insulating layer; an adhesive layer over the cover layer; and a reflection reduction layer over the adhesive layer, wherein an edge of the unit panel is defined by a cutting line, wherein a slot overlapping a portion of the cutting line is defined in the insulating layer, and wherein the adhesive layer fills the slot. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other aspects of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] FIG. 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0029] FIG. 2 As an example FIG. 1 FIG. 4 is a diagram showing a cross section of a display device illustrated in FIG.

[0030] FIG. 3 As an example FIG. 2 FIG. 4 is a diagram showing a cross section of a display panel illustrated in FIG.

[0031] FIG. 4 for FIG. 2 A plan view of the display panel illustrated in FIG.

[0032] FIG. 5 As an example and FIG. 4 FIG. 4 is a diagram showing a cross section of a display panel and an input sensing portion corresponding to a pixel illustrated in FIG.

[0033] FIG. 6 for FIG. 2 A plan view of the input sensing portion illustrated in FIG.

[0034] FIG. 7 for FIG. 6 An enlarged view of two adjacent first sensing portions and two adjacent second sensing portions illustrated in FIG.

[0035] FIG. 8 For the FIG. 7 sectional view taken along line AA' shown in FIG.

[0036] FIG. 9 For the FIG. 4 A cross-sectional view taken along line II' shown in FIG.

[0037] FIG. 10 For the FIG. 4 A cross-sectional view taken along line II-II' illustrated in FIG.

[0038] FIG. 11 For a brief example FIG. 9 Figure 2 shows the configuration illustrated in FIG.

[0039] FIG. 12 A diagram illustrating a cross-sectional configuration of a comparative display device.

[0040] FIG. 13 is a diagram illustrating a configuration of a display device according to one or more other embodiments of the present disclosure.

[0041] FIG. 14 For a brief example FIG. 13Figure 2 shows the configuration illustrated in FIG.

[0042] FIG. 15 As an example for FIG. 11 and FIG. 14 The display device exemplified in FIG. 12 Graphs illustrating external impact tests of comparative display devices are shown in FIG.

[0043] FIG. 16 is a diagram illustrating a planar configuration of a mother panel according to one or more embodiments of the present disclosure.

[0044] FIG. 17 for FIG. 16 An enlarged view of a unit panel is shown in FIG.

[0045] FIG. 18A For the FIG. 17 sectional view taken along line III-III' illustrated in FIG.

[0046] FIG. 18B As an example, FIG. 18A FIG. 4 is a diagram of a unit panel cut by a cutting line and separated from a mother panel.

[0047] FIG. 19 is a diagram illustrating a configuration of a unit panel according to one or more other embodiments of the present disclosure.

[0048] FIG. 20A For the FIG. 19 A cross-sectional view taken along line IV-IV' illustrated in FIG.

[0049] FIG. 20B As an example, FIG. 20A FIG. 4 is a diagram of a unit panel cut by a cutting line and separated from a mother panel.

[0050] FIG. 21 is a diagram illustrating a configuration of a unit panel according to one or more other embodiments of the present disclosure.

[0051] FIG. 22A For the FIG. 21 A cross-sectional view taken along line VV' illustrated in FIG.

[0052] FIG. 22B As an example, FIG. 22A FIG. 4 is a diagram of a unit panel cut by a cutting line and separated from a mother panel.

[0053] FIG. 23 is a diagram illustrating a configuration of a unit panel according to one or more other embodiments of the present disclosure.

[0054] FIG. 24A For the FIG. 23 A cross-sectional view taken along line VI-VI' illustrated in FIG.

[0055] FIG. 24B FIG. 1 is a diagram illustrating a configuration of a unit panel according to one embodiment of the present disclosure. FIG. 24A FIG. 2 is a diagram illustrating a unit panel cut by a cutting line illustrated in FIG. 1 and separated from a mother panel.

[0056] FIG. 25 FIG. 3 is a diagram illustrating a configuration of a unit panel according to one or more other embodiments of the present disclosure.

[0057] FIG. 26A FIG. 4 is a cross-sectional view taken along line VII-VII’ illustrated in FIG. 3. FIG. 25

[0058] FIG. 5 is a diagram illustrating a unit panel cut by a cutting line illustrated in FIG. 3 and separated from a mother panel. FIG. 26B FIG. 26A FIG. 6 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 3.

[0059] FIG. 27A FIG. 27B FIG. 7 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 4. FIG. 18A FIG. 18B FIG. 8 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 5.

[0060] FIG. 28A FIG. 28B FIG. 9 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 6. FIG. 20A FIG. 20B FIG. 10 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 7.

[0061] FIG. 29A FIG. 29B FIG. 11 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 8. FIG. 22A FIG. 22B FIG. 12 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 9.

[0062] FIG. 30A FIG. 30B FIG. 13 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 10. FIG. 24A FIG. 24B FIG. 14 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 11.

[0063] FIG. 31A FIG. 31B FIG. 15 is a diagram illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 12. FIG. 26A FIG. 26B FIG. 16 is a diagram illustrating a configuration on a unit panel according to other embodiments of the present disclosure.

[0064] FIG. 32 FIG. 33 FIG. 17 is a diagram illustrating a configuration on a unit panel according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0065] ​​​​​​​​​​​​Aspects of some embodiments of the present disclosure and methods of implementing them can be more readily understood by reference to the following detailed description, taken with the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the scope of the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are conventional in the art and that are not necessary for an understanding of the aspects of the present disclosure can be omitted or not described in order to avoid obscuring the focus of the present disclosure. Throughout the drawings and written description, like reference numerals, characters or combinations thereof refer to like elements, and thus repeated description of which can be omitted.

[0066] The described embodiments can have various modifications and can be implemented in different forms, and should not be interpreted as being limited to only the embodiments illustrated herein. The use of "can," "may," or "might" in describing the embodiments of the present disclosure corresponds to one or more embodiments of the present disclosure.

[0067] Those of ordinary skill in the art will appreciate, in light of the overall content of the present disclosure, that each suitable feature of various embodiments of the present disclosure can be combined in part or in whole with each other, and can be technically interrelated and operated in various suitable ways, and each embodiment can be implemented independently of or in combination with any other embodiment, unless otherwise specified or implied.

[0068] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, since the sizes (e.g., thicknesses) of elements in the drawings are arbitrarily illustrated for ease of description, the present disclosure is not limited thereto. In addition, cross-hatching and / or shading in the drawings has been generally provided to illustrate boundaries of adjacent elements. As such, the presence or absence of cross-hatching or shading does not indicate or imply any preference or requirement for particular material, material properties, dimensions, ratios, commonality of elements between illustrations, and / or any other characteristic, attribute, property, etc. of the elements illustrated.

[0069] Various embodiments are described herein with reference to cross-sectional illustrations of schematic diagrams of embodiments and / or intermediate structures. As such, variations to the shapes of the illustrations as a result of, e.g., manufacturing techniques and / or tolerances, are to be expected. Further, the specific structural or functional details disclosed herein are not to be interpreted as limiting but are merely intended to illustrate the embodiments in accordance with the present disclosure. Thus, embodiments disclosed herein are not to be interpreted as being limited to the illustrated shapes of the elements, but rather, are to include deviations in shapes that would result from, e.g., manufacturing.

[0070] For example, an implant region illustrated as rectangular will generally have rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary change from the implant region to a non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurs.

[0071] For purposes of this description, spatially relative terms such as "beneath", "below", "lower", "bottom", "under", "above", "upper", "higher", "top", "side" (as in "sidewall") and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "beneath" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first component is described as being "on" a second component, it can be either directly on the second component or otherwise on the second component with one or more intervening components present therebetween. The relative description allows for the possibility of additional structure intervening between two components. For example, describing a first component as "on" a second component encompasses both an arrangement where the first component is directly on the second component and an arrangement where one or more intervening components are present between the first component and the second component.

[0072] Further, the phrase "in plan view" means when looking at the object portion from above, and the phrase "in schematic cross-sectional view" means when looking at a schematic cross-section taken through a vertical cut of the object portion from the side. The term "overlapping" or "overlap" means that a first object can be above or below or to the side of a second object, or vice versa. Additionally, the term "overlapping" can include stacking, facing, extending past, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The expression "not overlapping" can include the meaning of "separated" or "set aside" or "offset", as well as any other suitable equivalent meaning as would be appreciated and understood by one of ordinary skill in the art. The term "facing" can mean that a first object can be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although still facing each other.

[0073] It will be understood that when an element, layer, region or component is referred to as being "formed on", "connected to" or "coupled with" (operatively or communicatively) another element, layer, region or component, it can be directly or indirectly formed on, connected to or coupled with the other element, layer, region or component, such that one or more intervening elements, layers, regions or components can exist. In addition, it can collectively mean direct or indirect coupling or connection and whole or partial coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or coupled to the other layer, region and / or component, or one or more intervening layers, regions or components can exist. The one or more intervening components can include switches, resistors, capacitors, etc. In describing embodiments, unless explicitly described as directly connected, expressions of connection represent electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected or coupled to another component, or on another component, without intervening components.

[0074] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" the other part, but also includes the case where there is yet another part between the part and the other part. Meanwhile, other expressions describing the relationship between components, such as "between", "directly between", or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also exist.

[0075] For purposes of this disclosure, expressions such as “at least one of,” “one or more of,” or “at least one of each of” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z,” “one or more of X, Y, or Z,” “at least one of each of X, Y and Z,” and “at least one of each of X, Y or Z” can be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z, such as, for example, X, Y, Z, XY, XZ, YZ, and XYZ, or any variation thereof. Similarly, expressions such as “at least one of A and B” and “at least one of A or B” can include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other similar phrases, when following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Unless specifically stated, when a statement “C to D” is made, it means C up to and D below.

[0076] It will be understood that, although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Thus, elements, components, regions, layers or sections described below as first elements, members, components, regions, areas, layers or sections can be called second elements, members, components, regions, areas, layers or sections, without departing from the spirit and scope of the present disclosure. Describing a component as a “first” component can not require or imply the presence of a second component or other components. The terms “first,” “second,” etc. can also be used herein to distinguish different categories or different groups of elements. For brevity, the terms “first,” “second,” etc. can represent “first category (or first group),” “second category (or second group),” etc., respectively.

[0077] In examples, the axis corresponding to the first direction DR1, the axis corresponding to the second direction DR2, and / or the axis corresponding to the third direction DR3 are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the axis corresponding to the first direction DR1, the axis corresponding to the second direction DR2, and the axis corresponding to the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0078] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0079] As used herein, the terms "substantially", "about", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of a recited value. As used herein, "about" or "approximately" includes the recited value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art to account for the errors in measurement and the limitations of measuring a particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within + / - 30%, 20%, 10%, or 5% of a recited value. Further, "may" as used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure".

[0080] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0081] FIG. 1 A perspective view of a display device according to one or more embodiments of the present disclosure.

[0082] Referring to FIG. 1 A display device DD according to one or more embodiments of the present disclosure can have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 crossing the first direction DR1 in a plan view. However, the display device DD is not limited thereto and can have various shapes such as a circular shape or other polygonal shapes in a plan view.

[0083] Hereinafter, a direction that substantially perpendicularly intersects with a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. Also, in the specification, the meaning of "when viewed on a plane" is defined as a state of viewing along the third direction DR3.

[0084] An upper surface of the display device DD can be defined as a display surface DS, and can have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated on the display device DD can be provided to a user through the display surface DS. The display device DD can sense a touch by the user through the user's hand US_F.

[0085] The display surface DS can include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA can display an image, and the non-display area NDA can not display an image. The non-display area NDA can surround the display area DA (for example, in a plan view), and can define an edge of the display device DD printed in a corresponding color.

[0086] FIG. 2 To illustrate FIG. 1 A cross-section of a display device illustrated in FIG. 2 A cross-section of the display device DD viewed along the first direction DR1 is illustrated.

[0087] Referring to FIG. 2 The display device DD can include a display panel DP, an input sensing part ISP, a reflection reduction layer (for example, an anti-reflection layer) RPL, a window WIN, a panel protection film PPF, and first, second, and third adhesive layers AL1, AL2, and AL3.

[0088] The display panel DP according to one or more embodiments of the disclosure can be a light-emitting display panel. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. A light-emitting layer of the organic light-emitting display panel can include an organic light-emitting material. A light-emitting layer of the inorganic light-emitting display panel can include quantum dots and / or quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0089] The input sensing part ISP can be located on the display panel DP. In one or more embodiments, the input sensing part ISP can include a plurality of sensing parts for capacitively sensing an external input. When the display device DD is manufactured, the input sensing part ISP can be directly manufactured on the display panel DP. However, the disclosure is not limited thereto, and the input sensing part ISP can be manufactured as a separate panel from the display panel DP, and can be attached to the display panel DP through an adhesive layer.

[0090] The reflection reduction layer RPL can be located on the input sensing part ISP. The reflection reduction layer RPL can be defined as a film that reduces or prevents reflection of external light. The reflection reduction layer RPL can reduce reflectance of external light input from the upper side of the display device DD toward the display panel DP. Due to the reflection reduction layer RPL, the external light can be invisible to the user.

[0091] When external light traveling toward the display panel DP can be reflected by the display panel DP and can be provided back to the external user, the user can perceive the external light like a mirror. In order to reduce or prevent the possibility of such a phenomenon, illustratively, the reflection reduction layer RPL can include a plurality of color filters that display the same color as the color of the pixels of the display panel DP.

[0092] The color filter can filter the external light into the same color as the color of the pixel. In this case, the external light can be invisible to the user. However, the present disclosure is not limited thereto, and the reflection reduction layer RPL can include a phase retarder and / or a polarizer to reduce the reflectance of the external light.

[0093] The window WIN can be located on the reflection reduction layer RPL. The window WIN can protect the display panel DP, the input sensing part ISP, and the reflection reduction layer RPL from external scratches and impacts.

[0094] The panel protection film PPF can be located under the display panel DP. The panel protection film PPF can protect the lower side of the display panel DP. The panel protection film PPF can include a flexible plastic material such as polyethylene terephthalate (PET).

[0095] The first adhesive layer AL1 can be located between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF can be bonded to each other by the first adhesive layer AL1.

[0096] The second adhesive layer AL2 can be located between the input sensing part ISP and the reflection reduction layer RPL, and the input sensing part ISP and the reflection reduction layer RPL can be bonded to each other by the second adhesive layer AL2.

[0097] The third adhesive layer AL3 can be located between the window WIN and the reflection reduction layer RPL, and the window WIN and the reflection reduction layer RPL can be bonded to each other by the third adhesive layer AL3.

[0098] FIG. 3 To illustrate FIG. 2 A diagram of a cross-section of a display panel.

[0099] FIG. 3 A cross-section of the display panel DP seen in a first direction DR1 is illustrated.

[0100] Reference FIG. 3The display panel DP includes a substrate SUB, a circuit element layer DP-CL located on the substrate SUB, a display element layer DP-OLED located on the circuit element layer DP-CL, and a thin film encapsulation layer TFE located on the display element layer DP-OLED.

[0101] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include a flexible plastic material such as glass or polyimide (PI). The display element layer DP-OLED may be located on the display area DA.

[0102] A plurality of pixels may be located on the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor located on the circuit element layer DP-CL and a light emitting element located on the display element layer DP-OLED and connected to the transistor.

[0103] The thin film encapsulation layer TFE may be located on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign substances.

[0104] FIG. 4 for FIG. 2 A plan view of the display panel illustrated in FIG.

[0105] refer to FIG. 4 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light emitting driver EDV, and a plurality of first pads PD1.

[0106] The display panel DP may have a rectangular shape in a plan view having long sides extending along a first direction DR1 and short sides extending along a second direction DR2, but the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA (e.g., in a plan view).

[0107] The display panel DP includes a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a power line PL, and a plurality of connection lines CNL, where m and n are natural numbers greater than 1.

[0108] The pixels PX may be located in the display area DA. The scan driver SDV and the light emitting driver EDV may be located in portions of the non-display area NDA adjacent to the long sides of the display panel DP. The data driver DDV may be located in a portion of the non-display area NDA adjacent to one of the short sides of the display panel DP. When viewed in a planar manner, the data driver DDV may be adjacent to the lower end of the display panel DP.

[0109] The scan lines SL1 to SLm can extend in the second direction DR2 and can be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn can extend in the first direction DR1 and can be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm can extend in the second direction DR2 and can be connected to the pixels PX and the emission driver EDV.

[0110] The power line PL can extend in the first direction DR1 and can be positioned in the non-display area NDA. The power line PL can be positioned between the display area DA and the emission driver EDV, but is not limited thereto, and can be positioned between the display area DA and the scan driver SDV.

[0111] The connection line CNL can extend in the second direction DR2 and can be arranged in the first direction DR1 to be connected to the power line PL and the pixels PX. A driving voltage can be applied to the pixels PX through the power line PL and the connection line CNL connected to each other.

[0112] The first control line CSL1 can be connected to the scan driver SDV and can extend toward the lower end of the display panel DP. The second control line CSL2 can be connected to the emission driver EDV and can extend toward the lower end of the display panel DP. The data driver DDV can be positioned between the first control line CSL1 and the second control line CSL2.

[0113] The first pad PD1 can be positioned in a portion of the non-display area NDA adjacent to the lower end of the display panel DP and can be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the power line PL, the first control line CSL1, and the second control line CSL2 can be connected to the first pad PD1. The data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the first pad PD1 corresponding to the data lines DL1 to DLn.

[0114] In one or more embodiments, the display apparatus DD can further include a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the emission driver EDV. The timing controller can be mounted on a printed circuit board and can be connected to the first pad PD1 through the printed circuit board.

[0115] The scan driver SDV generates a plurality of scan signals, and the scan signals can be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV generates a plurality of data voltages, and the data voltages can be applied to the pixels PX through the data lines DL1 to DLn. The emission driver EDV can generate a plurality of emission signals, and the emission signals can be applied to the pixels PX through the emission lines EL1 to ELm.

[0116] The pixel PX can receive a data voltage in response to a scan signal. The pixel PX can display an image by emitting light having a luminance corresponding to the data voltage in response to a light emission signal.

[0117] The display device DD can include an insulating layer T-INS2 located on the display panel DP and a dummy insulating layer D-INS located on the display panel DP. Illustratively, in FIG. 4 In the embodiment, the insulating layer T-INS2 and the dummy insulating layer D-INS are illustrated in gray.

[0118] The edge of the display panel DP can include a first side S1, a second side S2, a third side S3, and a fourth side S4 when viewed in a plan view. The first side S1 and the second side S2 can define short sides of a rectangular shape of the display panel DP and can extend along the second direction DR2. The third side S3 and the fourth side S4 define long sides of the rectangular shape of the display panel DP and can extend along the first direction DR1.

[0119] The first side S1 can be defined as an upper side of the display panel DP, and the second side S2 can be defined as a lower side of the display panel DP. The third side S3 can be defined as a left side of the display panel DP, and the fourth side S4 can be defined as a right side of the display panel DP.

[0120] The insulating layer T-INS2 can have a rectangular shape having long sides extending along the first direction DR1 and short sides extending along the second direction DR2 when viewed in a plan view. The insulating layer T-INS2 can have an area greater than an area of the display area DA. The insulating layer T-INS2 can be located inside the edge of the display panel DP. Accordingly, an edge of the insulating layer T-INS2 can be spaced apart from the edge of the display panel DP and can be located inside the edge of the display panel DP.

[0121] The edge of the insulating layer T-INS2 can include a first side S1’, a second side S2’, a third side S3’, and a fourth side S4’. The first side S1’ and the second side S2’ can define short sides of a rectangular shape of the insulating layer T-INS2 and can extend along the second direction DR2. The third side S3’ and the fourth side S4’ define long sides of the rectangular shape of the insulating layer T-INS2 and can extend along the first direction DR1.

[0122] The first side S1’ can be defined as an upper side of the insulating layer T-INS2, and the second side S2’ can be defined as a lower side of the insulating layer T-INS2. The third side S3’ can be defined as a left side of the insulating layer T-INS2, and the fourth side S4’ can be defined as a right side of the insulating layer T-INS2.

[0123] The first side S1, the second side S2, the third side S3, and the fourth side S4 can be spaced apart from the first side S1', the second side S2', the third side S3', and the fourth side S4', respectively. A distance between the second side S2 and the second side S2' can be greater than a distance between the first side S1 and the first side S1', greater than a distance between the third side S3 and the third side S3', and greater than a distance between the fourth side S4 and the fourth side S4'.

[0124] The first side S1, the third side S3, and the fourth side S4 of the display panel DP and the first side S1', the third side S3', and the fourth side S4' of the insulating layer T-INS2 can be defined by a stepped portion STP when viewed in a plan. A cross-sectional shape of the stepped portion STP will be exemplified in FIG. 9 and FIG. 11

[0125] The dummy insulating layer D-INS can be located between the insulating layer T-INS2 and the second side S2 of the display panel DP when viewed in a plan. The dummy insulating layer D-INS can be spaced apart from the second side S2 and can be located between the data driver DDV and the second side S2' of the insulating layer T-INS2.

[0126] A groove GV can be defined between the dummy insulating layer D-INS and the insulating layer T-INS2. The groove GV can extend in the second direction DR2. A cross-sectional shape of the groove GV will be exemplified in FIG. 10 The stepped portion STP and the groove GV can be continuously defined, can have a rectangular closed ring shape, and can surround the display area DA in a plan view.

[0127] FIG. 5 To exemplify a cross-section of the display panel and the input sensing portion corresponding to the pixel exemplified in FIG. 4

[0128] Referring to FIG. 5 , a pixel PX can be located on a substrate SUB. The pixel PX can include a transistor TR and a light emitting element OLED. The light emitting element OLED includes a first electrode (or anode) AE, a second electrode (or cathode) CE, a hole control layer HCL, an electron control layer ECL, and a light emitting layer EML.

[0129] The transistor TR and the light emitting element OLED can be located on the substrate SUB. Although one transistor TR is exemplified by way of example, basically, the pixel PX can include a plurality of transistors for driving the light emitting element OLED and at least one capacitor.

[0130] The display area DA can include a light emitting area LA corresponding to each of the pixels PX and a non-light emitting area NLA around the light emitting area LA. The light emitting element OLED can be located in the light emitting area LA. ​​

[0131] The buffer layer BFL can be located on the substrate SUB, and the buffer layer BFL can include an inorganic insulating layer. The semiconductor pattern can be located on the buffer layer BFL. The semiconductor pattern can include polysilicon, amorphous silicon, or metal oxide.

[0132] The semiconductor pattern can be doped with an N-type dopant or a P-type dopant. The semiconductor pattern can include a high-doped region and a low-doped region. The high-doped region has a higher conductivity than the low-doped region, and the high-doped region can substantially function as a source electrode and a drain electrode of the transistor TR. The low-doped region can substantially correspond to an active part (or a channel) of the transistor.

[0133] The source part S, the active part A, and the drain part D of the transistor TR can be formed of the semiconductor pattern. The first insulating layer INS1 can be located on the semiconductor pattern. The gate part G of the transistor TR can be located on the first insulating layer INS1. The second insulating layer INS2 can be located on the gate part G. The third insulating layer INS3 can be located on the second insulating layer INS2.

[0134] The connection electrode CNE can include a first connection electrode CNE1 and a second connection electrode CNE2 to connect the transistor TR and the light emitting element OLED. The first connection electrode CNE1 can be located on the third insulating layer INS3, and can be connected to the drain part D through a first contact hole CH1 defined in the first insulating layer INS1 to the third insulating layer INS3.

[0135] The fourth insulating layer INS4 can be located on the first connection electrode CNE1. The fifth insulating layer INS5 can be located on the fourth insulating layer INS4. The second connection electrode CNE2 can be located on the fifth insulating layer INS5. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4 and the fifth insulating layer INS5.

[0136] The sixth insulating layer INS6 can be located on the second connection electrode CNE2. Layers from the buffer layer BFL to the sixth insulating layer INS6 can be defined as a circuit element layer DP-CL. The first insulating layer INS1 to the fourth insulating layer INS4 can include an inorganic insulating layer, and the fifth insulating layer INS5 and the sixth insulating layer INS6 can include an organic insulating layer.

[0137] The first electrode AE can be located on the sixth insulating layer INS6. The first electrode AE can be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the sixth insulating layer INS6. A pixel definition layer PDL in which an opening PX_OP for exposing a corresponding part of the first electrode AE is defined can be located on the first electrode AE and the sixth insulating layer INS6.

[0138] The hole control layer HCL can be located on the first electrode AE and the pixel definition layer PDL. The hole control layer HCL can include a hole transport layer and a hole injection layer.

[0139] The light emitting layer EML can be located on the hole control layer HCL. The light emitting layer EML can be located in a region corresponding to the opening PX_OP. The light emitting layer EML can include an organic and / or inorganic material. The light emitting layer EML can generate any one of red light, green light, and / or blue light.

[0140] The electron control layer ECL can be located on the light emitting layer EML and the hole control layer HCL. The electron control layer ECL can include an electron transport layer and an electron injection layer. The hole control layer HCL and the electron control layer ECL can be collectively located in the light emitting area LA and the non-light emitting area NLA.

[0141] The second electrode CE can be located on the electron control layer ECL. The second electrode CE can be collectively located in the pixel PX. Layers on which the light emitting element OLED is located can be defined as a display element layer DP-OLED.

[0142] The thin film encapsulation layer TFE can be located on the second electrode CE to cover the pixel PX. The thin film encapsulation layer TFE includes a first encapsulation layer EN1 located on the second electrode CE, a second encapsulation layer EN2 located on the first encapsulation layer EN1, and a third encapsulation layer EN3 located on the second encapsulation layer EN2.

[0143] The first encapsulation layer EN1 and the third encapsulation layer EN3 can include an inorganic insulating layer, and can protect the pixel PX from moisture and / or oxygen. The second encapsulation layer EN2 includes an organic insulating layer, and can protect the pixel PX from foreign substances such as dust particles.

[0144] A first voltage can be applied to the first electrode AE through the transistor TR, and a second voltage having a level lower than that of the first voltage can be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML can combine with each other to form an exciton. When the exciton transitions to a ground state, the light emitting element OLED can emit light.

[0145] The input sensing part ISP can be located on the thin film encapsulation layer TFE. The input sensing part ISP can be directly located on an upper surface of the thin film encapsulation layer TFE.

[0146] The base layer BSL can be located on the thin film encapsulation layer TFE. The base layer BSL can include an inorganic insulating layer. At least one inorganic insulating layer can be provided on the thin film encapsulation layer TFE as the base layer BSL.

[0147] The input sensing part ISP can include a first conductive pattern CTL1 on the display panel DP and a second conductive pattern CTL2 on the first conductive pattern CTL1. The first conductive pattern CTL1 can be on the base layer BSL. A first insulating layer T-INS1 can be on the base layer BSL to cover the first conductive pattern CTL1. The first insulating layer T-INS1 can include an inorganic insulating layer or an organic insulating layer.

[0148] The second conductive pattern CTL2 can be on the first insulating layer T-INS1. A second insulating layer T-INS2 can be on the first insulating layer T-INS1 to cover the second conductive pattern CTL2. The second insulating layer T-INS2 can be FIG. 4 the insulating layer T-INS2 described in the above. The second insulating layer T-INS2 can include an organic insulating layer. A cover layer COV can be on the second insulating layer T-INS2. The cover layer COV can include an organic insulating layer.

[0149] The first conductive pattern CTL1 and the second conductive pattern CTL2 can overlap with the non-light emitting area NLA. In one or more embodiments, the first conductive pattern CTL1 and the second conductive pattern CTL2 can be on the non-light emitting area NLA between the light emitting areas LA and can have a mesh shape.

[0150] The first conductive pattern CTL1 and the second conductive pattern CTL2 can form a sensor of the input sensing part ISP described above. For example, the first mesh-shaped conductive pattern CTL1 and the second mesh-shaped conductive pattern CTL2 can be separated from each other in a corresponding area to form a sensor. A portion of the second conductive pattern CTL2 can be connected to the first conductive pattern CTL1. The configuration of the sensor formed by the first conductive pattern CTL1 and the second conductive pattern CTL2 will be described in detail in the below FIG. 6 to FIG. 8

[0151] FIG. 6 For FIG. 2 a plan view of the input sensing part exemplified in the above.

[0152] Referring to FIG. 6 , the input sensing part ISP includes a plurality of sensing electrodes SE1 and SE2, a plurality of lines TX1 to TXh, a plurality of lines RX1 to RXk, a plurality of first pads PD1, a plurality of second pads PD2, and a plurality of third pads PD3. The sensing electrodes SE1 and SE2, the lines TX1 to TXh and RX1 to RXk, and the second pads PD2 and the third pads PD3 can be on the thin film encapsulation layer TFE.

[0153] ​The planar area of the input sensing portion ISP can include an active area AA and an inactive area NAA (e.g., in a plan view) surrounding the active area AA. The active area AA can overlap the display area DA, and the inactive area NAA can overlap the non-display area NDA.

[0154] The sensing electrodes SE1 and SE2 can be located in the active area AA, and the second and third pads PD2 and PD3 can be located in the inactive area NAA. When viewed in plan, the second and third pads PD2 and PD3 can be adjacent to a lower end of the input sensing portion ISP. When viewed in plan, the first pad PD1 can be located between the second and third pads PD2 and PD3.

[0155] The lines TX1 to TXh and RX1 to RXk can be connected to ends of the sensing electrodes SE1 and SE2, and can extend to the inactive area NAA and can be connected to the second and third pads PD2 and PD3. In one or more embodiments, a sensing control unit that controls the input sensing portion ISP can be connected to the second and third pads PD2 and PD3 through a printed circuit board.

[0156] The sensing electrodes SE1 and SE2 include a plurality of first sensing electrodes SE1 extending along a first direction DR1 and arranged along a second direction DR2, and a plurality of second sensing electrodes SE2 extending along the second direction DR2 and arranged along the first direction DR1. The second sensing electrodes SE2 can extend to cross the first sensing electrodes SE1 while being insulated therefrom.

[0157] The lines TX1 to TXh and RX1 to RXk include a plurality of first lines TX1 to TXh connected to the first sensing electrodes SE1 and a plurality of second lines RX1 to RXk connected to the second sensing electrodes SE2, “h” and “k” being natural numbers greater than 1. The first lines TX1 to TXh can extend to the inactive area NAA and can be connected to the second pad PD2. The second lines RX1 to RXk can extend to the inactive area NAA and can be connected to the third pad PD3.

[0158] Illustratively, when viewed in plan, the first lines TX1 to TXh can be located in a portion of the inactive area NAA adjacent to a lower side of the active area AA. When viewed in plan, the second lines RX1 to RXk can be located in a portion of the inactive area NAA adjacent to a right side of the active area AA. The first lines TX1 to TXh can be defined as transmission lines, and the second lines RX1 to RXk can be defined as sensing lines.

[0159] Each of the first sensing electrodes SE1 can include a plurality of first sensing parts SP1 positioned along the first direction DR1 and a plurality of connection patterns CP connecting the first sensing parts SP1. Each of the connection patterns CP is located between two first sensing parts SP1 adjacent to each other along the first direction DR1 to connect the two first sensing parts SP1.

[0160] Each of the second sensing electrodes SE2 can include a plurality of second sensing parts SP2 positioned along the second direction DR2 and a plurality of extension patterns EP extending from the second sensing parts SP2. Each of the extension patterns EP can be located between two second sensing parts SP2 adjacent to each other along the second direction DR2 and can extend from the two second sensing parts SP2.

[0161] The first sensing parts SP1 and the second sensing parts SP2 do not overlap each other but can be spaced apart from each other and can be alternately positioned. An electrostatic capacitance can be formed by the first sensing parts SP1 and the second sensing parts SP2. The extension patterns EP can not overlap the connection patterns CP.

[0162] FIG. 7 For FIG. 6 An enlarged view of two adjacent first sensing parts and two adjacent second sensing parts exemplified in the middle.

[0163] Referring to FIG. 7 The first sensing parts SP1 and the second sensing parts SP2 can have a mesh shape. To have the mesh shape, each of the first sensing parts SP1 and the second sensing parts SP2 can include a plurality of first branch parts BP1 extending in a first diagonal direction DDR1 and a plurality of second branch parts BP2 extending in a second diagonal direction DDR2.

[0164] The first diagonal direction DDR1 can be defined as a direction crossing the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2. The second diagonal direction DDR2 can be defined as a direction crossing the first diagonal direction DDR1 on the plane defined by the first direction DR1 and the second direction DR2. Exemplarily, the first direction DR1 and the second direction DR2 can substantially perpendicularly cross each other, and the first diagonal direction DDR1 and the second diagonal direction DDR2 can substantially perpendicularly cross each other.

[0165] The first branch parts BP1 of each of the first sensing parts SP1 and the second sensing parts SP2 can cross the second branch parts BP2 of each of the first sensing parts SP1 and the second sensing parts SP2 and can be integrally formed with each other. A touch opening TOP of a diamond shape can be defined by the first branch parts BP1 and the second branch parts BP2.

[0166] The light emitting region LA can be located in the touch opening TOP when viewed in plan. The light emitting element OLED can be located in the light emitting region LA. Each of the light emitting regions LA can be FIG. 5 The first and second sensing portions SP1 and SP2 can be located in the non-light emitting region NLA. Because the first and second sensing portions SP1 and SP2 are located in the non-light emitting region NLA, light generated in the light emitting region LA can be normally output without being affected by the first and second sensing portions SP1 and SP2.

[0167] The connection pattern CP can extend to not overlap with the extension pattern EP, thereby connecting the first sensing portion SP1. The connection pattern CP can be connected to the first sensing portion SP1 through a plurality of contact holes TC-CH. The structure of the contact holes TC-CH will be exemplified in the FIG. 8 The connection pattern CP can extend toward the first sensing portion SP1 via a region overlapping with the second sensing portion SP2.

[0168] The extension pattern EP can be located between adjacent first sensing portions SP1 in the first sensing portion SP1 and can extend from the second sensing portion SP2. The second sensing portion SP2 and the extension pattern EP can be integrally formed. The extension pattern EP can have a mesh shape.

[0169] The extension pattern EP, the first sensing portion SP1, and the second sensing portion SP2 can be located on the same layer and can be formed by patterning the same material at the same time or substantially at the same time. The connection pattern CP can be located on a different layer from the extension pattern EP, the first sensing portion SP1, and the second sensing portion SP2.

[0170] The connection pattern CP can include a first connection pattern CP1 and a second connection pattern CP2 having shapes symmetrical to each other in the second direction DR2. The extension pattern EP can be located between the first connection pattern CP1 and the second connection pattern CP2. The first connection pattern CP1 and the second connection pattern CP2 can have a meander shape.

[0171] The first connection pattern CP1 can extend toward the first sensing portion SP1 via one of the two second sensing portions SP2. The second connection pattern CP2 can extend toward the first sensing portion SP1 via the other of the two second sensing portions SP2.

[0172] The contact hole TC-CH can be adjacent to opposite ends of the first connection pattern CP1 and the second connection pattern CP2. The contact hole TC-CH can overlap with the first sensing portion SP1 when viewed in plan. The first connection pattern CP1 and the second connection pattern CP2 can be connected to the first sensing portion SP1 through the contact hole TC-CH.

[0173] In one or more embodiments, the bent portion of the first connection pattern CP1 and the bent portion of the second connection pattern CP2 can overlap with the second sensing portion SP2. A single touch opening TOP can be defined in each of the bent portion of the first connection pattern CP1 and the bent portion of the second connection pattern CP2. In one or more embodiments, each of the first connection pattern CP1 and the second connection pattern CP2 can include two grid lines extending toward the first sensing portion SP1.

[0174] FIG. 8 To illustrate a cross-sectional view taken along the line A-A’ in FIG. 7

[0175] Referring to FIG. 7 and FIG. 8 , the base layer BSL can be located on the thin film encapsulation layer TFE (as used herein, “on” can mean “above”). The connection pattern CP can be located on the base layer BSL. The first insulating layer T-INS1 can be located on the connection pattern CP and the base layer BSL. The first insulating layer T-INS1 can be located on the base layer BSL to cover the connection pattern CP. The connection pattern CP can be defined as the first conductive pattern CTL1 described above.

[0176] The first sensing portion SP1 and the second sensing portion SP2 can be located on the first insulating layer T-INS1. The extension pattern EP formed integrally with the second sensing portion SP2 can also be located on the first insulating layer T-INS1. The connection pattern CP can be connected to the first sensing portion SP1 through a plurality of contact holes TC-CH defined in the first insulating layer T-INS1.

[0177] The extension pattern EP, the first sensing portion SP1, and the second sensing portion SP2 can be located on the first insulating layer T-INS1 and can be located in the same layer. The extension pattern EP, the first sensing portion SP1, and the second sensing portion SP2 can be defined as the second conductive pattern CTL2 described above. The connection pattern CP can be located under the extension pattern EP, the first sensing portion SP1, and the second sensing portion SP2.

[0178] The second insulating layer T-INS2 can be located on the first sensing portion SP1 and the second sensing portion SP2 as well as the first insulating layer T-INS1, and the cover layer COV can be located on the second insulating layer T-INS2.

[0179] FIG. 9 To illustrate a cross-sectional view taken along the line I-I’ in FIG. 4

[0180] Referring to FIG. 9 ​​The buffer layer BFL and the first to fourth insulating layers INS1 to INS4 can extend toward the non-display area NDA. The periphery of the buffer layer BFL and the first to fourth insulating layers INS1 to INS4 can be spaced apart from the edge of the substrate SUB.

[0181] The fifth and sixth insulating layers INS5 and INS6 can extend to a portion of the non-display area NDA adjacent to the display area DA. The buffer layer BFL and the first to fourth insulating layers INS1 to INS4 can extend farther to the non-display area NDA than the fifth and sixth insulating layers INS5 and INS6. The pixel definition layer PDL can not extend to the non-display area NDA.

[0182] The display panel DP can include a first dam DM1, a second dam DM2, and a third dam DM3 spaced apart from the display area DA in sequence. In the non-display area NDA, the first and second dams DM1 and DM2 can be located on the fourth insulating layer INS4. The first dam DM1 can be located between the second dam DM2 and the display area DA. In the non-display area NDA, the first dam DM1 can be located between the second dam DM2 and side surfaces of the fifth and sixth insulating layers INS5 and INS6.

[0183] The second dam DM2 can be higher (e.g., thicker) than the first dam DM1. For example, the first dam DM1 can be formed of three layers stacked on each other, and the second dam DM2 can be formed of four layers stacked on each other.

[0184] In one or more embodiments, the first dam DM1 can include a layer formed of the same material as that of the fifth, sixth insulating layers INS5 and INS6 and the pixel definition layer PDL. In one or more embodiments, the second dam DM2 can include a layer formed of the same material as that of the fifth, sixth insulating layers INS5 and INS6 and the pixel definition layer PDL. Further, the second dam DM2 can further include a layer (e.g., an organic layer) positioned higher than the pixel definition layer PDL.

[0185] The third dam DM3 can be located between the second dam DM2 and the edge of the substrate SUB. The third dam DM3 can be located on the fourth insulating layer INS4. The third dam DM3 can cover the periphery of the buffer layer BFL and the first to fourth insulating layers INS1 to INS4. The third dam DM3 can be formed of the same material as that of the fifth insulating layer INS5.

[0186] The hole control layer HCL, the electron control layer ECL, and the second electrode CE can extend to the non-display area NDA adjacent to the display area DA and can be located on the sixth insulating layer INS6.

[0187] The first encapsulation layer EN1 can extend to the non-display area NDA. In the non-display area NDA, the first encapsulation layer EN1 can be positioned on the fourth insulating layer INS4 to cover the first dam DM1 and the second dam DM2. Also, the first encapsulation layer EN1 can be positioned on the substrate SUB to cover the third dam DM3.

[0188] The second encapsulation layer EN2 can extend to the non-display area NDA. The second encapsulation layer EN2 can be positioned up to the first dam DM1. The first encapsulation layer EN1 can extend farther than the second encapsulation layer EN2 to the non-display area NDA.

[0189] When the display device DD is manufactured, the organic material having fluidity can be cured to form the second encapsulation layer EN2. Even when the fluid organic material flows to the non-display area NDA, it can be blocked at the first dam DM1. In one or more embodiments, the organic material overflowing the first dam DM1 can be further blocked at the second dam DM2.

[0190] The third encapsulation layer EN3 can extend to the non-display area NDA. The third encapsulation layer EN3 can be positioned on the first encapsulation layer EN1 and the second encapsulation layer EN2 in the non-display area NDA.

[0191] The base layer BSL can extend to the non-display area NDA and can be positioned on the third encapsulation layer EN3. The first insulating layer T-INS1 can extend to the non-display area NDA and can be positioned on the base layer BSL.

[0192] The periphery of the first encapsulation layer EN1 and the third encapsulation layer EN3, the base layer BSL, and the first insulating layer T-INS1 can be spaced apart from the edge of the substrate SUB. In the non-display area NDA, the periphery of the first encapsulation layer EN1 and the third encapsulation layer EN3, the base layer BSL, and the first insulating layer T-INS1 can overlap each other.

[0193] The second insulating layer T-INS2 can extend to the non-display area NDA and can be positioned on the first insulating layer T-INS1. In the non-display area NDA, the second insulating layer T-INS2 can be positioned to cover the periphery of the first encapsulation layer EN1 and the third encapsulation layer EN3, the base layer BSL, and the first insulating layer T-INS1. The second insulating layer T-INS2 can be in direct contact with a portion of the upper surface of the substrate SUB adjacent to the side surface of the first encapsulation layer EN1 and the third encapsulation layer EN3, the base layer BSL, and the first insulating layer T-INS1. The edge of the second insulating layer T-INS2 can be spaced apart from the edge of the substrate SUB.

[0194] The cover layer COV can extend to the non-display area NDA and can be located on the second insulating layer T-INS2. An edge of the cover layer COV can be spaced apart from an edge of the substrate SUB. An edge of the cover layer COV can overlap with an edge of the second insulating layer T-INS2. Accordingly, when viewed in plan, the cover layer COV can be positioned to be spaced apart from the second insulating layer T-INS2. FIG. 4 The insulating layer T-INS2 (e.g., the second insulating layer T-INS2) is illustrated as being gray in

[0195] The second adhesive layer AL2 can be located on the cover layer COV. The reflection reduction layer RPL is located on the second adhesive layer AL2, and the reflection reduction layer RPL can be attached to the cover layer COV by the second adhesive layer AL2.

[0196] In the non-display area NDA, the second adhesive layer AL2 can be located on the substrate SUB to cover the second insulating layer T-INS2 and a periphery (or edge) of the cover layer COV. The second adhesive layer AL2 can be in direct contact with a portion of the upper surface of the substrate SUB adjacent to the edge of the substrate SUB. An edge of the second adhesive layer AL2 can overlap with the edge of the substrate SUB.

[0197] The stepped portion STP can be defined by an edge of the substrate SUB defining an edge of the display panel DP and an edge of the second insulating layer T-INS2. For example, the stepped portion STP can be defined by an edge (e.g., the third side S3) of the substrate SUB and an edge (e.g., the third side S3’) of the second insulating layer T-INS2 located at different heights.

[0198] Basically, the edge of the substrate SUB defining the stepped portion STP can be the first side S1, the third side S3, and the fourth side S4 illustrated above in FIG. 4 In addition, the edge of the second insulating layer T-INS2 defining the stepped portion STP can be the first side S1’, the third side S3’, and the fourth side S4’ illustrated above in FIG. 4

[0199] FIG. 10 is illustrated in FIG. 2B. FIG. 4 is a cross-sectional view taken along the line II-II’ illustrated in

[0200] Referring to FIG. 10 , the second insulating layer T-INS2 and the dummy insulating layer D-INS can be located on the fourth insulating layer INS4. The trench GV can be defined between the second insulating layer T-INS2 and the dummy insulating layer D-INS. The second insulating layer T-INS2 and the dummy insulating layer D-INS can be formed at the same time or substantially at the same time from substantially the same material.

[0201] FIG. 11 is a diagram briefly illustrating a configuration illustrated in FIG. 9 ​​

[0202] For ease of description, FIG. 11 The display panel DP in FIG. 1A is exemplified as a single layer. Also, layers between the second insulating layer T-INS2 and the display panel DP are omitted.

[0203] Referring to FIG. 11 The edge of the second insulating layer T-INS2 and the edge of the cover layer COV can overlap each other, or can be aligned with each other, can be spaced apart from the edge of the display panel DP, and can be located inside the edge of the display panel DP.

[0204] The display device DD can further include a side cover layer S-COV on or in contact with side surfaces of the display panel DP, the second adhesive layer AL2, and the reflection reduction layer RPL. Exemplarily, the side cover layer S-COV is exemplified as a dotted line. The side cover layer S-COV can include an organic insulating layer. The side cover layer S-COV can absorb an external impact.

[0205] FIG. 12 FIG. 1B is a diagram illustrating a cross-sectional configuration of a comparative display device. FIG. 12 is exemplified as a cross-section corresponding to FIG. 11

[0206] Referring to FIG. 12 The edge of the second insulating layer T-INS2 and the edge of the cover layer COV of the comparative display device DD' can overlap with the edge of the display panel DP. When the side cover layer S-COV is not positioned, the edge of the second insulating layer T-INS2 and the edge of the cover layer COV can be exposed to the outside.

[0207] An external impact can be applied to the side cover layer S-COV. The side cover layer S-COV can absorb the external impact, but when the external impact is large, the amount of impact transmitted to the edge of the second insulating layer T-INS2 and the edge of the cover layer COV can increase.

[0208] When the amount of impact transmitted to the edge of the second insulating layer T-INS2 and the edge of the cover layer COV is large enough to damage the second insulating layer T-INS2 and the cover layer COV, the edge of the second insulating layer T-INS2 and the edge of the cover layer COV can be delaminated. Accordingly, the side surface of the comparative display device DD' can be damaged.

[0209] Referring to FIG. 11 The edge of the second insulating layer T-INS2 and the edge of the cover layer COV can be spaced apart from the edge of the display panel DP, and the second adhesive layer AL2 can cover the edge of the second insulating layer T-INS2 and the edge of the cover layer COV.

[0210] ​Even when an external impact is applied to the side cover layer S-COV, the side cover layer S-COV and the second adhesive layer AL2 can double-absorb the external impact. Accordingly, the amount of the external impact transmitted to the edge of the second insulating layer T-INS2 and the edge of the cover layer COV can be reduced, and thus the edge of the second insulating layer T-INS2 and the edge of the cover layer COV can not be delaminated. Accordingly, the side portion of the display device DD can not be damaged.

[0211] FIG. 13 FIGS. 1 to 3 are diagrams illustrating configurations of display devices according to embodiments of the disclosure. FIG. 14 For brief illustration FIG. 13 of the configurations illustrated in

[0212] FIG. 13 are illustrated as being the same as FIG. 9 the corresponding cross-sections, and FIG. 14 are illustrated as being the same as FIG. 11 the corresponding cross-sections. Hereinafter, the configurations illustrated in FIG. 13 and FIG. 14 will be described, with an emphasis on configurations different from the configurations illustrated in FIG. 9 and FIG. 11 .

[0213] Referring to FIG. 13 , the edge of the second insulating layer T-INS2 can be spaced apart from the edge of the substrate SUB. The cover layer COV-1 of the display device DD-1 can be located on the substrate SUB to cover the edge of the second insulating layer T-INS2. The cover layer COV-1 can be in direct contact with a portion of the upper surface of the substrate SUB adjacent to the edge of the substrate SUB. The edge of the cover layer COV-1 can overlap the edge of the substrate SUB. The second adhesive layer AL2 can be located on the cover layer COV-1 covering the edge of the second insulating layer T-INS2.

[0214] Referring to FIG. 14 , the edge of the second insulating layer T-INS2 can be spaced apart from the edge of the display panel DP, and the cover layer COV-1 can be located on the display panel DP to cover the edge of the second insulating layer T-INS2. The edge of the cover layer COV-1 and the edge of the second adhesive layer AL2 can overlap the edge of the display panel DP. Since the external impact can be absorbed by the side cover layer S-COV and the cover layer COV-1, the amount of the impact transmitted to the second insulating layer T-INS2 can be reduced.

[0215] FIG. 15 FIGS. 10 to 12 are diagrams illustrating an external impact test for FIG. 11 and FIG. 14 the display devices illustrated in FIG. 12 and the comparative display device illustrated in

[0216] InFIG. 15 In the graph, the vertical axis represents stress, and the unit of stress can be mega pascal (MPa). The stress can substantially correspond to the amount of impact transmitted to the second insulating layer T-INS2. Also, in the graph, FIG. 15 In the graph, the values exemplified on the display devices DD and DD-1 can represent the distance between the edge of the substrate SUB and the edge of the second insulating layer T-INS2.

[0217] Referring to FIG. 15 The amount of impact transmitted to the second insulating layer T-INS2 from the display devices DD and DD-1 can be reduced compared to the amount of impact transmitted to the second insulating layer T-INS2' from the comparative display device DD'. Also, in the graph, FIG. 15 In the graph, as the distance between the edge of the substrate SUB and the edge of the second insulating layer T-INS2 becomes larger, i.e., as the edge of the second insulating layer T-INS2 becomes spaced farther apart from the edge of the substrate SUB, the amount of impact transmitted to the second insulating layer T-INS2 can be reduced.

[0218] FIG. 16 A graph to exemplify a planar configuration of a mother panel according to one or more embodiments of the disclosure. FIG. 17 To exemplify FIG. 16 An enlarged view of any one of the unit panels exemplified in the graph.

[0219] Referring to FIG. 16 The mother panel M-PN can include a plurality of unit panels U-PN arranged along the first direction DR1 and the second direction DR2. Each of the unit panels U-PN can be the display panel DP described above. In FIG. 16 In the graph, the display area DA and the data driver DDV are exemplified as dotted lines.

[0220] The edge of each of the unit panels U-PN is exemplified as a dotted line. The edge of each of the unit panels U-PN can be defined as a cutting line CL. That is, the cutting line CL is exemplified as a dotted line. The mother panel M-PN is cut along the cutting line CL of each of the unit panels U-PN, and thus the unit panels U-PN can be separated from the mother panel M-PN. Accordingly, the cutting line CL can correspond to the first to fourth sides S1, S2, S3, and S4 of the display panel DP described above.

[0221] Basically, after the input sensing part ISP and the reflection reduction layer RPL described above are positioned on the unit panel U-PN, the unit panel U-PN can be separated from the mother panel M-PN. When the unit panel U-PN is separated, the input sensing parts ISP can also be separated from each other, and the reflection reduction layers RPL can also be separated from each other.

[0222] The second insulating layer T-INS2 and the dummy insulating layer D-INS can be located on each of the unit panels U-PN. The groove GV can be defined between the second insulating layer T-INS2 and the dummy insulating layer D-INS. This configuration will be exemplified and described in more detail in FIG. 17 .

[0223] Referring to FIG. 17 , the groove GV can be defined on the unit panel U-PN, and the groove GV can correspond to the stepped portion STP and the groove GV exemplified in FIG. 4 , FIG. 9 and FIG. 10 . FIG. 17 A portion of the groove GV exemplified in FIG. 4 may be retained on the display panel DP, and thus, the groove GV exemplified in may be defined.

[0224] Accordingly, FIG. 16 and FIG. 17 the groove GV exemplified in FIG. 4 is represented by using the same reference numerals as those of the groove GV exemplified in FIG. 17 . For example, in order to more clearly exemplify and describe the shape of the groove GV in FIG. 17 , the groove GV exemplified in FIG. 4 is exemplified to be relatively large than the groove GV exemplified in .

[0225] The dummy insulating layer D-INS can be located around the second insulating layer T-INS2 to surround the second insulating layer T-INS2. The groove GV can be defined between the second insulating layer T-INS2 and the dummy insulating layer D-INS. The groove GV can be defined in a substantially rectangular closed ring shape corresponding to the shape of the second insulating layer T-INS2.

[0226] The groove GV can overlap a portion of the cutting line CL. For example, the groove GV can overlap a portion of the cutting line CL adjacent to each of the first side S1', the third side S3', and the fourth side S4'.

[0227] The groove GV overlapping the portion of the cutting line CL adjacent to the first side S1' can extend in the second direction DR2. The groove GV overlapping the portion of the cutting line CL adjacent to each of the third side S3' and the fourth side S4' can extend in the first direction DR1. The groove GV spaced apart from the second side S2 and defined between the second side S2' and the dummy insulating layer D-INS can extend in the second direction DR2.

[0228] A width of the groove GV overlapping with a portion of the cutting line CL adjacent to the first side S1', the third side S3', and the fourth side S4' can be greater than a width of the groove GV defined between the second side S2' and the dummy insulating layer D-INS. In the specification, the "width" can be defined as a value measured in a direction crossing the configured extension direction.

[0229] The above step portion STP can be formed at a portion cut along a portion of the cutting line CL adjacent to the first side S1', the third side S3', and the fourth side S4' when the unit panel U-PN is separated from the mother panel M-PN. The groove GV defined between the second side S2' and the dummy insulating layer D-INS can be retained on the unit panel U-PN when the unit panel U-PN is separated from the mother panel M-PN.

[0230] An opening D-OP can be defined in the dummy insulating layer D-INS. The opening D-OP can expose the data driver DDV. The opening D-OP can expose a portion of the unit panel U-PN adjacent to the data driver DDV. The groove GV can be defined between the opening D-OP and the display area DA.

[0231] FIG. 18A To cut along the cutting line CL, FIG. 17 a cross-sectional view taken along the line III-III' in FIG. 3B. FIG. 18B to cut along the cutting line CL, FIG. 18A a view of the unit panel cut along the cutting line and separated from the mother panel. FIG. 18A is illustrated in a simplified manner similar to FIG. 11 .

[0232] Referring to FIG. 18A , an insulating layer P-INS can be located on the unit panel U-PN. The groove GV overlapping with the cutting line CL can be defined in the insulating layer P-INS. The insulating layer P-INS can be separated into the second insulating layer T-INS2 and the dummy insulating layer D-INS by the groove GV. Accordingly, the second insulating layer T-INS2 and the dummy insulating layer D-INS can be formed simultaneously or substantially simultaneously from the same material.

[0233] In one or more embodiments, FIG. 9 the first conductive pattern CTL1 and the second conductive pattern CTL2 illustrated in FIG. 3B can be located on the unit panel U-PN, and the insulating layer P-INS can be located on the second conductive pattern CTL2. For example, the second insulating layer T-INS2 of the insulating layer P-INS can be located on the second conductive pattern CTL2.

[0234] The cover layer COV can be located on the insulating layer P-INS. For example, the cover layer COV can be located on the second insulating layer T-INS2 of the insulating layer P-INS. The organic ink having fluidity can be provided on the second insulating layer T-INS2, and the organic ink can be cured to form the cover layer COV.

[0235] When the organic ink is provided on the second insulating layer T-INS2, the organic ink can be positioned to the edge of the second insulating layer T-INS2 according to its surface tension, and the side surface of the organic ink can have a curved shape. Accordingly, the side surface of the cover layer COV formed by curing the organic ink can also have a curved shape. When the organic ink is excessively provided on the second insulating layer T-INS2, the organic ink can overflow beyond the second insulating layer T-INS2. In this case, the organic ink overflowing the second insulating layer T-INS2 can be accommodated in the groove GV.

[0236] The second adhesive layer AL2 can be located on the cover layer COV and the dummy insulating layer D-INS, and the reflection reduction layer RPL can be located on the second adhesive layer AL2. The second adhesive layer AL2 can be located on the unit panel U-PN to fill the groove GV.

[0237] Reference FIG. 18A and FIG. 18B The mother panel M-PN can be cut along the cutting line CL, and the unit panel U-PN can be separated from the mother panel M-PN. The unit panel U-PN separated from the mother panel M-PN can be defined as the display panel DP.

[0238] FIG. 19 A diagram illustrating a configuration of a unit panel according to one or more other embodiments of the disclosure. FIG. 20A A cross-sectional view taken along FIG. 19 in the diagram. FIG. 20B A diagram illustrating a unit panel cut along FIG. 20A in the diagram and separated from a mother panel.

[0239] FIG. 19 A plan view corresponding to FIG. 17 is illustrated. Further, FIG. 20A and FIG. 20B are respectively illustrated as cross-sectional views corresponding to FIG. 18A and FIG. 18B .

[0240] Hereinafter, configurations illustrated in FIG. 19 , FIG. 20A and FIG. 20B will be described, with a focus on configurations different from those illustrated in FIG. 17 , FIG. 18A and FIG. 18B .

[0241] Referring to FIG. 21 The first dam layer DML1 can be located on the unit panel U-PN. The first dam layer DML1 can surround the second insulating layer T-INS2 when viewed in plan. The first dam layer DML1 can surround the display area DA when viewed in plan. The dummy insulating layer D-INS can surround the first dam layer DML1 when viewed in plan.

[0242] A groove GV can be defined between the dummy insulating layer D-INS and the first dam layer DML1. The groove GV can surround the first dam layer DML1. A first groove GV1 can be defined between the first dam layer DML1 and the second insulating layer T-INS2.

[0243] When the organic ink is provided on the second insulating layer T-INS2, the organic ink can extend to an edge of the second insulating layer T-INS2 according to its surface tension. When the organic ink is excessively provided on the second insulating layer T-INS2, and when the organic ink overflows the second insulating layer T-INS2, the organic ink overflowing the second insulating layer T-INS2 can be accommodated in the first groove GV1. That is, the first dam layer DML1 can function as a dam.

[0244] When the excessive organic ink is more excessively provided on the second insulating layer T-INS2, the organic ink can overflow beyond the first dam layer DML1. In this case, the organic ink overflowing the first dam layer DML1 can be additionally accommodated in the groove GV.

[0245] Referring to FIG. 22A and FIG. 22B The unit panel U-PN can be separated from the mother panel M-PN to form a display panel DP. The first dam layer DML1 can be located on the display panel DP, and the first dam layer DML1 can be spaced apart from an edge of the display panel DP. The first dam layer DML1 can be located between the edge of the display panel DP and the second insulating layer T-INS2 in a plan view. The first dam layer DML1 and the second insulating layer T-INS2 can be formed from the same material at the same time or substantially the same time.

[0246] FIG. 18A A diagram illustrating a configuration of a unit panel according to one or more other embodiments of the disclosure. FIG. 18B A cross-sectional view taken along FIG. 21 in the diagram. FIG. 22A A diagram illustrating a unit panel cut along a cutting line illustrated in FIG. 22B in the diagram and separated from the mother panel.

[0247] FIG. 17 A plan view illustrating a corresponding plan view of FIG. 18A Furthermore, FIG. 18B and FIG. 21 illustrate a plan view of FIG. 22A and FIG. 22BA corresponding cross-sectional view.

[0248] Hereinafter, configurations exemplified in FIG. 23 , FIG. 23 and FIG. 24B will be described, with a focus on configurations different from those exemplified in FIG. 24A , FIG. 23 and FIG. 17 .

[0249] Referring to FIG. 24A , the first dam layer DML1’ and the second dam layer DML2’ can be located on the unit panel U-PN. The first dam layer DML1’ can surround the second insulating layer T-INS2 when viewed in plan. The second dam layer DML2’ can surround the first dam layer DML1’ when viewed in plan. The first dam layer DML1’ and the second dam layer DML2’ can surround the display area DA when viewed in plan. The dummy insulating layer D-INS can surround the second dam layer DML2’.

[0250] A groove GV can be defined between the dummy insulating layer D-INS and the second dam layer DML2’. The groove GV can surround the second dam layer DML2’. A first groove GV1’ can be defined between the first dam layer DML1’ and the second insulating layer T-INS2. A second groove GV2’ can be defined between the second dam layer DML2’ and the first dam layer DML1’.

[0251] When the organic ink is provided on the second insulating layer T-INS2, the organic ink can be positioned to an edge of the second insulating layer T-INS2 according to its surface tension. However, when the organic ink is provided in excess, it can overflow beyond the second insulating layer T-INS2, the first dam layer DML1’, or the second dam layer DML2’. In this case, the organic ink can be accommodated in the first groove GV1’, the second groove GV2’, or the groove GV.

[0252] Referring to FIG. 24B and FIG. 18A , the unit panel U-PN can be separated from the mother panel M-PN to form a display panel DP. The first dam layer DML1’ and the second dam layer DML2’ can be located on the display panel DP, and the first dam layer DML1’ and the second dam layer DML2’ can be separated from an edge of the display panel DP.

[0253] The first dam layer DML1’ can be located between an edge of the display panel DP and the second insulating layer T-INS2 in plan view. The second dam layer DML2’ can be located between the edge of the display panel DP and the first dam layer DML1’ in plan view. The second insulating layer T-INS2, the first dam layer DML1’, and the second dam layer DML2’ can be formed simultaneously or substantially simultaneously from the same material.

[0254] The first dam layer DML1’ and the second dam layer DML2’ can have a width of about 1 micrometer to about 30 micrometers, for example, about 5 micrometers to about 20 micrometers. The first trench GV1’ and the second trench GV2’ can have a width of about 1 micrometer to about 20 micrometers, for example, about 5 micrometers to about 15 micrometers. The first dam layer DML1’ and the second dam layer DML2’ can have a thickness of about 0.1 micrometer to about 3 micrometers, for example, about 1.5 micrometers to about 2.5 micrometers.

[0255] FIG. 18B FIG. 24a is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure. FIG. 23 FIG. 24b is a cross-sectional view taken along line VI-VI’ in FIG. 24a. FIG. 24A FIG. 24c is a plan view illustrating a unit panel cut along a cutting line illustrated in FIG. 24b. FIG. 24B FIG. 24d is a plan view illustrating a unit panel cut and separated from a mother panel along the cutting line illustrated in FIG. 24b.

[0256] FIG. 17 FIG. 25a is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure. FIG. 18A FIG. 25b is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure. FIG. 18B FIG. 25c is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure. FIG. 23 FIG. 25d is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure. FIG. 24A FIG. 25e is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure. FIG. 24B FIG. 25f is a plan view illustrating a configuration of a unit panel according to an embodiment of the disclosure.

[0257] Hereinafter, configurations illustrated in FIGS. 26a to 26f will be described, focusing on configurations different from those illustrated in FIGS. 24a to 24f. FIG. 25 FIG. 26A FIG. 25 FIG. 26B FIG. 26A FIG. 25

[0258] Referring to FIG. 26a, a dummy insulating layer D-INS can be positioned to overlap a portion of the cutting line CL adjacent to the first side S1’, the third side S3’, and the fourth side S4’. The dummy insulating layer D-INS can surround the second insulating layer T-INS2, and a dummy trench DGV can be defined between the dummy insulating layer D-INS and the second insulating layer T-INS2. The dummy trench DGV can be defined inside the cutting line (e.g., an edge of the unit panel U-PN). FIG. 17

[0259] Referring to FIGS. 26b to 26f, the unit panel U-PN can be separated from the mother panel M-PN to form a display panel DP. The dummy insulating layer D-INS, which is located on and remains on the display panel DP, can be defined as a dummy dam layer DDML. The dummy dam layer DDML can be spaced apart from the second insulating layer T-INS2, and an edge of the dummy dam layer DDML can overlap or align with an edge of the display panel DP. The dummy trench DGV can be defined between the dummy dam layer DDML and the second insulating layer T-INS2. FIG. 26A FIG. 26B ​​​​​​​​​

[0260] FIG. 18A A diagram illustrating a configuration of a unit panel according to one or more other embodiments of the disclosure. FIG. 18B A diagram illustrating a configuration of a unit panel according to one or more other embodiments of the disclosure. FIG. 25 A cross-sectional view taken along the line VII-VII' illustrated in FIG. 26A A diagram illustrating a unit panel cut and separated from a mother panel along a cutting line illustrated in FIG. 26B A diagram illustrating a unit panel cut and separated from a mother panel along a cutting line illustrated in

[0261] FIG. 17 A diagram illustrating a unit panel according to one or more other embodiments of the disclosure. FIG. 18A A corresponding plan view. In addition, FIG. 18B A diagram illustrating a unit panel according to one or more other embodiments of the disclosure. FIG. 25 A corresponding plan view. In addition, FIG. 23 A diagram illustrating a unit panel according to one or more other embodiments of the disclosure. FIG. 26A A corresponding plan view. In addition,

[0262] Hereinafter, a configuration illustrated in FIG. 26B , FIG. 27A , FIG. 27B will be described, focusing on a configuration different from a configuration illustrated in FIG. 28A , FIG. 28B , and FIG. 29A .

[0263] Referring to FIG. 29B , the dummy insulating layer D-INS can have substantially the same configuration as that of the dummy insulating layer D-INS illustrated in FIG. 30A . The first dummy dam layer DDML1 can be located between the dummy insulating layer D-INS and the second insulating layer T-INS2. The first dummy dam layer DDML1 can be located on the unit panel U-PN. The first dummy dam layer DDML1 can surround the second insulating layer T-INS2, and the dummy insulating layer D-INS can surround the first dummy dam layer DDML1.

[0264] The first dummy groove DGV1 can be defined between the first dummy dam layer DDML1 and the second insulating layer T-INS2. The second dummy groove DGV2 can be defined between the dummy insulating layer D-INS and the first dummy dam layer DDML1.

[0265] Referring to FIG. 30B and FIG. 31A , the unit panel U-PN can be separated from the mother panel M-PN to form a display panel DP. The dummy dam layer DDML and the first dummy dam layer DDML1 can be located on the display panel DP.

[0266] The dummy dam layer DDML can be spaced apart from the second insulating layer T-INS2, and a first dummy dam layer DDML1 can be located between the dummy dam layer DDML and the second insulating layer T-INS2. A first dummy trench DGV1 can be defined between the first dummy dam layer DDML1 and the second insulating layer T-INS2, and a second dummy trench DGV2 can be defined between the dummy dam layer DDML and the first dummy dam layer DDML1.

[0267] FIG. 31B , FIG. 27A , FIG. 27B , FIG. 18A , FIG. 18B , FIG. 28A , FIG. 28B , FIG. 20A , FIG. 20B and FIG. 29A are diagrams illustrating configurations on a unit panel according to various embodiments of the disclosure.

[0268] FIG. 29B and FIG. 22A are diagrams illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 22B and FIG. 30A . FIG. 30B and FIG. 24A are diagrams illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 24B and FIG. 31A . FIG. 31B and FIG. 26A are diagrams illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 26B and FIG. 18A . FIG. 18B and FIG. 20A are diagrams illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 20B and FIG. 22A . FIG. 22B and FIG. 24A are diagrams illustrating one or more embodiments modified from one or more embodiments corresponding to FIG. 24B and FIG. 26A .

[0269] Hereinafter, a configuration different from the configurations illustrated in FIG. 26B , FIG. 27A , FIG. 27B , FIG. 28A , FIG. 28B , FIG. 29A , FIG. 29B , FIG. 30A , FIG. 30B and ​ will be described. ​ , ​ ,​ 、 ​ 、 ​ 、 ​ 、 ​ 、 ​ 、 Figure 31A and Figure 31B illustrated in

[0270] Referring to Figure 27A and Figure 27B , the cover layer COV-1 can be located on the second insulating layer T-INS2, the dummy insulating layer D-INS, and the unit panel U-PN. The cover layer COV-1 can fill the groove GV. The second adhesive layer AL2 can be located on the cover layer COV-1. The unit panel U-PN can be separated from the mother panel M-PN to form the display panel DP. Figure 27B The configuration illustrated in Figure 14 may be substantially the same as the configuration illustrated in

[0271] Referring to Figure 28A and Figure 28B , the cover layer COV-1 can be located on the second insulating layer T-INS2, the dummy insulating layer D-INS, the first dam layer DML1, and the unit panel U-PN. The cover layer COV-1 can fill the groove GV and the first groove GV1. The second adhesive layer AL2 can be located on the cover layer COV-1. The unit panel U-PN can be separated from the mother panel M-PN to form the display panel DP.

[0272] Referring to Figure 29A and Figure 29B , the cover layer COV-1 can be located on the second insulating layer T-INS2, the dummy insulating layer D-INS, the first dam layer DML1', the second dam layer DML2', and the unit panel U-PN. The cover layer COV-1 can fill the groove GV, the first groove GV1', and the second groove GV2'. The second adhesive layer AL2 can be located on the cover layer COV-1. The unit panel U-PN can be separated from the mother panel M-PN to form the display panel DP.

[0273] Referring to Figure 30A and Figure 30B , the cover layer COV-1 can be located on the second insulating layer T-INS2, the dummy insulating layer D-INS, and the unit panel U-PN. The cover layer COV-1 can fill the dummy groove DGV. The unit panel U-PN can be separated from the mother panel M-PN to form the display panel DP. The cover layer COV-1 can be located on the dummy dam layer DDML located on the display panel DP.

[0274] Referring to Figure 31A and Figure 31BThe cover layer COV-1 can be located on the second insulating layer T-INS2, the dummy insulating layer D-INS, the first dummy dam layer DDML1, and the unit panel U-PN. The cover layer COV-1 can fill the first dummy groove DGV1 and the second dummy groove DGV2. The unit panel U-PN can be separated from the mother panel M-PN to form the display panel DP. The cover layer COV-1 can be located on the dummy dam layer DDML and the first dummy dam layer DDML1, which are located on the display panel DP.

[0275] Figure 32 and Figure 33 FIGS. 1A and 1B are diagrams illustrating configurations on a unit panel according to embodiments of the disclosure.

[0276] Figure 32 and Figure 33 FIGS. 2A and 2B are diagrams illustrating configurations on a unit panel according to other embodiments of the disclosure. Figure 21

[0277] In the following, configurations illustrated in FIGS. 3A and 3B will be described, with the focus on configurations different from those illustrated in FIGS. 1A and 1B. Figure 32 Figure 33 Figure 21

[0278] Referring to FIGS. 4A and 4B, Figure 32 Figure 33 The first dam layer DML1' can be located adjacent to the first side S1', the third side S3', and the fourth side S4'. The plurality of dummy dam layers DDML' can be located between the second side (or lower side) S2 of the display panel DP and the second insulating layer T-INS2 in a plan view. For example, the dummy dam layers DDML' can be located between the second dam layer DML2' and the second side S2' of the second insulating layer T-INS2.

[0279] Referring to FIGS. 5A and 5B, Figure 32 The dummy dam layers DDML' can be arranged in a zigzag form or shape along the second direction DR2.

[0280] Referring to FIGS. 6A and 6B, Figure 33 The dummy dam layers DDML' can be arranged in a zigzag form or shape along the second direction DR2.

[0281] According to the disclosure, the side surface of the insulating layer of the input sensing part and the side surface of the cover layer located on the insulating layer are spaced apart from the edge of the display panel, and the adhesive layer can be located on the cover layer to cover the side surface of the insulating layer and the side surface of the cover layer. Since the adhesive layer absorbs external impact, external impact applied to the side surface of the insulating layer and the side surface of the cover layer can be reduced.

[0282] ​​​​​Since the external impact applied to the side surface of the insulation layer and the side surface of the cover layer is reduced, the side surface of the insulation layer and the side surface of the cover layer do not delaminate from each other. As a result, damage to the side portion of the display device can be reduced or prevented.

[0283] Although the present disclosure has been described with reference to the embodiments, it will be understood by those having ordinary skill in the technical field to which the present disclosure pertains that various modifications and changes can be made in the present disclosure without departing from the spirit and technical scope of the present disclosure, within the scope of the appended claims. Therefore, the technical scope of the present disclosure should not be limited to the detailed description of the specification, but all technical ideas falling within the scope of the claims and equivalents of the claims fall within the scope of the present disclosure.

Claims

1. A display device comprising: a display panel; a first conductive pattern over the display panel; a second conductive pattern over the first conductive pattern; an insulating layer over the second conductive pattern; and a cover layer over the insulating layer, wherein an edge of the insulating layer and an edge of the cover layer are aligned and spaced apart from an edge of the display panel.

2. The display device of claim 1, further comprising: an adhesion layer over the cover layer and the display panel to cover the edge of the insulating layer and the edge of the cover layer; and a reflection reduction layer over the adhesion layer.

3. The display device of claim 2, wherein the display panel comprises: a substrate; and a pixel over the substrate, and wherein the adhesion layer is in direct contact with a portion of an upper surface of the substrate adjacent to an edge of the substrate.

4. The display device of claim 1, wherein an upper side, a left side, and a right side of the display panel and an upper side, a left side, and a right side of the insulating layer define a step portion.

5. The display device of claim 4, further comprising a dummy insulating layer over the display panel and between the insulating layer and a lower side of the display panel in plan view, wherein a slot is defined between the dummy insulating layer and the insulating layer.

6. The display device of claim 5, wherein the dummy insulating layer and the insulating layer comprise a same material.

7. The display device of claim 5, wherein the step portion and the slot have a closed ring shape and surround a display area of the display panel in plan view.

8. The display device of claim 1, further comprising a first dam layer over the display panel and between the edge of the display panel and the insulating layer in plan view, wherein a first slot is defined between the first dam layer and the insulating layer.

9. The display device of claim 1, further comprising: a first dam layer over the display panel and between the edge of the display panel and the insulating layer in plan view; and a second dam layer over the display panel and between the edge of the display panel and the first dam layer in plan view, wherein a first slot is defined between the first dam layer and the insulating layer, and wherein a second slot is defined between the second dam layer and the first dam layer.

10. The display device of claim 9, wherein the insulating layer, the first dam layer, and the second dam layer comprise a same material.

11. The display device of claim 9, wherein the first dam layer and the second dam layer surround a display area of the display panel in plan view.

12. The display device of claim 1, further comprising a dummy dam layer over the display panel and spaced apart from the insulating layer, wherein an edge of the dummy dam layer is aligned with the edge of the display panel, and wherein a dummy slot is defined between the dummy dam layer and the insulating layer. ​ ​ ​ ​ 13. The display device according to claim 1, further comprising: a dummy dam layer over the display panel and spaced apart from the insulating layer; and a first dummy dam layer over the display panel and between the dummy dam layer and the insulating layer, wherein a first dummy trench is defined between the first dummy dam layer and the insulating layer, and wherein a second dummy trench is defined between the dummy dam layer and the first dummy dam layer.

14. The display device according to claim 1, further comprising a dummy dam layer between a lower side of the display panel and the insulating layer in plan view.

15. The display device according to claim 14, wherein the dummy dam layer is arranged in a direction parallel to the lower side of the display panel.

16. The display device according to claim 14, wherein the dummy dam layer is arranged in a zigzag form in a direction parallel to the lower side of the display panel.

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