Display panel and display device

Abstract

According to the display panel and the display device, an active layer is located on the side, away from a substrate, of at least one conducting layer, so that the conducting layers can emit light to the bottom of the active layer, the adverse effect of illumination on transistor elements can be reduced, and the display effect is improved. In addition, a plurality of pixel circuits are formed in the active layer and the multi-layer conductive layer, output nodes of the pixel circuits are electrically connected with a first pole of the light-emitting device, and a second pole of the light-emitting device is connected with a first power line. In the pixel circuit, the first electrode of the first transistor is electrically connected with the second power line, the second electrode of the first transistor is electrically connected with the output node, and the first power line and the second power line are connected with the same voltage signal, so that the current for initializing the first electrode of the light-emitting device can be increased; therefore, the driving force for initializing the first pole of the light-emitting device is improved, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, users have higher and higher requirements for display quality.

[0003] In the prior art, the display panel has the problem of poor display effect. SUMMARY

[0004] The present application provides a display panel and a display device to improve the display effect of the display panel and improve user experience.

[0005] According to an aspect of the present application, a display panel is provided, comprising:

[0006] a substrate;

[0007] an active layer and a plurality of conductive layers are stacked on one side of the substrate, the active layer is located on the side of the at least one conductive layer away from the substrate; and a plurality of pixel circuits are formed in the active layer and the plurality of conductive layers;

[0008] a light emitting device, a first electrode of the light emitting device is electrically connected to an output node of the pixel circuit, and a second electrode of the light emitting device is electrically connected to a first power supply line, the first power supply line being located in the at least one conductive layer;

[0009] wherein the pixel circuit further comprises a first transistor, a first electrode of the first transistor is electrically connected to a second power supply line, and a second electrode of the first transistor is electrically connected to the output node; and the first power supply line and the second power supply line are connected to the same voltage signal.

[0010] According to another aspect of the present application, a display device is provided, comprising the display panel of any of the above embodiments of the present application.

[0011] The display panel and the display device of the embodiments of the present application have the active layer located on the side of the at least one conductive layer away from the substrate, so that the conductive layer can irradiate the active layer from the bottom, which is beneficial to reduce the adverse effects of light on the transistor elements and improve the display effect. In addition, the plurality of pixel circuits are formed in the active layer and the plurality of conductive layers, the first electrode of the light emitting device is electrically connected to the output node of the pixel circuit, and the second electrode of the light emitting device is connected to the first power supply line. The first electrode of the first transistor in the pixel circuit is electrically connected to the second power supply line, and the second electrode of the first transistor is electrically connected to the output node, which can improve the current for initializing the first electrode of the light emitting device, and further improve the driving force for initializing the first electrode of the light emitting device, thereby improving the display effect.

[0012] It is to be understood that the details described in this section are not intended to identify key or critical elements of the embodiments of the application or to limit the scope of the application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0014] Figure 1 is a top view of a display panel provided by an embodiment of the present application;

[0015] Figure 2 is a sectional view of a display panel provided by an embodiment of the present application;

[0016] Figure 3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0017] Figure 4 is a top view of another display panel provided by an embodiment of the present application;

[0018] Figure 5 is a top view of another display panel provided by an embodiment of the present application;

[0019] Figure 6 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0020] Figure 7 is a top view of another display panel provided by an embodiment of the present application;

[0021] Figure 8 is a top view of a fourth conductive layer in a display panel;

[0022] Figure 9 is a top view of a fourth conductive layer and a fifth conductive layer in a display panel;

[0023] Figure 10 is a top view of a fourth conductive layer, a fifth conductive layer and an active layer in a display panel;

[0024] Figure 11 is a top view of a fourth conductive layer, a fifth conductive layer, an active layer and a first conductive layer in a display panel;

[0025] Figure 12 is a sectional view of another display panel provided by an embodiment of the present application;

[0026] Figure 13 is a top view of another display panel provided by an embodiment of the present application;

[0027] Figure 14 is a top view of still another display panel provided by an embodiment of the present application;

[0028] Figure 15 is a top view of yet another display panel provided by an embodiment of the present application;

[0029] Figure 16 is a sectional view of another display panel provided by an embodiment of the present application;

[0030] Figure 17 is a top view of still another display panel provided by an embodiment of the present application;

[0031] Figure 18 is a top view of another display panel provided by an embodiment of the present application; Figure 17 is a partial enlarged view of the middle red frame area;

[0032] Figure 19 is a sectional view of another display panel provided by an embodiment of the present application;

[0033] Figure 20 is a sectional view of still another display panel provided by an embodiment of the present application;

[0034] Figure 21 is a partial enlarged view of an embodiment of the present application;

[0035] Figure 22 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0036] Figure 23 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative work should fall within the protection scope of the present application.

[0038] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and in the above-described drawings are intended to distinguish similar objects and not necessarily describe a particular sequential or chronological order. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the application described herein can be practiced in other than the illustrated or described order. Furthermore, the terms "comprise" and "have", and any variations thereof, are intended to cover non-exclusive inclusion, for example, processes, methods, systems, products, or devices that include a list of steps or units not necessarily limited to those clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products, or devices.

[0039] Figure 1 is a top view of a display panel provided by an embodiment of the present application, Figure 2 is a sectional view of a display panel provided by an embodiment of the present application, wherein Figure 2 may correspond Figure 1 obtained by cutting along AA', Figure 3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application, with reference to Figures 1-3 The display panel comprises: a substrate 10; an active layer 20 and a plurality of conductive layers 30 stacked on one side of the substrate 10, the active layer 20 being located on the side of at least one conductive layer 30 away from the substrate 10; a plurality of pixel circuits formed in the active layer 20 and the plurality of conductive layers 30; a light emitting device D1, a first electrode of the light emitting device D1 being electrically connected to an output node OUT1 of the pixel circuit, a second electrode of the light emitting device D1 being electrically connected to a first power supply line, the first power supply line being located in at least one conductive layer 30; wherein the pixel circuit further comprises a first transistor T1, a first electrode of the first transistor T1 being electrically connected to a second power supply line VSS2, a second electrode of the first transistor T1 being electrically connected to the output node OUT1; the first power supply line and the second power supply line VSS2 are connected to the same voltage signal. The second power supply line VSS2 is located in at least one conductive layer 30.

[0040] Specifically, the substrate 10 serves to provide protection and support for the display panel, wherein the substrate 10 can be a flexible substrate formed of a material such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a hard substrate formed of a material such as glass. The substrate 10 has the active layer 20 and the plurality of conductive layers 30 provided on one side thereof, the active layer 20 and the adjacent conductive layer 30 are provided with an insulating layer, and the plurality of conductive layers 30 are isolated from each other by the insulating layer. The active layer 20 and the plurality of conductive layers 30 have a plurality of pixel circuits formed therein, the pixel circuits are used to drive the light emitting element to emit light. The pixel circuit includes a transistor element, since the channel region of the transistor element located in the active layer 20 is sensitive to light, the light irradiated to the channel region of the transistor element will affect the electrical performance of the transistor element. In the embodiment, the active layer 20 is provided on the side of at least one conductive layer 30 away from the substrate 10, so that the conductive layer 30 can provide bottom light shielding for the active layer 20, which is beneficial to reduce the adverse effects of light on the transistor element and improve the display effect.

[0041] The display panel further includes a light emitting display panel and a light emitting element D1, the light emitting element D1 can be a light emitting diode, for example, can be an organic light emitting diode, the light emitting element D1 includes a first electrode, a light emitting functional layer, and a second electrode which are provided in a stack, and the light emitting element D1 is located on the side of the active layer 20 and the plurality of conductive layers 30 away from the substrate 10. Optionally, the first electrode is an anode of the light emitting element D1, and the second electrode is a cathode of the light emitting element D1. The first electrode of the light emitting element D1 is electrically connected to an output node OUT1 of the pixel circuit, and the second electrode of the light emitting element D1 is electrically connected to a first power supply line. The pixel circuit can output a driving current to the light emitting element D1 through the output node OUT1, thereby driving the light emitting element D1 to display.

[0042] The pixel circuit further includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to a second power supply line VSS2, and a second electrode of the first transistor T1 is electrically connected to the output node OUT1. When the first transistor T1 is turned on, the second power supply voltage on the second power supply line VSS2 can be transmitted to the first electrode of the light emitting element D1. Since the first power supply line and the second power supply line VSS2 are connected to the same voltage signal, the voltages of the first electrode and the second electrode of the light emitting element D1 are equal (in the case that the transmission resistances of the first power supply line and the second power supply line VSS2 are the same) or close (in the case that the transmission resistances of the first power supply line and the second power supply line VSS2 are different), thereby realizing the initialization effect on the first electrode of the light emitting element D1. The first power supply line and the second power supply line VSS2 can be electrically connected to a power supply chip. Compared with the prior art scheme of providing an initialization voltage for the first electrode of the light emitting element D1 by using a driving chip in the display panel, the driving force can be improved, which is beneficial to improve the display effect.

[0043] The display panel provided by the embodiment of the present application has the active layer located on the side of the at least one conductive layer away from the substrate, so that the conductive layer can irradiate the active layer from the bottom, which is beneficial to reducing the adverse effects of light on the transistor element and improving the display effect. In addition, the active layer and the plurality of conductive layers form a plurality of pixel circuits, the output node of the pixel circuit is electrically connected to the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the first power supply line. The first electrode of the first transistor in the pixel circuit is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the output node. The first power supply line and the second power supply line are connected to the same voltage signal, so that the current for initializing the first electrode of the light-emitting device can be improved, and the driving force for initializing the first electrode of the light-emitting device can be improved, thereby improving the display effect.

[0044] Figure 4 is a top view of another display panel provided by the embodiment of the present application, referring to Figure 3 and Figure 4 Optionally, the display panel includes a display area AA and a non-display area NAA; in the non-display area NAA, the first power supply line VSS1 and the second power supply line VSS2 are electrically connected to the same power supply bus VSS0; in the display area AA, the first power supply line VSS1 and the second power supply line VSS2 are not connected; in the non-display area NAA, the first power supply line VSS1 is electrically connected to the second electrode; and in the display area AA, the second power supply line VSS2 is electrically connected to the second electrode of the first transistor T1.

[0045] Optionally, the second electrodes of the plurality of light-emitting devices D1 in the display panel are electrically connected to each other. For example, the second electrodes of all the light-emitting devices D1 in the display panel are electrically connected to form a whole second electrode.

[0046] Specifically, the first power supply line VSS1 and the second power supply line VSS2 are electrically connected in the non-display area NAA, so that the first power supply line VSS1 and the second power supply line VSS2 can be connected to the same voltage signal in the non-display area NAA. Since the first power supply line VSS1 is electrically connected to the second electrode of the light-emitting device D1, the voltage transmission voltage drop caused by the second electrode will be large. In the embodiment, the first power supply line VSS1 and the second power supply line VSS2 are not connected in the display area AA, so that the second power supply line VSS2 is less affected by the voltage drop caused by the second electrode, and the voltage of the first electrode of the light-emitting device D1 in the pixel circuit at different positions in the display panel after being initialized by the first transistor T1 is less different, which is beneficial to further improving the display effect.

[0047] Continuing to refer to Figure 4Optionally, the display panel further comprises a power bus VSS0, the power bus VSS0 is arranged around the display area AA, the first power line VSS1 is electrically connected with the power bus VSS0 at at least two sides of the display area AA, and the second power line VSS2 is electrically connected with the power bus VSS0 at one side of the display area AA.

[0048] By arranging the first power line VSS1 to be electrically connected with the power bus VSS0 at at least two sides of the display area AA, the voltage drop transmitted to the second electrode of the light emitting device D1 can be reduced, which is beneficial to improve the display uniformity and further improve the display effect. By arranging the second power line VSS2 to be electrically connected with the power bus VSS0 at one side of the display area AA, the voltage on the second power line VSS2 is less affected by the voltage drop caused by the second electrode of the light emitting device D1, which further ensures that the voltage provided by the first transistor T1 to the first electrode of the light emitting device D1 in the pixel circuits at different positions in the display panel is closer, and further improves the display effect.

[0049] With reference to Figure 3 Optionally, the non-display area NAA comprises a first non-display area NAA1, the first non-display area NAA1 is located at one side of the display area AA, and the first power line VSS1 and the second power line VSS2 are respectively electrically connected with the power bus VSS0 in the first non-display area NAA1. The first non-display area NAA1 can be a non-display area NAA in which a power chip is arranged in the display panel, and the power chip can be connected with the power bus VSS0 in the first non-display area NAA1. For example, for the rectangular display panel shown in Figure 3 The first non-display area NAA1 can be the lower frame of the display panel.

[0050] Optionally, the non-display area NAA comprises a second non-display area NAA2 which is away from the first non-display area NAA1 of the display area AA, the first power line VSS1 is electrically connected with the power bus VSS0 in the second non-display area NAA2, and the second power line VSS2 is not connected with the power bus VSS0. In this way, the voltage on the second power line VSS2 is further reduced by the voltage drop caused by the second electrode of the light emitting device D1, which is beneficial to further improve the display effect.

[0051] Optionally, in display area AA, the first power line VSS1 includes a first signal line VSS11 and a second signal line VSS12. The first signal line VSS11 extends along a first direction x, and the second signal line VSS12 extends along a second direction y. The first direction x and the second direction y intersect, and the first signal line VSS11 and the second signal line VSS12 are electrically connected to form a mesh-like first power line VSS1. This arrangement can reduce the resistance of the first power line VSS1, lowering the voltage drop across the first power line VSS1. This reduces the difference in voltage between the first electrodes of the first transistors T1 of the various pixel circuits transmitted via the first power line VSS1, thereby further improving the display performance.

[0052] Optionally, in display area AA, the second power line VSS2 includes a third signal line VSS21 and a fourth signal line VSS22. The third signal line VSS21 extends along a first direction x, and the fourth signal line VSS22 extends along a second direction y. The first direction x and the second direction y intersect, and the third signal line VSS21 and the fourth signal line VSS22 are electrically connected to form a mesh-like second power line VSS2. This arrangement can reduce the resistance of the second power line VSS2. When the second power line VSS2 is connected to the second electrode of the light-emitting device D1 via the second power bus VSS0, the parallel connection resistance of the second power line VSS2, the power bus VSS0, and the second electrode of the light-emitting device D1 is further reduced relative to the resistance of the second electrode of the light-emitting device D1. This allows the voltages received by the second electrodes of the light-emitting devices D1 at different locations in the display panel to be closer, further improving display uniformity and enhancing display quality.

[0053] In some optional embodiments, the first direction x and the second direction y are perpendicular.

[0054] Optionally, the first signal line VSS11 and the third signal line VSS21 are located in the same conductive layer, which helps reduce the number of conductive layers in the display panel and simplifies the display panel manufacturing process. A gap is provided between the first signal line VSS11 and the third signal line VSS21 to ensure that the first signal line VSS11 and the third signal line VSS21 are not connected.

[0055] Optionally, the second signal line VSS12 and the fourth signal line VSS22 are located in the same conductive layer, which also helps reduce the number of conductive layers in the display panel and simplifies the display panel manufacturing process. A gap is provided between the second signal line VSS12 and the fourth signal line VSS22 to ensure that the second signal line VSS12 and the fourth signal line VSS22 are not connected.

[0056] Optionally, the first signal line VSS11 and the second signal line VSS12 are located in different conductive layers, and the third signal line VSS21 and the fourth signal line VSS22 are located in different conductive layers.

[0057] Optionally, the power supply bus VSS0 is located in at least two layers of conductive layers, and the at least two layers of conductive layers include a conductive layer in which the first power supply line VSS1 and the second power supply line VSS2 are located. In this way, the resistance of the power supply bus VSS0 itself can be small, and the transmission voltage drop of the power supply bus VSS0 can be reduced.

[0058] Figure 5 is another top view of a display panel provided by an embodiment of the present application, referring to Figure 5 Optionally, in the first non-display area NAA1, a first adapter bus VSS31 is further included, the first adapter bus VSS31 is electrically connected with the power supply bus VSS0, and the second power supply line VSS2 is electrically connected with the first adapter bus VSS31.

[0059] Specifically, in the prior art, the first adapter bus VSS31 is usually connected with a driving chip, and the driving chip provides a voltage to the second power supply line VSS2 through the first adapter bus VSS31. In this case, the second power supply line VSS2 accesses an initialization voltage output by the driving chip, and the driving force is poor. The display panel structure of the embodiment can retain the first adapter bus VSS31 of the existing display panel. Different from the prior art, the first adapter bus VSS31 is electrically connected with the power supply bus VSS0. In this way, on the one hand, the second power supply line VSS2 can access a power supply voltage through the first adapter bus VSS31 and the power supply bus VSS0, and the driving force is improved; on the other hand, the structure of the first adapter bus VSS31 in the existing display panel is fully utilized, which is conducive to simplifying the process flow.

[0060] Continuing to refer to Figure 5 Optionally, in the second non-display area NAA2, a second adapter bus VSS32 is further included, the second adapter bus VSS32 is not connected with the power supply bus VSS0, and the second power supply line VSS2 is electrically connected with the second adapter bus VSS32. In this way, the second power supply line VSS2 is not connected with the power supply bus VSS0 in the second non-display area NAA2, the influence of the transmission voltage drop caused by the second electrode of the light emitting device D1 on the voltage transmitted by the second power supply line VSS2 is reduced, and the display effect is improved.

[0061] Optionally, in the first non-display area NAA1, the orthographic projection of the first adapter bus VSS31 on the substrate is located on a side of the orthographic projection of the adapter bus on the substrate that is closer to the display area AA. This allows the length of the third signal line VSS21 of the second power line VSS2 to be relatively short, reducing the transmission voltage drop of the first power line VSS1. This also helps reduce the transmission voltage drop of the first power line VSS1 and improve the display effect.

[0062] Optionally, in the second non-display area NAA2, the orthographic projection of the second transfer bus VSS32 on the substrate is located on the side of the orthographic projection of the transfer bus on the substrate close to the display area AA; in this way, the length of the third signal line VSS21 of the second power line VSS2 can be further made relatively short, reducing the transmission voltage drop of the first power line VSS1.

[0063] Optionally, the connection direction of the first non-display area NAA1 and the second non-display area NAA2 is the second direction y, and the non-display area NAA further includes a third non-display area NAA3 and a fourth non-display area NAA4 located on both sides of the display area AA along the first direction x; in the third non-display area NAA3, a third transfer bus ( Figure 5 Not shown), the third transfer bus is not connected to the power bus VSS0, the second power line VSS2 is electrically connected to the third transfer bus; in the fourth non-display area NAA4, a fourth transfer bus ( Figure 5 (not shown in the figure), the fourth adapter bus is disconnected from the power bus VSS0, and the second power line VSS2 is electrically connected to the fourth adapter bus. This prevents the second power line VSS2 from being connected to the power bus VSS0 in the second non-display area NAA2 and the third non-display area NAA3, reducing the impact of the transmission voltage drop caused by the second electrode of the light-emitting device D1 on the voltage transmitted by the second power line VSS2, thereby improving the display quality. Furthermore, this helps reduce the transmission voltage drop of the first power line VSS1, thereby improving the display quality.

[0064] Optionally, the first transfer bus VSS31 , the second transfer bus VSS32 , the third transfer bus and the fourth transfer bus are located in the same conductive layer as the first signal line VSS11 and the third signal line VSS21 .

[0065] Continue to refer Figure 1 Optionally, the active layer 20 includes a first active layer 21, the channel region of the first transistor T1 is located in the first active layer 21, and the first active layer 21 extends along the second direction y; the conductive layer includes a first conductive layer 31, and the first conductive layer 31 is located on the side of the first active layer 21 away from the substrate 10; the gate of the first transistor T1 is located in the first conductive layer 31.

[0066] Specifically, the channel region of the first transistor T1 is located at a position where the projection of the gate of the first transistor T1 on the first active layer 21 is located. As shown in Figure 1 The first conductive layer 31 can include a first metal line J1 extending along the first direction x, and the first metal line J1 can include the gate of the first transistor T1. On the first active layer 21, the position where the first active layer 21 intersects with the first metal line J1 is the channel region of the first transistor T1.

[0067] With reference to Figure 1 Optionally, the conductive layer further includes a second conductive layer 32 located on the side of the first active layer 21 away from the substrate 10, and the third signal line VSS21 is located on the second conductive layer 32. The projection of the third signal line VSS21 on the substrate 10 overlaps with the projection of the first active layer 21 on the substrate 10, and at the overlapping position, the third signal line VSS21 is electrically connected with the first active layer 21 to realize the electrical connection between the second power supply line VSS2 and the first electrode of the first transistor T1.

[0068] Specifically, the third signal line VSS21 extends along the first direction x, and the first active layer 21 extends along the second direction y, so the third signal line VSS21 intersects with the first active layer 21. At the overlapping position of the projection of the third signal line VSS21 on the substrate 10 and the projection of the first active layer 21 on the substrate 10, that is, at the position where the third signal line VSS21 intersects with the first active layer 21, the third signal line VSS21 is electrically connected through a via hole passing through the insulating layer between them. In the above embodiment, when the first signal line VSS11 of the first power supply line VSS1 is in the same layer as the third signal line VSS21, the first signal line VSS11 is also located on the second conductive layer 32.

[0069] Optionally, the second conductive layer 32 is located on the side of the first conductive layer 31 away from the substrate 10.

[0070] With reference to Figure 1 and Figure 2 Optionally, the display panel further includes a first connection line L1, the first end of the first connection line L1 is electrically connected with the second electrode of the first transistor T1, and the second end of the first connection line L1 serves as an output node OUT1. Optionally, the display panel further includes a third conductive layer 33 located on the side of the second conductive layer 32 away from the substrate 10, and the first connection line L1 is located on the third conductive layer 33.

[0071] Specifically, the first end of the first connection line L1 can be electrically connected with the second electrode of the first transistor T1 through the insulating layers between the third conductive layer 33 and the first active layer 21, and the second end of the first connection line L1 is connected with the first electrode of the light emitting device D1 as the output node OUT1 of the pixel circuit. By arranging the first connection line L1, the connection between the second electrode of the first transistor T1 and the output node OUT1 of the pixel circuit is realized, that is, the second electrode of the first transistor T1 and the first electrode of the light emitting device D1 are connected through the first connection line L1, which is conducive to optimizing the layout of the circuit to reduce the parasitic capacitance in the circuit. Optionally, the fourth signal line and the second signal line are located in the third conductive layer.

[0072] Figure 6 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application, Figure 7 is a top view of another display panel provided by an embodiment of the present application, with reference to Figure 6 and Figure 7 The pixel circuit further includes a driving transistor T0 and a first capacitor C1, and the multi-layer conductive layer further includes a fourth conductive layer 34 and a fifth conductive layer 35. Figure 8 is a top view of the fourth conductive layer in the display panel, Figure 9 is a top view of the fourth conductive layer and the fifth conductive layer in the display panel, Figure 10 is a top view of the fourth conductive layer, the fifth conductive layer and the active layer in the display panel, Figure 11 is a top view of the fourth conductive layer, the fifth conductive layer, the active layer and the first conductive layer in the display panel, Figure 12 is a sectional view of another display panel provided by an embodiment of the present application, Figure 12 may correspond to Figure 11 obtained by cutting along BB', the fourth conductive layer 34 and the fifth conductive layer 35 are located on the side of the active layer 20 close to the substrate 10, and the fifth conductive layer 35 is located on the side of the fourth conductive layer 34 away from the substrate 10; the first plate 01 of the first capacitor C1 is located on the fourth conductive layer 34, and the second plate of the capacitor is located on the fifth conductive layer 35, and the first plate 01 of the first capacitor C1 is electrically connected with the first gate G1 of the driving transistor T0.

[0073] The first gate G1 is the bottom gate of the driving transistor T0. Among them, the fourth conductive layer 34 and the fifth conductive layer 35 are located on the side of the active layer 20 close to the substrate 10, the first plate 01 of the first capacitor C1 is located on the fourth conductive layer 34, and the second plate 02 of the first capacitor C1 is located on the fifth conductive layer 35, which can make the first capacitor C1 located below the driving transistor T0, so that the first plate 01 of the first capacitor C1 is located below the active layer 20 of the driving transistor T0, so that the first plate 01 of the first capacitor C1 can perform bottom light shielding for the driving transistor T0, which is conducive to improving the adverse effects of light on the driving transistor T0, and further improving the display effect.

[0074] In some optional embodiments, the first plate 01 of the first capacitor C1 is multiplexed as the first gate G1, which is located in the fourth conductive layer 34. In this way, the first plate located in the first conductive layer 31 can serve as the lower plate of the first capacitor C1, and the first capacitor C1 can also serve as the light shielding layer of the driving transistor T0, thereby saving layout space, improving layout space utilization, and avoiding changes in the electrical performance of the driving transistor T0 caused by light, which is conducive to improving the reliability of the pixel circuit and thus improving the reliability of the screen.

[0075] Optionally, the first plate 01 of the first capacitor C1 is electrically connected to the output node OUT1. Specifically, in the prior art, the first gate G1 is usually electrically connected to the first electrode of the driving transistor T0, but this connection method requires a jumper design to realize the connection between the active layer 20 and the fourth conductive layer 34, and the bottom gate of the driving transistor T0 and the first plate 01 of the first capacitor C1 need to be disconnected. In the present embodiment, the first plate 01 of the first capacitor C1 is electrically connected to the output node OUT1, and correspondingly, the first gate G1 of the driving transistor T0 is electrically connected to the output node OUT1, so that the bottom gate of the first transistor T1 and the first plate 01 of the first capacitor C1 do not need to be disconnected, and therefore no jumper design is required, reducing the occupation of layout space, improving the pixel density, and ensuring the uniformity of brightness.

[0076] In combination with Figures 6-12 Optionally, the active layer 20 includes a second active layer 22, which is in the same layer as the first active layer 21 corresponding to the first transistor T1 and is not connected; the channel region of the driving transistor T0 is located in the second active layer 22, and the orthographic projection of the first plate 01 of the first capacitor C1 on the substrate 10 at least covers part of the orthographic projection of the channel region of the driving transistor T0 on the substrate 10.

[0077] Specifically, the channel region of the driving transistor T0 is located at the orthographic projection position of the first gate G1 of the driving transistor T0 on the second active layer 22. The orthographic projection of the first plate 01 of the first capacitor C1 on the substrate 10 at least covers part of the orthographic projection of the channel region of the driving transistor T0 on the substrate 10, so that the first plate 01 of the first capacitor C1 can perform bottom light shielding on the channel region of the driving transistor T0, thereby at least blocking part of the light entering the channel region of the driving transistor T0, ensuring the electrical performance of the driving transistor T0, and thus being conducive to improving the display effect.

[0078] Optionally, the orthographic projection of the first plate 01 of the first capacitor C1 on the substrate 10 at least partially overlaps the orthographic projection of the second plate 02 of the first capacitor C1 on the substrate 10. The overlapping part of the first plate 01 and the second plate of the first capacitor C1 forms the effective capacitor of the first capacitor C1.

[0079] Figure 13 is a top view of another display panel provided by an embodiment of the present application, Figure 14 is a top view of yet another display panel provided by an embodiment of the present application, wherein Figure 13 and Figure 14 shows the fifth conductive layer 35, the active layer 20 and the first conductive layer 31 in the display panel, and Figure 12 shows the first type via hole K1 in the display panel in Figure 12 shows the second type via hole K2 in the display panel, and the insulating layer in the display panel through which the first type via hole K1 and the second type via hole K2 pass are different.

[0080] Referring to Figure 11 and Figure 12 Optionally, the multilayer conductive layer further comprises a first conductive layer 31, the first conductive layer 31 is located on the side of the active layer 20 away from the substrate 10; the driving transistor T0 further comprises a second gate G2, the second gate G2 is located on the first conductive layer 31, and the second gate G2 is electrically connected with the second plate.

[0081] Optionally, the second gate G2 is used as the top gate of the driving transistor T0, and the driving transistor T0 can be of a top gate driving type. Since the second gate G2 of the driving transistor T0 and the second plate are located on different conductive layers, the two can be connected through a via hole.

[0082] Optionally, the orthographic projection of the second gate G2 on the substrate 10 at least partially covers the orthographic projection of the channel region of the driving transistor T0 on the substrate 10. Optionally, the orthographic projection of the second plate 02 of the first capacitor C1 on the substrate 10 does not overlap with the orthographic projection of the second gate G2 on the substrate 10. In this way, it is beneficial to avoid that the second plate 02 of the first capacitor C1 shields the area of the first plate corresponding to the first gate G1.

[0083] Optionally, the orthographic projection of the second plate 02 of the first capacitor C1 on the substrate 10 is L-shaped.

[0084] Figure 15 is a top view of still another display panel provided by an embodiment of the present application, wherein Figure 15 shows the fifth conductive layer 35, the active layer 20, the first conductive layer 31 and the second conductive layer 32 in the display panel, Figure 16 is a cross-sectional view of another display panel, wherein Figure 16 may correspond to Figure 15 is obtained by cutting along CC', referring to Figure 15 and Figure 16Optionally, the display panel further includes a second connecting line L2, one end of the second connecting line L2 is electrically connected to the second gate G2, and the other end of the second connecting line L2 is electrically connected to the second plate O2 of the first capacitor C1.

[0085] The second connection line L2 can extend along the first direction x, one end of the second connection line L2 is connected to the second gate G2 of the driving transistor T0 through the second type via K2, and the other end of the second connection line L2 is connected to the second plate O2 of the first capacitor C1 through the first type via K1.

[0086] Continue to refer Figure 15 and Figure 16 Optionally, the multi-layer conductive layer further includes a second conductive layer 32 , the second conductive layer 32 is located on a side of the first conductive layer 31 away from the substrate 10 , and the second connecting line L2 is located in the second conductive layer 32 .

[0087] Optionally, the first type via K1 is a via connecting the second conductive layer 32 and the fourth conductive layer 34, or a via connecting the second conductive layer 32 and the fifth conductive layer 35; the second type via K2 is a via connecting the second conductive layer 32 and the active layer 20, or a via connecting the second conductive layer 32 and the first conductive layer 31.

[0088] Figure 17 is a top view of another display panel provided by an embodiment of the present invention, wherein: Figure 17 The fifth conductive layer 35, the active layer 20, the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 in the display panel are shown. Figure 17 Optionally, the display panel also includes a third power line VDD, which is electrically connected to the pixel circuit, and the driving transistor T0 is connected between the third power line VDD and the output node OUT1; the third power line VDD includes a fifth signal line VDD1, and the fifth signal line VDD1 and the second connection line L2 both extend along the second direction y, and the orthographic projection of the fifth signal line VDD1 on the substrate 10 has no overlap or partially overlaps with the orthographic projection of the second connection line L2 on the substrate 10.

[0089] Specifically, since the second connection line L2 is electrically connected with the second gate G2 of the driving transistor T0, the potential of the second connection line L2 is equal to the potential of the second gate G2 of the driving transistor T0. Since the first transistor T1 is connected with the second power supply line VSS2 and the output node OUT1 of the pixel circuit respectively, and the output node OUT1 of the pixel circuit and the second gate G2 of the driving transistor T0 are connected with the first capacitor C1, the voltage of the output node OUT1 of the pixel circuit will affect the voltage of the second gate G2 through the coupling effect of the first capacitor C1. Since there is a voltage drop when the second power supply line VSS2 transmits voltage to the first transistor T1 in the pixel circuit, the greater the overlapping area between the fifth signal line VDD1 and the second connection line L2, that is, the greater the parasitic capacitance formed by the fifth signal line VDD1 and the second connection line L2, the greater the influence of the voltage drop on the voltage transmission of the second sub power supply line VSS2 on the gate voltage of the driving transistor T0, and the worse the uniformity of the display panel. Therefore, the non-overlapping of the orthogonal projection of the fifth signal line VDD1 on the substrate 10 can make the fifth signal line VDD1 and the second connection line L2 have no overlapping area, reduce the parasitic capacitance formed by the fifth signal line VDD1 and the second connection line L2, and improve the influence of the voltage drop on the voltage transmission of the second sub power supply line VSS2 on the display uniformity, and improve the display effect. The partial overlapping of the orthogonal projection of the fifth signal line VDD1 on the substrate 10 and the orthogonal projection of the second connection line L2 on the substrate 10 makes the parasitic capacitance formed by the fifth signal line VDD1 and the second connection line L2 not too large, which also has a certain effect on improving the influence of the voltage drop on the voltage transmission of the second sub power supply line VSS2 on the display uniformity.

[0090] Figure 18 is Figure 17 the local enlarged view of the red box area in FIG. 10, referring to Figure 17 and Figure 18 Optionally, the second connection line L2 comprises a first connection part L21 and a second connection part L22, the orthogonal projection of the first connection part L21 on the substrate 10 is covered by the orthogonal projection of the fifth signal line VDD1 on the substrate; the orthogonal projection of the second connection part L22 on the substrate 10 is located outside the orthogonal projection of the fifth signal line VDD1 on the substrate.

[0091] Optionally, the display panel further comprises a data line data, the data line data extends along the second direction y, and the data line data is located on the side of the fifth signal line VDD1 away from the second connection line L2.

[0092] By setting the second connection line L2 including the first connection portion L21 and the second connection portion L22, the orthogonal projection of a part of structure (i.e. the first connection portion L21) of the second connection line L2 on the substrate is ensured to overlap with the orthogonal projection of the fifth signal line VDD1 on the substrate, so that the fifth signal line VDD1 shields the influence of the signal on the data line data on the potential of the second gate G2 of the driving transistor T0, and further ensures that the potential of the second gate G2 of the driving transistor T0 is more stable, and improves the display effect. Moreover, the orthogonal projection of another part of structure (the second connection portion L22) of the second connection line L2 on the substrate is ensured to have no overlap with the orthogonal projection of the fifth signal line VDD1 on the substrate, so that the parasitic capacitance formed between the fifth signal line VDD1 and the second connection line L2 is small, and the display uniformity is improved.

[0093] Optionally, the area of the second connection portion L22 is greater than the area of the first connection portion L21. In this way, the parasitic capacitance formed between the fifth signal line VDD1 and the second connection line L2 can be further reduced, and the display uniformity is further improved.

[0094] Optionally, the fifth signal line VDD1 includes a first structure portion VDD11 and a second structure portion VDD12, the first structure portion VDD11 is connected with the second structure portion VDD12, and the first structure portion VDD11 and the second structure portion VDD12 both extend along the second direction y, the orthogonal projection of the first structure portion VDD11 on the substrate has partial overlap with the orthogonal projection of the second connection line L2 on the substrate, the orthogonal projection of the second structure portion VDD12 on the substrate has no overlap with the orthogonal projection of the second connection line L2 on the substrate, and the width of the first structure portion VDD11 is smaller than the width of the second structure portion VDD12. Figure 17 As shown in FIG. 6, along the second direction y, the first structure portion VDD11 can be located on both sides of the second structure portion VDD12. By setting the first structure portion VDD11 to have a larger width, the resistance of the third power line VDD can be reduced, and further the transmission voltage drop of the second power voltage on the third power line VDD is reduced, which is beneficial to improve the display uniformity and improve the display effect. By setting the second structure portion VDD12 to have a smaller width, the overlapping area of the second structure portion VDD12 and the second connection line L2 can be small, and further the parasitic capacitance formed between the fifth signal line VDD1 and the second connection line L2 is reduced, which is beneficial to further improve the display uniformity and improve the display effect.

[0095] Continuing to refer to Figure 17 Optionally, the display panel further includes a third conductive layer 33, the third conductive layer 33 is located on the side of the second conductive layer 32 away from the substrate 10, and the fifth signal line VDD1 and the data line data are located on the third conductive layer 33.

[0096] Optionally, the third power supply line VDD further comprises a sixth signal line VDD2, the sixth signal line VDD2 extends along the first direction x, and the sixth signal line VDD2 is electrically connected with the fifth signal line VDD1 to form the meshed third power supply line VDD. In this way, the resistance of the third power supply line VDD can be reduced, the transmission voltage drop of the third power supply line VDD can be reduced, and the display uniformity can be improved. Optionally, the sixth signal line is located in the second conductive layer 32.

[0097] With reference to the foregoing description Figures 6-18 Optionally, the pixel circuit further comprises a second transistor T2, a gate of the second transistor T2 is located in the first conductive layer 31, and a channel region of the second transistor T2 is located in the second active layer 22; a first electrode of the second transistor T2 is electrically connected with a second electrode of the driving transistor T0, and a second electrode of the second transistor T2 is electrically connected with the second gate G2. The second transistor T2 is configured to compensate for a threshold voltage of the driving transistor T0 in response to a first scan signal.

[0098] The channel region of the second transistor T2 is located at a position of a normal projection of the gate of the second transistor T2 on the second active layer 22. Figure 15 And Figure 16 The second end of the second connection line L2 is further electrically connected with the second electrode of the second transistor T2, so as to realize the electrical connection between the second electrode of the second transistor T2 and the second gate G2 of the driving transistor T0, and the electrical connection between the first electrode of the second transistor T2 and the second electrode of the driving transistor T0 in the second active layer 22. The gate of the second transistor T2 is located in the first conductive layer 31, for example, the first metal line J1 of the first conductive layer 31 comprises the gate of the second transistor T2. On the second active layer 22, the position where the second active layer 22 intersects with the first metal line J1 is the channel region of the second transistor T2. That is, the first metal line J1 comprises the gates of the second transistor T2 and the first transistor T1, and the gate of the second transistor T2 and the gate of the first transistor T1 are connected to the same signal.

[0099] Optionally, the display panel further comprises a first scan signal line S1, the first scan signal line S1 extends along the first direction x. The first scan signal line S1 is located in the second conductive layer 32, and the first scan signal line S1 is connected with the gate of the first transistor T1 and the gate of the second transistor T2. Specifically, the first scan signal line S1 can be electrically connected with the first metal line J1 through the second type via hole, so as to provide the first scan signal to the gates of the first transistor T1 and the second transistor T2 through the first scan line. The first transistor T1 is turned on when the first scan signal is at an effective level, transmits the voltage on the second power supply line VSS2 to the output node OUT1 of the pixel circuit, and realizes the initialization of the first electrode of the light emitting device D1. The first transistor T1 is turned on when the first scan signal is at an effective level, and the threshold voltage of the driving transistor T0 is compensated.

[0100] Optionally, the first scan signal line S1 is located on the second conductive layer 32, and a projection of the first scan signal line S1 on the substrate 10 at least partially covers a projection of the gate of the first transistor T1 and the gate of the second transistor T2 on the substrate 10. In this way, the first scan signal line S1 can at least partially cover the channel region of the first transistor T1 and the channel region of the second transistor T2 from the top, reducing the influence of top light on the performance of the first transistor T1 and the second transistor T2, and improving the display effect.

[0101] Continuing to refer to Figures 6-18 Optionally, the display panel further includes an initialization signal line Vini, and a projection of the initialization signal line Vini on the substrate 10 is located on a side of a projection of the first gate G1 of the driving transistor T0 on the substrate 10 away from a projection of the first scan signal line S1 on the substrate 10. The pixel circuit further includes a second capacitor C2 and a third transistor T3, the gate of the third transistor T3 is located on the first conductive layer 31, the active layer 20 further includes a third active layer 23, the third active layer 23 extends along the second direction y, the third active layer 23 is in the same layer as the second active layer 22 and the first active layer 21 and is not connected, and the channel region of the third transistor T3 is located on the third active layer 23. The display panel further includes a data line data, and the pixel circuit further includes a fourth transistor T4, the gate of the fourth transistor T4 is located on the first conductive layer 31, and the channel region of the fourth transistor T4 is located on the third active layer 23.

[0102] The display panel further includes the initialization signal line Vini and the data line data, the first electrode of the third transistor T3 is connected to the initialization signal line Vini, and the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are connected to the first node N1. The first electrode of the fourth transistor T4 is connected to the data line data, and the second capacitor C2 is connected between the second electrode of the driving transistor T0 and the first node. Among them, the third transistor T3 is used to transmit a fixed voltage to the first node, the fourth transistor T4 is used to transmit a data voltage to the first node N1, and the second capacitor C2 is used to couple the voltage change amount of the first node to the second electrode of the driving transistor T0 and transmit it to the second gate G2 of the driving transistor T0 through the second transistor T2, so that the voltage of the second gate G2 of the driving transistor T0 is associated with the data voltage.

[0103] Optionally, the channel region of the third transistor T3 is located at a projection position of the gate of the third transistor T3 on the third active layer 23, the first electrode of the third transistor T3 is connected to the initialization signal line Vini, the second electrode of the third transistor T3 is connected to the first plate 03 of the second capacitor C2, the second plate 04 of the second capacitor C2 is electrically connected to the second electrode of the driving transistor T0; and the third transistor T3 is used to transmit an initialization voltage to the first plate 03 of the second capacitor C2.

[0104] Optionally, the third active layer 23 has an overlapping projection on the substrate 10 with the initialization signal line Vini, and the first electrode of the third transistor T3 is connected to the initialization signal line Vini at the overlapping position of the third active layer 23 and the initialization signal line Vini. Specifically, the initialization signal line Vini has an overlapping projection on the substrate 10 with the third active layer 23, and the first electrode of the third transistor T3 is connected to the initialization signal line Vini through the second type via hole K2 at the overlapping position. In this way, the first electrode of the third transistor T3 and the initialization signal line Vini do not need to be connected through a wire, which reduces the layout space of the wire and is beneficial to improving the pixel density.

[0105] Figure 19 is a cross-sectional view of another display panel provided by an embodiment of the present application, Figure 20 is a cross-sectional view of another display panel provided by an embodiment of the present application, Figure 19 may correspond to Figure 7 obtained by cutting along DD', Figure 20 may correspond to Figure 7 obtained by cutting along EE'. Optionally, the first plate 03 of the second capacitor C2 is located in the fourth conductive layer 34, the second plate 04 of the second capacitor C2 is located in the fifth conductive layer 35, and the projection of the second capacitor C2 on the substrate 10 is located on the side away from the projection of the first scan signal line S1 on the substrate 10. The display panel further includes a third connection line L3 and a fourth connection line L4. The first end of the third connection line L3 is electrically connected to the second electrode of the third transistor T3, and the second end of the third connection line L3 is electrically connected to the first plate 03 of the second capacitor C2. The first end of the fourth connection line L4 is electrically connected to the second electrode of the driving transistor T0, and the second end of the fourth connection line L4 is electrically connected to the second plate 04 of the second capacitor C2. Optionally, the third connection line L3 and the fourth connection line L4 are located in the second conductive layer 32.

[0106] The first end of the third connection line L3 can be electrically connected to the second electrode of the third transistor T3 through the second type via hole K2, and the second end of the third connection line L3 can be electrically connected to the first plate 03 of the second capacitor C2 through the first type via hole K1. The first end of the fourth connection line L4 can be electrically connected to the second electrode of the driving transistor T0 through the second type via hole K2, and the second end of the fourth connection line L4 can be electrically connected to the second plate 04 of the second capacitor C2 through the first type via hole K1.

[0107] Optionally, the display panel further comprises a first light-emitting control signal line EM1, the first light-emitting control signal line EM1 is located on the second conductive layer 32, and the first light-emitting control signal line EM1 is connected to the gate of the third transistor T3; the orthographic projection of the first light-emitting control signal line EM1 on the substrate 10 at least partially covers the orthographic projection of the third transistor T3 on the substrate 10. In this way, the first light-emitting control signal line EM1 can at least partially cover the channel region of the third transistor T3 from the top, reducing the influence of top light on the performance of the third transistor T3 and improving the display effect.

[0108] The first conductive layer 31 can include a second metal line J2, the second metal line J2 includes the gate of the third transistor T3, and the third active layer 23 is crossed by the second metal line J2. The position where the third active layer 23 is crossed by the second metal line J2 is the channel region of the third transistor T3. The first light-emitting control signal line EM1 can be connected to the second metal line J2.

[0109] Optionally, the first light-emitting control signal line EM1 extends along the first direction x, and the initialization signal line Vini extends along the first direction x; optionally, the initialization signal line Vini is at least partially located on the second conductive layer 32; optionally, the first light-emitting control signal line EM1 is located on the side of the initialization signal line Vini away from the first active layer 21. In this way, it is beneficial to optimize the positions of the transistors in the layout, reduce the occupied space of the layout, improve the space utilization of the layout, and improve the pixel density.

[0110] Optionally, the channel region of the fourth transistor T4 is located at the position of the orthographic projection of the gate of the fourth transistor T4 on the third active layer 23, the first pole of the fourth transistor T4 is connected to the data line data, and the second pole of the fourth transistor T4 is connected to the second pole of the third transistor T3 on the third active layer 23; the fourth transistor T4 is used to transmit a data voltage to the first plate 03 of the second capacitor C2, and the second capacitor C2 is used to write voltage information associated with the data voltage to the second gate G2 of the driving transistor T0.

[0111] Reference Figure 17 Optionally, the display panel further comprises a fifth connection line L5, the first end of the fifth connection line L5 is electrically connected to the data line data, and the second end of the fifth connection line L5 is electrically connected to the first pole of the fourth transistor T4. Optionally, the fifth connection line L5 is located on the second conductive layer 32.

[0112] Specifically, the display panel further comprises a third type of via K3, the third type of via K3 is a via connecting the second conductive layer 32 and the third conductive layer 33. The first end of the fifth connection line L5 is electrically connected to the data line data through the third type of via K3, and the second end of the fifth connection line L5 is electrically connected to the first pole of the fourth transistor T4 through the second type of via K2.

[0113] Optionally, the display panel further comprises a second scan signal line S2, the second scan signal line S2 is located on the second conductive layer 32, and the second scan signal line S2 is connected to the gate of the fourth transistor T4; the orthographic projection of the second scan signal line S2 on the substrate 10 at least partially covers the orthographic projection of the fourth transistor T4 on the substrate 10; optionally, the second scan signal line S2 extends along the first direction x. In this way, the second scan signal line S2 can at least partially cover the channel region of the fourth transistor T4 from the top, reducing the impact of top light on the performance of the fourth transistor T4, and improving the display effect.

[0114] Continuing to refer to Figure 17 The first conductive layer 31 can include a third metal line J3, the third metal line J3 includes the gate of the fourth transistor T4, and the third active layer 23 is crossed by the third metal line J3 at the position of the channel region of the fourth transistor T4. The second scan signal line S2 can be electrically connected to the third metal line J3 through the second type of via hole K2, and then provide the second scan signal to the gate of the fourth transistor T4 through the second scan signal line S2. The fourth transistor T4 is turned on when the second scan signal is at an effective level, and transmits the data voltage to the first plate 03 of the second capacitor C2.

[0115] Optionally, the orthographic projection of the first emission control signal line EM1 on the substrate is located between the orthographic projection of the initialization signal line Vini on the substrate and the orthographic projection of the second scan signal line S2 on the substrate. Optionally, along the second direction y, the first emission control signal line EM1, the second scan signal line S2 and the initialization signal line Vini are located on the same side of the first active layer 21. In this way, it is beneficial to optimize the position of each transistor in the layout, reduce the occupied space of the layout, improve the space utilization of the layout, and improve the pixel density.

[0116] Optionally, the pixel circuit further comprises a fifth transistor T5, the gate of the fifth transistor T5 is located on the first conductive layer 31, and the channel region of the fifth transistor T5 is located on the second active layer 22. The first pole of the fifth transistor T5 is connected to the output node OUT1, and the second pole of the fifth transistor T5 is connected to the second power supply line VSS2. The fifth transistor T5 is used to initialize the light emitting device D1 within a frame to realize low-frequency driving.

[0117] Specifically, the channel region of the fifth transistor T5 is located at a position where the projection of the gate of the fifth transistor T5 on the second active layer 22 is located, and the gate of the fifth transistor T5 is connected to the second scan signal line S2. The third metal line J3 further includes the gate of the fifth transistor T5, and the position where the second active layer 22 crosses the third metal line J3 is the channel region of the fifth transistor T5. The second scan signal line S2 can be electrically connected to the third metal line J3 through the second type of via hole K2, and then the second scan signal line S2 provides the second scan signal to the gate of the fifth transistor T5, and the fifth transistor T5 is turned on when the second scan signal is at an effective level, and the voltage on the second power supply line VSS2 is transmitted to the output node OUT1, and the first electrode of the light emitting device D1 is initialized in the holding frame.

[0118] Optionally, the projection of the second scan signal line S2 on the substrate 10 at least partially covers the projection of the gate of the fifth transistor T5 on the substrate 10. In this way, the second scan signal line S2 can at least partially cover the channel region of the channel region of the fifth transistor T5 from the top, reducing the influence of top light on the performance of the fifth transistor T5 and improving the display effect.

[0119] Optionally, the pixel circuit further includes a sixth transistor T6 and a seventh transistor T7, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both located in the first conductive layer 31, and the channel region of the sixth transistor T6 and the channel region of the seventh transistor T7 are located in the second active layer 22. The first electrode of the sixth transistor T6 is connected to the third power supply line VDD, and the second electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T0; the first electrode of the seventh transistor T7 is connected to the first electrode of the driving transistor T0, and the second electrode of the seventh transistor T7 is electrically connected to the output node OUT1.

[0120] Optionally, the projection of the third power supply line VDD on the substrate 10 overlaps the projection of the second active layer 22 on the substrate 10, and at the overlapping position, the third power supply line VDD is electrically connected to the first electrode of the sixth transistor T6; in this way, the third power supply line VDD and the first electrode of the sixth transistor T6 do not need to be connected across the line, reducing the layout space occupied by the corresponding line crossing, which is beneficial to improve the pixel density. The second electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor T0 in the second active layer 22.

[0121] Optionally, the display panel further comprises a second light-emitting control signal line EM2 extending along the first direction x, and a projection of the first light-emitting control signal line EM1 on the substrate 10 and a projection of the second light-emitting control signal line EM2 on the substrate 10 are located on two sides of a projection of the first active layer 21 on the substrate 10, respectively. Optionally, the projection of the second light-emitting control signal line EM2 on the substrate 10 is located on a side away from a projection of the first scan signal line S1 on the substrate 10 relative to a projection of the third signal line VSS21 of the second power supply line 2VSS on the substrate 10. In this way, the positions of the transistors in the layout can be optimized, the layout occupation space can be reduced, the layout space utilization rate can be improved, and the pixel density can be improved.

[0122] Optionally, a gate of the sixth transistor T6 is connected to the second light-emitting control signal line EM2, and a gate of the seventh transistor T7 is connected to the first light-emitting control signal line EM1.

[0123] Specifically, the first conductive layer 31 further comprises a fourth metal line J4, and the fourth metal line J4 comprises a gate of the sixth transistor T6. On the first active layer 21, a position where the first active layer 21 intersects with the fourth metal line J4 is a channel region of the sixth transistor T6. The second light-emitting control signal line EM2 can be electrically connected to the fourth metal line J4 through a second type of via hole K2, so as to provide a second light-emitting control signal to the gate of the sixth transistor T6 through the second light-emitting control signal line EM2. The sixth transistor T6 is turned on when the second light-emitting control signal is at an effective level, and transmits the second power supply voltage to the second electrode of the driving transistor T0. The second metal line J2 further comprises a gate of the seventh transistor T7. On the second active layer 22, a position where the second active layer 22 intersects with the second metal line J2 is a channel region of the seventh transistor T7.

[0124] Optionally, the fourth conductive layer 34 further comprises a first light-blocking layer Z1, and the first light-blocking layer Z1 is multiplexed as a first plate 01 of the first capacitor C1. A projection of the first light-blocking layer Z1 on the substrate 10 at least partially covers a projection of a channel region of the driving transistor T0 on the substrate 10. In this way, the first light-blocking layer Z1 can perform bottom light blocking on the channel region of the driving transistor T0, and improve the influence of light on the electrical performance of the driving transistor T0.

[0125] Optionally, the fourth conductive layer 34 further comprises a second light-blocking layer Z2, and the second light-blocking layer Z2 is not connected to the first light-blocking layer Z1. A projection of the second light-blocking layer Z2 on the substrate 10 at least partially covers projections of channel regions of the first transistor T1, the second transistor T2, and the sixth transistor T6 on the substrate 10. In this way, the second light-blocking layer Z2 can perform bottom light blocking on the channel regions of the first transistor T1, the second transistor T2, and the sixth transistor T6, and improve the influence of light on the electrical performance of the driving transistor T0.

[0126] Optionally, the fourth conductive layer 34 further comprises a third light shielding layer Z3, the third light shielding layer Z3 is not connected with the first light shielding layer Z1 and the second light shielding layer Z2, and a projection of the third light shielding layer Z3 on the substrate 10 at least partially covers projections of channel regions of the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 on the substrate 10. In this way, the third light shielding layer Z3 can shield the channel regions of the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 from the bottom, thereby improving the influence of light on the electrical performance of the driving transistor T0.

[0127] Optionally, along the first direction x, the third light shielding layer Z3, the first plate 03 of the second capacitor C2, the first light shielding layer Z1 and the second light shielding layer Z2 are arranged in sequence.

[0128] Figure 21 is a partial enlarged view of an embodiment of the present application, with reference to Figure 21 Optionally, a projection of the first electrode M1 of the light emitting device on the substrate covers channel regions of at least some transistors in the pixel circuit. Among them Figure 20 Exemplarily, a projection of the first electrode M1 of the light emitting device on the substrate covers channel regions of the driving transistor T0, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 in the pixel circuit. In this way, the anode of the light emitting device can shield the transistors from the top, thereby further improving the influence of light on the performance of the transistors.

[0129] Figure 22 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application, in combination with Figure 6 and Figure 22 The working process of the pixel circuit includes an initialization and threshold voltage compensation phase, a data writing phase and a light emitting phase. Optionally, each transistor in the pixel circuit is an N-type transistor, which can be an oxide transistor, for example, an indium gallium zinc oxide transistor.

[0130] In the initialization and threshold voltage compensation phase t1, the first scan signal on the first scan signal line S1 is high, the first transistor T1 and the second transistor T2 are turned on, and the voltage on the second power supply line VSS2 is transmitted to the first plate of the first capacitor C1 through the first transistor. The first light emitting control signal on the first light emitting control signal line EM1 is high, the third transistor T3 and the seventh transistor T7 are turned on, and the initialization voltage Vini is transmitted to the first node N1 through the third transistor T3. The second gate G2 of the driving transistor T0 is discharged to the second power supply line VSS2 through the second transistor T2, the driving transistor T0 and the first transistor T1, and in this phase, the initialization of the first electrode of the light emitting device D1 and the threshold voltage compensation of the driving transistor T0 are realized.

[0131] In the data writing stage t2, the first scan signal on the first scan signal line S1 and the second scan signal on the second scan signal line S2 are high level signals, the first transistor T1 and the second transistor T2 are turned on, the fourth transistor T4 and the fifth transistor T5 are turned on, the data voltage on the data line data is transmitted to the first node N1 through the fourth transistor T4, and the second capacitor C2 couples the change amount of the data voltage relative to the initialization voltage to the second gate G2 of the driving transistor T0 through the second transistor T2.

[0132] In the light emitting stage t3, the signals on the first light emitting control signal line EM1 and the second light emitting control signal line EM2 are high level signals, the sixth transistor T6 and the seventh transistor T7 are turned on, and the driving transistor T0 drives the light emitting device D1 to emit light.

[0133] It can be known from the analysis of the working process of the pixel circuit that the voltage on the first power supply line VSS1 not only affects the initialization of the first electrode of the light emitting device D1, but also affects the threshold voltage compensation of the driving transistor T0. In the above embodiment of the present application, Figure 4 and Figure 5 The display panel structure shown in the above embodiment of the present application is provided with the first power supply line VSS1 and the second power supply line VSS2 which are not connected at the position of the first non-display area NAA1, so that the voltage on the second power supply line is less affected by the voltage drop caused by the second electrode of the light emitting device, the voltage provided by the first transistor to the first electrode of the light emitting device in the pixel circuit at different positions in the display panel is more close, the difference in the threshold voltage compensation of different pixel circuits in the display panel can be reduced, the display uniformity is further improved, and the display effect is further improved.

[0134] The display device 200 provided by the embodiment of the present application is shown in FIG. 8. Figure 23 is a structural schematic diagram of a display device provided by the embodiment of the present application, referring to Figure 23 The display device 200 includes the display panel of any of the above embodiments of the present application. The display device can be a mobile phone, or any electronic product with display function, including but not limited to the following categories: display panel in products such as television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc., which are not specially limited in the embodiment of the present application.

[0135] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, in sequence or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0136] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can be made to the detailed description. Any modification, equivalent replacement and improvement etc. made within the spirit and principle of the application shall be included in the scope of the application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; an active layer and a plurality of conductive layers stacked on one side of the substrate, the active layer being located on the side of at least one of the conductive layers away from the substrate; a plurality of pixel circuits formed in the active layer and the plurality of conductive layers; a light emitting device, a first electrode of the light emitting device being electrically connected to an output node of the pixel circuit, a second electrode of the light emitting device being electrically connected to a first power line, the first power line being located in at least one of the conductive layers; wherein the pixel circuit further comprises a first transistor, a first electrode of the first transistor being electrically connected to a second power line, a second electrode of the first transistor being electrically connected to the output node; the first power line and the second power line being connected to the same voltage signal.

2. The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area; in the non-display area, the first power line and the second power line are electrically connected; in the display area, the first power line and the second power line are not connected; in the non-display area, the first power line is electrically connected to the second electrode; in the display area, the second power line is electrically connected to the second electrode of the first transistor; Preferably, the display panel further comprises a power bus, the power bus being arranged around the display area, the first power line being electrically connected to the power bus on at least two sides of the display area, the second power line being electrically connected to the power bus on one side of the display area; Preferably, the non-display area comprises a first non-display area, the first non-display area being located on one side of the display area, in the first non-display area, the first power line and the second power line are respectively electrically connected to the power bus; Preferably, the non-display area comprises a second non-display area away from the first non-display area, in the second non-display area, the first power line is electrically connected to the power bus, and the second power line is not electrically connected to the power bus; Preferably, in the display area, the first power line comprises a first signal line and a second signal line, the first signal line extending in a first direction, the second signal line extending in a second direction, the first direction intersecting the second direction, the first signal line and the second signal line being electrically connected to form a mesh-shaped first power line; Preferably, in the display area, the second power line comprises a third signal line and a fourth signal line, the third signal line extending in a first direction, the fourth signal line extending in a second direction, the first direction intersecting the second direction, the third signal line and the fourth signal line being electrically connected to form a mesh-shaped second power line; Preferably, the first signal line and the third signal line are located in the same conductive layer; Preferably, the second signal line and the fourth signal line are located in the same conductive layer; Preferably, the first signal line and the second signal line are located in different conductive layers, and the third signal line and the fourth signal line are located in different conductive layers; Preferably, the power bus is located in at least two conductive layers, the at least two conductive layers comprising the conductive layers in which the first power line and the second power line are located. Preferably, the power bus in the first non-display area is electrically connected with a power chip.

3. The display panel of claim 2, wherein, In the first non-display area, a first adapter bus is further included, the first adapter bus is electrically connected with the power bus, and the second power line is electrically connected with the first adapter bus. Preferably, in the second non-display area, a second adapter bus is further included, the second adapter bus is not connected with the power bus. The second power line is electrically connected with the second adapter bus. Preferably, in the first non-display area, the orthographic projection of the first adapter bus on the substrate is located on the side of the orthographic projection of the adapter bus on the substrate close to the display area. Preferably, in the second non-display area, the orthographic projection of the second adapter bus on the substrate is located on the side of the orthographic projection of the adapter bus on the substrate close to the display area. Preferably, the connection direction of the first non-display area and the second non-display area is the second direction, and the non-display area further includes a third non-display area and a fourth non-display area located on both sides of the display area along the first direction; in the third non-display area, a third adapter bus is further included, the third adapter bus is not connected with the power bus, and the second power line is electrically connected with the third adapter bus. In the fourth non-display area, a fourth adapter bus is further included, the fourth adapter bus is not connected with the power bus, and the second power line is electrically connected with the fourth adapter bus. Preferably, the first adapter bus, the second adapter bus, the third adapter bus and the fourth adapter bus are located in the same conductive layer with the first signal line and the third signal line.

4. The display panel of claim 2, wherein, The active layer includes a first active layer, the channel region of the first transistor is located in the first active layer, and the first active layer extends along the second direction; the conductive layer includes a first conductive layer, the first conductive layer is located on the side of the first active layer away from the substrate; the gate of the first transistor is located in the first conductive layer; Preferably, the conductive layer further includes a second conductive layer, the second conductive layer is located on the side of the first active layer away from the substrate; the third signal line is located in the second conductive layer, the orthographic projection of the third signal line on the substrate overlaps with the orthographic projection of the first active layer on the substrate, and in the overlapping position, the third signal line is electrically connected with the first active layer to realize the electrical connection between the second power line and the first pole of the first transistor; Preferably, the second conductive layer is located on the side of the first conductive layer away from the substrate. Preferably, the display panel further includes a first connection line, the first end of the first connection line is electrically connected with the second pole of the first transistor, and the second end of the first connection line serves as the output node. Preferably, the display panel further includes a third conductive layer, the third conductive layer is located on the side of the second conductive layer away from the substrate, and the first connection line is located in the third conductive layer. Preferably, the fourth signal line and the second signal line are located in the third conductive layer.

5. The display panel according to any one of claims 1-4, characterized in that, The pixel circuit further comprises a driving transistor and a first capacitor, the multi-layer conductive layer further comprises a fourth conductive layer and a fifth conductive layer, the fourth conductive layer and the fifth conductive layer are both located on the side of the active layer close to the substrate, and the fifth conductive layer is located on the side of the fourth conductive layer away from the substrate; the first plate of the first capacitor is located on the fourth conductive layer, the second plate of the capacitor is located on the fifth conductive layer, and the first plate of the first capacitor is electrically connected with the first gate of the driving transistor; Preferably, the first gate is located on the fourth conductive layer, and the first plate of the first capacitor is multiplexed as the first gate; Preferably, the active layer comprises a second active layer, the second active layer is in the same layer as the first active layer corresponding to the first transistor and is not connected; the channel region of the driving transistor is located on the second active layer, and the orthographic projection of the first plate of the first capacitor on the substrate at least covers part of the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor on the substrate; Preferably, the first plate of the first capacitor is connected with the output node.

6. The display panel of claim 5, wherein, The multi-layer conductive layer further comprises a first conductive layer, the first conductive layer is located on the side of the active layer away from the substrate; the driving transistor further comprises a second gate, the second gate is located on the first conductive layer, and the second gate is electrically connected with the second plate; Preferably, the orthographic projection of the second gate on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the second plate of the first capacitor on the substrate does not overlap with the orthographic projection of the second gate on the substrate; Preferably, the orthographic projection of the second plate of the first capacitor on the substrate is L-shaped; Preferably, the display panel further comprises a second connection line, a first end of the second connection line is electrically connected with the second gate, and a second end of the second connection line is electrically connected with the second plate of the first capacitor; Preferably, the multi-layer conductive layer further comprises a second conductive layer, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the second connection line is located on the second conductive layer.

7. The display panel of claim 6, wherein, Further comprising a third power line, the third power line is electrically connected with the pixel circuit, and the driving transistor is connected between the third power line and the output node; The third power line comprises a fifth signal line, the fifth signal line and the second connection line both extend along a second direction, and the orthographic projection of the fifth signal line on the substrate does not overlap or partially overlaps with the orthographic projection of the second connection line on the substrate; Preferably, the second connection line comprises a first connection part and a second connection part, the orthographic projection of the first connection part on the substrate is covered by the orthographic projection of the fifth signal line on the substrate; and the orthographic projection of the second connection part on the substrate is located outside the orthographic projection of the fifth signal line on the substrate. Preferably, the second connecting part has an area greater than that of the first connecting part; Preferably, the display panel further comprises a data line extending along the second direction, the data line being located on a side of the fifth signal line away from the second connecting line; Preferably, the fifth signal line comprises a first structure part and a second structure part, the first structure part is connected with the second structure part, and the first structure part and the second structure part both extend along the second direction, a projection of the first structure part on the substrate partially overlaps with a projection of the second connecting line on the substrate, a projection of the second structure part on the substrate does not overlap with the projection of the second connecting line on the substrate, and a width of the first structure part is less than a width of the second structure part; Preferably, the display panel further comprises a third conductive layer, the third conductive layer being located on a side of the second conductive layer away from the substrate, the fifth signal line and the data line being located on the third conductive layer; Preferably, the third power supply line further comprises a sixth signal line extending along the first direction, the sixth signal line being electrically connected with the fifth signal line to form a mesh-shaped third power supply line; Preferably, the sixth signal line is located on the second conductive layer.

8. The display panel of claim 6, wherein, The pixel circuit further comprises a second transistor, a gate of the second transistor being located on the first conductive layer, and a channel region of the second transistor being located on the second active layer; a first electrode of the second transistor is electrically connected with a second electrode of the driving transistor, and a second electrode of the second transistor is electrically connected with the second gate; Preferably, the channel region of the second transistor is located at a position of a projection of the gate of the second transistor on the second active layer; a second end of the second connecting line is further electrically connected with the second electrode of the second transistor, and the first electrode of the second transistor is electrically connected with the second electrode of the driving transistor in the second active layer; Preferably, the second transistor is used for compensating a threshold voltage of the driving transistor; Preferably, the display panel further comprises a first scan signal line, the first scan signal line being located on the second conductive layer, and the first scan signal line being connected with the gate of the first transistor and the gate of the second transistor; Preferably, the first scan signal line extends along the first direction; Preferably, a projection of the first scan signal line on the substrate at least partially covers projections of the gate of the first transistor and the gate of the second transistor on the substrate; Preferably, the display panel further comprises an initialization signal line, a projection of the initialization signal line on the substrate being located on a side of a projection of the first gate of the driving transistor on the substrate away from a projection of the first scan signal line on the substrate. Preferably, the pixel circuit further comprises a second capacitor and a third transistor, a gate electrode of the third transistor is located on the first conductive layer, the active layer further comprises a third active layer, the third active layer extends along the second direction, the third active layer is in the same layer and not connected with the second active layer and the first active layer, and a channel region of the third transistor is located on the third active layer. Preferably, the channel region of the third transistor is located at a position where the gate electrode of the third transistor is orthographically projected on the third active layer, a first electrode of the third transistor is connected with the initialization signal line, a second electrode of the third transistor is connected with a first plate of the second capacitor, and a second plate of the second capacitor is electrically connected with the second electrode of the driving transistor; and the third transistor is used for transmitting an initialization voltage to the first plate of the second capacitor. Preferably, the first plate of the second capacitor is located on the fourth conductive layer, the second plate of the second capacitor is located on the fifth conductive layer, and an orthographic projection of the second capacitor on the substrate is located on a side of an orthographic projection of the first capacitor on the substrate away from an orthographic projection of the first scan signal line on the substrate. Preferably, the display panel further comprises a third connection line and a fourth connection line, a first end of the third connection line is electrically connected with the second electrode of the third transistor, and a second end of the third connection line is electrically connected with the first plate of the second capacitor; a first end of the fourth connection line is electrically connected with the second electrode of the driving transistor, and a second end of the fourth connection line is electrically connected with the second plate of the second capacitor. Preferably, the third connection line and the fourth connection line are located on the second conductive layer. Preferably, an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the initialization signal line on the substrate. Preferably, at a position where the third active layer intersects with the initialization signal line, the first electrode of the third transistor is connected with the initialization signal line. Preferably, the display panel further comprises a first light-emitting control signal line, the first light-emitting control signal line is located on the second conductive layer, and the first light-emitting control signal line is connected with the gate electrode of the third transistor. An orthographic projection of the first light-emitting control signal line on the substrate at least partially covers an orthographic projection of the third transistor on the substrate. Preferably, the first light-emitting control signal line extends along the first direction, and the initialization signal line extends along the first direction. Preferably, the initialization signal line is at least partially located on the second conductive layer. Preferably, the first light-emitting control signal line is located on a side of the initialization signal line away from the first active layer. Preferably, the display panel further comprises a data line, and the pixel circuit further comprises a fourth transistor, a gate electrode of the fourth transistor is located on the first conductive layer, and a channel region of the fourth transistor is located on the third active layer. Preferably, the channel region of the fourth transistor is located at the position where the gate of the fourth transistor is projected onto the third active layer, the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the second electrode of the third transistor; the fourth transistor is configured to transmit a data voltage to the first plate of the second capacitor, and the second capacitor is configured to write voltage information associated with the data voltage to the second gate of the driving transistor; Preferably, the display panel further comprises a fifth connection line, a first end of the fifth connection line is electrically connected to the data line, and a second end of the fifth connection line is electrically connected to the first electrode of the fourth transistor; Preferably, the fifth connection line is located in the second conductive layer; Preferably, the display panel further comprises a second scan signal line, the second scan signal line is located in the second conductive layer, and the second scan signal line is connected to the gate of the fourth transistor; the second scan signal line is at least partially overlapped with the fourth transistor on the substrate; Preferably, the second scan signal line extends along the first direction; Preferably, the first light-emitting control signal line is located between the initialization signal line and the second scan signal line on the substrate; Preferably, along the second direction, the first light-emitting control signal line, the second scan signal line, and the initialization signal line are located on the same side of the first active layer; The pixel circuit further comprises a fifth transistor, the gate of the fifth transistor is located in the first conductive layer, and the channel region of the fifth transistor is located in the second active layer; Preferably, the channel region of the fifth transistor is located at the position where the gate of the fifth transistor is projected onto the second active layer, the first electrode of the fifth transistor is connected to the output node, the second electrode of the fifth transistor is connected to the second power supply line, and the gate of the fifth transistor is connected to the second scan signal line; Preferably, the second scan signal line is at least partially overlapped with the gate of the fifth transistor on the substrate; Preferably, the pixel circuit further comprises a sixth transistor and a seventh transistor, the gate of the sixth transistor and the gate of the seventh transistor are both located in the first conductive layer, and the channel region of the sixth transistor and the channel region of the seventh transistor are both located in the second active layer; Preferably, the first electrode of the sixth transistor is connected to a third power supply line, the second electrode of the sixth transistor is connected to the second electrode of the driving transistor, the first electrode of the seventh transistor is connected to the first electrode of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the output node; Preferably, a projection of the third power line on the substrate overlaps with a projection of the second active layer on the substrate, and the third power line is electrically connected with the first electrode of the sixth transistor at the overlapping position; the second electrode of the sixth transistor is electrically connected with the second electrode of the driving transistor in the second active layer; Preferably, the display panel further comprises a second light-emitting control signal line extending along the first direction, and a projection of the first light-emitting control signal line on the substrate and a projection of the second light-emitting control signal line on the substrate are respectively located on two sides of a projection of the first active layer on the substrate; Preferably, a projection of the second light-emitting control signal line on the substrate is located on a side of a projection of the third signal line of the second power line on the substrate away from a projection of the first scan signal line on the substrate; Preferably, a gate of the sixth transistor is connected with the second light-emitting control signal line, and a gate of the seventh transistor is connected with the first light-emitting control signal line; Preferably, a projection of the first electrode of the light-emitting device on the substrate covers at least part of a channel region of a transistor in the pixel circuit; Preferably, a projection of the first electrode of the light-emitting device on the substrate covers channel regions of the driving transistor, the third transistor, the fourth transistor, the fifth transistor and the seventh transistor in the pixel circuit.

9. The display panel of claim 8, wherein, The fourth conductive layer further comprises a first light-blocking layer, the first light-blocking layer is multiplexed as a first electrode plate of the first capacitor, and a projection of the first light-blocking layer on the substrate at least partially covers a projection of a channel region of the driving transistor on the substrate; Preferably, the fourth conductive layer further comprises a second light-blocking layer, the second light-blocking layer is not connected with the first light-blocking layer, and a projection of the second light-blocking layer on the substrate at least partially covers projections of channel regions of the first transistor, the second transistor and the sixth transistor on the substrate; Preferably, the fourth conductive layer further comprises a third light-blocking layer, the third light-blocking layer is not connected with the first light-blocking layer and the second light-blocking layer, and a projection of the third light-blocking layer on the substrate at least partially covers projections of channel regions of the third transistor, the fourth transistor, the fifth transistor and the seventh transistor on the substrate; Preferably, along the first direction, the third light-blocking layer, the first electrode plate of the second capacitor, the first light-blocking layer and the second light-blocking layer are arranged in sequence.

10. A display device comprising: The display panel of any one of claims 1-9. The display panel of any one of claims 1-9.

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