Method and system for rapidly testing sampling synchronism of large digital array system

Abstract

The embodiment of the invention provides a method and a system for rapidly testing the sampling synchronism of a large-scale digital array system, which can solve the technical problem that a tested system with a large-channel-number characteristic cannot be judged in related technologies. The method comprises the steps of obtaining a judgment threshold based on a test signal bandwidth and a sampling rate; under the condition of receiving a broadband test signal, completing sampling of each channel and recording data to obtain a collection data set of each channel; confirming the lowest frequency and the highest frequency in the collected data set of each channel; obtaining the lowest frequency point phase and the highest frequency point phase of each channel; determining the lowest phase difference and the highest phase difference between other channels except the reference channel and the reference channel; further obtaining a channel frequency phase difference of each channel; and obtaining a synchronous detection result through a preset condition according to the channel frequency phase difference and the judgment threshold. The method is extremely high in testing efficiency for a large digital array system with thousands of sampling channels or even tens of thousands of sampling channels.

Description

Technical Field

[0001] This application relates to the field of digital array testing technology, and in particular to a rapid testing method and system for the sampling synchronization of a large digital array system. Background Technology

[0002] A digital array system (DAS) is a phased array system based on a fully digital architecture. Its core feature is that each antenna element (or subarray) is directly connected to an independent digital transceiver unit (TRM) at its back end, enabling spatial signal processing through digital beamforming (DBF) algorithms. Compared to traditional analog arrays, DAS offers significant advantages in beam flexibility, multi-target processing capabilities, and system reconfigurability. To achieve high-gain channel synthesis, synchronization testing of all sampling channels in the DAS is essential. The A / D converter is the core device under test for synchronization testing of the DAS, as the physical characteristics of its clock network determine the synchronization performance of the sampling channels.

[0003] Currently, when the number of sampling channels in the system under test is small, an oscilloscope can be used for inspection. First, hardware connections are established. A homogeneous OCXO crystal oscillator is used to distribute the sampling clock to all A / D devices via a passive power divider. Simultaneously, a 100MHz sine wave test signal is generated by a low-phase-noise signal source and injected into the input terminals of each sampling channel via the power divider. The oscilloscope is directly connected to the digital output bus of the A / D devices through a high-bandwidth differential probe, and the ADC master clock is set as an external trigger source. A high-resolution acquisition mode is set to capture waveforms of more than 10 signal cycles. In the data processing stage, using channel 1 as a reference, cross-correlation calculations are performed on the other channels to calculate the time deviation, convert the actual offset value, and finally determine the synchronization.

[0004] However, when the number of sampling channels of the system under test reaches thousands or even tens of thousands, the workload of testing will be enormous, making it impossible to operate. Summary of the Invention

[0005] This application provides a method and system for rapid testing of sampling synchronization in a large digital array system, which can solve the technical problem in related technologies of being unable to determine the number of channels in a tested system.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a method for rapid testing of sampling synchronization in a large digital array system. This method includes: obtaining a decision threshold based on the test signal bandwidth and sampling rate; sampling and recording data for each channel while receiving a broadband test signal to obtain a dataset for each channel; the bandwidth of the broadband test signal is the same as the test signal bandwidth, and the broadband test signal satisfies the operating frequency band condition and spacing condition; confirming the lowest and highest frequencies in the dataset for each channel; obtaining the lowest frequency phase of each channel based on the sampling data corresponding to the lowest frequency of each channel; obtaining the highest frequency phase of each channel based on the sampling data corresponding to the highest frequency of each channel; confirming the lowest phase difference between the lowest frequency phase of each channel other than the reference channel and the lowest frequency phase of the reference channel; confirming the highest phase difference between the highest frequency phase of each channel other than the reference channel and the highest frequency phase of the reference channel; the reference channel is any one of all channels; obtaining the channel frequency phase difference of each channel based on the lowest phase difference and the highest phase difference of each channel; and obtaining a synchronization detection result based on preset conditions according to the channel frequency phase difference and the decision threshold.

[0008] Based on the above description of the rapid testing method for sampling synchronization of a large digital array system provided in this application embodiment, it can be seen that the rapid testing method for sampling synchronization of a large digital array system includes first setting a decision threshold based on the system's operating bandwidth and sampling rate, then injecting a broadband test signal into all channels to synchronously trigger the acquisition and storage of datasets from tens of thousands of channels. In the data processing stage, the frequency domain boundary values ​​of each channel's dataset are automatically extracted, and the minimum and maximum phase differences between the reference channel and the target channel are obtained through analysis, thereby calculating the channel frequency phase difference. Finally, the test results are output in batches based on preset conditions. This scheme reduces the time complexity of the traditional oscilloscope method and requires only a single signal source and distributed acquisition nodes, significantly reducing the maintenance cost of large digital arrays. This testing method is simple and fast, and its testing efficiency is extremely high, especially for large digital array systems with thousands or even tens of thousands of sampling channels, making it highly valuable for engineering applications.

[0009] In the feasible implementation of the first aspect, the formula for calculating the decision threshold includes:

[0010] η = 360 * B / S;

[0011] Where η represents the decision threshold in °; B represents the test signal bandwidth in GHz; and S represents the sampling rate in Gsps.

[0012] In the feasible implementation of the first aspect, the broadband test signal is emitted by a radiation source system consisting of a signal source, an RF cable, and a standard horn; the spacing condition includes the far-field condition; the calculation formula for the far-field condition includes:

[0013]

[0014] Where d represents the distance between the system under test and the radiation source system; D represents the diameter of the system under test; λ represents the wavelength of the test waveform, and its relationship with the operating frequency f is: c represents the speed of light.

[0015] In the feasible implementation of the first aspect, the operating frequency band condition includes that the operating frequency band of the system under test can cover [f0-B / 2, f0+B / 2]; where f0 represents the center frequency and B represents the test signal bandwidth.

[0016] In the feasible implementation of the first aspect, the formula for calculating the spacing condition also includes:

[0017] d>2D 2 (f0+B / 2) / c;

[0018] Where c represents the speed of light; D represents the diameter of the system under test; f0 represents the center frequency; and B represents the bandwidth of the test signal.

[0019] In the feasible implementation of the first aspect, the lowest frequency is I. n_1 +j*Q n_1 n = 1, 2, ..., N; the highest frequency is I n_2 +j*Q n_2 n = 1, 2, ..., N; the lowest frequency phase is The highest frequency point phase is Where N represents the number of sampling channels of the system under test; I n_1 Q represents the real part of the sampled signal at the lowest frequency point corresponding to the nth channel; n_1 I represents the imaginary part of the sampled signal at the lowest frequency point corresponding to the nth channel; n_2 Q represents the real part of the sampled signal at the highest frequency point corresponding to the nth channel; n_2 This represents the imaginary part of the sampled signal at the highest frequency point corresponding to the nth channel.

[0020] In the feasible implementation of the first aspect, the channel frequency phase difference is n = 2, 3, ..., N; where N represents the number of sampling channels of the system under test; Δθ n_2 Represented as the highest phase difference; Δθ n_2 This is represented as the lowest phase difference.

[0021] In the feasible implementation of the first aspect, if the channel frequency phase difference of the target channel is less than the decision threshold, it is determined that the target channel and the reference channel are sampled synchronously; the target channel is any channel among all channels except the reference channel; if the channel frequency phase difference of the target channel is greater than the decision threshold, it is determined that the target channel and the reference channel are sampled asynchronously; if all target channels and the reference channel are synchronized, the synchronization detection result is that the sampling synchronization of the entire system is normal.

[0022] Secondly, embodiments of this application provide a rapid testing system for the sampling synchronization of a large digital array system. The rapid testing system for the sampling synchronization of a large digital array system includes: at least one processor; a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method provided in the first aspect.

[0023] First, a decision threshold is set based on the system's operating bandwidth and sampling rate. Then, a broadband test signal is injected into all channels, simultaneously triggering the acquisition and storage of datasets from tens of thousands of channels. During the data processing phase, the frequency domain boundary values ​​of each channel's dataset are automatically extracted. By analysis, the minimum and maximum phase differences between the reference and target channels are obtained, and the channel frequency phase differences are calculated. Finally, the test results are output in batches based on preset conditions. This scheme reduces the time complexity of the traditional oscilloscope method and requires only a single signal source and distributed acquisition nodes, significantly reducing the maintenance cost of large digital array systems. This testing method is simple and fast, and its testing efficiency is extremely high, especially for large digital array systems with thousands or even tens of thousands of sampling channels, making it highly valuable for engineering applications.

[0024] Thirdly, embodiments of this application provide a computer-readable medium having computer program instructions stored thereon, which can be executed by a processor to implement the method provided in the first aspect.

[0025] First, a decision threshold is set based on the system's operating bandwidth and sampling rate. Then, a broadband test signal is injected into all channels, simultaneously triggering the acquisition and storage of datasets from tens of thousands of channels. During the data processing phase, the frequency domain boundary values ​​of each channel's dataset are automatically extracted. By analysis, the minimum and maximum phase differences between the reference and target channels are obtained, and the channel frequency phase differences are calculated. Finally, the test results are output in batches based on preset conditions. This scheme reduces the time complexity of the traditional oscilloscope method and requires only a single signal source and distributed acquisition nodes, significantly reducing the maintenance cost of large digital array systems. This testing method is simple and fast, and its testing efficiency is extremely high, especially for large digital array systems with thousands or even tens of thousands of sampling channels, making it highly valuable for engineering applications. Attached Figure Description

[0026] Figure 1A schematic diagram of a rapid testing system for sampling synchronization of a large digital array system provided in this application embodiment;

[0027] Figure 2 This is a flowchart illustrating a rapid testing method for sampling synchronization of a large digital array system, provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the embodiments of the present invention, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0029] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner for ease of understanding.

[0030] The principles and features of this application are described below. The examples given are only for explaining this application and are not intended to limit the scope of this application.

[0031] In digital array systems, each antenna element is equipped with an independent analog-to-digital / digital-to-analog converter (ADC / DAC) to directly convert RF signals to digital baseband signals. A "near-element processing" architecture is employed, embedding computing resources (such as FPGAs / DSPs) near the array elements to reduce data transmission latency. Beam pointing, waveform parameters, and operating modes are dynamically adjusted through software programming.

[0032] For example, in a K-band digital array microsystem, millimeter-wave transceiver chips and SOC chips are integrated through an LTCC (low-temperature co-fired ceramic) adapter board to achieve full-channel digitization.

[0033] In digital array systems, the sampling synchronization of A / D devices is a core factor affecting beamforming performance. Asynchronous sampling leads to inter-channel time delay errors, which in turn cause problems such as beam pointing deviation and increased sidelobe levels. For example, an inter-channel sampling time deviation (Δt) introduces a phase difference Δφ = 2πf·Δt (where f is the signal frequency), causing main lobe splitting or gain reduction. Furthermore, in multi-beam systems such as MIDAS, asynchronous sampling causes inter-beam crosstalk, reducing communication security and radar resolution. If the sampling times of each channel are inconsistent, high-gain channel synthesis cannot be achieved. Therefore, synchronization testing of all sampling channels in a digital array system is essential.

[0034] Since the sampling synchronization of the A / D devices in each channel is inconsistent in terms of time delay, the channel amplitude and phase testing methods that are traditionally applicable to narrowband systems cannot be applied to this testing scenario.

[0035] This application provides a method for rapid testing of sampling synchronization in a large digital array system, applicable to synchronization testing scenarios in digital array systems.

[0036] This application provides a rapid testing system for the sampling synchronization of a large digital array system, which can execute the rapid testing method for the sampling synchronization of a large digital array system provided in this application. Figure 1 This is a schematic diagram of the structure of a rapid testing system for sampling synchronization of a large digital array system provided in an embodiment of this application.

[0037] like Figure 1 As shown, the large digital array system sampling synchronization rapid test system 001 includes at least one processor 011 and a memory 012 communicatively connected to the at least one processor; wherein, the memory 012 stores instructions that can be executed by the at least one processor 011, and the instructions are executed by the at least one processor 011 to enable the at least one processor 011 to execute the large digital array system sampling synchronization rapid test method provided in the embodiments of this application.

[0038] Figure 2 This is a flowchart illustrating a rapid testing method for sampling synchronization of a large digital array system, provided as an embodiment of this application. Figure 2 As shown, in some embodiments, the rapid testing method for sampling synchronization of this large digital array system includes the following steps:

[0039] S1, based on the test signal bandwidth and sampling rate, yields the decision threshold.

[0040] The test signal bandwidth refers to the bandwidth of the test signal. The test signal must be a broadband signal with a certain bandwidth. For example, its bandwidth is B, and the unit is GHz.

[0041] In some embodiments, the formula for calculating the decision threshold includes:

[0042] η = 360 * B / S;

[0043] Where η represents the decision threshold in degrees (°); B represents the test signal bandwidth in GHz; and S represents the sampling rate in Gsps. The channel-frequency phase difference between each channel and the reference channel is calculated in subsequent steps and then compared with η to determine whether each channel has sampling synchronization with the reference channel.

[0044] In other words, if the system's sampling rate is S, in Gsps, then the time interval between each sampling is 1 / S, in ns.

[0045] In some embodiments, the broadband test signal is emitted by a radiation source system consisting of a signal source, radio frequency cables, and a standard speaker. The signal source radiates the broadband signal throughout the system, and each channel of the system performs quick-sampling and recording of the broadband signal.

[0046] S2, upon receiving the broadband test signal, completes sampling and records data for each channel, obtaining the acquisition dataset for each channel.

[0047] The bandwidth of the broadband test signal is the same as the test signal bandwidth, and the broadband test signal meets the operating frequency band conditions and spacing conditions.

[0048] In some embodiments, the broadband test signal is emitted by a radiation source system consisting of a signal source, radio frequency cables, and a standard horn. Spacing conditions include far-field conditions; the formula for calculating far-field conditions includes:

[0049]

[0050] Where d represents the distance between the system under test and the radiation source system; D represents the diameter of the system under test; λ represents the wavelength of the test waveform, and its relationship with the operating frequency f is: c represents the speed of light.

[0051] A broadband test signal is generated using a signal source, with its center frequency set to f0 and signal bandwidth to B.

[0052] In some embodiments, the operating frequency band conditions include the fact that the operating frequency band of the system under test can cover [f0-B / 2, f0+B / 2]; where f0 represents the center frequency and B represents the test signal bandwidth.

[0053] In some embodiments, the formula for calculating the spacing condition further includes:

[0054] d>2D 2 (f0+B / 2) / c;

[0055] Where c represents the speed of light; D represents the diameter of the system under test; f0 represents the center frequency; and B represents the bandwidth of the test signal.

[0056] The system controls the radiation source system to radiate a broadband test signal to the system under test, and controls each sampling channel of the system under test to simultaneously complete a quick sampling of the test signal, and records the sampling data of each channel.

[0057] S3, confirm the lowest and highest frequencies in the acquisition dataset for each channel.

[0058] In some embodiments, the lowest frequency, that is, the sampling signal corresponding to the lowest frequency, is:

[0059] I n_1 +j*Q n_1 n = 1, 2, ..., N.

[0060] In some embodiments, the highest frequency, that is, the sampling signal corresponding to the highest frequency, is

[0061] I n_2 +j*Q n_2 n = 1, 2, ..., N.

[0062] Extract the sampling point data corresponding to the lowest and highest frequencies of each channel.

[0063] S4, based on the lowest frequency of each channel, obtains the lowest frequency point phase of each channel.

[0064] In some embodiments, the sampling signal corresponding to the lowest frequency is I. n_1 +j*Q n_1 For n = 1, 2, ..., N, the corresponding lowest frequency phase, i.e., the phase of the lowest frequency sampled signal, is:

[0065]

[0066] Where N represents the number of sampling channels of the system under test; I n_1 Q represents the real part of the sampled signal at the lowest frequency point corresponding to the nth channel; n_1 This represents the imaginary part of the sampled signal at the lowest frequency point corresponding to the nth channel.

[0067] S5 obtains the phase of the highest frequency point of each channel based on the sampling data of the highest frequency signal of each channel.

[0068] In some embodiments, the sampling signal corresponding to the highest frequency is I. n_2 +j*Q n_2 For n = 1, 2, ..., N, the phase of the corresponding highest frequency point, i.e., the phase of the sampled signal at the highest frequency point, is:

[0069]

[0070] Where N represents the number of sampling channels of the system under test; I n_2 Q represents the real part of the sampled signal at the highest frequency point corresponding to the nth channel; n_2 This represents the imaginary part of the sampled signal at the highest frequency point corresponding to the nth channel.

[0071] S6, confirm the lowest frequency phase of each channel other than the reference channel, and the lowest phase difference between the lowest frequency phase of the reference channel and the lowest frequency phase of the reference channel.

[0072] The reference channel is any one of all channels.

[0073] Subtract the phase of the sampled data corresponding to the lowest frequency of all other channels from the corresponding phase data of the reference channel to obtain the channel phase difference between each channel and the reference channel at the lowest frequency.

[0074] In some embodiments, the formula for calculating the minimum phase difference is:

[0075] Δθ n_1 =θ n_1 -θ 1_1 n = 2, 3, ..., N;

[0076] Where, θ n 1 Let θ represent the lowest frequency phase of the nth channel. 1_1 This represents the lowest frequency phase of the reference channel.

[0077] S7, confirm the highest phase difference between the highest frequency phase of each channel other than the reference channel and the highest frequency phase of the reference channel.

[0078] The reference channel is any one of all channels.

[0079] Subtract the phase of the sampled data corresponding to the highest frequency of all other channels from the corresponding phase data of the reference channel to obtain the channel phase difference between each channel and the reference channel at the highest frequency.

[0080] In some embodiments, the formula for calculating the maximum phase difference is:

[0081] Δθ n_2 =θ n_2 -θ 1_2 n = 2, 3, ..., N;

[0082] Where, θ n_2 Let θ represent the phase of the highest frequency point of the nth channel. 1_2 This represents the phase at the highest frequency point of the reference channel.

[0083] S8, based on the lowest phase difference and the highest phase difference of each channel, obtains the channel frequency phase difference of each channel.

[0084] In some embodiments, the channel frequency phase difference is n = 2, 3, ..., N; where N represents the number of sampling channels of the system under test; Δθ n_2 Represented as the highest phase difference; Δθ n-1 This is represented as the lowest phase difference.

[0085] The channel phase difference of each channel is calculated from the phase difference between the low and high frequencies of each channel and the reference channel. The channel frequency phase difference of N-1 channels is obtained by subtracting the channel phase differences between each channel and the reference channel at the low and high frequencies.

[0086] S9 obtains the synchronization detection result based on the channel frequency phase difference and decision threshold, according to preset conditions.

[0087] Based on the channel frequency phase difference and decision threshold, and by using preset conditions, it can be determined whether a certain channel satisfies sampling synchronization compared to the reference channel.

[0088] In some embodiments, when performing step S9, the preset conditions include:

[0089] S91, if the channel frequency phase difference of the target channel is less than the decision threshold, then the target channel is determined to be in sync with the reference channel. This means that the channel-frequency phase difference of all channels except the reference channel is compared with the decision threshold.

[0090] The target channel is any channel among all channels except the reference channel.

[0091] S92, if the phase difference of the target channel frequency is greater than the decision threshold, it is determined that the target channel and the reference channel are not in sync.

[0092] S93, if all target channels are synchronized with the reference channels, the synchronization detection result is to determine that the sampling synchronization of the entire system is normal.

[0093] Compare in turn With respect to the magnitude of η, if there exist certain channels that satisfy...

[0094]

[0095] This indicates that the sampling synchronization of the aforementioned channels is abnormal.

[0096] If all channels except the reference channel satisfy

[0097]

[0098] This indicates that the sampling synchronization of the entire system is normal.

[0099] First, a decision threshold is set based on the system's operating bandwidth and sampling rate. Then, a single-channel broadband test signal is injected into all channels, simultaneously triggering the acquisition and storage of datasets from tens of thousands of channels. During the data processing phase, the frequency domain boundary values ​​of each channel's dataset are automatically extracted. By analysis, the minimum and maximum phase differences between the reference and target channels are obtained, and the channel frequency phase differences are calculated. Finally, the test results are output in batches based on preset conditions. This scheme reduces the time complexity of the traditional oscilloscope method and requires only a single signal source and distributed acquisition nodes, significantly reducing the maintenance cost of large digital array systems. This testing method is simple and fast, and its testing efficiency is extremely high, especially for large digital array systems with thousands or even tens of thousands of sampling channels, making it highly valuable for engineering applications.

[0100] Based on the same concept, this application also provides a rapid testing system for the sampling synchronization of a large digital array system. The method corresponding to this rapid testing system can be the rapid testing method for the sampling synchronization of a large digital array system in the aforementioned embodiments, and its problem-solving principle is similar to that method. The rapid testing system for the sampling synchronization of a large digital array system provided in this application includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the methods and / or technical solutions of the various embodiments of this application.

[0101] Another embodiment of this application provides a computer-readable storage medium having computer program instructions stored thereon, which can be executed by a processor to implement the methods and / or technical solutions of any one or more embodiments of this application described above.

[0102] Specifically, this embodiment may employ any combination of one or more computer-readable media. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0103] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0104] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0105] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0106] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0107] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0108] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or page components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some interfaces, and may be electrical, mechanical, or other forms.

[0109] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0110] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0111] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0113] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device through software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any specific order.

Claims

1. A rapid testing method for sampling synchronization of a large digital array system, characterized in that, include: The decision threshold is obtained based on the test signal bandwidth and sampling rate; When receiving a broadband test signal, sampling and data recording are performed on each channel to obtain the acquisition dataset for each channel; the bandwidth of the broadband test signal is the bandwidth of the test signal, and the broadband test signal satisfies the operating frequency band condition and spacing condition; Identify the lowest and highest frequencies in the acquisition dataset for each of the channels; Based on the lowest frequency of each channel, the lowest frequency point phase of each channel is obtained; Based on the highest frequency of each channel, the phase of the highest frequency point of each channel is obtained; Identify the lowest phase difference between the lowest frequency phase of each channel other than the reference channel and the lowest frequency phase of the reference channel; Identify the highest phase difference between the highest frequency point phase of each channel other than the reference channel and the highest frequency point phase of the reference channel; The reference channel is any one of all the channels; Based on the lowest phase difference and the highest phase difference of each channel, the channel frequency phase difference of each channel is obtained; Based on the channel frequency phase difference and the decision threshold, a synchronization detection result is obtained through preset conditions.

2. The rapid testing method for sampling synchronization of a large digital array system according to claim 1, characterized in that, The calculation formula for the decision threshold includes: η = 360 * B / S Where η represents the decision threshold in °; B represents the test signal bandwidth in GHz; and S represents the sampling rate in Gsps.

3. The rapid testing method for sampling synchronization of a large digital array system according to claim 1 or 2, characterized in that, The broadband test signal is emitted by a radiation source system consisting of a signal source, radio frequency cable, and a standard speaker; the spacing conditions include far-field conditions. The formula for calculating the far-field condition includes: Where d represents the distance between the system under test and the radiation source system; D represents the diameter of the system under test; λ represents the wavelength of the test waveform, and its relationship with the operating frequency f is: c represents the speed of light.

4. The rapid testing method for sampling synchronization of a large digital array system according to claim 3, characterized in that, The operating frequency band conditions include that the operating frequency band of the system under test can cover [f0-B / 2, f0+B / 2]; where f0 represents the center frequency and B represents the test signal bandwidth.

5. The rapid testing method for sampling synchronization of a large digital array system according to claim 4, characterized in that, The calculation formula for the spacing condition also includes: d>2D 2 (f0+B / 2) / c; Where c represents the speed of light; D represents the diameter of the system under test; f0 represents the center frequency; and B represents the bandwidth of the test signal.

6. The rapid testing method for sampling synchronization of a large digital array system according to claim 1 or 2, characterized in that, The sampling data corresponding to the lowest frequency is I. n_1 +j*Q n_1 n = 1, 2, ..., N; The sampling data corresponding to the highest frequency is I. n_2 +j*Q n_2 n = 1, 2, ..., N; The lowest frequency point phase is The phase of the highest frequency point is Where N represents the number of sampling channels of the system under test; I n_1 Q represents the real part of the sampled signal at the lowest frequency point corresponding to the nth channel; n_1 I represents the imaginary part of the sampled signal at the lowest frequency point corresponding to the nth channel; n_2 Q represents the real part of the sampled signal at the highest frequency point corresponding to the nth channel; n_2 This represents the imaginary part of the sampled signal at the highest frequency point corresponding to the nth channel.

7. The rapid testing method for sampling synchronization of a large digital array system according to claim 6, characterized in that, The channel frequency phase difference is Where N represents the number of sampling channels of the system under test; Δθ n_2 Represented as the highest phase difference; Δθ n_2 This is represented as the lowest phase difference.

8. The rapid testing method for sampling synchronization of a large digital array system according to claim 7, characterized in that, If the channel frequency phase difference of the target channel is less than the decision threshold, then the target channel is determined to be sampled synchronously with the reference channel; the target channel is any channel among all the other channels except the reference channel. If the channel frequency phase difference of the target channel is greater than the decision threshold, it is determined that the target channel and the reference channel are not in sync. If all the target channels are synchronized with the reference channels, then the synchronization detection result indicates that the sampling synchronization of the entire system is normal.

9. A rapid testing system for sampling synchronization of a large digital array system, characterized in that, include: At least one processor; A memory that is communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 8.

10. A computer-readable medium having computer program instructions stored thereon, characterized in that, The computer program instructions can be executed by a processor to implement the method as described in any one of claims 1 to 8.

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