Method for detecting mask conflicts in a design layout

Abstract

This invention provides a method for detecting mask conflicts in a design layout, relating to the field of computer lithography technology, comprising: Step S1: Loading complete layout data of the circuit design to be tested, the layout data including the position information of all vias in the layout and the spacing information between each via; Step S2: Dividing the complete layout into multiple detection areas; Step S3: For each detection area, extracting all vias in that area as nodes and constructing a corresponding topology diagram; Step S4: Traversing all nodes in the topology diagram, filtering out nodes with a number of neighboring nodes not less than a set value and classifying them into a group to be judged, and performing corresponding conflict detection on the group to be judged according to the number of mask layers to be detected; Step S5: Marking violation nodes based on the conflict detection results, and creating a mask conflict violation area corresponding to the detection area based on the violation nodes; Repeating steps S3-S5 until mask conflict detection of all detection areas is completed. This invention can improve detection speed and efficiency.

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