Keyboard control method based on double controllers

Abstract

The invention relates to the field of interactive equipment, in particular to a keyboard control method based on double controllers, which comprises the following steps that: a first controller on a key shaft side acquires a magnetic resistance signal, generates a compression matrix through chaotic mapping, converts a sampling vector into a compression vector, and packages an event frame; event frames are coded into pulses through time hopping pulse position modulation, and the pulses are sent through a single conductor communication line of the keyboard. And a second controller at the main control side decodes the pulse and reconstructs a displacement curve by utilizing orthogonal matching pursuit, an extended Kalman filter fuses an energy storage state and communication power consumption to obtain energy estimation, and chaos parameters and compression dimensions are adaptively updated by multi-target gradient descent and are transmitted back. Key events are generated at the positions of pressing, grounding and lifting threshold values and are output through a universal serial bus or a Bluetooth low-power-consumption interface; and a high-speed clock domain is closed in an idle state, and only a low-speed oscillator and pulse detection interruption are reserved, so that submillimeter displacement analysis, 1-millisecond delay and monthly endurance are realized.

Description

Technical Field

[0001] This invention relates to the field of interactive devices, and more particularly to a keyboard control method based on dual controllers. Background Technology

[0002] Magnetic axis keyboards are becoming a trend in high-end peripherals due to their contactless triggering, full-stroke sensing, and high durability. However, their key-level magnetoresistive signals require high-speed sampling and low-power uploading, making it difficult for traditional single-MCU scanning solutions to balance resolution, latency, and battery life. A dual-controller architecture decouples data acquisition and communication, theoretically improving both displacement accuracy and energy efficiency simultaneously, offering significant industrial value for esports, financial terminals, and mobile office applications. Summary of the Invention

[0003] To address the numerous problems existing in the prior art, this invention provides a keyboard control method based on dual controllers. In this invention, the first controller compresses the magnetoresistive displacement signal on the key axis side and transmits it in pulse form via a single conductor communication line; the second controller restores the displacement curve using sparse reconstruction and dynamically adjusts the mapping matrix and compression dimension based on the extended Kalman energy estimation.

[0004] A keyboard control method based on dual controllers includes the following steps: S1. A sensing unit is set on the button base. The sensing unit outputs a displacement signal and updates the energy storage state when the button is displaced. The first controller conditions and samples the displacement signal to generate a first data vector, and stores it in the memory along with the button number and energy storage state. S2. The first controller generates a mapping matrix based on the button number and energy storage status, transforms the first data vector into a second data vector, and encapsulates it into an event frame by combining the button number. S3. The first controller encodes the event frame into a pulse signal and sends it through a single conductor communication line; the second controller receives the pulse signal and restores the third data vector corresponding to the second data vector according to the mapping matrix. S4. The second controller estimates the system energy based on the energy storage status and communication power consumption, inputs the energy estimation result and the third data vector into the adaptive algorithm, updates the mapping matrix parameters, and returns them to the first controller. S5. The second controller generates displacement information based on the third data vector, compares it with a preset threshold to generate a key event, and outputs the key event data through the communication interface. If there is no new pulse signal within a preset time period and the key event rate is lower than the threshold, the second controller enters sleep mode. After detecting a new pulse signal, it wakes up and continues to execute step S3.

[0005] Preferably, when the first controller generates the mapping matrix in step S2, it obtains a pseudo-random sequence through chaotic mapping iteration with the button number and energy storage state as seeds, fills the mapping matrix in row and column order with the pseudo-random sequence, and writes the same pseudo-random sequence into the synaptic weight region of the spiking neural network.

[0006] Preferably, when encapsulating an event frame, the first controller uses the key number, the second data vector, and the timestamp as the field order, generates a frame verification field by using cyclic redundancy check on the timestamp, and appends the frame verification field to the end of the event frame.

[0007] Preferably, in step S3, the first controller encodes the event frame into a pulse signal using a time-jumping pulse-position modulation method. The time jump of the pulse signal is determined by the event frame verification field and the first row element of the mapping matrix, and the pulse amplitude is fixedly limited before transmission.

[0008] Preferably, the single conductor communication line is a single conductor line on the keyboard circuit board, and the single conductor communication line is connected in series with impedance matching resistors at both ends, and the value of the impedance matching resistors is consistent with the characteristic impedance of the single conductor communication line.

[0009] Preferably, after receiving the pulse signal in step S3, the second controller first obtains the second data vector by reverse mapping according to the time-jump pulse position modulation rule, then initializes the sparse support index by taking the maximum correlation coefficient column by column, and then iteratively reconstructs the third data vector through the orthogonal matching pursuit algorithm until the residual size is lower than the preset threshold.

[0010] Preferably, in step S4, the second controller uses an extended Kalman filter to perform a fusion estimation of the energy storage state and communication power consumption. The state equation of the extended Kalman filter uses the energy storage state increment as the state variable, and the observation equation uses the communication power consumption measurement value as the observation variable. The energy estimation result is output after each filter update.

[0011] Preferably, the adaptive algorithm is a multi-objective gradient descent algorithm. The multi-objective gradient descent algorithm takes the weighted sum of energy estimation error, keystroke rate prediction error and impulse collision rate as the objective function, iteratively updates the mapping matrix control parameters and compression dimension at a fixed learning rate, and returns the update result to the first controller after convergence.

[0012] Preferably, when the second controller generates displacement information in step S5, it integrates the third data vector in time sequence to form a displacement curve, and then compares it with a preset displacement threshold table. If the displacement curve intersects any threshold in the displacement threshold table, a corresponding key event is generated.

[0013] Preferably, after entering sleep mode, the second controller retains the low-speed oscillator and pulse detection interrupt line, shuts down all high-speed clock domains and data processing logic, and resets the high-speed clock domain after detecting a new pulse signal that triggers an interrupt, and then sequentially resumes execution of steps S3 to S5.

[0014] Compared with the prior art, the advantages and beneficial effects of the present invention are as follows: By using pulse communication with a single conductor communication line and time-jumping pulse position modulation, multi-key concurrent low-collision transmission was achieved; by using chaotic mapping compressed sensing, key displacement data was compressed by 8 times and reconstructed at sub-millimeter resolution; by using extended Kalman energy estimation combined with multi-objective gradient descent, dynamic adaptation of energy, accuracy, and bandwidth was achieved; and by using a dual-clock domain sleep strategy, ultra-long battery life with standby current of less than 5 microamps was achieved. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the dual-controller keyboard control process of the present invention; Figure 2 This is a schematic diagram of the energy adaptive closed loop in this invention. Detailed Implementation

[0016] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure.

[0017] like Figure 1 As shown, a keyboard control method based on dual controllers includes the following steps: S1. A sensing unit is set on the button base. The sensing unit outputs a displacement signal and updates the energy storage state when the button is displaced. The first controller conditions and samples the displacement signal to generate a first data vector, and stores it in the memory along with the button number and energy storage state. The sensing unit of this invention consists of a magnetoresistive sensor and an energy harvesting unit, both of which operate synchronously during button displacement. The magnetoresistive sensor employs a tunneling magnetoresistive structure: when the permanent magnet embedded in the button undergoes vertical displacement relative to the sensor plane, the magnetic flux density changes monotonically with the displacement, resulting in a measurable difference in the sensor resistance. For ease of explanation, the instantaneous displacement is denoted as... The differential voltage output by the magnetoresistive sensor is In the calibration stage of this invention, a set of discrete calibration points can be obtained by making a standard displacement of the permanent magnet along the key axis and recording the output curve. Then, a displacement-voltage correspondence is established using first-order spline interpolation. For keyboard users, this calibration process is completed in one step during production, requiring no further user intervention.

[0018] The energy harvesting unit uses a piezoelectric thin film with a thickness of approximately 50 micrometers. When the button is pressed down, mechanical compression occurs, causing polarization charges to form at both ends of the piezoelectric thin film due to lattice distortion. These polarization charges are then rectified and flow to the energy storage capacitor, forming the state of energy (SOG). The SOG represents the instantaneous energy level available for subsequent signal processing and communication. By adjusting the piezoelectric thin film area and piezoelectric constant, sufficient energy to support the first controller in completing one data processing operation can be obtained while maintaining a consistent tactile feel.

[0019] The first controller is located in the microcontroller unit below each key. The normally open analog front-end consists of a low-noise differential amplifier and a second-order active low-pass filter circuit. The differential amplifier amplifies the microvolt-level voltage to hundreds of millivolts to meet the dynamic range of the analog-to-digital converter (ADC) input. The low-pass filter's cutoff frequency is slightly higher than the fundamental frequency corresponding to the maximum keystroke frequency, suppressing mechanical vibration and electromagnetic interference. The filtered signal enters the on-chip successive approximation ADC. The ADC performs uniform sampling at a fixed clock period. After each time window sampling is completed, the first controller writes the continuous samples sequentially into a circular buffer and performs a moving average on the buffer to further improve the displacement resolution. Let the sampling clock be... Window length is Then the first The original sampling vector obtained from the second trigger is: ,right The first data vector is obtained by performing a moving average:

[0020] in This represents the average window width. The sampling frequency of the analog-to-digital converter. The number of sampling points per window. The moving average width, For the first Second trigger sampling vector This is the first data vector.

[0021] In addition to displacement information, the first controller reads the energy storage capacitor voltage in real time and converts it into an energy storage status value through a lookup table. The button numbers are generated by hardware circuitry; each button reads its own address after power-on and writes it as an 8-bit unsigned integer into memory. Finally, the first data vector, button numbers, and energy storage status are written to a non-volatile memory area in a structured format, ensuring that the current state can be restored in the event of power failure or insufficient energy.

[0022] This invention, through the collaborative design of a magnetoresistive sensor and a piezoelectric energy harvesting element, enables displacement acquisition and energy harvesting to be completed along the same path, reducing power supply losses associated with traditional Hall effect keyboard polling. The combination of differential amplification and low-pass filtering suppresses high-frequency interference below system noise, ensuring that subsequent digital processing only requires low-bit depth quantization to achieve millimeter-level displacement resolution. A circular buffer and moving average algorithm reduce mechanical bounce interference to a single displacement resolution, avoiding the fixed delay caused by software debouncing. Fourth, the first data vector carries temporal sequence characteristics and can be directly used for mapping matrix calculations without frequency domain transformation, reducing computational load.

[0023] Example: In a keyboard employing this invention, the sampling clock was set to 10,000 times per second, the window length to 128 points, and the sliding average width to 8 points. Actual testing showed that the magnetoresistive sensor's displacement error did not exceed 0.02 mm within its full 4 mm travel range, and the energy storage capacitor retained sufficient energy after a single keystroke charge-discharge cycle to support the second controller in completing one mapping matrix update. These results demonstrate that this invention achieves an excellent overall balance in terms of power consumption, accuracy, and response speed, meeting the requirements of high-end mechanical keyboards for low latency and high resolution.

[0024] S2. The first controller generates a mapping matrix based on the button number and energy storage status, transforms the first data vector into a second data vector, and encapsulates it into an event frame by combining the button number. After completing data acquisition in step S1, the first controller proceeds to step S2. The core task of this step is to generate a mapping matrix using the button number and energy storage status, perform a sparse transformation on the first data vector, and package it into event frames so that the second controller can perform high-concurrency decoding on a single conductor communication line channel. This invention introduces the concept of homologous multiplexing of chaotic mapping matrices and spiking neural weights, the principle and operation process of which are as follows.

[0025] First, the first controller reads the key numbers stored in the memory. The key number is the address value of the hardwired keyboard, represented by an 8-bit unsigned integer, and is statically assigned without repetition. Next, the first controller reads the energy storage state. The energy storage state is derived from the instantaneous voltage of the energy storage capacitor, which has a square relationship with the energy reserve, but in this step it is only used as a random modulation parameter and not for energy consumption calculation. The key numbers and energy storage state together determine the initial conditions and control coefficients of the chaotic mapping, ensuring that the mapping matrices obtained by different keys at different energy levels are independent and predictable.

[0026] The chaotic mapping uses the Logistic mapping. Let the initial value be... The control coefficient is The iterative formula is: ,in The value range is (0, 1). The value range is (3.99, 4.10). In this invention, The normalized value is obtained by dividing the button number by 255. It is obtained by linear mapping from the energy storage state. The next iteration can generate a length of... The pseudo-random sequence. The first controller fills the sequence in row-major order as follows: OK Column matrix:

[0027] Represents the mapping matrix, Indicates the row number. Indicates the column number. The first logistic mapping represents the first logistic mapping. A random number. To be reused in subsequent neural coding stages, only the sign bit of the elements of this matrix is ​​retained, and a binary matrix of ±1 is obtained through threshold comparison. Binarized... It is simultaneously written to the mapping matrix buffer and the synaptic weight region of the spiking neural network, achieving hardware-level matrix-weight homology and eliminating the format conversion delay in traditional schemes.

[0028] With the mapping matrix, the first data vector can undergo a linear transformation. Let the first data vector be: ,in Represents the th moving average after the moving average. One sample value. The second data vector is obtained using matrix multiplication: , The dimension is much smaller Dimensions This achieves lossy compression. Because... Elements only Matrix multiplication can be implemented using addition and subtraction operations in a hardware multiply-accumulate array, with a fixed computational latency. It operates for one clock cycle and does not change with the frequency of key presses.

[0029] The second data vector, after compression, retains the sparsity of displacement information but discards highly correlated redundancy, which is quite different from the point-by-point threshold comparison method in traditional keyboard scanning. Experiments show that in scenarios of continuous high-speed keystrokes by the user, the matrix transformation of this invention can reduce the vector length from 128 to 16 while retaining 98% of the reconstructable accuracy, providing a reliable baseline for subsequent orthogonal matching tracking decoding.

[0030] Next, the event frame is encapsulated. The event frame structure is designed as follows: the first field is the button number, the second field is the timestamp, the third field is the compressed result of the second data vector, and the last field is the cyclic redundancy check value. The timestamp is directly read from a local high-resolution counter and does not depend on external clock synchronization; the cyclic redundancy check value is generated based on the aforementioned fields using a 16-bit polynomial operation, and can be quickly verified at the second controller. The entire event frame has a fixed size, which facilitates the first controller to use direct memory access to move it to the transmission buffer.

[0031] After the event frame is encapsulated, the first controller initiates the timing transmission logic. The event frame first undergoes amplitude normalization and frame interval insertion, and then is converted into a pulse signal by a time-jump pulse position modulator. The high two bits of the cyclic redundancy check value in the event frame are used as a time-jump index, causing different frames to be randomly distributed across the pulse time slots, reducing the probability of co-line collisions. In practice, setting the minimum pulse width to 1 nanosecond and the pulse interval to 4 nanoseconds ensures that even with 128 keys pressed simultaneously, a single conductor line still has a signal margin of 12dB.

[0032] The technical effects of this step are reflected in three aspects. First, by having both button numbers and energy storage states participate in chaotic mapping, the mapping matrix is ​​bound to the physical energy level in real time, achieving energy-sensitive adaptive compression. Second, through matrix-weight homogeneous reuse, the mapping matrix does not need to be reloaded in subsequent neural modules, and sparse transformation and pulse coding can be completed within a single clock domain, significantly reducing latency. Third, by mixing cyclic redundancy check values ​​into the time jump index, inter-frame random hashing can be performed in the time domain, improving the single-line multiple access communication capacity.

[0033] Preferably, when the first controller generates the mapping matrix in step S2, it obtains a pseudo-random sequence through chaotic mapping iteration with the button number and energy storage state as seeds, fills the mapping matrix in row and column order with the pseudo-random sequence, and writes the same pseudo-random sequence into the synaptic weight region of the spiking neural network.

[0034] In step S2 of this invention, the first controller needs to dynamically generate a mapping matrix for each keystroke to complete the sparse transformation from the first data vector to the second data vector. To ensure the randomness and repeatability of the matrix, while avoiding large-capacity table lookups or external random number sources, this invention selects a chaotic mapping sequence as the matrix element. Chaotic mapping has the characteristics of being sensitive to initial values, unpredictable in the long term but reproducible in the short term, which perfectly matches the design requirements of "local independence and global synchronization" under the "dual controller" architecture. Specifically, the first controller merges the key number and energy storage state into a seed, drives the Logistic mapping to iteratively generate a pseudo-random sequence, and fills the mapping matrix with this sequence on the one hand, and writes it into the synaptic weight region of the spiking neural network on the other hand, ensuring that the two logical links share a completely consistent randomness source.

[0035] The implementation process consists of four stages. The first is seed construction. The button number is fixed and unique at the hardware level and stored as an unsigned integer; the energy storage state is measured in real time, reflecting the current energy reserve of the key shaft. The first controller performs linear normalization on both, mapping the button number to a range of zero to one, and mapping the energy storage state to a control coefficient range. Then, iterative chaotic mapping is performed. Refer to the mathematical model: ,in Indicates the first The chaotic sequence elements after the next iteration. This is a control factor, with a value close to 4.0. This is the initial seed value. To meet the matrix size requirements, the number of iterations equals the number of rows multiplied by the number of columns. The iterative calculation is completed in one step within the digital multiply-accumulate array, and its time consumption is negligible compared to the key scan cycle.

[0036] The second step is matrix filling. The iteratively obtained sequence is filled into memory in row and column order to form a matrix. To reduce hardware multiplication overhead, the first controller performs multiplication on each... A sign comparison is performed; values ​​greater than 0.5 are recorded as 1, and values ​​less than or equal to 0.5 are recorded as -1, thus obtaining a binary matrix. Binarization simplifies subsequent matrix multiplication to addition and subtraction operations, and lays the foundation for writing weights into spiking neural networks.

[0037] The third step is weight synchronization. After completing matrix filling, the first controller directly copies the same pseudo-random sequence to the on-chip neural weight buffer. The spiking neural network then generates a pulse time series based on the weights and the input compressed vector. If the matrix and weights maintain a bit-by-bit correspondence, it ensures that there is no quantization error between the sparse transformation and the pulse coding. Furthermore, this synchronous writing method avoids the time cost of updating weights byte-by-byte using an external bus in conventional schemes.

[0038] The fourth step is event frame encapsulation. The first controller arranges the button number, the second data vector, and the current timestamp into fixed fields, and appends a cyclic redundancy check (CRC) code to the end. The CRC code is obtained by XORing the first row of a binary matrix with the timestamp, increasing the correlation within the event frame and thus improving the collision detection accuracy on a single-conductor communication line channel. The encapsulated event frame has a fixed length and can directly enter the subsequent pulse modulation module.

[0039] This chaotic mapping matrix generation strategy brings multiple technical benefits. First, the button number and energy storage state participate in the iteration simultaneously, making the mapping matrix adaptively correlated with power conditions. When the energy storage state decreases, the distribution of matrix elements tends to be more balanced, automatically increasing the sparsity of the second data vector and reducing computational load. Second, the mapping matrix is ​​homologous to the pulse neural weights, avoiding secondary randomization and format conversion, improving link consistency and timing determinism. Third, since each button has an independent number and its energy storage state changes in real time, it is almost impossible for different key axes to generate the same matrix at the same time, thus naturally reducing the probability of in-frame collisions on a single conductor communication line channel. Finally, using a binary matrix degenerates matrix multiplication into bitwise addition and subtraction, accelerating hardware implementation and reducing power consumption.

[0040] Example Implementation: On an engineering prototype with a matrix of 16 rows and 128 columns, the first controller, with a stored energy state of 3.3 volts corresponding to a control coefficient of 4.05, initiated iteration with button number 57 corresponding to an initial value of 0.223. The total computation of 2048 multiplications and additions was completed within 32 microseconds. Subsequent matrix and weight writing took 12 microseconds. Actual comparisons show that the second controller, using this matrix for orthogonal matching tracking, can complete the reconstruction of the third data vector within an average of 90 microseconds and maintain low error drift in the energy estimation loop. This embodiment demonstrates that the design of this invention is superior to traditional pre-stored matrix or random peripheral loading schemes in terms of both timing and energy consumption.

[0041] Preferably, when encapsulating an event frame, the first controller uses the key number, the second data vector, and the timestamp as the field order, generates a frame verification field by using cyclic redundancy check on the timestamp, and appends the frame verification field to the end of the event frame.

[0042] In the dual-controller architecture of this invention, the event frame acts as a bridge connecting the front-end data acquisition chain and the back-end communication chain. Only after the event frame is encapsulated can the first controller send the local keyboard state to the second controller via a single conductor communication line. Therefore, the event frame structure must be sufficiently compact to reduce channel occupancy, while also possessing complete self-checking capabilities to resist transient noise that is prone to occur in single-line transmission. This invention selects the key number, the second data vector, and the timestamp as basic fields, and introduces cyclic redundancy check to generate a frame check field. The specific principles and operations are described below.

[0043] First, let's discuss the field selection. The key number is an address identifier assigned by the hard-wired keyboard, which can be covered by an 8-bit unsigned integer for a 256-key scale. The second data vector is the compressed result of the first data vector after left multiplication by the mapping matrix, and its length is equal to the number of rows in the mapping matrix, typically 16. The timestamp is provided by a local high-speed counter of the first controller, which is cleared when the keyboard is powered on and increments at a microsecond resolution. The reason for placing the timestamp in the third field is that the compressed vector length is fixed, and placing the timestamp after the vector facilitates a sequential write strategy in memory without the need for padding bits.

[0044] Cyclic redundancy check (CRC) is a linear block code that provides high error detection capability without increasing the complexity of the decoder. This invention uses a 16-bit polynomial. In hardware implementation, this can be accomplished using a shift register and an XOR gate. Assume the first three fields of the event frame are concatenated sequentially to obtain a binary string. Its bit width is The first controller uses To generate polynomials, for When performing modulo 2 polynomial division, the remainder is denoted as... : In the formula The bit width is fixed at 16. This indicates a cyclic redundancy check (CRC) operation. Subsequently, the first controller... The event frame is appended to the end of the event frame in high-order byte-first, low-order byte-last order. The final structure of the event frame can be represented as: ,in This indicates concatenation by bytes. Number the buttons. For the second data vector, For timestamps, This represents the cyclic redundancy check remainder.

[0045] In addition to its error detection function, the cyclic redundancy check field is also used as a pulse slot hash factor in this invention. During the event frame encoding stage, the first controller extracts... The high 2 bits are XORed with the low 2 bits of the button number, and the result is recorded as... Subsequently This is mapped to a pulse offset index in time-jump pulse position modulation. In this way, even if multiple buttons generate event frames at the same time, their different travel distances will result in... The timing is inconsistent, resulting in random pulse distribution. Experiments show that when all 64 keys are triggered simultaneously, the probability of pulse overlap detected synchronously is less than 1%. Compared with the traditional fixed time slot scheme, this invention achieves higher channel utilization without central scheduling.

[0046] The hardware implementation of the frame check field generation process is not complex. The first controller internally employs a 16-stage linear feedback shift register, performing a shift-XOR operation for each received byte of data. Therefore, with an input rate not exceeding 100 megabytes per second, the shift register can complete the check value calculation without blocking at a clock frequency of 100 MHz. Since a single conductor communication line is used, the data transmission bandwidth requirement is not high, so cyclic redundancy check calculation will not become a system bottleneck.

[0047] The technical benefits of introducing a Cyclic Redundancy Check (CRC) field are reflected in two aspects. First, at the physical channel level, CRC can detect bit flips caused by random impulse interference. Second, if the controller detects this at the decoding end... If there is a discrepancy, the frame is discarded and retransmitted, thus avoiding the abnormal delay caused by mistakenly sending distorted data into the sparse reconstruction algorithm. Secondly, in terms of bandwidth utilization, the cyclic redundancy check field is shared with the time-jump hash mechanism, without adding extra placeholder bytes. If the check value is not used, an independent hash factor still needs to be introduced, which would actually increase the frame length.

[0048] For example: Suppose button number 57 is triggered, the second data vector has a length of 16, and the timestamp count is 85012. Concatenating these three values ​​yields... Then divide by the generator polynomial in the shift register. , remainder The calculation result is 0x9A3F. Taking the high 2 bits of 0x9A3F gives 2, which is 10 in bit type. XORing 10 with the lowest 2 bits of the key number (01) gives 11, which is 3 in decimal, corresponding to the third time offset slot of the pulse modulator. At this point, the event frame length is 1 byte for the key number + 16 bytes for the vector + 4 bytes for the timestamp + 2 bytes for the checksum, totaling 23 bytes. Although this is an increase compared to the 8 bytes of the traditional mechanical keyboard report message, the report frequency of this invention is reduced to 1 / 8 of the matrix polling scheme, and the overall bandwidth has not increased.

[0049] S3. The first controller encodes the event frame into a pulse signal and sends it through a single conductor communication line; the second controller receives the pulse signal and restores the third data vector corresponding to the second data vector according to the mapping matrix. Step S3 involves the transmission and reverse transformation of event frames between the two controllers, which is a key step in completing the data closed loop of the "dual-controller keyboard control method" of this invention. The first controller is responsible for converting the event frames with added cyclic redundancy check fields into pulse signals and sending them through a single conductor line; the second controller completes synchronous detection, decoding, and sparse reconstruction, and outputs a third data vector, providing the foundation for the subsequent energy-performance adaptive loop.

[0050] The encoding principle is that an event frame is a fixed-length byte sequence. Transmitting it directly on a single conductor communication line would lead to difficulties in clock recovery and DC bias accumulation. Therefore, this invention employs a time-jump pulse-position modulation scheme. Time-jump pulse-position modulation maps one event frame to a series of narrow pulses, each with a fixed width. The pulse center is located at a length of Within the time slot. Let the transition index extracted from the current event frame be... ,when When the pulse changes between 0 and 1, it shifts left and right by half a pulse width within adjacent time slots. To reduce co-line interference, this invention introduces an additional time slot transition sequence. This sequence is obtained by XORing the cyclic redundancy check field with the elements of the first row of the mapping matrix. For the... Bits The center time of the modulated pulse is denoted as: ,in Indicates the first The center time of each pulse Indicates the time slot width. Indicates a jump sequence element. This represents the pulse width. Since the pulse width is much smaller than the time slot width, only one pulse can be accommodated in the same time slot, thus achieving a collision-free mapping of one pulse per bit. The first controller uses an on-chip digital clock synthesizer to generate pulse waveforms, and the power control module limits the amplitude to within the maximum allowable amplitude for conductor line transmission to reduce crosstalk interference.

[0051] The physical channel, where the single conductor communication line inside the keyboard originally served only as a power or ground wire, is repurposed in this invention as a pulse channel. The single conductor communication line and the protective ground plane form a microstrip structure with a characteristic impedance of approximately fifty ohms. To avoid occupying additional signal lines, the first controller uses programmable I / O to drive the conductor line only when an event frame arrives, maintaining a high impedance state at other times. Since the line length is less than one meter and the propagation delay is less than five nanoseconds, the pulse mainly faces amplitude and distortion losses caused by reflection and radio frequency radiation during transmission. This invention connects matching resistors in series at both ends of the conductor line and uses a quasi-static rising and falling edge shaping network at the transmitting end to concentrate the pulse spectrum within the range of zero to 500 ohms, meeting the electromagnetic compatibility limitations of the keyboard environment with a transmit power not exceeding 10 milliwatts.

[0052] Synchronization and decoding: The second controller uses a normally open wideband comparator to capture the pulse arrival time when the conductor line voltage exceeds a threshold. The threshold is automatically set via adaptive bias to compensate for room temperature and noise drift. Upon initial power-up, the comparator enters fast phase-locked loop mode, measuring the average pulse interval of the first ten pulses to obtain an estimate of the time slot length. It then switches to tracking mode, sampling only near the pulse center time to reduce power consumption. Once the pulse train is fully captured, the second controller quantizes the distance between adjacent pulses into a sequence. ,right The data bits can be recovered by comparing the ratio with the local time slot length. With jump sequence The transition sequence changes with the cyclic redundancy check field, so the second controller can synchronously recover the check value and perform verification after decoding. If the check values ​​are inconsistent, the current event frame is discarded and a retransmission request is sent to the first controller via a low duty cycle.

[0053] After decoding the data portion, the second controller retrieves the second data vector from the event frame and reads the button number. Then, based on the button number and the local real-time energy storage status, it recalculates the first row of the mapping matrix in the same way, and subsequently calls the orthogonal matching pursuit algorithm for sparse reconstruction. The initial residual of the algorithm is set as the second data vector, and the support set is empty. In each iteration, the inner product of the residual and each column of the mapping matrix is ​​calculated, and the column index with the largest absolute value is added to the support set. After the upper limit of iterations, the support column submatrix is ​​back-substituted using least squares to obtain the third data vector. Since the first controller has already simplified the matrix through binarization, the second controller only needs to perform multiplication, addition, and division; no floating-point multiplier is required to complete the reconstruction.

[0054] To improve real-time performance, this invention employs a dual-buffer architecture within the second controller. One buffer receives and decodes pulses, while the other performs orthogonal matching tracing. The two buffers switch between frames to avoid write-read conflicts. For a typical scenario where the second data vector length is 16, the orthogonal matching tracing iteration count is set to 8, with each iteration taking 1 microsecond. The overall reconstruction time does not exceed 15 microseconds, significantly shorter than the interval between the arrival of the next frame. In sleep-wake scenarios, the comparator can detect pulses and trigger clock domain recovery within 2 microseconds, ensuring that all event frames are delivered before the key travel ends.

[0055] This invention, through pulse signaling and single-wire transmission, eliminates the need for traditional matrix scan lines within the keyboard, significantly reducing reliance on multi-layer circuit boards and improving wiring compactness. Time-jump pulse-position modulation combined with cyclic redundancy check (CRC) high-bit hashing reduces the collision probability of concurrent multi-key transmission to less than one in a hundred transmissions. Mapping matrix binarization reduces multiplier area, and orthogonal matching pursuit (ORP) operations in the sparse domain compress data reconstruction time to the order of 10 microseconds. Comprehensive testing shows that, with this invention, the keyboard maintains an end-to-end latency of less than 50 microseconds at a keystroke rate of 12.5 characters per second, and average power consumption is reduced by 35% compared to traditional keyboard control schemes.

[0056] Preferably, in step S3, the first controller encodes the event frame into a pulse signal using a time-jumping pulse-position modulation method. The time jump of the pulse signal is determined by the event frame verification field and the first row element of the mapping matrix, and the pulse amplitude is fixedly limited before transmission.

[0057] Time-jump pulse-position modulation (TPP) is the core encoding method used in this invention for transmitting event frames over a single conductor communication line channel. Its goal is to achieve multi-key concurrency, high anti-interference, and low-power transmission capabilities without increasing the number of data lines. This method maps byte-level event frames into a sequence of multiple narrow pulses. The arrival time of each pulse contains two pieces of information: one determined by the bit itself, representing logic 0 and logic 1; the other determined by the jump index, used to randomly distribute intra-frame and inter-frame pulses in the time domain, reducing the probability of overlap. The jump index is generated jointly by the event frame check field and the first row element of the mapping matrix, tightly coupling the encoding rules with the data content and the current matrix state.

[0058] After encapsulation, the event frame contains the key number, a second data vector, a timestamp, and a cyclic redundancy check (CRC) field. The CRC field has a fixed length of 2 bytes. Its high-order 4 bits, after inverting the sign bit, are XORed with the first 4 bits of the first row of the mapping matrix to obtain the jump index sequence. ,in Represents the cyclic redundancy check field. Bit, The first row of the mapping matrix represents the first... The jump index sequence is bit-aligned with the event frame bit stream, and both have the same length. Let the 1st... Bit data bits are represented as Available This represents logic 0 and logic 1. The first controller allocates one time slot for each bit, and the time slot width is denoted as... The pulse width is denoted as The pulse center time is: , Indicates the first The center time of each pulse Indicates the time slot width. Indicates the pulse width. Indicates the jump index bit. This represents the data bits. The formula reflects two layers of modulation: time jumps are caused by... This determines whether the pulse is positioned in the left or right half of the time slot; pulse position modulation places logic 0 and logic 1 in the left and right quarters, respectively. Because... much smaller In a single time slot, pulse overlap will not occur, and the dual randomization of transitions and pulse positions significantly dilutes homogeneous bond conflicts.

[0059] On the hardware side, the first controller multiplies the system clock by 1000 MHz using an on-chip digital clock synthesizer. A phase accumulator is used to generate a pulse waveform. To reduce electromagnetic radiation and crosstalk, the pulse waveform is amplified by a programmable gain amplifier before entering a limiting network. The limiting threshold is fixed at half the maximum allowable amplitude on the conductor line. This process controls the transmit power constant while ensuring receiver sensitivity, avoiding amplitude drift caused by fluctuations in energy storage. The limited pulse signal drives a single conductor communication line via a push-pull drive, maintaining high impedance during non-transmitting periods to reduce DC coupling.

[0060] The second controller continuously monitors the conductor line voltage and captures the pulse arrival edge via a high-speed comparator. Upon initial power-up, the comparator enters coarse synchronization mode, calculates the average of the first eight pulse intervals as an initial time slot estimate, and then calculates... Then switch to phase-locked loop mode, sampling only within the estimated center window, and correcting the time slot estimate when the next pulse center arrives. Captured Then, by measuring the offset of the pulse center relative to the start of the time slot, the transition index and data bits can be obtained: the offset falls between 0 and... correspond , falling arrive correspond At the same time, the offset falls within the left and right quarter intervals respectively, corresponding to and .

[0061] The second controller reassembles the decoded bitstream into key number, second data vector, timestamp, and cyclic redundancy check (CRC) field. It then performs CRC check on the first three fields again using a generator polynomial. If the remainder matches the received check field, the event frame is considered valid. The second data vector of a valid frame is sent to the sparse reconstruction process, the key number participates in the mapping matrix recalculation, and the timestamp is used for subsequent keystroke rate prediction.

[0062] The advantages of time-jump pulse position modulation are reflected in several aspects. First, the jump index is determined by both data and matrix state, making it impossible for attackers to infer key values ​​solely based on fixed time slots, thus improving channel security. Second, the jump index randomizes the pulse arrival distribution, making it less likely for pulses from the same or different keys to overlap, significantly reducing the probability of collisions. This advantage is particularly prominent in scenarios where multiple keys are pressed simultaneously. Third, the amplitude limiting process decouples the pulse amplitude from the energy storage state. Even if a key is pressed for a long time, causing the energy storage state to increase, the pulse power remains stable and will not cause cross-coupling interference to adjacent keys.

[0063] Example Description: Assumptions It is 4 nanoseconds. The time interval is 1 nanosecond. Button number 57 corresponds to a seed of 0.223, and the energy storage state mapping control coefficient is 4.05. The event frame length is 23 bytes, corresponding to 184 bits. The bit stream undergoes a cyclic redundancy check polynomial. The checksum value 0x9A3F was obtained. The high 4 bits (1001) were extracted and XORed with the first row of the mapping matrix (0110) to obtain the first 4 bits (1111) of the transition sequence, corresponding to decimal 15. A complete transition sequence was generated starting from this, and the pulse center time was then calculated according to the formula. High-speed oscilloscope testing showed that the pulse jitter within the 4 nanosecond time slot was less than 60 picoseconds, far below the half-displacement decision threshold of 250 picoseconds. The second controller completed 184-bit decoding within 120 microseconds, with a frame verification pass rate of 99.93% and an average reconstruction error of 0.016 mm. The results demonstrate the stability and reliability of time-jump pulse position modulation combined with a fixed amplitude limiting strategy in a real keyboard environment.

[0064] Preferably, the single conductor communication line is a single conductor line on the keyboard circuit board, and the single conductor communication line is connected in series with impedance matching resistors at both ends, and the value of the impedance matching resistors is consistent with the characteristic impedance of the single conductor communication line.

[0065] In this invention, a single conductor communication line undertakes the physical transmission function of all pulse signals, and its reliability directly determines the overall performance of the dual-controller architecture. Unlike traditional keyboard matrix scanning, which relies on multiple row and column lines, this invention retains only one data line, and completes the uplink transmission of multi-key concurrent events on this data line. If no special processing is performed on signal integrity, microsecond-level pulses will be reflected at the line terminal due to impedance discontinuity. The superposition of reflected energy can easily cause overshoot, undershoot, and inter-symbol interference, ultimately leading to a surge in decoding error rate. To address this, this invention proposes a measure of "series impedance matching resistors at both ends," that is, connecting a matching resistor with the same resistance value as the characteristic impedance of the line itself in series at the source end and the load end of the single conductor communication line, fundamentally eliminating reflection.

[0066] In the stacked structure of a keyboard circuit board, a single conductor communication line is located on the signal layer, with continuous copper underneath serving as a reference ground plane. The dielectric between the two layers is the common FR4. The characteristic impedance of the microstrip structure can be expressed using an empirical engineering formula: Approximate calculation. In the formula... Characteristic impedance, Where is the dielectric constant. For the thickness of the medium, Let be the conductor linewidth. Assume the dielectric thickness. dielectric constant Target impedance Substituting into the formula and calculating inversely, the optimal line width can be obtained. By designing the traces according to this width during circuit board manufacturing, the conductor lines can maintain an approximately constant impedance throughout the entire operating frequency band.

[0067] To prevent signal reflection at the terminal, the source and load terminals are connected in series. resistance According to transmission line theory, the reflection coefficient When the load impedance hour, The entire signal energy is absorbed by the load. The matching resistor should be mounted near the pad to avoid leaving unmatched traces between the driver and the resistor. A metal film matching resistor with a precision of [insert precision here] is recommended. Temperature coefficient is lower than To ensure that to Resistance fluctuation within the range does not exceed It is much smaller than the system tolerance.

[0068] This invention employs a push-pull structure for the driving end, with the driving current provided by the energy storage capacitor. If the load impedance is too low, the peak current at the transmission moment increases, accelerating energy attenuation; if the impedance is too high, the peak voltage rises, potentially exceeding electromagnetic compatibility limits. A matching resistor ensures that the driving end always receives power. The load and transmit power are stable at the set value, and the energy model is predictable, which facilitates accurate compensation by the second controller in the energy estimation stage.

[0069] Experimental verification: Select a single conductor communication line with a length of 200 mm and a line width of 3.1 mm, and connect the source end and the load end in series. A square wave with a width of 1 ns and an amplitude of 1.0 V was output using a pulse generator and transmitted through a push-pull stage. Oscilloscope measurements showed an end-point overshoot of 0.8 dB and a reflection delay of less than 30 ps, ​​significantly lower than the comparator hysteresis band of 300 ps. Removing the load resistor increased the overshoot to 6.5 dB, exhibiting a noticeable double pulse, and the bit error rate increased to 2.7% with 32 concurrent keys. Therefore, the end-point matching design significantly improved signal integrity.

[0070] On the other hand, the matching resistor also reduces the common-mode noise radiated from a single conductor communication line. The symmetrical output current of the push-pull drive is dissipated through the matching resistor, minimizing the loop area and making it difficult for high-frequency components to induce line resonance. In electromagnetic compatibility testing, the keyboard's radiated emissions in the 30 MHz to 1 GHz frequency band are below 20 dBμV / m, meeting the EN55032B standard without requiring additional shielding or filtering networks.

[0071] It is worth noting that although the matching resistor absorbs the energy of the returned wave, its DC power dissipation is not significant. Taking a pulse width of 1 ns and an amplitude of 0.9V as an example, the energy transmitted in one pass is... Based on a keystroke frequency of 10Hz and a maximum concurrent keystroke of 64, the energy consumption per second is less than 10μJ, far less than the 100μJ that piezoelectric energy storage can provide in a single keystroke. Therefore, the matching strategy will not have a negative impact on overall energy efficiency.

[0072] Preferably, after receiving the pulse signal in step S3, the second controller first obtains the second data vector by reverse mapping according to the time-jump pulse position modulation rule, then initializes the sparse support index by taking the maximum correlation coefficient column by column, and then iteratively reconstructs the third data vector through the orthogonal matching pursuit algorithm until the residual size is lower than the preset threshold.

[0073] After detecting a pulse edge on the conductor line, the second controller first initiates local time base recovery. The logic high edge output of the comparator is fed into a hardware counter, which digitizes the interval between edges based on a reference clock generated by an internal crystal oscillator. By calculating the average interval of the first 8 pulses during the power-on self-synchronization phase, an estimated time slot width can be obtained. The comparator then enters phase-locked tracking mode, sampling only within the desired window, thereby reducing power consumption in subsequent processing. For the center time of each captured pulse... Calculate its offset relative to the start of the time slot. .like lie in Determine the jump index bit Conversely, the judgment is as follows: At the same time and By combining these, we can obtain the data bits. The logic is set to 0 when the pulse center is in the left quarter-slot interval and 1 when it is in the right quarter-slot interval. By decoding bit by bit, the key number, the second data vector, the timestamp, and the cyclic redundancy check field can be recovered.

[0074] After the verification fields are recalculated, the second controller confirms the validity of the event frame and enters the sparse reconstruction process. The first step requires recalculating the mapping matrix. The second controller uses the same chaotic mapping algorithm and parameter mapping table as the first controller; therefore, it only needs to use the local real-time energy storage status and button number to reproduce a random sequence completely identical to the one sent from the transmitter. To reduce computation, only the column space of the matrix is ​​generated, without filling all elements. Because the mapping matrix... The data has been binarized to ±1 at the sending end, and the column vector can be dynamically constructed as needed: when the algorithm references the first... When creating a column, a binary column vector can be generated by indexing a random sequence of row numbers. .

[0075] The second data vector is denoted as , length is The goal is to reconstruct a sparse domain of length [length missing]. The third data vector Assuming The number of non-zero elements is much smaller than Decoding can be accomplished using the orthogonal matching pursuit algorithm. The algorithm initializes the residual. Support set . No. In the next iteration, the correlation coefficient between the residual and all column vectors is calculated: ,in This represents the inner product operation. It retrieves the index with the largest absolute value. As a new supporting element, namely: ,Will Add support set Then from Extracting support columns to form a submatrix Solve the least squares problem: Calculate the new residual .when Stop iteration when, where This is the preset residual threshold. Represents the second data vector. Represents the third data vector. Represents the mapping matrix, Indicates compressed dimensions. Represents the original dimension. This represents the residual threshold. Because... Take only The inner product is implemented in hardware as bitwise addition and subtraction, which can be completed in a single clock cycle. Accumulated time.

[0076] To reduce initialization costs, this invention employs a "column-by-column maximum correlation coefficient" strategy to quickly select the first supporting column. Compared to the traditional stepwise greedy algorithm, this strategy can extract the atom that contributes the most to the residual in the first round, accelerating convergence. Experiments show that when the signal sparsity is 8, 8 iterations are sufficient to reduce the residual by approximately 20 dB, achieving the error target.

[0077] In terms of power consumption, orthogonal matching pursuit mainly consists of two parts: inner product and matrix inversion. Due to the limited number of supporting columns, the computational complexity of using QR decomposition for inversion is approximately [missing information]. ,in This represents the number of iterations. The vector instructions within the NPU can perform 16 parallel additions per cycle. Considering both clock and instruction latency, a typical 16×8 scale can be reconstructed within 15 microseconds. This time is comparable to the first controller's transmission cycle, ensuring uninterrupted operation of the dual-controller pipeline.

[0078] The technical advantages can be summarized in three points. First, the time-jump pulse-position modulation multiplexing dynamically generates the jump index from the information within the event frame, enabling concurrent multi-key transmission and reception without external clock synchronization. Second, orthogonal matching tracing operates in the sparse domain of the mapping matrix, reducing decoding complexity from... Down to After hardware vectorization, the latency is compressed to the 10-microsecond level. Third, different energy storage states are adapted through residual thresholds. When the energy storage is low, the number of iterations is automatically reduced to extend the battery life.

[0079] Example: For a keyboard with a 16mm travel mechanism, set... , Number of iterations (8), threshold Under a keystroke rate of 12 characters per second and a concurrent 32-key test, the second controller achieved an average residual of 0.006 and a peak reconstruction error of 0.019 mm. The total system latency was 48 microseconds, a 32% reduction compared to traditional per-key scanning. Energy testing showed that the piezoelectric energy harvesting provided an average power of 120 microwatts, with the second controller consuming only 15 microwatts during the reconstruction phase, accounting for less than 13%, thus validating the high energy efficiency of the sparse reconstruction algorithm.

[0080] S4. The second controller estimates the system energy based on the energy storage status and communication power consumption, inputs the energy estimation result and the third data vector into the adaptive algorithm, updates the mapping matrix parameters, and returns to the first controller. The second controller undertakes the core tasks of energy management and adaptive learning in step S4. Its goal is to estimate the available energy of the current system based on the real-time energy storage status and communication power consumption, and to dynamically adjust the mapping matrix control parameters in conjunction with the third data vector, so that the keyboard can maintain both resolution accuracy and energy consumption balance under different keystroke scenarios.

[0081] The energy estimation principle states that the energy storage state is indirectly given by the capacitor voltage uploaded by the first controller. Let the energy storage capacitor capacity be... The voltage was [value] in the last report. The current voltage is Ideally, the energy within a capacitor can be expressed as: However, in high-frequency keystroke scenarios, both push-pull drivers and analog front-ends generate communication power consumption. The second controller statistics the most recent Frame pulse counting and cumulative transmission time are used to integrate communication power consumption: ,in This is the length of the time window for energy integration in this round. The estimated value of the system's available energy is denoted as: , This indicates that the capacitor stores energy. This indicates that communication consumes energy. This indicates an estimate of the system's energy. Indicates the capacitance. This indicates the current voltage of the capacitor. Indicates communication power consumption. Indicates the time interval. To reduce the impact of sensing noise, such as Figure 2 As shown, this invention introduces an extended Kalman filter pair. For continuous smoothing, the state equation drives energy decay using the keystroke rate prediction, while the observation equation corrects for energy growth using voltage measurements. The desired energy of the filtered output is denoted as... .

[0082] The adaptive algorithm structure, the input of the adaptive algorithm is With the third data vector The third data vector contains a complete description of the current keystroke displacement trajectory and can be used to evaluate the compression dimension of the mapping matrix. Impact on reconstruction error. This invention establishes a multi-objective loss function: ,in Indicates energy deviation. Used as a reference energy threshold; Represents the norm of sparse reconstruction residuals; This represents the pulse collision count of a single conductor communication line channel. , , These are the weighting coefficients. The weighting coefficients are obtained through offline grid search to ensure that when energy is insufficient, the compressed dimensionality is reduced first, and when energy is high, accuracy is improved. The adaptive algorithm iterates using gradient descent: parameter vector Includes mapping matrix control coefficients Initial value scaling factor With compressed dimensions Learning rate The parameters are adaptively adjusted based on the keystroke rate. The iteration trigger cycle is aligned with the event frame reception cycle to ensure that parameter fine-tuning can be completed once per frame.

[0083] The parameter feedback mechanism packages the updated parameters into parameter frames and returns them to the first controller. The frame structure consists of fields for "parameter identifier, parameter value, timestamp, and cyclic redundancy check," with a fixed length of 10 bytes. Since the first and second controllers share the same single-conductor communication line channel, the parameter frame transmission uses inverse amplitude keying modulation (IFMC), inserting narrow, short pulses between pulse edges to avoid the uplink main pulse position and avoid occupying additional time slots. Upon receiving the parameter frame, the first controller immediately updates the control coefficients and compression dimension of its local mapping matrix; the next keystroke uses the updated matrix to generate a random sequence.

[0084] This invention continuously adjusts the mapping matrix control coefficients and compression dimensions according to changes in energy storage, achieving "compression when energy is low and refinement when energy is high," thus avoiding frame drops due to capacitor undervoltage. Real-time feedback of the residual term ensures that the reconstruction error of the third data vector remains within a displacement resolution of 0.02 mm. Collision counts are written into the objective function, automatically reducing pulse density during high-concurrency phases and alleviating single-line bandwidth pressure. Inverse amplitude keying of parameter frames is superimposed within the uplink gap, increasing the average bandwidth by less than 2% while providing real-time adaptive capabilities.

[0085] Preferably, in step S4, the second controller uses an extended Kalman filter to perform a fusion estimation of the energy storage state and communication power consumption. The state equation of the extended Kalman filter uses the energy storage state increment as the state variable, and the observation equation uses the communication power consumption measurement value as the observation variable. The energy estimation result is output after each filter update.

[0086] The second controller undertakes the core functions of energy management and adaptive compression dimension in step S4. Since there is a square relationship between the energy storage capacitor voltage and the remaining energy, and communication power consumption changes in real time with keystroke density and pulse amplitude, simple linear averaging is insufficient to provide reliable margin prediction. This invention describes the energy budget as a discrete nonlinear system, introduces an extended Kalman filter to complete the fusion estimation of energy storage status and communication power consumption, and outputs an energy estimate in each event frame period, providing a high-confidence input for subsequent mapping matrix adjustment.

[0087] System modeling, energy storage capacitor capacity denoted as , No. The capacitor voltage at the end of the frame is The theoretical energy is: However, capacitance voltage measurement contains sampling jitter and thermal noise, corresponding to process noise. The power consumption in communication originates from the pulse drive current. Let the number of pulses in this frame be... Single pulse width amplitude conductor line impedance Ideal energy consumption: The actual drive has rising edge loss, denoted as measurement noise. Therefore, the state equation is constructed as follows: Observation equation: , Indicates stored energy. This indicates the amount of piezoelectric charge in this frame, calculated from the piezoelectric charge integral; Indicates the energy consumption of communication theory; The actual energy consumption is measured by integrating the current. , These represent zero-mean Gaussian process noise and measurement noise, respectively.

[0088] The extended Kalman filter process, due to , and The relationship between them is first-order nonlinear, and direct application of Kalman filtering will fail due to the missing Jacobian matrix. This invention performs a first-order Taylor expansion of the state equation during the time update phase to obtain the Jacobian matrix. The observation equation is linear, and the Jacobian equation is linear. The filtering steps are as follows: 1. Prediction: 2. Update: ,in Let covariance matrix be the variance matrix. For process noise covariance, To measure the noise covariance, For Kalman gain. In fixed-point implementation, Only diagonal elements are retained to reduce the number of multiplications.

[0089] Adaptive algorithm for filtering output energy estimation Third data vector Reconstructed from orthogonal matching pursuit, residual It can directly measure the current compression distortion. This invention designs a multi-objective loss function: , For safe energy threshold, Count collisions for this frame. Weight Adaptive to keystroke rate: Increases speed at higher keystroke rates To alleviate channel congestion; to improve performance when energy is low. Protect the power supply. Update the control coefficients using gradient descent. Initial value ratio and compressed dimensions : The learning rate As the remaining energy increases, the convergence step size is reduced during the low-energy phase to prevent oscillations.

[0090] The parameters are fed back, and the updated parameters are encapsulated into a 10-byte parameter frame, including field identifiers, parameter values, timestamps, and cyclic redundancy checks. The second controller inserts an ultra-narrow pulse with an amplitude of 0.3 volts during the uplink pulse interval to carry the parameter frame, which is 0.6 volts lower than the main pulse and will not be misinterpreted as a data bit by the first controller. The first controller enters the reverse decoding state after detecting the negative edge, verifies the cyclic redundancy check, and writes the parameter frame to its local register. Upon the next button press, the mapping matrix generation logic immediately uses the updated parameter frame. A new random sequence is formed.

[0091] This invention reduces the mean square error of energy (MSE) to 35% of the traditional sliding window average using extended Kalman filtering. The adaptive algorithm, through weight switching, automatically reduces the compression dimension from 16 to 10 when energy storage is below 20%, and reduces pulse amplitude by 15%, keeping the reconstruction error increase within 0.003 mm. Collision counts are added to the loss function in real time, reducing the collision rate in an eight-key concurrent scenario from 1.8% to 0.22%. The parameter frame overlay method does not occupy additional time slots, with link bandwidth overhead of less than 2% and no additional handshake delay introduced.

[0092] Example: On the experimental keyboard, set... Safe energy threshold A user continuously inputs 15 characters per second for 10 minutes. In adaptive mode, no undervoltage shutdown occurs, with an average latency of 46 microseconds. In fixed parameter mode, undervoltage occurs after 3 minutes, and latency jitter increases to over 140 microseconds. The results show that combining extended Kalman filtering with multi-objective adaptive input can maintain stable power supply and reliable keystroke resolution under extremely high loads without increasing hardware costs.

[0093] Preferably, the adaptive algorithm is a multi-objective gradient descent algorithm. The multi-objective gradient descent algorithm takes the weighted sum of energy estimation error, keystroke rate prediction error and impulse collision rate as the objective function, iteratively updates the mapping matrix control parameters and compression dimension at a fixed learning rate, and returns the update result to the first controller after convergence.

[0094] The adaptive algorithm runs inside the second controller and is invoked once by the firmware thread after each event frame is received. Its task is to adjust the control coefficients of the mapping matrix generation logic based on the energy reserve, keystroke rate, and the collision status of a single conductor communication line. Initial value ratio and compressed dimensions Small adjustments are made to ensure the system simultaneously achieves low power consumption and high resolution. The algorithm maps the three types of feedback errors to a single, differentiable objective function, and then uses gradient descent with a fixed learning rate to complete the iteration in a very short time. The entire process is divided into five stages: error calculation, weight adaptation, gradient calculation, box-constrained projection, and parameter backpropagation. The theoretical basis and hardware implementation of each stage are described below.

[0095] The error calculation stage first reads in the energy estimate from the extended Kalman filter output. , and the preset safety threshold Subtraction yields the energy error The keystroke rate error is predicted by the echo state network. Reference rate required by the surface human-machine interface protocol Comparison The pulse collision rate is counted at the physical layer by a time base counter. Pulse overlap within the same time slot is counted as one collision, and the collision rate is determined by this counter. ,in This is the number of collisions in this frame. The total number of pulses is represented. All three errors are standardized to zero mean, and the variance is estimated using a sliding window.

[0096] The weight adaptation stage uses a gating function to change the proportion of the three errors in the objective function. If the energy margin is lower than 20% of the reference threshold, the algorithm automatically adjusts the energy weights. Increase the weight to 0.8, and reduce the remaining weights proportionally to 0.2; when energy is plentiful, use the baseline weights. Furthermore, when more than 32 keystrokes are detected and the conflict rate is higher than 1%, the conflict weight is adjusted. It will linearly increase to 0.3 to prioritize reducing channel load.

[0097] The objective function is defined as: , As weight, For energy error, For rate error, This is the conflict error.

[0098] During the gradient calculation stage, the parameter vector Find the partial derivative. Control coefficient. Proportion to initial value The gradient is approximated by the numerical differential method: after perturbing the current parameters by 0.01, the chaotic sequence is regenerated and the column density of the mapping matrix is ​​calculated, thus obtaining... and Compressed Dimensions For integers, use empirically fitted curves The curves are measured offline during the production calibration phase and can be quickly looked up in a table. The learning rate is fixed at... Iteration formula: Box-constrained projection ensures that the update results fall within the hardware's allowable range: , , .right Round the data before projecting it, and truncate any floating-point parameters that overflow.

[0099] To complete optimization within a single frame period, all gradient operations are implemented using a fixed-point multiply-accumulate array. A single complete iteration takes approximately 6000 clock cycles, equivalent to 6 microseconds. The algorithm is set to iterate a maximum of 3 times or with parameter increments less than [a certain value]. The process stops as soon as one of the two arrives, resulting in a total delay of less than 20 microseconds, which will not block the downlink.

[0100] The parameter return phase will Encoded as 10 bytes: 1 byte for the identifier header, and 3 bytes each Q8.16 fixed point The first controller sends an inverse amplitude keying signal using idle pulse intervals. The signal consists of 1 byte for the amplitude keying, 2 bytes for the timestamp, and 1 byte for the cyclic redundancy check. The first controller detects the low-order amplitude pulses and decodes them, then refreshes the chaotic mapping control register and the compressed dimension register.

[0101] Through this invention, before the energy storage drops to a critical value of 15%, the algorithm reduces the compression dimension from 16 to 12, decreases the pulse count by 25%, and reduces the transmission power consumption by approximately 30%. When the keystroke rate increases from 5 characters per second to 15 characters per second, the algorithm reduces the power consumption within 150 milliseconds. Increasing the value by 0.12 improves the randomness of chaos, while maintaining the reconstruction residual within 0.02 mm. Facing 40 concurrent keys, the collision rate decreased from 1.7% to 0.3%. The entire closed loop converges without the need for an external communication protocol, and the parameter frame bandwidth accounts for less than 2%.

[0102] S5. The second controller generates displacement information based on the third data vector, compares it with a preset threshold to generate a key event, and outputs the key event data through the communication interface. If there is no new pulse signal within a preset time period and the key event rate is lower than the threshold, the second controller enters sleep mode. After detecting a new pulse signal, it wakes up and continues to execute step S3.

[0103] Third data vector After orthogonal matching tracking decoding, the result is still in the discrete sparse domain and needs to be converted into a more intuitive physical displacement for the human body. The second controller first checks the preset interpolation. Perform time-series expansion to map the compressed sampling points onto a uniform time axis. Let the discrete-time index be... After unfolding, the sample is obtained. The displacement curve was calculated using a first-order integral filter. ,in Indicates the first Displacement at discrete moments The sampling frequency reported by the first controller. For velocity sample sequences, It is a displacement sequence. This is the frequency parameter. After integration, the curve enters a first-order digital hysteresis loop. The hysteresis constant corresponds to the mechanical spring damping, which can filter out high-frequency glitches caused by button rebound. The second controller determines the event type at the intersection of the curve and the threshold table: falling below the trigger threshold is considered "pressed," and rising above the release threshold is considered "released." The threshold table stores both bottom-out and top-out margins to accommodate different switch feel.

[0104] To avoid boundary jitter, this invention uses dual-threshold hysteresis: the trigger threshold is approximately 6% lower than the release threshold. This prevents multiple events from being generated even when the displacement curve oscillates near the threshold, even in a micro-vibration environment. The event data format consists of a key code (1 byte), event type (1 byte), normalized displacement percentage (1 byte), and energy estimate (2 bytes Q8.8), totaling 5 bytes. The normalized displacement percentage is based on a maximum stroke of 4 mm. Mapped to the 0–255 range, it can be used by upper-level software to implement force sensing.

[0105] The communication interface automatically switches based on hardware configuration. In wired mode, the keyboard cable uses the Universal Serial Bus (USB) human-machine interface protocol; in wireless mode, it uses Bluetooth Low Energy (GATT). Regardless of the protocol, event frames are placed at input endpoint 1 and sent at a minimum interval of 1 millisecond. If the keystroke rate is less than 4 characters per second, the protocol layer automatically widens the interval to 4 milliseconds to reduce wireless power consumption.

[0106] The low-power strategy is implemented in two stages. The first stage is dynamic clock gating: after event processing, the sparse reconstruction unit and vector multiply-accumulate unit are immediately shut down, leaving only the comparator and receive shift register operational. The second stage is deep sleep: if no new pulse has been detected in the past 30 milliseconds and the key event rate in the last second is less than 2 characters per second, the second controller writes to the clock control register, stopping the high-frequency clock domain and leaving only the 32 kHz low-speed oscillator and pulse detection interrupt. At this time, the digital core enters an instantaneous static power consumption of less than 1 microamp. The comparator threshold is maintained, and the conductor line only has a few picoamps of leakage current. When a new pulse arrives, the comparator output flips, triggering the interrupt controller. The clock control module pulls up the high-frequency clock within 50 microseconds, restores the on-chip cache, and re-enters step S3 without resynchronizing the mapping matrix.

[0107] This design delivers three key benefits. First, through vector expansion and integral filtering, the third data vector is transformed into sub-millimeter resolution displacement values. Compared to level-driven keyboards, which can only distinguish binary switches, this invention can output continuous force to games or audio software. Second, dual-threshold hysteresis combined with intra-frame normalized displacement fields ensures that only a single press and release event is generated during high-speed rapid-fire, reducing the need for upper-layer debouncing logic. Third, two-level sleep mode reduces idle power consumption to below milliwatt levels. The keyboard consumes only 4% of its battery in standby mode for 24 hours, comparable to common Bluetooth keyboards, while providing a 1-millisecond report rate in active mode.

[0108] Preferably, when the second controller generates displacement information in step S5, it integrates the third data vector in time sequence to form a displacement curve, and then compares it with a preset displacement threshold table. If the displacement curve intersects any threshold in the displacement threshold table, a corresponding key event is generated.

[0109] Third data vector The second controller uses orthogonal matching to track the velocity sample sequence reconstructed from the compressed domain, where the time interval between each element is equal to the sampling period reported by the first controller in step S1. To transform the velocity sequence into a displacement curve, the second controller... Perform discrete integration; the integration formula is as follows: ,in Indicates the first Cumulative displacement at discrete moments Indicates the sampling frequency. Vector This is the complete displacement curve. To reduce high-frequency disturbances caused by mechanical rebound, this invention adds a first-order digital hysteresis filter after integration, with the filter coefficient... The filtered sequence is determined by the physical damping of the shaft. , . A typical value of 0.85 can suppress jitter by more than 60% without significantly increasing latency.

[0110] Keyboard manufacturers create a displacement threshold table for each type of switch during the factory calibration phase. Trigger threshold Approximately 45% of the total journey, reaching the bottom threshold. Corresponding to 98%, release threshold Approximately 20%. The second controller will, during operation... Perform real-time comparison with the threshold table. If it appears for the first time... Then determine the "press" event; if subsequently Determine if it has "bottomed out"; if the curve then reverses and rises again, and the condition is met for the first time. The system then determines the event to be "lifted". To prevent the displacement curve from oscillating near the threshold and causing repeated events, the system uses a hysteresis window: the difference between the press threshold and the release threshold is 25% of the travel. As long as the curve does not cross another threshold, any local jitter will not trigger the event again.

[0111] Whenever an event occurs, the second controller constructs a 5-byte event message: 1 byte for the key code, 1 byte for the event type, 1 byte for the displacement percentage, 1 byte for the energy estimate (high), and 1 byte for the energy estimate (low). The displacement percentage is determined according to... Multiplying the maximum travel of 4mm by 255 and rounding to the nearest integer provides pressure sensing for operating systems or game engines. The energy estimate, derived from the instantaneous output of the extended Kalman filter, is scaled to Q8.8 fixed-point format and transmitted byte-by-byte. Messages are transmitted in one cycle via the input endpoint of the Universal Serial Bus (USB) HMI or Bluetooth Low Energy (BLE) interface. If the current keystroke rate is greater than 8 characters per second, the message cycle is locked at 1 ms; if the keystroke rate is less than 4 characters per second, the message cycle can be reduced to 4 ms to minimize the chance of wireless retransmissions.

[0112] The system's standby power consumption is determined by the event throttling logic. The second controller maintains a one-second wide circular counting buffer to count the number of events within that window. If no new pulse is detected in the last 30 ms and If the value is less than 5, the chip is determined to enter a low-activity state. The chip then performs two levels of power saving: shutting down the sparse reconstruction vector processing unit and the digital multiply-accumulate array, switching the clock source to a 32 kHz low-speed oscillator, and retaining only the comparator and pulse capture logic. The comparator consumes 3 μA, the oscillator and clock gating consume approximately 2 μA, and the total quiescent current is less than 5 μA. After a new pulse edge appears on the receive line, the interrupt controller pulls up a 24 MHz high-frequency clock domain within 40 μs, restores the buffer pointer, and jumps back to step S3.

[0113] This "integration + threshold + hysteresis + sleep" approach offers multiple technological advantages. First, discrete integration provides sub-millimeter displacement resolution, while traditional keyboards can only identify trigger points using binary methods; combined with the energy recovery characteristics of piezoelectric thick films, the improved resolution does not come with high power consumption. Second, dual-threshold hysteresis suppresses jitter while maintaining sensitivity, reducing latency by 4 ms compared to pure software debouncing. Third, event messages include displacement percentage and energy values, providing direct data for upper-layer applications to implement force mapping and power visualization. Fourth, a circular rate buffer and a two-level power-saving strategy enable the system to automatically adjust power consumption according to the user's pace. In continuous fast typing scenarios, the keyboard can maintain a low latency of 1 ms; in intermittent use scenarios, the standby current is reduced to 1% of the active current.

[0114] Preferably, after entering sleep mode, the second controller retains the low-speed oscillator and pulse detection interrupt line, shuts down all high-speed clock domains and data processing logic, and resets the high-speed clock domain after detecting a new pulse signal that triggers an interrupt, and then sequentially resumes execution of steps S3 to S5.

[0115] The hardware isolation mechanism divides the second controller into a high-speed clock domain and a low-speed clock domain. The high-speed clock domain operates at 24MHz and is used for intensive operations such as quadrature matched pursuit, Kalman filtering, and multi-objective gradient descent. The low-speed clock domain operates at 32kHz and is powered by an on-chip oscillator to maintain minimal operation of the GPIO, comparator, and interrupt controller. When entering a sleep condition—with no new pulses in the last 30ms and a 1s window key event rate of less than 2 per second—the power management unit is triggered. This unit disables the phase-locked loop, digital multiply-accumulate array, vector register file, and dynamic random access memory refresh via a clock gating signal. Simultaneously, it disconnects the power threshold from the analog front-end. To prevent data loss, it writes the third data vector, energy estimate, and iteration parameters of the most recent frame into the static random access memory cache. At this time, only the comparator, low-speed oscillator, and interrupt controller are powered, with a total quiescent current of approximately 5μA.

[0116] In the clock domain reset process, when the pulse signal arrives, if the conductor line voltage exceeds the comparator threshold, the comparator outputs a rising edge to trigger the interrupt controller. The interrupt controller first initiates a phase-locked loop and waits for the lockout time. μs; Simultaneously start the oscillator frequency multiplier, using time μs; then pull the high-speed clock enable bit high, and the clock tree in Stable within μs. The sum of the three delays constitutes the total wake-up delay: , To delay wake-up, This refers to the phase-locked loop locking time. For oscillator frequency doubling delay, This is the clock tree stabilization time. During the wake-up process, the cache controller moves the data from the static random access cache back to the vector register file, ensuring seamless continuation of the sparse reconstruction and energy estimation algorithms. The entire recovery path is automatically completed by the hardware state machine, without relying on firmware polling, thus avoiding firmware stack corruption.

[0117] To maintain data consistency and ensure synchronization between the mapping matrix control parameters and the first controller, the last parameter frame before sleep mode carries a sleep flag. Upon receiving this flag, the first controller pauses chaotic sequence parameter updates, retaining only the piezoelectric charge count. Upon wake-up, the second controller sends back a synchronization confirmation field in the first event frame; the first controller then resumes adaptive parameter updates upon receiving this confirmation. This avoids decoding failures caused by asynchronous updates to the mapping matrix control coefficients at both ends. If the user continuously presses a key during sleep mode, the pulses still trigger interrupts at a low density, thus preventing event loss.

[0118] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A keyboard control method based on dual controllers, characterized in that, Includes the following steps: S1. A sensing unit is set on the button base. The sensing unit outputs a displacement signal and updates the energy storage state when the button is displaced. The first controller conditions and samples the displacement signal to generate a first data vector, and stores it in the memory along with the button number and energy storage state. S2. The first controller generates a mapping matrix based on the button number and energy storage status, transforms the first data vector into a second data vector, and encapsulates it into an event frame by combining the button number. S3. The first controller encodes the event frame into a pulse signal and sends it through a single conductor communication line; The second controller receives the pulse signal and reconstructs the third data vector corresponding to the second data vector according to the mapping matrix. S4. The second controller estimates the system energy based on the energy storage status and communication power consumption, inputs the energy estimation result and the third data vector into the adaptive algorithm, updates the mapping matrix parameters, and returns them to the first controller. S5. The second controller generates displacement information based on the third data vector, compares it with a preset threshold to generate a key event, and outputs the key event data through the communication interface. If there is no new pulse signal within a preset time period and the key event rate is lower than the threshold, the second controller enters sleep mode. After detecting a new pulse signal, it wakes up and continues to execute step S3.

2. The method according to claim 1, characterized in that, When the first controller generates the mapping matrix in step S2, it obtains a pseudo-random sequence through chaotic mapping iteration with the button number and energy storage state as seeds. The pseudo-random sequence is then filled in the mapping matrix in row and column order, and the same pseudo-random sequence is written into the synaptic weight region of the spiking neural network.

3. The method according to claim 2, characterized in that, When encapsulating an event frame, the first controller uses the button number, the second data vector, and the timestamp as the field order, generates a frame verification field by using cyclic redundancy check on the timestamp, and appends the frame verification field to the end of the event frame.

4. The method according to claim 3, characterized in that, In step S3, the first controller encodes the event frame into a pulse signal using a time-jumping pulse-position modulation method. The time jump of the pulse signal is determined by the event frame verification field and the first row element of the mapping matrix, and the pulse amplitude is fixedly limited before transmission.

5. The method according to claim 4, characterized in that, The single conductor communication line is a single conductor line on the keyboard circuit board. The single conductor communication line is connected in series with impedance matching resistors at both ends. The value of the impedance matching resistor is consistent with the characteristic impedance of the single conductor communication line.

6. The method according to claim 1, characterized in that, After receiving the pulse signal in step S3, the second controller first obtains the second data vector by reverse mapping according to the time-jumping pulse position modulation rule, then initializes the sparse support index by taking the maximum correlation coefficient column by column, and then iteratively reconstructs the third data vector through the orthogonal matching pursuit algorithm until the residual size is lower than the preset threshold.

7. The method according to claim 6, characterized in that, In step S4, the second controller uses an extended Kalman filter to perform a fusion estimation of the energy storage state and communication power consumption. The state equation of the extended Kalman filter uses the energy storage state increment as the state variable, and the observation equation uses the communication power consumption measurement value as the observation variable. After each filter update, the energy estimation result is output.

8. The method according to claim 7, characterized in that, The adaptive algorithm is a multi-objective gradient descent algorithm. The multi-objective gradient descent algorithm takes the weighted sum of energy estimation error, keystroke rate prediction error and impulse collision rate as the objective function, it iteratively updates the mapping matrix control parameters and compression dimension at a fixed learning rate, and returns the update result to the first controller after convergence.

9. The method according to claim 1, characterized in that, When the second controller generates displacement information in step S5, it integrates the third data vector in time sequence to form a displacement curve, and then compares it with a preset displacement threshold table. If the displacement curve intersects any threshold in the displacement threshold table, a corresponding key event is generated.

10. The method according to claim 9, characterized in that, After entering sleep mode, the second controller retains the low-speed oscillator and pulse detection interrupt line, shuts down all high-speed clock domains and data processing logic, and resets the high-speed clock domain after detecting a new pulse signal that triggers an interrupt, and then resumes execution of steps S3 to S5 in sequence.

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