Data management method and device, equipment and medium

Abstract

The invention discloses a data management method, a data management device, data management equipment and a medium, relates to the technical field of computers, is applied to a storage system, and is characterized in that an MRAM (Magnetic Random Access Memory), an RRAM (Resistance Random Access Memory) and a master control in the storage system are integrated on a PCB (Printed Circuit Board) substrate after being packaged by a silicon interlayer in a bare chip form; the method comprises the steps of receiving a data management instruction issued by a host; acquiring a target storage address by utilizing the master controller; if the MRAM meets the preset priority execution condition, controlling the MRAM to execute a data management operation corresponding to the data management instruction based on the target storage address; if the MRAM does not meet the preset priority execution condition, controlling the RRAM to execute a data management operation corresponding to the data management instruction based on the target storage address; and returning a data management result generated by the MRAM or the RRAM to the host by utilizing the master control. And the storage capacity and the storage performance are balanced in data management.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to data management methods, apparatus, devices and media. Background Technology

[0002] In today's era of digital information explosion, the demand for data storage is growing exponentially. Enterprise-level storage systems have increasingly stringent requirements for performance, capacity, and stability. Dynamic Random-Access Memory (DRAM) is commonly used for data caching to improve data read and write efficiency. However, DRAM is volatile, increasing system power consumption. Furthermore, capacitors are typically installed on the printed circuit board (PCB) to power the DRAM; however, PCB space is limited, making it increasingly difficult to place a larger number of DRAM chips within that limited space. In the search for solutions to DRAM-related problems, Magnetic Random Access Memory (MRAM), with its unique characteristics, has become a strong competitor to DRAM. MRAM is non-volatile, meaning data is not lost after power is off, a characteristic that gives it a significant advantage in data storage stability.

[0003] However, as the capacity of MRAM continues to increase, some problems have also been exposed. As the capacity increases and the size of the storage array expands, interference and delay issues in the signal transmission process gradually become prominent, leading to a decrease in access speed. This creates an irreconcilable contradiction between capacity and performance in large-capacity application scenarios.

[0004] It is evident that balancing storage capacity and storage performance in data management is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a data management method, apparatus, device, and medium that balances storage capacity and storage performance in data management. The specific solution is as follows:

[0006] In a first aspect, the present invention discloses a data management method applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated on a PCB substrate in bare chip form after being packaged through a silicon interlayer; the method includes:

[0007] Receive data management instructions sent by the host; wherein the data management instructions are data read instructions or data write instructions;

[0008] The main controller is used to obtain the target storage address corresponding to the data management instruction;

[0009] Determine whether the MRAM memory meets the preset priority execution conditions;

[0010] If the MRAM memory meets the preset priority execution condition, then the MRAM memory is controlled to perform a data management operation corresponding to the data management instruction based on the target storage address, and the MRAM memory is controlled to send the generated data management result to the main controller;

[0011] If the MRAM memory does not meet the preset priority execution condition, then the RRAM memory is controlled to perform a data management operation corresponding to the data management instruction based on the target storage address, and the RRAM memory is controlled to send the generated data management result to the main controller;

[0012] The main controller returns the data management results to the host.

[0013] Optionally, the master controller includes an address mapping manager, an NVMe controller, an RRAM controller, and an MRAM controller; obtaining the target storage address corresponding to the data management instruction using the master controller includes:

[0014] The NVMe controller is used to parse and process the data management instructions to obtain processed instructions;

[0015] The address mapping manager is controlled to send the processed instructions to the RRAM controller;

[0016] The RRAM controller reads the target memory address corresponding to the processed instruction from the address mapping table stored in the RRAM memory, and returns the target memory address to the address mapping manager.

[0017] Optionally, determining whether the MRAM memory meets the preset priority execution conditions includes:

[0018] If the data management instruction is a data read instruction, then determine whether the target storage address is located in the MRAM memory;

[0019] If the target memory address is located in the MRAM memory, then the MRAM memory is determined to meet the preset priority execution conditions;

[0020] Accordingly, controlling the RRAM memory to execute the data management operation corresponding to the data management instruction based on the target memory address, and controlling the RRAM memory to send the generated data management result to the main controller, includes:

[0021] Determine whether the target storage address is located in the RRAM memory;

[0022] If the target storage address is located in the RRAM memory, then the RRAM memory is controlled to read the target data at the target storage address, and the RRAM memory is controlled to send the target data to the master controller.

[0023] Optionally, the storage system further includes a NAND Flash memory integrated on the PCB substrate; after determining whether the target storage address is located in the RRAM memory, the method further includes:

[0024] If the target storage address is not located in the RRAM memory, then the target storage address is determined to be located in the NAND Flash memory, and the target data at the target storage address is saved to the RRAM memory;

[0025] The RRAM memory is controlled to send the target data to the main controller.

[0026] Optionally, determining whether the MRAM memory meets the preset priority execution conditions includes:

[0027] If the data management instruction is a data write instruction, then determine whether the amount of data stored in the MRAM memory is greater than a first preset threshold.

[0028] If the amount of data stored in the MRAM memory is not greater than the first preset threshold, then the MRAM memory is determined to meet the preset priority execution condition.

[0029] Accordingly, controlling the RRAM memory to execute the data management operation corresponding to the data management instruction based on the target memory address includes:

[0030] Determine whether the amount of data stored in the RRAM memory is greater than a second preset threshold;

[0031] If the amount of data stored in the RRAM memory is not greater than the second preset threshold, the main controller determines the first address to be written from the RRAM memory and updates the first address to be written to the new target storage address.

[0032] The RRAM memory is controlled to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address based on the target storage mode; wherein, the target storage mode is a single-bit storage mode or a multi-bit storage mode.

[0033] Optionally, the storage system further includes a NAND Flash memory integrated on the PCB substrate; after determining whether the amount of data stored in the RRAM memory is greater than a second preset threshold, the system further includes:

[0034] If the amount of data stored in the RRAM memory is greater than the second preset threshold, the main controller determines the second address to be written from the NAND Flash memory and updates the second address to be written to the new target storage address.

[0035] The NAND Flash memory is controlled to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address.

[0036] Optionally, the MRAM memory is an STT-MRAM memory or a SOT-MRAM memory; wherein, the STT-MRAM memory includes a first transistor and a first magnetic tunnel junction, the first transistor being connected to the free layer of the first magnetic tunnel junction; the SOT-MRAM memory includes a second transistor, a third transistor, a second magnetic tunnel junction and an SOT layer, the second transistor being connected to the fixed layer of the second magnetic tunnel junction, and the third transistor being connected to the SOT layer.

[0037] Secondly, this invention discloses a data management device applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated onto a PCB substrate in bare-chip form after being packaged through a silicon interlayer; the device includes:

[0038] The instruction receiving module is used to receive data management instructions issued by the host; wherein the data management instructions are data read instructions or data write instructions.

[0039] The address acquisition module is used to obtain the target storage address corresponding to the data management instruction using the main control unit;

[0040] The execution judgment module is used to determine whether the MRAM memory meets the preset priority execution conditions;

[0041] The first management module is used to control the MRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address if the MRAM memory meets the preset priority execution condition, and to control the MRAM memory to send the generated data management result to the main controller.

[0042] The second management module is used to control the RRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address if the MRAM memory does not meet the preset priority execution condition, and to control the RRAM memory to send the generated data management result to the main controller.

[0043] The result return module is used to return the data management results to the host using the main controller.

[0044] Thirdly, the present invention discloses an electronic device, comprising:

[0045] Memory, used to store computer programs;

[0046] A processor for executing computer programs to implement the steps of the aforementioned disclosed data management method.

[0047] Fourthly, the present invention discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed data management method.

[0048] Therefore, this invention is applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated on a PCB substrate in bare chip form after being packaged through a silicon interlayer; the method includes: receiving a data management instruction issued by a host; wherein the data management instruction is a data read instruction or a data write instruction; obtaining the target storage address corresponding to the data management instruction using the main controller; determining whether the MRAM memory meets a preset priority execution condition; if the MRAM memory meets the preset priority execution condition, controlling the MRAM memory to execute a data management operation corresponding to the data management instruction based on the target storage address, and controlling the MRAM memory to send the generated data management result to the main controller; if the MRAM memory does not meet the preset priority execution condition, controlling the RRAM memory to execute a data management operation corresponding to the data management instruction based on the target storage address, and controlling the RRAM memory to send the generated data management result to the main controller; and using the main controller to return the data management result to the host.

[0049] The beneficial effects are as follows: The MRAM memory, RRAM memory, and main controller of the storage system of this invention are integrated on the PCB substrate in bare chip form through silicon interlayer packaging. Therefore, this packaging method can shorten the communication distance between the three by means of copper interconnects and silicon vias inside the silicon interlayer, reduce signal transmission latency, and make instruction transmission and data interaction between the main controller and the MRAM and RRAM memories faster. At the same time, by judging whether the MRAM memory meets the preset priority execution conditions, the MRAM memory is used first to perform data management operations, giving full play to the advantage of the fast read and write speed of the MRAM memory. When the MRAM memory does not meet the conditions, the execution is switched to the RRAM memory, using the large capacity of the RRAM memory to make up for the insufficient capacity of the MRAM memory, forming a complementary two-level cache mechanism that balances storage capacity and performance. The main controller is responsible for obtaining the target storage address, coordinating the execution of operations by the MRAM and RRAM memories, and returning the results. Combined with the low latency characteristics brought by the packaging method, the response speed of the entire data management process is faster, improving the efficiency of data management and overall performance, and ensuring that the host can quickly obtain the data management results. Attached Figure Description

[0050] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A flowchart of a data management method provided in an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of a first specific storage system packaging method provided in an embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram of a second specific storage system packaging method provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of a specific STT-MRAM memory provided in an embodiment of the present invention;

[0055] Figure 5 A specific SOT-MRAM memory schematic diagram provided for an embodiment of the present invention;

[0056] Figure 6 A flowchart illustrating a specific data management method provided in this embodiment of the invention;

[0057] Figure 7This is a schematic diagram illustrating the first type of data management result return provided in an embodiment of the present invention;

[0058] Figure 8 This is a schematic diagram illustrating the second type of data management result return provided in this embodiment of the invention;

[0059] Figure 9 A flowchart illustrating another specific data management method provided in this embodiment of the invention;

[0060] Figure 10 A schematic diagram of a specific storage system structure provided in an embodiment of the present invention;

[0061] Figure 11 A schematic diagram of a data management device structure provided in an embodiment of the present invention;

[0062] Figure 12 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0064] In today's era of digital information explosion, the demand for data storage is growing exponentially. Enterprise-level storage systems have increasingly stringent requirements for performance, capacity, and stability. Dynamic Random Access Memory (DRAM) is commonly used for data caching to improve data read / write efficiency. However, DRAM is volatile, increasing system power consumption. Furthermore, capacitors are typically installed on printed circuit boards (PCBs) to power the DRAM; however, PCB space is limited, making it increasingly difficult to place a larger number of DRAM chips within that limited space. In the search for solutions to DRAM-related problems, Magnetic Random Access Memory (MRAM), with its unique characteristics, has become a strong competitor to DRAM. MRAM is non-volatile, meaning data is not lost after power is off, a characteristic that gives it a significant advantage in data storage stability.

[0065] However, as the capacity of MRAM continues to increase, some problems have also been exposed. As the capacity increases and the size of the storage array expands, interference and delay issues in the signal transmission process gradually become prominent, leading to a decrease in access speed. This creates an irreconcilable contradiction between capacity and performance in large-capacity application scenarios.

[0066] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0067] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0068] Next, a data management solution provided by an embodiment of the present invention will be described in detail. Figure 1 A data management method provided by an embodiment of the present invention is applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated on a PCB substrate in bare chip form after being packaged through a silicon interlayer; the method includes:

[0069] Step S11: Receive data management instructions issued by the host; wherein the data management instructions are data read instructions or data write instructions.

[0070] The storage system includes MRAM memory, RRAM memory, a controller, and NAND Flash memory. For example... Figure 2 The diagram shows the first specific storage system packaging method. Traditional packaging methods package MRMA memory, RRAM (Resistive Random-Access Memory) memory, NAND Flash memory and the main controller separately and then integrate them onto the PCB substrate. With the rapid development of artificial intelligence and big data, storage systems face higher performance requirements. This traditional packaging method has exposed obvious limitations. Due to the long interconnect lines on the PCB, the signal will be affected by factors such as resistance, capacitance and inductance during transmission, resulting in signal attenuation and increased delay, which in turn affects the read and write performance of the storage system.

[0071] For example Figure 3The diagram illustrates the second specific storage system packaging method. To overcome the drawbacks of traditional packaging methods, this embodiment interconnects the MRAM memory, RRAM memory, and controller through a silicon interlayer. Specifically, the MRMA and RRAM memories are unpackaged, existing as bare dies. These are then packaged together with the controller's bare die via the silicon interlayer, reducing communication distance, lowering communication latency, and improving read / write performance. The silicon interlayer is then interconnected with the NAND Flash memory via a PCB substrate. The MRMA memory's bare die IO (Input / Output) interface and power interface are connected to the upper interface of the silicon interlayer using micro-bump technology. The silicon interlayer contains numerous copper interconnects, enabling rapid connection between the MRAM memory, RRAM memory, and controller, significantly shortening signal transmission distance and effectively reducing communication latency. Simultaneously, the silicon interlayer also has numerous TSVs (Through-Silicon Vias). Through-Silicon Vias (TSVs) penetrate the silicon interlayer, enabling efficient interconnection between the upper and lower interfaces of the silicon interlayer. In this way, the silicon interlayer not only connects the MRAM memory, RRAM memory, and controller in the horizontal direction, but also establishes a reliable signal transmission path in the vertical direction, further optimizing the signal transmission performance of the entire storage system. The silicon interlayer is then interconnected with the NAND Flash memory through the PCB substrate, ultimately forming a compact and high-performance storage system package structure.

[0072] The storage system also includes a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface. The host issues data management commands, which are specifically data read commands or data write commands. The PCIe interface receives the data management commands issued by the host.

[0073] Step S12: Use the main controller to obtain the target storage address corresponding to the data management instruction.

[0074] In this embodiment, the master controller includes an address mapping manager, an NVMe controller, an RRAM controller, and an MRAM controller. The master controllers interact with each other to enable data exchange between the various memory modules.

[0075] In this embodiment, obtaining the target storage address corresponding to the data management instruction using the master controller includes: parsing and processing the data management instruction using the NVMe controller to obtain a processed instruction; controlling the address mapping manager to send the processed instruction to the RRAM controller; using the RRAM controller to read the target storage address corresponding to the processed instruction from the address mapping table stored in the RRAM memory, and returning the target storage address to the address mapping manager.

[0076] The PCIe interface forwards data management commands to the NVMe controller. The NVMe controller parses and processes these commands to obtain the processed commands. Since RRAM has a large storage capacity, an address mapping table can be stored in it. Therefore, upon receiving the processed command, the corresponding target memory address needs to be found. Specifically, the address mapping manager sends the processed command to the RRAM controller. The RRAM controller reads the target memory address corresponding to the processed command from the address mapping table stored in the RRAM and returns the target memory address to the address mapping manager. In this embodiment, MRAM is used as the first cache; that is, if it is a data write command, it is written to MRAM first, and if it is a data read command, it is read from MRAM first. In this way, the MRAM controller can receive the target memory address so that it can subsequently prioritize performing corresponding data management operations on the MRAM. It should be noted that the address in the data management command is a virtual address, while the target memory address is a physical address. The address mapping table records the physical addresses of the saved data and the virtual addresses corresponding to each physical address.

[0077] Step S13: Determine whether the MRAM memory meets the preset priority execution conditions.

[0078] In this embodiment, the MRAM memory is an STT-MRAM memory or a SOT-MRAM memory; wherein, the STT-MRAM memory includes a first transistor and a first magnetic tunnel junction, the first transistor being connected to the free layer of the first magnetic tunnel junction; the SOT-MRAM memory includes a second transistor, a third transistor, a second magnetic tunnel junction and an SOT layer, the second transistor being connected to the fixed layer of the second magnetic tunnel junction, and the third transistor being connected to the SOT layer.

[0079] The characteristics of MRAM memory are determined by several important parameters, including thermal stability factor, retention time, bit error rate, write current, read / write latency, and endurance. MRAM memory can be either STT-MRAM (Spin-TransferTorque Magnetoresistive Random-Access Memory) or SOT-MRAM (Spin-Orbit Torque Magnetoresistive Random-Access Memory). Both STT-MRAM and SOT-MRAM memory include a magnetic tunnel junction (MTJ). The thermal stability factor (TSF) describes the stability of the magnetization direction in the MTJ. TSF can be adjusted through design parameters such as the size, shape, and material type of the MTJ. Controlling the TSF affects retention time, read / write current, read / write latency, cell size, and read / write energy. A larger TSF value can extend data retention time, but it also increases write latency due to the need for a larger current to change the magnetization direction. Conversely, a lower TSF can shorten write latency, but at the expense of retention time. In this approach, the MRAM retention time can be reduced, write latency reduced, and write current and power consumption reduced by decreasing the thickness of the tunneling layer and the size of the MTJ.

[0080] In a first specific embodiment, for example Figure 4 The diagram shows a specific STT-MRAM memory. The STT-MRAM memory includes one transistor and one magnetic tunnel junction (MTJ), specifically a first transistor T1 and a first magnetic tunnel junction. The first magnetic tunnel junction includes a free layer, a tunneling layer, and a fixed layer. The first transistor T1 is connected to the free layer of the first magnetic tunnel junction. The magnetic tunnel junction is the basic storage cell. The free layer and the fixed layer are magnetic layers. However, the magnetization reversal of the fixed layer is difficult to change, while the magnetization direction of the free layer is easier to change. When the magnetization directions of the magnetic layers are parallel and antiparallel, the resistance exhibits a low-resistance state and a high-resistance state, storing logic "1" and "0". When transistor T1 is turned on, current flows through MTJ. The current interacts with the magnetic layer, causing its magnetism to reverse, thus changing the resistance. Currents with different polarities will result in different reversals.

[0081] In the second specific embodiment, for example Figure 5The diagram illustrates a specific SOT-MRAM memory. The basic storage unit of the SOT-MRAM memory consists of two transistors, one MTJ, and one SOT layer. Specifically, the SOT-MRAM memory includes a second transistor T2, a third transistor T3, a second magnetic tunnel junction, and an SOT layer. The second magnetic tunnel junction also includes a free layer, a tunneling layer, and a fixed layer. The second transistor T2 is connected to the fixed layer of the second magnetic tunnel junction, and the third transistor T3 is connected to the SOT layer. It is important to note that the connection path between the second transistor T2 and the fixed layer is a read path, and the connection path between the third transistor T3 and the SOT layer is a write path. Specifically, when transistor T3... When the SOT-MRAM is turned on, the write current passes through the SOT layer, generating a spin current that enters the free layer, flips the magnetization direction of the free layer, and causes a change in the resistance of the MRAM memory. When the T2 transistor is turned on, a small read current passes through the MTJ to read its resistance state. In this way, the SOT-MRAM read and write paths are separated. Because the SOT-MRAM read and write paths are separated, large write currents will not pass through the tunneling layer, improving the lifespan. Moreover, the write speed is faster than that of STT-MRAM. Using SOT-MRAM as a cache for this memory system can improve the overall read and write performance and lifespan of the system. Higher read and write speeds can be obtained by reducing the thickness of the tunneling layer and the size of the MTJ.

[0082] MRAM memory has a high read and write speed, so it is prioritized as the first cache, meaning that data management operations are performed on MRAM memory first. However, due to the small capacity of MRAM memory, although data management operations are performed on MRAM memory first, data read and write operations cannot be performed on MRAM memory every time. It is necessary to determine whether MRAM memory meets the preset priority execution conditions. The preset priority execution conditions vary depending on the type of data management instruction. However, all preset execution conditions indicate that the MRAM memory currently meets the executable conditions. Specifically, if the data management instruction is a data read instruction, it is necessary to determine whether the target memory address is located in the MRAM memory, that is, whether the target data corresponding to the data read instruction is stored in the MRAM memory. If it does not exist, the target data cannot be read from the MRAM memory. In other words, if the target memory address is not located in the MRAM memory, it means that the MRAM memory does not meet the preset priority execution conditions; if the target memory address is located in the MRAM memory, it means that the MRAM memory meets the preset priority execution conditions. If the data management instruction is a data write instruction, it is necessary to determine whether the MRAM memory can still be written to, and to monitor the amount of data stored in the MRAM memory in real time. If the amount of data stored in the MRAM memory is too large, it means that the MRAM memory does not meet the preset priority execution conditions; if the amount of data stored in the MRAM memory is small, it means that the MRAM memory meets the preset priority execution conditions.

[0083] Step S14: If the MRAM memory meets the preset priority execution condition, then control the MRAM memory to execute the data management operation corresponding to the data management instruction based on the target storage address, and control the MRAM memory to send the generated data management result to the master controller.

[0084] Understandably, when the MRAM memory meets the preset priority execution conditions, a data management operation is performed on the MRAM memory. That is, the MRAM memory is controlled to perform the data management operation corresponding to the data management instruction based on the target memory address. Specifically, if the data management instruction is a data write instruction, the data carried by the data management instruction is written to the storage area corresponding to the target memory address in the MRAM memory, and a data management result indicating that the data write is complete is generated. Then, the data management result is returned to the master controller, specifically to the MRAM controller. If the data management instruction is a data read instruction, the data is read from the storage area corresponding to the target memory address in the MRAM memory, thus obtaining a data management result indicating that the data has been successfully read. Furthermore, the data management result is fed back to the master controller, specifically, the read data is fed back to the MRAM controller.

[0085] Step S15: If the MRAM memory does not meet the preset priority execution condition, then control the RRAM memory to execute the data management operation corresponding to the data management instruction based on the target storage address, and control the RRAM memory to send the generated data management result to the master controller.

[0086] If the MRAM memory does not meet the preset priority execution conditions, the second cache in the storage system, namely the RRAM memory, is activated. This means that the RRAM memory is controlled to perform the data management operation corresponding to the data management instruction based on the target memory address. Specifically, if the data management instruction is a write instruction, the RRAM memory is controlled to write the data carried by the data management instruction into the storage area corresponding to the target memory address, generating a data management result indicating that the data write is complete. This result is then returned to the master controller, specifically feeding back to the RRAM controller. If the data management instruction is a read instruction, data is read from the storage area corresponding to the target memory address in the RRAM memory, resulting in a data management result indicating successful data read. This result is then fed back to the master controller, specifically feeding back the read data to the RRAM controller.

[0087] Step S16: Use the main controller to return the data management result to the host.

[0088] If the data management instruction is a write instruction, the master controller returns the data management result to the host via the PCIe interface. For example, the MRAM controller or RRAM controller might return the data management result to the host via the PCIe interface. Furthermore, if the data management instruction is a write instruction, after the data carried by the instruction is written to the corresponding storage area, the physical address of the data (i.e., its storage address) and the corresponding virtual address are recorded in the address mapping table. In other words, if the data management instruction is a write instruction, the storage address of the target data carried by the instruction is recorded in the address mapping table of the RRAM memory according to the data management result. This way, if the data needs to be read later, the corresponding storage address can be found in the address mapping table to complete the data read operation.

[0089] If the data management instruction is a data read instruction, the master controller can return the data management result to the host in several ways. If the MRAM memory meets the preset priority execution conditions, the MRAM controller returns the data management result to the host through the PCIe interface. If the MRAM memory does not meet the preset priority execution conditions, there are two possible methods: one is that the RRAM controller returns the data management result to the host through the PCIe interface, and the other is that the RRAM controller writes the read data into the MRAM memory, and then the MRAM controller returns the data management result to the host through the PCIe interface.

[0090] It is important to note that the amount of data stored in the MRAM memory is monitored in real time. If the amount of stored data exceeds a third preset threshold, cold data is filtered out from the MRAM memory and migrated to the RRAM memory. The storage address of the cold data is then recorded in the address mapping table of the RRAM memory. Cold data refers to data in the MRAM memory whose access frequency is lower than a fourth preset threshold. Furthermore, because the MRAM memory has a fast read speed, hot data in the RRAM memory can also be migrated to the MRAM memory, and the storage address of the hot data is recorded in the address mapping table of the RRAM memory. Hot data refers to data in the RRAM memory whose access frequency is higher than a fifth preset threshold. In this way, high-frequency access data can be quickly read from the MRAM memory while ensuring that the MRAM memory does not store too much redundant data, allowing data to be written to the MRAM memory quickly.

[0091] The beneficial effects are as follows: The MRAM memory, RRAM memory, and main controller of the storage system of this invention are integrated on the PCB substrate in bare chip form through silicon interlayer packaging. Therefore, this packaging method can shorten the communication distance between the three by means of copper interconnects and silicon vias inside the silicon interlayer, reduce signal transmission latency, and make instruction transmission and data interaction between the main controller and the MRAM and RRAM memories faster. At the same time, by judging whether the MRAM memory meets the preset priority execution conditions, the MRAM memory is used first to perform data management operations, giving full play to the advantage of the fast read and write speed of the MRAM memory. When the MRAM memory does not meet the conditions, the execution is switched to the RRAM memory, using the large capacity of the RRAM memory to make up for the insufficient capacity of the MRAM memory, forming a complementary two-level cache mechanism that balances storage capacity and performance. The main controller is responsible for obtaining the target storage address, coordinating the execution of operations by the MRAM and RRAM memories, and returning the results. Combined with the low latency characteristics brought by the packaging method, the response speed of the entire data management process is faster, improving the efficiency of data management and overall performance, and ensuring that the host can quickly obtain the data management results.

[0092] See Figure 6 This invention discloses a specific data management method. Compared to the previous embodiment, this embodiment further explains and optimizes the technical solution. It is applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated onto a PCB substrate in bare-chip form after being packaged through a silicon interlayer. The method includes:

[0093] Step S21: Receive a data management instruction issued by the host; wherein the data management instruction is a data read instruction or a data write instruction.

[0094] In addition to MRAM, RRAM, and the main controller, the storage system also includes a PCIe interface and an NVMe controller. When the host sends data management commands through the PCIe interface, the NVMe controller receives, parses, and processes the commands.

[0095] Step S22: Use the main controller to obtain the target storage address corresponding to the data management instruction.

[0096] The main control unit includes an address mapping manager, an NVMe controller, an RRAM controller, and an MRAM controller. The address mapping manager interacts with the RRAM controller, reads the address mapping table from the RRAM memory, and looks up the target memory address corresponding to the virtual address in the data management command.

[0097] Step S23: If the data management instruction is a data read instruction, then determine whether the target storage address is located in the MRAM memory; if the target storage address is located in the MRAM memory, then determine that the MRAM memory meets the preset priority execution conditions.

[0098] If the data management instruction is a data read instruction, it is determined whether the target memory address is located in the MRAM memory. That is, the MRAM controller determines whether the target memory address is located in the MRAM memory. It can be understood that if the target memory address is located in the MRAM memory, it means that the data to be read is stored in the MRAM memory, that is, the MRAM memory is determined to meet the preset priority execution condition. If the target memory address is not located in the MRAM memory, it means that the data to be read is not stored in the MRAM memory, that is, the MRAM memory is determined to not meet the preset priority execution condition.

[0099] Step S24: If the MRAM memory meets the preset priority execution condition, then control the MRAM memory to execute the data management operation corresponding to the data management instruction based on the target storage address, and control the MRAM memory to send the generated data management result to the master controller.

[0100] If the MRAM memory meets the preset priority execution conditions, the control MRAM memory reads data from the storage area corresponding to the target storage address and returns the data to the master controller, that is, to the MRAM controller. In other words, the MRAM controller reads the target data from the MRAM memory.

[0101] Step S25: If the MRAM memory does not meet the preset priority execution condition, then control the RRAM memory to execute the data management operation corresponding to the data management instruction based on the target storage address, and control the RRAM memory to send the generated data management result to the master controller.

[0102] In this embodiment, controlling the RRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address, and controlling the RRAM memory to send the generated data management result to the master controller, includes: determining whether the target storage address is located in the RRAM memory; if the target storage address is located in the RRAM memory, controlling the RRAM memory to read the target data at the target storage address, and controlling the RRAM memory to send the target data to the master controller.

[0103] If the MRAM memory does not meet the preset priority execution conditions, it is determined whether the target memory address is located in the RRAM memory. If the target memory address is located in the RRAM memory, it means that the data to be read is stored in the RRAM memory. Then, the RRAM memory is controlled to read the target data at the target memory address, and the RRAM memory is controlled to send the target data to the main controller. Specifically, the target data is sent to the RRAM controller, that is, the RRAM controller is responsible for reading the target data from the RRAM memory.

[0104] In this embodiment, the storage system further includes a NAND Flash memory integrated on the PCB substrate; after determining whether the target storage address is located in the RRAM memory, the method further includes: if the target storage address is not located in the RRAM memory, then determining that the target storage address is located in the NAND Flash memory, and saving the target data at the target storage address to the RRAM memory; controlling the RRAM memory to send the target data to the main controller.

[0105] Furthermore, if the data to be read is neither in the MRAM memory nor the RRAM memory, it means that the data is stored in the NAND Flash memory. The NAND Flash memory is integrated on the PCB substrate. The main controller also includes a Flash controller, which saves the target data at the target storage address in the NAND Flash memory to the RRAM memory. That is, the Flash controller is responsible for reading the target data at the target storage address in the NAND Flash memory and storing it in the RRAM memory, and then controlling the RRAM memory to send the target data to the main controller, specifically by sending the target data to the RRAM controller.

[0106] Step S26: Use the main controller to return the data management result to the host.

[0107] For example Figure 7 The diagram shown illustrates the first type of data management result return. If the MRAM controller acquires the target data, it directly returns the target data to the host via the PCIe interface. However, if the RRAM controller acquires the target data, it needs to store the target data in the MRAM memory first, then read the target data from the MRAM memory and return it to the host via the PCIe interface. This process is suitable for application scenarios with high read speed requirements, making full use of the high-speed read and write characteristics of MRAM.

[0108] For example Figure 8 The second type of data management result return diagram shown indicates that if the MRAM controller obtains the target data, it will directly return the target data to the host through the PCIe interface. If the RRAM controller obtains the target data, it will return the target data to the host through the PCIe interface.

[0109] Therefore, this invention solves the problem of data loss during power outages and enhances stability. By utilizing the non-volatility of MRAM and RRAM to store data and address mapping tables, it avoids the risk of data and address mapping table loss that occurs with DRAM when power is lost. This allows the system to quickly restore the data access path after restarting following an abnormal power outage, greatly enhancing the data stability of the storage system. This invention also optimizes space utilization and reduces design complexity. Because MRAM is non-volatile, it reduces the reliance on supercapacitors for powering DRAM during abnormal power outages. As SSD storage system capacity increases, there is no need to use a large number of high-performance, large-volume capacitors to meet the power supply needs of more DRAM, thus optimizing PCB board space utilization. This not only facilitates the miniaturization and high-density development of storage devices but also reduces the complexity of PCB design and manufacturing, thereby lowering costs.

[0110] See Figure 9 This invention discloses a specific data management method. Compared to the previous embodiment, this embodiment further explains and optimizes the technical solution. It is applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated onto a PCB substrate in bare-chip form after being packaged through a silicon interlayer. The method includes:

[0111] Step S31: Receive a data management instruction issued by the host; wherein the data management instruction is a data read instruction or a data write instruction.

[0112] The storage system includes MRAM memory, RRAM memory, a controller, NAND Flash memory, and a PCIe interface. The controller includes an address mapping manager, an NVMe controller, an RRAM controller, an MRAM controller, and a Flash controller. Data management commands are received through the PCIe interface; specifically, data read commands and data write commands are received through the PCIe interface.

[0113] Step S32: Use the main controller to obtain the target storage address corresponding to the data management instruction.

[0114] The NVMe controller receives and parses the data management instructions to obtain the processed instructions. It then controls the address mapping manager to send the processed instructions to the RRAM controller. The RRAM controller reads the target memory address corresponding to the processed instructions from the address mapping table stored in the RRAM memory and returns the target memory address to the address mapping manager. In other words, the address mapping manager interacts with the RRAM controller to read the address mapping table from the RRAM memory and convert the virtual address into the physical address of the MRAM.

[0115] Step S33: If the data management instruction is a data write instruction, then determine whether the amount of data stored in the MRAM memory is greater than a first preset threshold; if the amount of data stored in the MRAM memory is not greater than the first preset threshold, then determine that the MRAM memory meets the preset priority execution condition.

[0116] During data storage, the storage status of the MRAM memory is monitored in real time, and a judgment is made based on a preset MRAM storage quantity threshold. Specifically, it is determined whether the amount of data stored in the MRAM memory is greater than a first preset threshold. If the amount of data stored in the MRAM memory is not greater than the first preset threshold, that is, the amount of data stored in the MRAM memory is small, then the MRAM memory is determined to meet the preset priority execution condition. Conversely, if the amount of data stored in the MRAM memory is greater than the first preset threshold, that is, the amount of data stored in the MRAM memory is large, then the MRAM memory is determined not to meet the preset priority execution condition.

[0117] Step S34: If the MRAM memory meets the preset priority execution condition, then control the MRAM memory to execute the data management operation corresponding to the data management instruction based on the target storage address, and control the MRAM memory to send the generated data management result to the master controller.

[0118] If the MRAM memory meets the preset priority execution condition, the MRAM controller, after receiving the target storage address, encodes the data to be stored in the MRAM, stores the encoded data in the MRAM memory, writes the target data carried by the data management instruction into the storage area corresponding to the target storage address, generates a data processing result indicating that the data has been written, and returns the data processing result to the MRAM controller, that is, the MRAM controller has completed the data reading.

[0119] Step S35: If the MRAM memory does not meet the preset priority execution condition, then control the RRAM memory to execute the data management operation corresponding to the data management instruction based on the target storage address, and control the RRAM memory to send the generated data management result to the master controller.

[0120] In this embodiment, controlling the RRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address includes: determining whether the amount of data stored in the RRAM memory is greater than a second preset threshold; if the amount of data stored in the RRAM memory is not greater than the second preset threshold, then using the master controller to determine a first address to be written from the RRAM memory and updating the first address to be written to a new target storage address; controlling the RRAM memory to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address based on the target storage mode; wherein, the target storage mode is a single-bit storage mode or a multi-bit storage mode.

[0121] The system determines whether the amount of data stored in the RRAM memory is greater than a second preset threshold. If the amount of data stored in the RRAM memory is not greater than the second preset threshold, the main controller determines the first address to be written from the RRAM memory and updates the first address to be written to the new target storage address. That is, the address mapping manager converts the MRAM address to the RRAM address and controls the RRAM memory to write the target data corresponding to the data management instruction to the storage area corresponding to the target storage address based on the target storage mode. The target storage mode is either a single-bit storage mode (1-bit storage mode) or a multi-bit storage mode (multi-bit mode).

[0122] In this embodiment, the storage system further includes a NAND Flash memory integrated on the PCB substrate; after determining whether the amount of data stored in the RRAM memory is greater than the second preset threshold, the system further includes: if the amount of data stored in the RRAM memory is greater than the second preset threshold, then using the main controller to determine a second address to be written from the NAND Flash memory, and updating the second address to be written to a new target storage address; controlling the NAND Flash memory to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address.

[0123] When the amount of data stored in the RRAM reaches a threshold, the address mapping manager converts the RRAM address to a NAND Flash address. That is, if the amount of data stored in the RRAM exceeds a second preset threshold, the main controller determines a second write address from the NAND Flash memory and updates it to the new target storage address. The RRAM controller and Flash controller collaborate to transmit data to the Flash controller, thereby controlling the NAND Flash memory to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address. Before storing the target data in the NAND Flash memory, the data undergoes encryption, scrambling, and encoding operations sequentially. The encoding uses the LDPC (Low-Density Parity-Check Code) algorithm to further improve the data's error correction and detection capabilities, ensuring long-term stable storage of the data in the NAND Flash. This involves preprocessing the initial data corresponding to the data management instruction to obtain the target data, and then controlling the NAND Flash memory to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address. The preprocessing includes encryption, scrambling, and encoding operations based on the LDPC algorithm.

[0124] Step S36: Use the main controller to return the data management result to the host.

[0125] Therefore, this invention balances the contradiction between capacity and performance, improves overall performance, and constructs a complementary storage architecture. It combines high-speed, low-capacity MRAM with high-capacity, slightly slower RRAM to form a two-level caching mechanism. MRAM acts as the first-level cache for fast data reception and processing, while RRAM acts as the second-level cache to compensate for the insufficient capacity of MRAM and balance the read / write latency difference between MRAM and NAND Flash, thus improving overall storage performance. Optimized data processing flows and designed data write and read flows further enhance system performance. During writes, data migrates rationally between MRAM and RRAM based on thresholds to avoid MRAM write congestion. During reads, the two flows are tailored to different application scenarios, comprehensively improving data processing capabilities and meeting the diverse needs of different business scenarios. Improved MRAM read / write performance is achieved by reducing the tunneling layer thickness and MTJ size to decrease MRAM hold time (holding force), thereby reducing write latency, write current, and power consumption, and increasing MRAM read / write speed to better meet the storage system's requirements for rapid data processing. Extending the lifespan of MRAM memory: When using SOT-MRAM memory, its separate read / write path structure prevents large write currents from passing through the tunneling layer, thus extending the lifespan of SOT-MRAM memory. Simultaneously, its write speed is faster than STT-MRAM memory, further improving the overall read / write performance and stability of the system. Reducing communication latency and improving read / write performance: The silicon interlayer interconnect packaging solution changes the traditional method of separate packaging and integration onto the PCB substrate. It allows MRAM memory, RRAM memory, and the controller to be packaged together in bare die form through a silicon interlayer. Utilizing the copper interconnects and TSVs within the silicon interlayer, the communication distance between components is shortened, effectively reducing signal transmission latency and significantly improving the read / write performance of the storage system. This enables better collaboration with high-performance components such as high-speed processors, fully leveraging the computing and storage potential of the entire system.

[0126] For example Figure 10The diagram illustrates a specific storage system architecture. The storage system includes a PCIe interface, an NVMe protocol controller, NAND Flash memory, a Flash controller, MRMA memory, an MRAM controller, RRAM memory, an RRAM controller, and an address mapping manager. The PCIe interface acts as a bridge between the storage system and the host, receiving data and commands from the host to ensure accurate and efficient data and instruction transmission. It employs high-speed serial communication technology to meet the high bandwidth requirements of enterprise applications. The NVMe protocol controller is responsible for implementing the NVMe (Non-Volatile Memory Host Controller Interface) protocol. It efficiently manages commands, optimizes data transmission processes, and fully leverages the advantages of the NVMe protocol in low latency and high concurrency. Through proper command scheduling and processing, the NVMe protocol controller enables the storage system to maintain high performance even under multi-task concurrent access. The address mapping manager's core function is to translate virtual addresses into physical addresses, a crucial step for accurate data storage and fast access. By maintaining a complex address mapping table, it can quickly locate the actual position of data in the storage medium. The Flash controller is responsible for comprehensive control of the NAND Flash memory. It translates received commands into commands and timing sequences acceptable to the NAND Flash storage, ensuring correct data writing and reading. The Flash controller integrates ECC (Error Correcting Code) and uses the LDPC algorithm for data error correction. The LDPC algorithm has powerful error correction capabilities, effectively correcting errors caused by noise, interference, and other factors during NAND Flash data storage and transmission, improving data reliability. Simultaneously, the Flash controller also includes a PHY (Physical Layer), responsible for handling physical signal transmission with the NAND Flash, ensuring correct data transmission at the electrical layer. MRAM Controller: Tailored to the characteristics of MRAM memory, the MRAM controller precisely controls its command and data transmission. It also integrates an ECC unit and PHY to ensure the correctness and reliable transmission of MRAM data.MRAM controllers are compatible with protocols such as DDR3 (Double Data Rate 3 Synchronous Dynamic Random-Access Memory), DDR4 (Double Data Rate 4 Synchronous Dynamic Random-Access Memory), and LPDDR4 (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory), allowing the storage system to flexibly adapt to different host systems and application scenarios. MRAM memory is responsible for data caching. By reducing the MRAM's hold time (i.e., reducing the hold strength), the write and read speeds of MRAM can be improved. To maintain data correctness, refresh circuitry can be added. Compared to DRAM, MRAM has lower power consumption due to its non-volatility and longer refresh time. Because MRAM memory requires faster read and write speeds, its capacity is smaller. RRAM memory has lower write and read speeds than MRAM memory, but it has the advantage of large capacity and can store large amounts of data. In a storage system, it serves as a secondary cache to compensate for the low retention rate and small capacity of MRAM, while also balancing the read / write latency between MRAM and NAND Flash. The RRAM controller is responsible for controlling the read and write operations of the RRAM memory and includes an ECC cell and a PHY. The basic structure of RRAM memory consists of a transistor and a resistive switching memory (RSM). Storage is achieved by controlling the resistance change through a conductive filament, and it can also store multiple values.

[0127] Figure 11 This is a schematic diagram of a data management device provided in an embodiment of the present invention, applied to a storage system. The MRAM memory, RRAM memory, and main controller in the storage system are integrated onto a PCB substrate in bare-chip form after being packaged through a silicon interlayer. The device includes:

[0128] The instruction receiving module 11 is used to receive data management instructions issued by the host; wherein the data management instructions are data read instructions or data write instructions;

[0129] Address acquisition module 12 is used to acquire the target storage address corresponding to the data management instruction using the main control;

[0130] The execution judgment module 13 is used to determine whether the MRAM memory meets the preset priority execution conditions;

[0131] The first management module 14 is used to control the MRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address if the MRAM memory meets the preset priority execution condition, and to control the MRAM memory to send the generated data management result to the main controller.

[0132] The second management module 15 is used to control the RRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address if the MRAM memory does not meet the preset priority execution condition, and to control the RRAM memory to send the generated data management result to the main controller.

[0133] Result return module 16 is used to return the data management result to the host using the main control.

[0134] The beneficial effects are as follows: The MRAM memory, RRAM memory, and main controller of the storage system of this invention are integrated on the PCB substrate in bare chip form through silicon interlayer packaging. Therefore, this packaging method can shorten the communication distance between the three by means of copper interconnects and silicon vias inside the silicon interlayer, reduce signal transmission latency, and make instruction transmission and data interaction between the main controller and the MRAM and RRAM memories faster. At the same time, by judging whether the MRAM memory meets the preset priority execution conditions, the MRAM memory is used first to perform data management operations, giving full play to the advantage of the fast read and write speed of the MRAM memory. When the MRAM memory does not meet the conditions, the execution is switched to the RRAM memory, using the large capacity of the RRAM memory to make up for the insufficient capacity of the MRAM memory, forming a complementary two-level cache mechanism that balances storage capacity and performance. The main controller is responsible for obtaining the target storage address, coordinating the execution of operations by the MRAM and RRAM memories, and returning the results. Combined with the low latency characteristics brought by the packaging method, the response speed of the entire data management process is faster, improving the efficiency of data management and overall performance, and ensuring that the host can quickly obtain the data management results.

[0135] Furthermore, embodiments of this application also disclose an electronic device, Figure 12 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data management method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0136] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0137] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0138] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the data management method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0139] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned disclosed data management method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0140] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0141] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0142] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0143] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0144] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data management method, characterized in that, Applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated onto a PCB substrate in bare-chip form after being packaged through a silicon interlayer; the method includes: Receive data management instructions sent by the host; wherein the data management instructions are data read instructions or data write instructions; The main controller is used to obtain the target storage address corresponding to the data management instruction; Determine whether the MRAM memory meets the preset priority execution conditions; If the MRAM memory meets the preset priority execution condition, then the MRAM memory is controlled to perform a data management operation corresponding to the data management instruction based on the target storage address, and the MRAM memory is controlled to send the generated data management result to the main controller; If the MRAM memory does not meet the preset priority execution condition, then the RRAM memory is controlled to perform a data management operation corresponding to the data management instruction based on the target storage address, and the RRAM memory is controlled to send the generated data management result to the main controller; The main controller returns the data management results to the host.

2. The data management method according to claim 1, characterized in that, The master controller includes an address mapping manager, an NVMe controller, an RRAM controller, and an MRAM controller; obtaining the target storage address corresponding to the data management instruction using the master controller includes: The NVMe controller is used to parse and process the data management instructions to obtain processed instructions; The address mapping manager is controlled to send the processed instructions to the RRAM controller; The RRAM controller reads the target memory address corresponding to the processed instruction from the address mapping table stored in the RRAM memory, and returns the target memory address to the address mapping manager.

3. The data management method according to claim 1, characterized in that, The step of determining whether the MRAM memory meets the preset priority execution conditions includes: If the data management instruction is a data read instruction, then determine whether the target storage address is located in the MRAM memory; If the target memory address is located in the MRAM memory, then the MRAM memory is determined to meet the preset priority execution conditions; Accordingly, controlling the RRAM memory to execute a data management operation corresponding to the data management instruction based on the target memory address, and controlling the RRAM memory to send the generated data management result to the main controller, includes: Determine whether the target storage address is located in the RRAM memory; If the target storage address is located in the RRAM memory, then the RRAM memory is controlled to read the target data at the target storage address, and the RRAM memory is controlled to send the target data to the master controller.

4. The data management method according to claim 3, characterized in that, The storage system also includes a NAND Flash memory integrated on the PCB substrate; After determining whether the target storage address is located in the RRAM memory, the method further includes: If the target storage address is not located in the RRAM memory, then the target storage address is determined to be located in the NAND Flash memory, and the target data at the target storage address is saved to the RRAM memory; The RRAM memory is controlled to send the target data to the main controller.

5. The data management method according to claim 1, characterized in that, The step of determining whether the MRAM memory meets the preset priority execution conditions includes: If the data management instruction is a data write instruction, then determine whether the amount of data stored in the MRAM memory is greater than a first preset threshold. If the amount of data stored in the MRAM memory is not greater than the first preset threshold, then the MRAM memory is determined to meet the preset priority execution condition. Accordingly, controlling the RRAM memory to perform data management operations corresponding to the data management instructions based on the target memory address includes: Determine whether the amount of data stored in the RRAM memory is greater than a second preset threshold; If the amount of data stored in the RRAM memory is not greater than the second preset threshold, the main controller determines the first address to be written from the RRAM memory and updates the first address to be written to the new target storage address. The RRAM memory is controlled to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address based on the target storage mode; wherein, the target storage mode is a single-bit storage mode or a multi-bit storage mode.

6. The data management method according to claim 5, characterized in that, The storage system also includes a NAND Flash memory integrated on the PCB substrate; After determining whether the amount of data stored in the RRAM memory is greater than the second preset threshold, the method further includes: If the amount of data stored in the RRAM memory is greater than the second preset threshold, the main controller determines the second address to be written from the NAND Flash memory and updates the second address to be written to the new target storage address. The NAND Flash memory is controlled to write the target data corresponding to the data management instruction into the storage area corresponding to the target storage address.

7. The data management method according to any one of claims 1 to 6, characterized in that, The MRAM memory is an STT-MRAM memory or an SOT-MRAM memory; wherein, the STT-MRAM memory includes a first transistor and a first magnetic tunnel junction, the first transistor being connected to the free layer of the first magnetic tunnel junction; the SOT-MRAM memory includes a second transistor, a third transistor, a second magnetic tunnel junction and an SOT layer, the second transistor being connected to the fixed layer of the second magnetic tunnel junction, and the third transistor being connected to the SOT layer.

8. A data management device, characterized in that, Applied to a storage system, wherein the MRAM memory, RRAM memory, and main controller in the storage system are integrated onto a PCB substrate in bare-chip form after being packaged through a silicon interlayer; the device includes: The instruction receiving module is used to receive data management instructions issued by the host; wherein the data management instructions are data read instructions or data write instructions. The address acquisition module is used to obtain the target storage address corresponding to the data management instruction using the main control unit; The execution judgment module is used to determine whether the MRAM memory meets the preset priority execution conditions; The first management module is used to control the MRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address if the MRAM memory meets the preset priority execution condition, and to control the MRAM memory to send the generated data management result to the main controller. The second management module is used to control the RRAM memory to perform a data management operation corresponding to the data management instruction based on the target storage address if the MRAM memory does not meet the preset priority execution condition, and to control the RRAM memory to send the generated data management result to the main controller. The result return module is used to return the data management results to the host using the main controller.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data management method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data management method as described in any one of claims 1 to 7.

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