Communication system based on I2C bus

Abstract

The embodiment of the invention belongs to the technical field of I2C communication, and relates to a communication system based on an I2C bus, and the communication system comprises a host, a first pin of the host is connected with a first pin of a first slave and an input end of an inverter through a serial clock line, and a second pin of the first slave is connected with a second pin of a second slave through a serial clock line; a second pin of the host is connected with a second pin of the first slave and a second pin of the second slave through a serial data line; the output end of the phase inverter is connected with a first pin of the second slave through a serial clock line; and the phase inverter is used for inverting the clock signals received by the first slave and the second slave at the same moment. According to the method and the device, the host interacts with the first slave and the second slave at the same time in one round of communication interaction, so that the communication efficiency based on the I2C bus is improved.

Description

Technical Field

[0001] This application relates to I 2 In the field of C communication technology, this invention particularly relates to an I-based 2 C-bus communication system. Background Technology

[0002] I 2 The C (Inter-Integrated Circuit) bus is a serial communication bus used for communication between integrated circuits. 2 The C-bus provides a simple and efficient communication method for connecting digital integrated circuits and can be found in a variety of electronic devices, such as sensors, memory, and displays. It enables convenient data exchange and control between different devices.

[0003] According to I 2 According to the C protocol, a master device can only communicate with one slave device at a time. If there are other slave devices, the master device can only communicate with multiple slave devices by initiating multiple communication interactions, which reduces I / O efficiency. 2 Communication efficiency of the C bus. Summary of the Invention

[0004] The purpose of this application embodiment is to propose a method based on I 2 A C-bus communication system to solve I 2 The problem of low efficiency in C-bus communication.

[0005] To address the aforementioned technical problems, embodiments of this application provide a method based on I 2 The C-bus communication system adopts the following technical solution:

[0006] The master unit has its first pin connected to the first pin of the first slave unit and the input terminal of the inverter via a serial clock line, and its second pin is connected to the second pin of the first slave unit and the second pin of the second slave unit via a serial data line.

[0007] The output of the inverter is connected to the first pin of the second slave device via a serial clock line;

[0008] The inverter is used to invert the clock signals received by the first slave device and the second slave device at the same time.

[0009] Furthermore, the inverter is a NOT gate or a CMOS inverter.

[0010] Furthermore, when the clock signal is at a high level, the data signal transitions from a high level to a low level. The host pulls the clock signal low and pulls the data signal high and then low to send a start signal to the first slave and the second slave.

[0011] Furthermore, after the host sends the start signal, the host sends the first slave address of the first slave device on the rising edge of the clock signal and the second slave address of the second slave device on the falling edge of the clock signal; wherein, both the first slave address and the second slave address include an address signal and a read / write flag bit, the address signal is used to specify the slave device communicating with the host, the read / write flag bit includes a write flag and a read flag, the data signal corresponding to the write flag is low level, and the data signal corresponding to the read flag is high level.

[0012] Furthermore, after the host sends the first slave address or the second slave address, the host releases the serial data line and reads the acknowledgment signal of the first slave on the rising edge of the clock signal and the acknowledgment signal of the second slave on the falling edge of the clock signal.

[0013] Furthermore, when the read / write flag is set to write and the acknowledgment signal received by the host is low, the host sends the write operation register address to the first slave or the second slave; wherein, the write operation register address is the address of the register in the first slave or the second slave where data will be written.

[0014] Furthermore, when the host receives a low-level response signal from the first slave or the second slave based on the write operation register address, it sends the data to be written to the register corresponding to the write operation register address.

[0015] Furthermore, when the read / write flag is set to read and the acknowledgment signal received by the host is low, the host sends a read operation register address to the first slave or the second slave; wherein, the read operation register address is the address of the register in the first slave or the second slave that will have data read by the host.

[0016] Furthermore, when the host receives a low-level response signal from the first slave or the second slave based on the read operation register address, the host reads the data in the register corresponding to the read operation register address from the first slave on the rising edge of the clock signal, and the host reads the data in the register corresponding to the read operation register address from the second slave on the falling edge of the clock signal.

[0017] Furthermore, when the clock signal is at a high level, the data signal transitions from a low level to a high level. The host pulls the clock signal low and then pulls the data signal low and then high to send an end signal to the first slave and the second slave.

[0018] Compared with the prior art, the embodiments of this application have the following main advantages: the first pin of the host is connected to the first pin of the first slave through a serial clock line, in I 2 An inverter is connected in series on the serial clock line of the C-bus. The master is also connected to the input of the inverter via the serial clock line. The output of the inverter is connected to the first pin of the second slave via the serial clock line. The second pin of the master is connected to the second pin of the first slave and the second pin of the second slave via the serial data line. 2 In the C-bus, devices read data signals on the rising edge of the clock signal, wasting the low-level bandwidth of the falling edge. An inverter inverts the clock signals received by the first and second slave devices simultaneously. When the clock signal received by the first slave device is a falling edge, the clock signal received by the second slave device through the inverter is a rising edge. The master can then utilize the original low-level bandwidth for communication, enabling the master to interact with both the first and second slave devices simultaneously in a single communication cycle, thus improving the efficiency of I-based communication. 2 Communication efficiency of the C bus. Attached Figure Description

[0019] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is an embodiment of the present application based on I 2 A schematic block diagram of the structure of a C-bus communication system;

[0021] Figure 2 This is an embodiment of the present application based on I 2 Timing diagram of the C-bus communication system. Detailed Implementation

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0025] refer to Figure 1 This application proposes a method based on I 2 The C-bus communication system includes: a master, whose first pin is connected to the first pin of the first slave and the input of the inverter via a serial clock line, and whose second pin is connected to the second pin of the first slave and the second pin of the second slave via a serial data line;

[0026] The output of the inverter is connected to the first pin of the second slave device via a serial clock line;

[0027] An inverter is used to invert the clock signals received by the first slave device and the second slave device at the same time.

[0028] Among them, I 2 The C-bus is a serial communication protocol that transmits data via two lines (serial data line SDA and serial clock line SCL). SDA is the signal line used to transmit the actual data. 2 In C-type communication, the master sends data to the slave device or receives data from the slave device via the SDA line. 2 In C / C communication, data is transmitted serially, one bit at a time. SCL is the clock signal line used for synchronous data transmission. In I / O... 2 In C / C communication, the host sends a clock signal via the SCL line to synchronize the data transmission speed and timing. The clock frequency for data transmission is determined by the frequency of the SCL line. 2 The C-bus allows multiple masters and multiple slaves to be connected on the same bus. The master is responsible for initiating communication and control of the bus, while the slaves passively respond to the master's requests.

[0029] Specifically, based on I 2 The C-bus communication system includes a master, a first slave, a second slave, and an inverter. The master, first slave, and second slave each have a first pin and a second pin; the first pin is a clock line pin used to connect to the serial clock line SCL; the second pin is a data line pin used to connect to the serial data line SDA.

[0030] In this application, the first pin of the master is connected to the first pin of the first slave and the input of the inverter via a serial clock line SCL, respectively. The output of the inverter is connected to the first pin of the second slave via the serial clock line SCL. The second pin of the master is connected to the second pin of the first slave and the second pin of the second slave via a serial data line.

[0031] The clock signal sent by the master through SCL is sent to the first slave and the second slave. For the second slave, the clock signal first passes through an inverter before reaching the second slave. The inverter can invert the clock signal, that is, reverse the phase of the input signal by 180°. Therefore, at the same time, the clock signals actually received by the first slave and the second slave are inverted.

[0032] in I 2 In the C-bus, the master reads data signals on the rising edge of the clock signal, thus wasting the low-level bandwidth of the falling edge. Due to the presence of inverters, the clock signals received by the first and second slave devices are inverted at the same time. The clock signal received by the first slave device is the same as the clock signal sent by the master. When the clock signal received by the first slave device is a falling edge, the clock signal actually received by the second slave device through the inverter is a rising edge. The master can utilize this low-level bandwidth for communication. In one round of communication, the master can interact with both the first and second slave devices simultaneously, improving the efficiency of I-based communication. 2 Communication efficiency of the C bus.

[0033] In this embodiment, the first pin of the master is connected to the first pin of the first slave via a serial clock line, in I 2 An inverter is connected in series on the serial clock line of the C-bus. The master is also connected to the input of the inverter via the serial clock line. The output of the inverter is connected to the first pin of the second slave via the serial clock line. The second pin of the master is connected to the second pin of the first slave and the second pin of the second slave via the serial data line. 2 In the C-bus, devices read data signals on the rising edge of the clock signal, wasting the low-level bandwidth of the falling edge. An inverter inverts the clock signals received by the first and second slave devices simultaneously. When the clock signal received by the first slave device is a falling edge, the clock signal received by the second slave device through the inverter is a rising edge. The master can then utilize the original low-level bandwidth for communication, enabling the master to interact with both the first and second slave devices simultaneously in a single communication cycle, thus improving the efficiency of I-based communication. 2 Communication efficiency of the C bus.

[0034] Furthermore, the inverter is a NOT gate or a CMOS inverter.

[0035] Specifically, the inverter in this application can be an existing NOT gate (TTL NOT gate, including input stage, intermediate stage and output stage) or a CMOS inverter (composed of two enhancement-mode MOS field-effect transistors, one of which is an NMOS transistor, called the driver transistor, and the other is a PMOS transistor, called the load transistor). Reference Figure 2 , Figure 2 One embodiment is based on I 2 The timing diagram of the C-bus communication system shows that SCL is the clock signal sent by the master and is also the clock signal actually received by the first slave; the inverted SCL is the clock signal actually received by the second slave; SDA is the data signal sent or received by the master. The clock signal sent by the master is inverted by 180° by the inverter, changing from "1" to "0" or from "0" to "1".

[0036] In this embodiment, the inverter is a NOT gate or a CMOS inverter, which enables the clock signal to be reversed by 180°, ensuring that the clock signals received by the first slave and the second slave at the same time are opposite.

[0037] Furthermore, when the clock signal is at a high level, the data signal transitions from a high level to a low level. The master pulls the clock signal low and then pulls the data signal high and then low again to send a start signal to the first slave and the second slave.

[0038] Specifically, the master first sends a start signal to request the start of communication. When the clock signal is high, the master first causes the data signal to transition from high to low; then, the master pulls the clock signal low and pulls the data signal high and then low again, thereby simultaneously sending start signals to the first slave and the second slave.

[0039] In this embodiment, the host causes the clock signal and data signal to change their levels in a preset manner in order to send a start signal to the first slave and the second slave, thereby initiating communication.

[0040] Furthermore, after the host sends the start signal, the host sends the first slave address of the first slave device on the rising edge of the clock signal and the second slave address of the second slave device on the falling edge of the clock signal. The first slave address and the second slave address both include an address signal and a read / write flag. The address signal is used to specify the slave device that communicates with the host. The read / write flag includes a write flag and a read flag. The data signal corresponding to the write flag is low level, and the data signal corresponding to the read flag is high level.

[0041] Specifically, after the master sends a start signal to the first and second slave devices, the master also needs to send slave addresses, including sending the first slave address on the rising edge of the clock signal and the second slave address on the falling edge of the clock signal. Both the first and second slave addresses include an address signal and read / write flags. The address signal can be 7 bits, and the read / write flag is 1 bit. The address signal is the slave's address, used to specify the slave device communicating with the master; the read / write flag includes a write flag and a read flag. 2 In the C bus, the data signal corresponding to the write flag is low, and the data signal corresponding to the read flag is high.

[0042] In this embodiment, the host sends the first slave address of the first slave device on the rising edge of the clock signal and the second slave address of the second slave device on the falling edge of the clock signal. Both the first slave address and the second slave address include an address signal and a read / write flag. The address signal identifies the slave device that needs to communicate with the host, and the read / write flag indicates whether the host needs to perform a read operation or a write operation, ensuring the smooth progress of the communication process.

[0043] Furthermore, after the host sends the first slave address or the second slave address, the host releases the serial data line and reads the first slave's acknowledgment signal on the rising edge of the clock signal and the second slave's acknowledgment signal on the falling edge of the clock signal.

[0044] Specifically, after the master sends the first slave address or the second slave address, it releases the serial data line and enters a waiting-for-acknowledgment state so that the slave can send an acknowledgment signal. The master reads the acknowledgment signal of the first slave on the rising edge of the clock signal and the acknowledgment signal of the second slave on the falling edge of the clock signal.

[0045] In this embodiment, after the master sends the slave address, it releases the serial data line to wait for the slave's response signal. It reads the first slave's response signal on the rising edge of the clock signal and the second slave's response signal on the falling edge of the clock signal, thus enabling the master to interact with the two slaves simultaneously.

[0046] Furthermore, when the read / write flag is set to write and the acknowledge signal received by the host is low, the host sends the write operation register address to the first slave or the second slave; wherein, the write operation register address is the address of the register in the first slave or the second slave where data will be written.

[0047] Among them, in I 2 In C / C communication, ACK (Acknowledge) and NACK (Not Acknowledge) are two possible acknowledgment signals sent by the slave device to the master device to confirm whether the data bytes sent by the master device have been successfully received.

[0048] When the slave device successfully receives a data byte, it sends an ACK (acknowledgment) signal to the master device, indicating that the data has been successfully received. The ACK signal tells the master device to continue sending more data bytes or to perform read / write operations.

[0049] If the slave device cannot receive data bytes, or does not want to continue receiving more data bytes, it will send a NACK (non-acknowledgment) signal to the master device. The NACK signal tells the master to stop sending data, or indicates some error condition (such as the device is not ready, the address is incorrect, etc.).

[0050] in I 2 In C communication, the ACK signal is set to low level and the NACK signal is set to high level.

[0051] in I 2 In I / O communication, after the master sends a data byte, it waits for the slave to send an acknowledgment signal. If the master receives an ACK signal, it will continue to send more data bytes or perform a read operation. If the master receives a NACK signal, it will take appropriate error handling measures depending on the specific situation, such as retransmitting data bytes, abandoning communication, or executing other error handling procedures. Therefore, ACK and NACK signals are crucial in I / O communication. 2 It plays an important role in C communication, used to achieve reliable data transmission and communication negotiation.

[0052] Specifically, when the read / write flag in the slave address sent by the master is set to write, it indicates that the master intends to perform a write operation on the slave. If the acknowledge signal received by the master is low, the master will then send the write operation register address to either the first or second slave. The write operation register address is the address of the register in the first or second slave that will be written to, indicating which register in the first or second slave the master intends to write to.

[0053] In this embodiment, when the read / write flag is set to write and the acknowledgment signal received by the host is low, the host sends the write operation register address to the first slave or the second slave, thereby indicating which register of the first slave or the second slave the host wants to write to.

[0054] Furthermore, when the host receives a low-level acknowledgment signal from the first or second slave device based on the write operation register address, it sends the data to be written to the register corresponding to the write operation register address.

[0055] Specifically, when the host receives a low-level acknowledgment signal from the first or second slave device based on the write operation register address, the host sends the data to be written to the register corresponding to the write operation register address, and the data to be written will be written to the register corresponding to the register address.

[0056] in I 2 In C / C communication, after the master sends one byte of data, it releases the serial data line and waits for an acknowledgment signal from the slave. If the acknowledgment signal is low, it indicates that the slave has successfully received the previous byte of data, and the master will continue to send the next byte of data until it receives a high-level acknowledgment signal. In this case, the master will retry sending or take other error handling measures.

[0057] Because the master reads the first slave's acknowledge signal on the rising edge and the second slave's acknowledge signal on the falling edge, and sends the data to be written when the acknowledge signal is low, the master communicates on both the high and low bandwidths of the clock signal, improving the I / O-based communication efficiency. 2 Communication efficiency of the C bus.

[0058] In this embodiment, when the master receives a low-level acknowledgment signal from the slave based on the write operation register address, it sends the data to be written to the register corresponding to the write operation register address, thereby realizing the write operation. Furthermore, since the first and second slaves send acknowledgment signals at different clock signal levels, the master can simultaneously perform write operations on both slaves in a single communication interaction, improving the efficiency of I / O-based write operations. 2 Communication efficiency of the C bus.

[0059] Furthermore, when the read / write flag is set to read and the acknowledge signal received by the host is low, the host sends the read operation register address to the first slave or the second slave; wherein, the read operation register address is the address of the register in the first slave or the second slave that will have data read by the host.

[0060] Specifically, when the read / write flag in the slave address sent by the master is set to read, it indicates that the master intends to perform a read operation on the slave. If the acknowledge signal received by the master is low, the master will then send the read operation register address to either the first or second slave. The read operation register address is the address of the register in the first or second slave that will have data read by the master, indicating which register in the first or second slave the master intends to read from.

[0061] In this embodiment, when the read / write flag is set to read and the response signal received by the host is low, the host sends the read operation register address to the first slave or the second slave, thereby indicating which register of the first slave or the second slave the host wants to read.

[0062] Furthermore, when the master receives a low-level response signal from the first slave or the second slave based on the read operation register address, the master reads the data from the register corresponding to the read operation register address from the first slave on the rising edge of the clock signal, and reads the data from the register corresponding to the read operation register address from the second slave on the falling edge of the clock signal.

[0063] Specifically, when the master receives a low-level acknowledgment signal from either the first or second slave device based on the read operation register address, the master initiates a read operation. If the register corresponding to the read operation register address is in the first slave device, the master will read data from the register on the rising edge of the clock signal. If the register corresponding to the read operation register address is in the second slave device, the actual clock signal of the second slave device will rise on the falling edge of the clock signal, and the master will then read data from the register.

[0064] Because the master reads data from the first slave device on the rising edge of the clock signal and data from the second slave device on the falling edge of the clock signal, the master communicates on both the high and low bandwidths of the clock signal, improving the I / O-based communication efficiency. 2 Communication efficiency of the C bus.

[0065] In this embodiment, when the slave device returns a low-level acknowledgment signal based on the read operation register address, the master device reads data from the first slave device on the rising edge of the clock signal, or reads data from the second slave device on the falling edge of the clock signal. This enables the master device to perform read operations on both the first and second slave devices simultaneously during a single communication interaction, improving the efficiency of I / O-based communication. 2 Communication efficiency of the C bus.

[0066] Furthermore, when the clock signal is at a high level, the data signal transitions from a low level to a high level. The master pulls the clock signal low and then pulls the data signal low and then high again to send an end signal to the first slave and the second slave.

[0067] Specifically, the master needs to send an end signal when ending a communication interaction. When the clock signal is high, the master first transitions the data signal from low to high. Then, the master pulls the clock signal low and then pulls the data signal low and then high again to simultaneously send an end signal to both the first and second slave devices.

[0068] In this embodiment, the host causes the clock signal and data signal to change their levels in a preset manner in order to send an end signal to the first slave and the second slave, thereby ending the communication.

[0069] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A method based on I 2 A C-bus communication system, characterized in that, include: The master unit has its first pin connected to the first pin of the first slave unit and the input terminal of the inverter via a serial clock line, and its second pin is connected to the second pin of the first slave unit and the second pin of the second slave unit via a serial data line. The output of the inverter is connected to the first pin of the second slave device via a serial clock line; The inverter is used to invert the clock signals received by the first slave device and the second slave device at the same time.

2. The I-based method according to claim 1 2 A C-bus communication system, characterized in that, The inverter is a NOT gate or a CMOS inverter.

3. The I-based method according to claim 1 2 A C-bus communication system, characterized in that, When the clock signal is high, the data signal transitions from high to low. The host pulls the clock signal low and pulls the data signal high and then low again to send a start signal to the first slave and the second slave.

4. The I-based method according to claim 3 2 A C-bus communication system, characterized in that, After the host sends the start signal, the host sends the first slave address of the first slave device on the rising edge of the clock signal and the second slave address of the second slave device on the falling edge of the clock signal; wherein, both the first slave address and the second slave address include an address signal and a read / write flag bit. The address signal is used to specify the slave device communicating with the host, and the read / write flag bit includes a write flag and a read flag. The data signal corresponding to the write flag is low level, and the data signal corresponding to the read flag is high level.

5. The I-based method according to claim 4 2 A C-bus communication system, characterized in that, After the host sends the first slave address or the second slave address, the host releases the serial data line and reads the acknowledgment signal of the first slave on the rising edge of the clock signal and the acknowledgment signal of the second slave on the falling edge of the clock signal.

6. The I-based method according to claim 5 2 A C-bus communication system, characterized in that, When the read / write flag is set to write and the acknowledgment signal received by the host is low, the host sends the write operation register address to the first slave or the second slave; wherein the write operation register address is the address of the register in the first slave or the second slave where data will be written.

7. The I-based method according to claim 6 2 A C-bus communication system, characterized in that, When the host receives a low-level response signal from the first slave or the second slave based on the write operation register address, it sends the data to be written to the register corresponding to the write operation register address.

8. The I-based method according to claim 5 2 A C-bus communication system, characterized in that, When the read / write flag is set to read and the acknowledgment signal received by the host is low, the host sends the read operation register address to the first slave or the second slave; wherein the read operation register address is the address of the register in the first slave or the second slave that will have data read by the host.

9. The I-based method according to claim 8 2 A C-bus communication system, characterized in that, When the host receives a low-level response signal from the first slave or the second slave based on the read operation register address, the host reads the data in the register corresponding to the read operation register address from the first slave on the rising edge of the clock signal, and the host reads the data in the register corresponding to the read operation register address from the second slave on the falling edge of the clock signal.

10. The I-based system according to claim 1 2 A C-bus communication system, characterized in that, When the clock signal is high, the data signal transitions from low to high. The host pulls the clock signal low and then pulls the data signal low and then high again to send an end signal to the first slave and the second slave.

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