Fingerprint sensor and display device including the same

Abstract

According to an aspect of the present invention, there is provided a fingerprint sensor for a display device and a display device including the same, the fingerprint sensor comprising: a substrate having a first surface and a second surface; a light-transmitting layer including a first layer including at least one first conductive layer and disposed on the first surface of the substrate and having a first opening in the at least one first conductive layer, and a second layer including at least one second conductive layer and disposed on the first surface of the substrate and having a second opening in the at least one second conductive layer, a second opening is formed in the at least one second conductive layer; a light emitting element layer disposed on the first layer and the second layer and having at least one light emitting element; and a sensor layer disposed on the second surface of the substrate and having a light sensor, in which at least a portion of the first opening at least partially overlaps at least a portion of the second opening and has a different size.

Description

[0001] This application is a divisional application of the patent application filed on May 28, 2020, with application number 202010465405.8 and entitled "Fingerprint Sensor and Display Device Including the Fingerprint Sensor". Technical Field

[0002] The invention generally relates to electronic devices, and more specifically, to fingerprint sensors and display devices including the fingerprint sensors. Background Technology

[0003] In recent years, with the widespread use of display devices such as smartphones and tablet PCs, biometric authentication methods using users' fingerprints have also become widely adopted. To provide fingerprint sensing functionality, fingerprint sensors can be provided in the form of embedded parts or attached to display devices.

[0004] For example, a fingerprint sensor can be a sensor using a light-sensing method. A fingerprint sensor may include a light source, a lens, and a light sensor array. Reflected light within the display device can act as noise that interferes with the light sensor array. When such a fingerprint sensor is attached to the display panel along with remedies to reduce light noise, it increases the thickness and manufacturing cost of the display device.

[0005] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] The fingerprint sensor constructed according to the principles and exemplary embodiments of the invention, and the display device including the fingerprint sensor, utilize a light-sensing method that can reduce module thickness and improve reliability. For example, the module thickness of the display device can be reduced by integrally forming a light-transmitting area with the circuit element layer in the fingerprint sensor.

[0007] Furthermore, the fingerprint sensor constructed according to the principles and exemplary embodiments of the invention and the display device including the fingerprint sensor can prevent or reduce the moiré effect that may occur in the fingerprint sensor by adjusting the resolution between the opening portion of the light-shielding layer and the light sensor disposed in the sensor layer.

[0008] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description or may be learned by practice of the inventive concept.

[0009] According to one aspect of the invention, a fingerprint sensor for a display device includes: a substrate having a first surface and a second surface; a light-transmitting layer including a first layer and a second layer, the first layer including at least one first conductive layer and disposed on the first surface of the substrate, and having a first opening in the at least one first conductive layer, the second layer including at least one second conductive layer and disposed on the first surface of the substrate, and having a second opening in the at least one second conductive layer; a light-emitting element layer disposed on the first layer and the second layer, and having at least one light-emitting element; and a sensor layer disposed on the second surface of the substrate, and having a light sensor, wherein at least a portion of the first opening and at least a portion of the second opening are at least partially superimposed and have different dimensions.

[0010] The first and second openings can have a width or diameter between approximately 5 μm and approximately 20 μm.

[0011] The first opening and the second opening may have a generally quadrilateral shape, wherein the width in the first direction and the width in the second direction perpendicular to the first direction are the same or different.

[0012] The width of the first opening can be larger than the width of the second opening.

[0013] The first layer may have a first light-shielding layer to block some of the ambient incident light and allow the remaining ambient incident light to pass through the first opening, and the second layer may have a second light-shielding layer to limit the field of view of the ambient incident light.

[0014] The second layer may include circuit elements to control the emission of light from the at least one light-emitting element.

[0015] The second layer may have: a semiconductor layer including an active pattern of circuit elements; a first gate layer including a gate electrode superimposed on the active pattern; and a source / drain layer including a source electrode and a drain electrode connected to the active pattern.

[0016] The second layer may further include a second gate layer disposed between the first gate layer and the source / drain layers, and includes at least one capacitor electrode.

[0017] The second opening may have multiple opening portions, which are stacked on top of each other among circuit elements disposed in the semiconductor layer, the first gate layer, the second gate layer and the source / drain layer.

[0018] The distance between the semiconductor layer and the source / drain layer can be approximately 300 μm or less.

[0019] The first gate layer may include light emission control lines to supply light emission control signals to circuit elements, the second gate layer may include initialization power lines to supply initialization power to circuit elements, and the source-drain layers may include power lines to apply power to circuit elements.

[0020] The second opening may include multiple layers of openings that are adjacent to and superimposed on the active pattern, the light-emitting control line, the initialization power line, and the power line.

[0021] The fingerprint sensor may also include: a protective layer disposed between the substrate and the sensor layer; and an adhesive layer disposed between the substrate and the protective layer.

[0022] According to another aspect of the invention, a display device includes: a substrate having a first surface and a second surface; a light-transmitting layer disposed on the first surface of the substrate and including a first opening having a first size; a circuit element layer disposed on the first surface of the substrate and including a plurality of conductive layers and a second opening located in the plurality of conductive layers, the second opening having at least a portion overlapping with the first opening and having a second size different from the first size; a light-emitting element layer disposed on the circuit element layer and including at least one light-emitting element; and a sensor layer disposed on the second surface of the substrate and including a light sensor.

[0023] The first and second openings can have a width or diameter between approximately 5 μm and approximately 20 μm.

[0024] The first dimension can have a first width, and the second dimension can have a second width, with the first width being greater than the second width.

[0025] The light-transmitting layer may have: a light-blocking layer that blocks some of the ambient incident light and allows the remaining ambient incident light to pass through the first opening; and a circuit element layer that limits the field of view of the ambient incident light.

[0026] The circuit element layer may include circuit elements to control the light emission of the at least one light-emitting element.

[0027] The circuit element layer may have: a semiconductor layer including an active pattern of circuit elements; a first gate layer including a gate electrode superimposed on the active pattern; a second gate layer disposed on the first gate layer and including at least one capacitor electrode; and a source / drain layer disposed on the second gate layer and including a source electrode and a drain electrode connected to the active pattern.

[0028] The distance between the semiconductor layer and the source / drain layer can be approximately 300 μm or less.

[0029] It will be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0030] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included in this specification and form part of this specification to provide a further understanding of the invention.

[0031] The above and other features of the invention will become more apparent from the description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0032] Figure 1 and Figure 2 This is a block diagram illustrating an exemplary embodiment of a display device constructed according to the principles of the invention;

[0033] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a plan view of an exemplary embodiment of a pixel and a light sensor constructed according to the principles of the invention, showing the relative arrangement of the pixel and the light sensor;

[0034] Figure 4A This is a cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the invention;

[0035] Figure 4B This is a cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention;

[0036] Figure 5 This is a plan view illustrating an exemplary embodiment of a light-shielding layer constructed according to the principles of the invention;

[0037] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a plan view of an exemplary embodiment of a pixel, pinhole, and light sensor constructed according to the principles of the invention, showing the relative arrangement of the pixel, pinhole, and light sensor;

[0038] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view of other exemplary embodiments of a display device constructed according to the principles of the invention;

[0039] Figure 13 This is a circuit diagram illustrating an exemplary embodiment of a representative pixel;

[0040] Figure 14This is a circuit diagram illustrating another exemplary embodiment of a representative pixel;

[0041] Figure 15 It is shown Figure 14 A plan view of an exemplary embodiment of the pixel layout shown;

[0042] Figure 16 It is along Figure 15 A sectional view taken by line I-I'; and

[0043] Figure 17 It is along Figure 15 The sectional view taken from line II-II'. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the specific shape, construction, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0045] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of various details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0046] Crosshairs and / or shading lines are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of the described sequence. Additionally, the same reference numerals denote the same elements.

[0047] When a component or layer is referred to as being "on" another component or layer, "set on" another component or layer, "connected to" or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as being "directly on" another component or layer, "directly set on" another component or layer, "directly connected to" or "directly bonded to" another component or layer, there are no intermediate components or intermediate layers. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without intermediate components. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0049] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in a “sidewall”) may be used herein to describe the relationship of one element to another (or other) elements as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be positioned “above” said other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be positioned otherwise (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to explain the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0051] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the figures will be anticipated due to factors such as manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific shapes shown for the regions, but will include deviations in shape due to factors such as manufacturing. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and this is not necessarily intended to be limiting.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0053] As used herein, "light-transmitting layer" may be abbreviated as "LTL" and refers to a layer comprising one or more light-transmitting aperture array layers (LTHL) and / or one or more light-shielding layers (PHL) as described herein. Exemplary embodiments of the light-transmitting layer may include a single layer (such as a light-transmitting aperture array layer (LTHL) or a circuit element layer (BPL)) or multiple layers (such as a BPL, a first substrate (SUB1), and a PHL).

[0054] As used herein, the terms “width” and “diameter” are used interchangeably when referring to generally circular openings (e.g., pinhole (PIH), first light-transmitting hole (LTH1), second light-transmitting hole (LTH2), and multi-layer opening portion (MLO)).

[0055] In the following description, exemplary embodiments of the invention will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

[0056] Figure 1 and Figure 2 This is a block diagram illustrating an exemplary embodiment of a display device constructed according to the principles of the invention. More specifically, Figure 1 and Figure 2 This is a schematic diagram illustrating a display panel included in a display device according to an embodiment and a driving circuit for driving the display panel. For convenience, in Figure 1 and Figure 2 In this embodiment, the display panel and the driving circuit are separate from each other, but exemplary embodiments of the invention are not limited thereto. More specifically, all or part of the driving circuit can be integrated onto the display panel.

[0057] Reference Figure 1 and Figure 2 The display device 10 includes a display panel 110 and a driving circuit 200 for driving the display panel 110.

[0058] Display panel 110 includes a display area AA and a non-display area NA. The display area AA is an area provided with a plurality of pixels PXL (which may be referred to as sub-pixels) and may be referred to as the effective area. In various embodiments, each of the pixels PXL may include at least one light-emitting element. Display device 10 displays an image on display area AA by driving the pixels PXL corresponding to externally input image data.

[0059] In various exemplary embodiments of the invention, the display area AA may include a sensing area SA. The sensing area SA may include at least some of the pixels PXL disposed in the display area AA.

[0060] In an embodiment, Figure 1 As shown, at least a portion of the display area AA can be set as the sensing area SA. In another example, as... Figure 2 As shown, the entire display area AA can be set as the sensing area SA.

[0061] Although Figure 1 An example is shown in which only one sensing area SA is formed on the display area AA, but exemplary embodiments of the invention are not limited thereto. That is, in various embodiments, multiple sensing areas SA arranged regularly or irregularly can be formed on the display area AA. In such embodiments, the multiple sensing areas SA can have the same or different areas and shapes.

[0062] Furthermore, despite Figure 1 An example is shown in which the sensing region SA is formed in at least a portion of the display region AA, but exemplary embodiments of the invention are not limited thereto. That is, in various embodiments, the display region AA and the sensing region SA may be configured such that only a portion of the display region AA and the sensing region SA overlap.

[0063] The non-display area NA is the area surrounding the display area AA and can be referred to as an inactive area. In various embodiments, the non-display area NA refers to the area on the display panel 110 other than the display area AA. In embodiments, the non-display area NA may include wiring areas, pads (or "solder pads"), various dummy areas, etc.

[0064] In various exemplary embodiments of the invention, the display device 10 may further include a plurality of light sensors PHS disposed in the sensing area SA. In embodiments, the light sensors PHS can sense light emitted from a light source being reflected by a user's finger and analyze the reflected light to sense the user's fingerprint. Exemplary embodiments of the invention will be described below using examples in which the light sensors PHS are used for fingerprint sensing purposes; however, in various embodiments, the light sensors PHS can be used for purposes such as performing various functions of a touch sensor or scanner.

[0065] In various exemplary embodiments of the invention, the light sensor PHS may be disposed within the sensing region SA. The light sensor PHS may be superimposed on at least some or all of the pixels PXL disposed within the sensing region SA, or it may be disposed around the pixels PXL. For example, at least some or all of the light sensor PHS may be disposed between the pixels PXL. (Refer to...) Figures 3A to 3E Various embodiments of the positional relationship between the optical sensor PHS and the pixel PXL are described in more detail.

[0066] In an embodiment where the optical sensor PHS and pixel PXL are arranged adjacent to each other, the optical sensor PHS can use a light-emitting element disposed in at least one pixel PXL as a light source, the at least one pixel PXL being disposed at or around the sensing region SA. In such an embodiment, the optical sensor PHS and the pixel PXL of the sensing region SA (specifically, the light-emitting element disposed in the pixel PXL) together can form a fingerprint sensor used in a photosensitive method. As described above, when the fingerprint sensor of an integrated display device uses pixel PXL as a light source without a separate external light source, the thickness of the fingerprint sensor and the module of the display device including the fingerprint sensor can be reduced, and manufacturing costs can be lowered.

[0067] In various embodiments, the light sensor PHS may be disposed on the rear surface (e.g., the back surface) of the display panel 110 opposite to the surface on which the image is displayed (e.g., the front surface). However, exemplary embodiments of the invention are not limited thereto.

[0068] The driving circuit 200 can drive the display panel 110. For example, the driving circuit 200 can output a data signal corresponding to image data to the display panel 110, or it can output a driving signal for the light sensor PHS and receive a sensing signal received from the light sensor PHS. The driving circuit 200 that receives the sensing signal can use the sensing signal to detect the user's fingerprint pattern.

[0069] In various exemplary embodiments of the invention, the driving circuit 200 may include a panel driver 210 and a fingerprint detector 220. For convenience, in Figure 1 and Figure 2 In this embodiment, the panel driver 210 and the fingerprint detector 220 are separate from each other, but the exemplary embodiments of the invention are not limited thereto. For example, at least a portion of the fingerprint detector 220 may be integrated with the panel driver 210 or may operate in conjunction with the panel driver 210.

[0070] The panel driver 210 can sequentially supply data signals corresponding to image data to the pixels PXL while sequentially scanning the pixels PXL of the display area AA. Then, the display panel 110 can display the image corresponding to the image data.

[0071] In one embodiment, the panel driver 210 may supply a driving signal for fingerprint sensing to the pixel PXL. The driving signal may be provided to cause the pixel PXL to emit light and serve as a light source for the light sensor PHS. In such an embodiment, the driving signal for fingerprint sensing may be provided to the pixel PXL located in a specific area within the display panel 110, for example, the pixel PXL located in the sensing area SA. In various embodiments, the driving signal for fingerprint sensing may be provided by the fingerprint detector 220.

[0072] The fingerprint detector 220 can transmit a drive signal for driving the optical sensor PHS to the optical sensor PHS, and can detect the user's fingerprint based on the sensing signal received from the optical sensor PHS.

[0073] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a plan view of an exemplary embodiment of a pixel and a light sensor constructed according to the principles of the invention, showing the relative arrangement of the pixel and the light sensor. Figures 3A to 3E Different embodiments involving the relative size, resolution, and positional relationship between at least one pixel PXL disposed in the sensing area SA and the light sensor PHS are shown.

[0074] Reference Figure 3A In the sensing area SA, the light sensors PHS can be set at the same resolution (density) as the pixels PXL. In other words, the same number of light sensors PHS as the number of pixels PXL can be set in the sensing area SA. In such an embodiment, the pixels PXL and light sensors PHS can be set to form a 1:1 pair. Figure 3A In one embodiment, the pixel PXL and the light sensor PHS are configured to overlap each other, but in other embodiments, the pixel PXL and the light sensor PHS may be configured not to overlap each other or only a portion of the pixel PXL and the light sensor PHS may overlap each other.

[0075] exist Figure 3A In one embodiment, the light sensor PHS has a size smaller than the pixel PXL, but exemplary embodiments of the invention are not limited thereto. That is, in other embodiments, the light sensor PHS may have the same size as the pixel PXL or may have a size larger than the pixel PXL. Such embodiments are... Figure 3C Shown in.

[0076] Reference Figures 3B to 3E The light sensor PHS can be set in the sensing area SA at a lower resolution than the pixel PXL. In other words, the number of light sensors PHS is smaller than the number of pixels PXL that can be set in the sensing area SA. Figures 3B to 3E The illustration shows an example in which one light sensor PHS is set for every four pixels PXL, but exemplary embodiments of the invention are not limited thereto.

[0077] In such an embodiment, such as Figure 3B and Figure 3E As shown, the light sensor PHS can have a size smaller than the pixel PXL, or as... Figure 3C and Figure 3D As shown, the light sensor PHS can have a size larger than the pixel PXL.

[0078] When the light sensor PHS is set at a resolution lower than that of the pixel PXL, part or all of the light sensor PHS can be set to overlap with the pixel PXL. That is, as Figure 3B and Figure 3C As shown, the light sensor PHS can be partially superimposed on a portion of the pixel PXL.

[0079] Optionally, such as Figure 3D As shown, the light sensor PHS can be disposed between pixels PXL and partially superimposed on pixels PXL. In such an embodiment, as Figure 3D As shown, the light sensor PHS can have a size larger than the pixel PXL. For example, the light sensor PHS can be large enough to cover at least one pixel PXL.

[0080] Optionally, such as Figure 3E As shown, the light sensor PHS may not be stacked with the pixel PXL.

[0081] In various exemplary embodiments of the invention, the relative position between the pixel PXL and the light sensor PHS is not limited to the structure described above. That is, various modifications can be made to the shape, arrangement, relative size, number, resolution, etc. of the pixel PXL and the light sensor PHS in the sensing area SA. Furthermore, in various embodiments, the pixel PXL and the light sensor PHS can be positioned such that... Figures 3A to 3EThe embodiments are configured in one or more combinations thereof.

[0082] in addition, Figures 3A to 3E An example is shown in which the optical sensor PHS is regularly arranged in the sensing area SA, but exemplary embodiments of the invention are not limited thereto. In other embodiments, the optical sensor PHS may be irregularly arranged in the sensing area SA.

[0083] Figure 4A This is a cross-sectional view of an exemplary embodiment of the display device according to the embodiments.

[0084] Reference Figure 4A According to an exemplary embodiment of the invention, the display device 10 may include a display panel 110 and a sensor layer PSL disposed on one surface of the display panel 110. Furthermore, the display device 10 may include a first substrate SUB1 and a circuit element layer BPL, a light-emitting element layer LDL, a first protective layer PTL1, a first adhesive layer ADL1, and a window WIN sequentially disposed on one surface (e.g., the upper surface) of the first substrate SUB1. Additionally, the display device 10 may also include a second adhesive layer ADL2 and a second protective layer PTL2 sequentially disposed on another surface (e.g., the lower surface) of the first substrate SUB1.

[0085] The first substrate SUB1 can be used as the base substrate of the display panel 110 and can be a substantially transparent transmissive substrate. The first substrate SUB1 can be a rigid substrate including glass or tempered glass or a flexible substrate of plastic material. However, the material of the first substrate SUB1 is not limited to these, and the first substrate SUB1 can be made of various materials.

[0086] The first base SUB1 may include, for example: Figure 1 and Figure 2 The diagram shows the display area AA and the non-display area NA. Additionally, the display area AA may include multiple pixel regions PXA in which each pixel PXL is set and / or forms.

[0087] The circuit element layer BPL may be disposed on one surface of the first substrate SUB1 and includes at least one conductive layer. For example, the circuit element layer BPL may include multiple circuit elements forming pixel circuitry for pixel PXL, as well as wiring for supplying various powers and signals to drive pixel PXL. In this case, the circuit element layer BPL may include various circuit elements such as at least one transistor and a capacitor, and multiple conductive layers for constructing wiring connected to the various circuit elements. Furthermore, the circuit element layer BPL may include at least one insulating layer disposed between the multiple conductive layers. Additionally, the circuit element layer BPL may include wiring portions disposed in the non-display area NA of the first substrate SUB1 and supplying powers and signals corresponding to the wiring connected to pixel PXL.

[0088] The light-emitting element layer (LDL) can be disposed on one surface of the circuit element layer (BPL). The LDL may include multiple light-emitting elements (LDs) connected to the BPL via contact holes or the like. In an embodiment, at least one of the multiple light-emitting elements (LDs) may be disposed in each pixel region (PXA).

[0089] Each pixel PXL may include a circuit element disposed in the circuit element layer BPL and at least one light-emitting element LD disposed in the light-emitting element layer LDL above the circuit element layer BPL. A detailed description of a representative structure of pixel PXL will be described below.

[0090] The first protective layer PTL1 can be disposed above the light-emitting element layer LDL to cover the display area AA. The first protective layer PTL1 may include a sealing member such as a thin film encapsulation (“TFE”) or a sealing substrate, and may also include a protective film in addition to the sealing member.

[0091] A first adhesive layer ADL1 is disposed between a first protective layer PTL1 and a window WIN to bond the first protective layer PTL1 to the window WIN. The first adhesive layer ADL1 may include a transparent adhesive such as an optically clear adhesive (“OCA”) and may include various adhesive materials.

[0092] The window WIN is a protective member disposed at the uppermost end of the module of the display device 10, which includes the display panel 110, and can be a substantially transparent transmissive substrate. The window WIN can have a multi-layer structure selected from glass substrates, plastic films, and plastic substrates. The window WIN can include a rigid substrate or a flexible substrate, and there are no particular limitations on the construction materials of the window WIN.

[0093] In various exemplary embodiments of the invention, the display device 10 may further include a polarizing plate and / or a touch sensor layer (touch electrode layer), etc. For example, the display device 10 may further include a polarizing plate and / or a touch sensor layer disposed between the first protective layer PTL1 and the window WIN.

[0094] The second protective layer PTL2 can be disposed on the other surface of the first substrate SUB1. The second protective layer PTL2 can be bonded to the first substrate SUB1 via the second adhesive layer ADL2.

[0095] The second adhesive layer ADL2 can firmly bond (or attach) the first substrate SUB1 to the second protective layer PTL2. The second adhesive layer ADL2 may include a transparent adhesive such as OCA. The second adhesive layer ADL2 may include a pressure-sensitive adhesive (“PSA”) in which the adhesive material functions when pressure is applied for bonding to the bonding surface. When the second adhesive layer ADL2 includes a PSA, the second adhesive layer ADL2 can be bonded to the bonding surface at room temperature by pressure alone, without the need for additional heating or UV processes.

[0096] In an embodiment, the second adhesive layer ADL2 may include a material that absorbs specific light, or it may include a material that blocks specific light. For example, the second adhesive layer ADL2 may include an infrared light absorbing material that absorbs infrared light with high energy density, or it may include an infrared light blocking material that blocks infrared light.

[0097] Infrared light absorbing materials may include, for example, inorganic oxides comprising antimony tin oxide (“ATO”), indium tin oxide (“ITO”), tungsten oxide, carbon black, etc., and metals such as silver (Ag). In the case of inorganic oxides, the infrared light absorbing material can selectively transmit light in the visible light region and absorb infrared light. Furthermore, infrared light absorbing materials may include, for example, organic dyes. Organic dyes may be, for example, dyes used in color filters included in the display panel 110.

[0098] For example, the infrared light blocking material can be at least one selected from mixtures of borates (esters), carbonates (esters), alumina, nitrates (esters), and nitrites (esters). For example, the infrared light blocking material can be selected from lithium borate, potassium borate, magnesium borate, calcium borate, strontium borate, barium borate, and sodium borate (e.g., Na₂B₄O₂). xThe infrared light blocking material may be at least one selected from the following: borosilicate, lithium carbonate, sodium carbonate, potassium carbonate, calcium carbonate (e.g., calcite), dolomite, and magnesite. Furthermore, the infrared light blocking material may be at least one selected from the following: nickel dithiol system, dithiophenol metal coordination compounds, cyanine dyes, squalium dyes, ketone dyes, diimonium dyes, ammonium (organic ammonium) dyes, ammonium (inorganic ammonium) dyes, phthalocyanine dyes, naphthyl phthalocyanine, anthraquinone dyes, naphthoquinone dyes, polymer condensed azopyrrole dyes (pyrrole azo dyes), polymethyst dyes, and acrylic dyes.

[0099] When a user's hand is placed on (or located on) the display surface of the display device 10 (e.g., a surface on which an image is displayed), the display device 10 can perform the function of sensing the user's fingerprint via the optical sensor PHS described below. When external light is input to the display device 10 while sensing the user's fingerprint, the visible light region of the external light is blocked by the user's hand, but infrared light is transmitted through the user's hand and incident on the optical sensor PHS. The infrared light incident on the optical sensor PHS acts as noise, reducing the recognition accuracy of the light reflected from the user's hand.

[0100] When the second adhesive layer ADL2 includes an infrared light absorbing material and / or an infrared light blocking material as described in the above embodiments, even if infrared light from external light passes through the user's hand, the infrared light is absorbed and / or blocked by the second adhesive layer ADL2, thus preventing infrared light from incident on the optical sensor PHS. Therefore, fingerprint recognition accuracy can be improved.

[0101] The second protective layer PTL2 can prevent oxygen and moisture from flowing in from the outside and can be provided in the form of a single layer or multiple layers. The second protective layer PTL2 can be formed as a film to further ensure the flexibility of the display panel 110. The second protective layer PTL2 can be bonded to the sensor layer PSL by another adhesive layer including a transparent adhesive such as OCA.

[0102] In various embodiments, a selective light-blocking film may be further disposed below the second protective layer PTL2. The selective light-blocking film can prevent light from entering the photosensitive sensor PHS of the sensor layer PSL by blocking specific frequency regions (e.g., infrared light) of external light incident on the display device 10. In the above description, the selective light-blocking film is further disposed below the second protective layer PTL2, but exemplary embodiments of the invention are not limited thereto. That is, in another embodiment, when the selective light-blocking film is disposed above the sensor layer PSL, the selective light-blocking film can be disposed as any layer of the display device 10. Furthermore, when the display panel 110 includes an infrared light-blocking component, the selective light-blocking film may be omitted.

[0103] The light-shielding layer PHL can be disposed between the light-emitting element layer LDL and the sensor layer PSL described below. For example, as Figure 4A As shown, the light-shielding layer PHL can be disposed between the first substrate SUB1 and the circuit element layer BPL. The light-shielding layer PHL may include multiple pinholes PIH.

[0104] The display panel 110 can be configured to be transparent in the area where the pinhole PIH is provided, so that reflected light from the fingerprint area of ​​the finger can be transmitted through the pinhole PIH. In addition, in order to reduce the loss of reflected light necessary for fingerprint sensing, the display panel 110 can be configured to allow light satisfying a predetermined field of view ("FOV", or "viewing angle") to be transmitted through each pinhole PIH.

[0105] For example, in an area having a larger area than the pinhole PIH and overlapping the pinhole PIH with the area where each pinhole PIH is provided as the center, the display panel 110 can be formed as transparent. Hereinafter, the area formed as transparent so that reflected light can be transmitted is referred to as the optical opening area (OPA).

[0106] Based on the center of each pinhole PIH, when the field of view of the exemplary range is θ, the thickness of the circuit element layer BPL is q, and the width of the optical opening region OPA formed at the boundary surface of the circuit element layer BPL and the light-emitting element layer LDL is 2p, the condition "2p=2×(q×tanθ)" can be satisfied. In embodiments, the field of view can be an angle ranging from approximately 30 degrees to approximately 60 degrees, for example, approximately 45 degrees, but is not limited thereto.

[0107] The pinhole PIH can have a width w within a predetermined range (e.g., approximately 5 μm to approximately 20 μm), and the width of the optical opening region OPA, taking this into account, can be 2p+w. In this way, as the distance from the light-shielding layer PHL increases (i.e., as the distance from each of the upper and lower portions of the light-shielding layer PHL increases), the width of the optical opening region OPA to be ensured in each layer of the display device 10 can gradually increase.

[0108] The width w (or diameter) of the pinhole PIH can be set to approximately 10 times or more the wavelength of the reflected light, for example, approximately 4 μm or approximately 5 μm or more, to prevent light diffraction. Furthermore, the width w of the pinhole PIH can be set to a size sufficient to prevent image blurring and to more clearly sense the shape of the fingerprint. For example, the width w of the pinhole PIH can be set to approximately 20 μm or less. However, exemplary embodiments of the invention are not limited thereto, and the width w of the pinhole PIH can vary depending on the wavelength of the reflected light and / or the thickness of each layer of the module.

[0109] The distance (or pitch) between adjacent pinhole PIHs can be set by considering the distance between the light-shielding layer PHL and the sensor layer PSL, as well as the wavelength range of the reflected light. For example, when the field of view of the reflected light to be ensured is approximately 45 degrees, the distance between adjacent pinhole PIHs can be set to twice or more the distance between the light-shielding layer PHL and the sensor layer PSL, and can be set to a value equal to or greater than the value obtained by adding a predetermined error range to that distance. In this case, the images observed by the individual light sensors PHS can be prevented from overlapping each other, thereby preventing image blurring.

[0110] A sensor layer PSL is attached to the rear surface (e.g., back surface) of the display panel 110 to overlap with at least one region of the display panel 110. The sensor layer PSL may be configured to overlap with the display panel 110 at least in the display area AA. The sensor layer PSL may include a plurality of light sensors PHS distributed at a predetermined resolution and / or distance. The distance between the light sensors PHS may be set closely such that reflected light from the object to be observed (e.g., a specific area of ​​a finger, such as a fingerprint area) can be incident on at least two adjacent light sensors PHS.

[0111] The optical sensor PHS in the sensor layer PSL can output an electrical signal corresponding to the reflected light received through the pinhole PIH as a sensing signal. Depending on whether the reflected light is due to valleys or ridges formed on the user's fingerprint, the reflected light received by each optical sensor PHS can have different optical characteristics (e.g., frequency, wavelength, size, etc.). Therefore, each of the optical sensors PHS can output a sensing signal with different electrical characteristics corresponding to the optical characteristics of the reflected light. The sensing signal output by the optical sensor PHS can be converted into image data and used for the user's fingerprint recognition.

[0112] As described above, the display device 10 includes a fingerprint sensor comprising a light-emitting element layer (LDL), a sensor layer (PSL), and a light-shielding layer (PHL). The LDL may include a light-emitting element (LD) that can also be used as a light source for a light-sensing method sensor. The PSL may include a light sensor (PHS) that receives light emitted from the LDL and reflected from an object located above the display device 10 (e.g., the fingerprint area of ​​a finger). The PHL may include a pinhole (PIH) disposed between the LDL and the PSL to selectively transmit reflected light.

[0113] According to an embodiment, the fingerprint sensor may further include an optical opening region (OPA) formed inside the display panel 110, etc., to reduce the loss of reflected light incident on each pinhole pinhole (PIH) within a predetermined field of view. Furthermore, the fingerprint sensor may include a light control layer disposed inside the display panel 110 to control the light path, thereby facilitating field of view control. Reference will be made below. Figures 9 to 12C Various embodiments of the optical control layer are described.

[0114] On the other hand, the display device 10 also utilizes the light-emitting element LD of the pixel PXL as the light source for the fingerprint sensor, but exemplary embodiments of the invention are not limited thereto. For example, the display device according to another embodiment may have a separate light source for fingerprint sensing.

[0115] The fingerprint sensing method of the display device 10 according to the above embodiment will now be briefly described. During the fingerprint sensing period when the light sensor PHS is activated, while the user's finger (e.g., the fingerprint area) is in contact with or near the display area AA, pixels PXL (specifically, light-emitting elements LD included in pixels PXL) of the display area AA may emit light. For example, during the fingerprint sensing period, all pixels PXL of the display area AA may emit light simultaneously or sequentially. Optionally, among the pixels PXL of the display area AA, only some pixels PXL may emit light at predetermined intervals, or selectively, some pixels PXL may emit light of a specific color (e.g., light with a short wavelength such as blue light).

[0116] Some of the light emitted from the pixel PXL can be reflected by the user's finger and pass through the optical opening regions OPA and pinhole PIH formed in the various layers of the display device 10, so as to be incident on the light sensor PHS. At this time, the user's fingerprint shape (fingerprint pattern) can be detected based on the difference in the amount of reflected light and / or the waveform of the reflected light reflected from the ridges and valleys of each fingerprint.

[0117] Figure 4B This is a cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention. Figure 4B In the middle, the above will be omitted. Figure 4A Detailed descriptions of the same or similar constructions in the embodiments are provided to prevent redundancy.

[0118] Reference Figure 4B The display panel 110 includes a second protective layer PTL2. The second protective layer PTL2 may include a substrate layer BSL and a first coating COL1 and a second coating COL2 formed on the lower and upper surfaces of the substrate layer BSL, respectively.

[0119] The base layer BSL can be formed in the form of a plastic film comprising at least one organic film. For example, the plastic film can be manufactured by at least one of thermoplastic polymer resins (such as polycarbonate (“PC”), polyimide (“PI”), polyethersulfone (“PES”), polyarylate (“PAr”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), cyclic olefin copolymers, epoxy resins), thermosetting polymer resins (such as unsaturated polyester, phenolic resin (PF), silicone, polyurethane), etc.

[0120] In this embodiment, the material of the substrate layer BSL is not limited to the materials described above. The material of the substrate layer BSL can be selected from materials capable of protecting the layers disposed thereon, depending on the design requirements of the display panel 110. According to this embodiment, the substrate layer BSL may also include the same material as the infrared light absorbing material and / or infrared light blocking material included in the second adhesive layer ADL2 of the display device 10.

[0121] Either the first coating COL1 or the second coating COL2 may be coated with an infrared light reflecting and blocking material, and the other may be coated with an infrared light absorbing material. For example, the first coating COL1 may be a layer on which a mixture of infrared light absorbing materials is applied (or coated), and the second coating COL2 may be a layer on which a mixture of infrared light reflecting and blocking materials is applied (or coated). Examples of infrared light reflecting and blocking materials may include titanium oxide (TiO2), magnesium fluoride (MgF2), etc., but exemplary embodiments of the invention are not limited thereto.

[0122] As described above, when the second protective layer PTL2 includes infrared light reflecting and / or blocking materials as well as infrared light absorbing materials, the infrared light will not be incident on the sensor layer PSL even if infrared light from external light is transmitted through the user's hand, due to the second protective layer PTL2 located above the sensor layer PSL. Therefore, the optical sensor PHS can more accurately identify the user's fingerprint without interference from external light.

[0123] According to an embodiment, infrared light can be blocked by configuring some structures of the display panel 110 (e.g., the second adhesive layer ADL2 and / or the second protective layer PTL2) to include infrared light absorbing materials and / or infrared light blocking materials, without adding separate components such as infrared light blocking films. Therefore, the manufacturing cost of the display device 10 can be reduced, and the thickness of the display device 10 can be further reduced.

[0124] The light-shielding layer PHL will be described in more detail below.

[0125] Figure 5This is a plan view illustrating an exemplary embodiment of a light-shielding layer constructed according to the principles of the invention.

[0126] Reference Figure 5 The light-shielding layer PHL may include a light-shielding mask LBM and multiple pinhole PIHs distributed in the light-shielding mask LBM.

[0127] Light-shielding masks (LBMs) ​​can be formed from light-blocking and / or light-absorbing materials. For example, a light-shielding mask LBM can be formed from an opaque metal layer (conductive layer) with localized openings in the region where each pinhole (PIH) is provided. However, the construction materials of light-shielding mask LBMs are not limited to metals, and light-shielding mask LBMs can be formed from various materials capable of blocking light transmission. For example, light-shielding mask LBMs can be formed from currently known black matrix materials.

[0128] Pinhole PIHs can be openings dispersed within a light-shielding mask LBM. Pinhole PIHs can be dispersed in regular or irregular patterns within the light-shielding mask LBM, with a defined size and spacing.

[0129] exist Figure 5 In the embodiments described, the pinhole PIH is shown as having a generally rectangular shape, but exemplary embodiments of the invention are not limited thereto. That is, in various embodiments, the pinhole PIH can have various shapes such as generally rectangular, circular, elliptical, and polygonal shapes. However, exemplary embodiments of the invention are not limited thereto, and the size, shape, number, resolution, and / or arrangement of the pinhole PIH can be varied.

[0130] The light-shielding layer PHL can be set Figures 1 to 4B The light-emitting element layer LDL, in which a light-emitting element LD is disposed, and the sensor layer PSL, in which a light sensor PHS is disposed, are located. The light-shielding layer PHL can form an optical system for selectively transmitting only some light while blocking the remaining light.

[0131] The light-shielding layer PHL can be formed together with the aforementioned light sensor PHS to create a fingerprint sensor. Furthermore, the light-shielding layer PHL can be integrally formed with the circuit element layer BPL of the display panel 110. In this case, the thickness of the fingerprint sensor and the display device including the fingerprint sensor can be reduced or minimized.

[0132] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a plan view illustrating an exemplary embodiment of the pixel, pinhole, and light sensor constructed according to the principles of the invention, showing the relative arrangement of the pixel, pinhole, and light sensor. Specifically, Figures 6A to 6D It shows the setting involved Figures 1 to 4BDifferent embodiments of the relative size, resolution, and / or setup relationship of the pixel PXL, pinhole PIH, and light sensor PHS in the sensing area SA.

[0133] Reference Figure 6A The sensing area SA may include a smaller number of pinhole PIHs and light sensors PHS than the number of pixels PXL. Furthermore, the pinhole PIHs and light sensors PHS may have a smaller size than the pixel PXL and may be distributed within the sensing area SA at a lower resolution than the pixel PXL.

[0134] On the other hand, despite Figure 6A An embodiment is shown in which the number of pinhole PIHs and light sensors PHS is less than the number of pixels PXL, but exemplary embodiments of the invention are not limited thereto. That is, in another embodiment, pinhole PIHs and light sensors PHS may be distributed in substantially the same number and at a distance in the sensing area SA, corresponding one-to-one. For example, pinhole PIHs and light sensors PHS may be configured to be stacked on top of each other in pairs. According to embodiments, a pair of pinhole PIHs and light sensors PHS may be configured to be stacked with any one of the pixels PXL disposed in the sensing area SA, but exemplary embodiments of the invention are not limited thereto. For example, pinhole PIHs and light sensors PHS may be alternately configured not to be stacked with each other, or may be configured not to be stacked with pixels PXL.

[0135] The pinhole PIH and the optical sensor PHS can have the same or different dimensions. That is, there are no particular restrictions on the relative size and resolution of the pinhole PIH and the optical sensor PHS.

[0136] Reference Figure 6B The sensing area SA may include a smaller number of pinhole PIHs than the number of pixels PXL and a larger number of light sensors PHS than the number of pixels PXL. Furthermore, the pinhole PIHs and light sensors PHS may have a smaller size than the pixel PXL, the pinhole PIHs may be distributed in the sensing area SA at a lower resolution than the pixel PXL, and the light sensors PHS may be densely distributed in the sensing area SA at a higher resolution than the pixel PXL.

[0137] At least a portion of the light sensor PHS may be stacked with any of the pinhole PIH and / or any of the pixels PXL, but exemplary embodiments are not limited thereto. For example, a portion of the light sensor PHS may be configured to be stacked with the pinhole PIH and / or the pixels PXL, while other light sensors PHS may be disposed in the gaps between the pixels PXL.

[0138] Reference Figure 6C and Figure 6DThe optical sensor PHS can be distributed in the sensing area SA to form a structure with a higher density than... Figure 6B The optical sensor PHS of the embodiment shown has a smaller size and is smaller than that of the PHS. Figure 6B The light sensor PHS in the illustrated embodiment has a high resolution. For example, multiple light sensors PHS can be stacked with each pinhole PIH and / or pixel PXL. On the other hand, the pinhole PIHs can be distributed in the sensing area SA with the same or different resolution as the pixel PXL. For example, as Figure 6C As shown, the pinhole PIH can be distributed in the sensing area SA at the same resolution as the pixel PXL, or as... Figure 6D As shown, the pixels can be distributed in the sensing area SA at a resolution lower than that of the pixel PXL.

[0139] Figures 6A to 6D An embodiment in which the pinhole PIH and the optical sensor PHS are arranged in a regular array within the sensing region SA is shown, but exemplary embodiments of the invention are not limited thereto. That is, the pinhole PIH and / or the optical sensor PHS may be irregularly dispersed within the sensing region SA, or may be distributed with different densities or arrangement structures depending on each region or portion of the sensing region SA.

[0140] The positional relationship between the pixel PXL, the pinhole PIH, and the light sensor PHS is not limited to... Figures 6A to 6D The embodiments shown are illustrated. For example, the shape, arrangement type, relative size, number, resolution, and / or mutual arrangement relationship of the pixel PXL, pinhole PIH, and / or light sensor PHS can be varied.

[0141] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention. Figures 7 to 12C In the middle, the references above will be omitted. Figures 1 to 6D The description provides a detailed description of at least one embodiment that is identical or similar to the one described in the description, in order to prevent redundancy.

[0142] Reference Figure 7 The display panel 110 may further include a second substrate SUB2 disposed on one surface (e.g., the lower surface) of the first substrate SUB1. The second substrate SUB2 may be disposed between the first substrate SUB1 and the sensor layer PSL. In such an embodiment, a barrier layer BRL may be disposed between the first substrate SUB1 and the second substrate SUB2.

[0143] The second substrate SUB2 can be formed of the same or different material as the first substrate SUB1. For example, both the first substrate SUB1 and the second substrate SUB2 can be thin film substrates of polyimide (“PI”) material. Optionally, the first substrate SUB1 and the second substrate SUB2 can be heterogeneous substrates comprising different materials. The second substrate SUB2 can include at least one material of the structural material previously referred to as the first substrate SUB1, and can be formed of various other materials.

[0144] Barrier layers (BRLs) can be provided in the form of a single layer or multiple layers. For example, a barrier layer (BRL) can be formed from a structure in which ten or more inorganic insulating layers are stacked.

[0145] Reference Figure 8 The circuit element layer BPL may include a first light-transmitting aperture array layer LTHL1 disposed in the sensing region SA. For example, the first light-transmitting aperture array layer LTHL1 may include a plurality of first light-transmitting apertures LTH1 distributed in the circuit element layer BPL. In such an embodiment, the first light-transmitting aperture array layer LTHL1 may be used instead of the light-shielding layer PHL. That is, the first light-transmitting apertures LTH1 may be used as pinholes PIH.

[0146] When Figure 8 As shown, when a pinhole PIH is formed by using multiple first light-transmitting holes LTH1 distributed in the circuit element layer BPL without a separate light-shielding layer PHL, the separate mask process for forming the light-shielding layer PHL can be omitted. Furthermore, according to... Figure 8 The display device 10 of the embodiment shown can prevent the increase in thickness caused by the separate setting of the light-shielding layer PHL, thereby reducing manufacturing costs and increasing process efficiency.

[0147] Furthermore, when such Figure 8 When the pinhole PIH shown is set in the circuit element layer BPL, due to the reference Figure 4A The distance between the described pinhole PIH and the optical aperture region OPA is reduced, so the width of the optical aperture region OPA can be reduced. Then, since the size of the pixel region PXA can be reduced, a high-resolution display device 10 can be realized.

[0148] Reference Figure 9 and Figure 10 The circuit element layer BPL may include a first light-transmitting aperture array layer LTHL1 comprising a plurality of first light-transmitting apertures LTH1. Furthermore, a light-shielding layer PHL comprising a plurality of pinhole PIHs may be disposed between the first substrate SUB1 and the circuit element layer BPL. Each first light-transmitting aperture LTH1 and each pinhole PIH is configured such that they are at least partially stacked.

[0149] In various exemplary embodiments of the invention, the first light-transmitting aperture LTH1 and the pinhole PIH may have the same or different sizes. For example, as Figure 9 As shown, the first light-transmitting aperture LTH1 can have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH. For example, the pinhole PIH and the first light-transmitting aperture LTH1 can have widths (or diameters) ranging from about 5 μm to about 20 μm, and the first light-transmitting aperture LTH1 can have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH.

[0150] In an embodiment, when the pinhole PIH and the first light-transmitting aperture LTH1 have a generally rectangular shape, the length of the first side of the pinhole PIH can be approximately 8.5 μm, and the length of the second side perpendicular to the first side can be approximately 9.4 μm. Furthermore, in such an embodiment, the length of the first side of the first light-transmitting aperture LTH1 can be approximately 4.5 μm, and the length of the second side perpendicular to the first side can be approximately 5.4 μm. These values ​​are merely examples, and exemplary embodiments of the invention are not limited thereto.

[0151] In embodiments where the first light-transmitting aperture LTH1 has a size smaller than that of the pinhole PIH, the first light-transmitting aperture array layer LTHL1 can perform the function of a light control layer LBL that controls the path of light (e.g., limiting the field of view of reflected light to a predetermined angular range), and the light-shielding layer PHL can perform the function of blocking light.

[0152] like Figure 10 As shown, the first light-transmitting aperture LTH1 can have a width (or diameter) larger than the width (or diameter) of the pinhole PIH. In such an embodiment, the first light-transmitting aperture array layer LTHL1 can perform a light-blocking function, and the light-shielding layer PHL can perform the function of a light control layer LBL that controls the path of light.

[0153] Reference Figure 11 The circuit element layer BPL may include a first light-transmitting aperture array layer LTHL1 comprising a plurality of first light-transmitting apertures LTH1. Furthermore, a light-shielding layer PHL comprising a plurality of pinhole PIHs may be disposed between the first substrate SUB1 and the second substrate SUB2. Each first light-transmitting aperture LTH1 and each pinhole PIH are configured such that they are at least partially stacked.

[0154] In various exemplary embodiments of the invention, the first light-transmitting aperture LTH1 and the pinhole PIH may have the same or different dimensions. For example, the first light-transmitting aperture LTH1 may have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH. In such embodiments, the first light-transmitting aperture array layer LTHL1 may function as a light control layer LBL that controls the path of light, and the light-shielding layer PHL may function as a light-blocking layer.

[0155] Reference Figures 12A to 12C The first substrate SUB1 may have a first surface FS and a second surface SS. The circuit element layer BPL may include a light-transmitting aperture array layer LTHL disposed in the sensing region SA. The light-transmitting aperture array layer LTHL may be formed by multiple layers. For example, the light-transmitting aperture array layer LTHL may include a first light-transmitting aperture array layer LTHL1 containing a first light-transmitting aperture LTH1 and a second light-transmitting aperture array layer LTHL2 containing a second light-transmitting aperture LTH2. The first light-transmitting aperture array layer LTHL1 may be a first layer (e.g., a first conductive layer) of the circuit element layer BPL, and the second light-transmitting aperture array layer LTHL2 may be a second layer (e.g., a second conductive layer).

[0156] The first light-transmitting aperture LTH1 and the second light-transmitting aperture LTH2 can be stacked on top of each other. The first light-transmitting aperture LTH1 and the second light-transmitting aperture LTH2 can have the same or different sizes.

[0157] For example, such as Figure 12A As shown, the first light-transmitting aperture LTH1 and the second light-transmitting aperture LTH2 can have substantially the same width (or diameter) and can be arranged to overlap each other. In such an embodiment, the first light-transmitting aperture LTH1 and the second light-transmitting aperture LTH2 can form a multi-layered pinhole PIH structure. For example, the first light-transmitting aperture LTH1 can form a first pinhole PIH1 disposed in the first layer of the circuit element layer BPL, and the second light-transmitting aperture LTH2 can form a second pinhole PIH2 disposed in the second layer of the circuit element layer BPL. In this case, the first light-transmitting aperture array layer LTHL1 including the first light-transmitting aperture LTH1 and the second light-transmitting aperture array layer LTHL2 including the second light-transmitting aperture LTH2 can form a multi-layered light-shielding layer PHL.

[0158] like Figure 12B As shown, the first light-transmitting aperture LTH1 can have a smaller size than the second light-transmitting aperture LTH2. In such an embodiment, the first light-transmitting aperture array layer LTHL1, including the first light-transmitting aperture LTH1, can perform the function of a light control layer LBL that controls the path of light, and the second light-transmitting aperture array layer LTHL2, including the second light-transmitting aperture LTH2, can replace the light-shielding layer PHL that performs the function of blocking light.

[0159] like Figure 12C As shown, the first light-transmitting aperture LTH1 can have a larger size than the second light-transmitting aperture LTH2. In such an embodiment, the first light-transmitting aperture array layer LTHL1, including the first light-transmitting aperture LTH1, can replace the light-shielding layer PHL that performs the light-blocking function, and the second light-transmitting aperture array layer LTHL2, including the second light-transmitting aperture LTH2, can perform the function of the light control layer LBL that controls the path of light.

[0160] Figure 13This is a circuit diagram illustrating an exemplary embodiment of a representative pixel. Figure 13 For ease of description, an active pixel is shown that is connected to the i-th (i is a natural number) scan line Si disposed in the i-th horizontal pixel row and the j-th (j is a natural number) data line Dj disposed in the j-th vertical pixel column, and includes two transistors. However, the structure of pixel PXL in the exemplary embodiments of the invention is not limited to... Figure 13 The structure shown.

[0161] Reference Figure 13 The pixel PXL may include a first transistor M1, a second transistor M2, a storage capacitor Cst, and a light-emitting element LD.

[0162] A first transistor M1 (driving transistor) is connected between the j-th data line Dj and the first node N1, and the gate electrode of the first transistor M1 is connected to the i-th scan line Si. When a scan signal with a gate turn-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the first transistor M1 is turned on. When the first transistor M1 is turned on, the j-th data line Dj and the first node N1 can be electrically connected to each other.

[0163] A second transistor M2 (switching transistor) is connected between the first power supply ELVDD and the light-emitting element LD, and the gate electrode of the second transistor M2 is connected to the first node N1. The second transistor M2 controls the amount of current supplied from the first power supply ELVDD to the second power supply ELVSS through the light-emitting element LD, corresponding to the voltage of the first node N1. In various embodiments, the first power supply ELVDD can be a high-potential pixel power supply, and the second power supply ELVSS can be a low-potential pixel power supply.

[0164] The storage capacitor Cst is connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal supplied to the first node N1.

[0165] The light-emitting element LD is connected between the second transistor M2 and the second power supply ELVSS. The light-emitting element LD emits light with a brightness corresponding to the current controlled by the second transistor M2. In various embodiments, the light-emitting element LD may be an organic light-emitting diode (“OLED”).

[0166] Figure 14 This is a circuit diagram illustrating another exemplary embodiment of a representative pixel. Figure 14For ease of description, an active pixel is shown that is connected to the i-th (i is a natural number) scan line Si in the i-th horizontal pixel row, the (i-1)-th scan line Si-1 in the (i-1)-th horizontal pixel row, the (i+1)-th scan line Si+1 in the (i+1)-th horizontal pixel row, and the j-th (j is a natural number) data line Dj in the j-th vertical pixel column, and includes seven transistors. However, the structure of pixel PXL in the exemplary embodiments of the invention is not limited to... Figure 14 The structure shown.

[0167] Reference Figure 14 According to another embodiment, the pixel PXL may include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0168] The first electrode of the first transistor M1 can be connected to the first power supply ELVDD via the fifth transistor M5, and the second electrode of the first transistor M1 can be connected to the anode electrode of the light-emitting element LD via the sixth transistor M6. Furthermore, the gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current flowing from the first power supply ELVDD through the light-emitting element LD to the second power supply ELVSS, corresponding to the voltage at the first node N1.

[0169] The second transistor M2 (switching transistor) can be connected between the j-th data line Dj and the first electrode of the first transistor M1. Furthermore, the gate electrode of the second transistor M2 can be connected to the i-th scan line Si. The second transistor M2 can be turned on when a scan signal is supplied to the i-th scan line Si, thereby electrically connecting the j-th data line Dj and the first electrode of the first transistor M1 to each other.

[0170] The third transistor M3 can be connected between the second electrode of the first transistor M1 and the first node N1. Furthermore, the gate electrode of the third transistor M3 can be connected to the i-th scan line Si. The third transistor M3 can be turned on when a scan signal with a gate on-voltage is supplied to the i-th scan line Si, thereby electrically connecting the second electrode of the first transistor M1 and the first node N1 to each other. Therefore, when the third transistor M3 is turned on, the first transistor M1 can be connected in the form of a diode.

[0171] The fourth transistor M4 (initialization transistor) can be connected between the first node N1 and the initialization power supply Vint. Furthermore, the gate electrode of the fourth transistor M4 can be connected to the (i-1)th scan line Si-1. The fourth transistor M4 can be turned on when the scan signal is supplied to the (i-1)th scan line Si-1 to supply the voltage of the initialization power supply Vint to the first node N1.

[0172] Figure 14An embodiment is shown in which the (i-1)th scan line Si-1 is used as an initialization control line for initializing the gate node (i.e., the first node N1) of the first transistor M1. However, exemplary embodiments of the invention are not limited thereto. For example, in another embodiment, another control line, such as the (i-2)th scan line, can be used as an initialization control line for initializing the gate node of the first transistor M1.

[0173] The fifth transistor M5 can be connected between the first power supply ELVDD and the first transistor M1. Furthermore, the gate electrode of the fifth transistor M5 can be connected to the i-th light-emitting control line Ei. The fifth transistor M5 can be turned off when a light-emitting control signal with a gate cutoff voltage is supplied to the i-th light-emitting control line Ei, and can be turned on under other conditions.

[0174] The sixth transistor M6 can be connected between the first transistor M1 and the light-emitting element LD. Furthermore, the gate electrode of the sixth transistor M6 can be connected to the i-th light-emitting control line Ei. The sixth transistor M6 can be turned off when a light-emitting control signal with a gate cutoff voltage is supplied to the i-th light-emitting control line Ei, and can be turned on under other conditions.

[0175] The seventh transistor M7 can be connected between the initialization power supply Vint and the first electrode (e.g., the anode electrode) of the light-emitting element LD. Furthermore, the gate electrode of the seventh transistor M7 can be connected to the (i+1)th scan line Si+1. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is supplied to the (i+1)th scan line Si+1, the seventh transistor can be turned on to supply the voltage of the initialization power supply Vint to the anode electrode of the light-emitting element LD. Here, the voltage of the initialization power supply Vint can be set to a voltage lower than the voltage of the data signal. That is, the voltage of the initialization power supply Vint can be set to be equal to or less than the minimum voltage of the data signal.

[0176] Figure 14 The illustration shows a case where the gate electrode of the seventh transistor M7 is connected to the anode initialization control line of the (i+1)th scan line Si+1. However, exemplary embodiments of the invention are not limited to this. For example, in another embodiment, the gate electrode of the seventh transistor M7 may be connected to the i-th scan line Si. In this case, when the scan signal of the gate on-state voltage is supplied to the i-th scan line Si, the voltage of the initialization power supply Vint can be supplied to the anode electrode of the light-emitting element LD through the seventh transistor M7.

[0177] The storage capacitor Cst can be connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

[0178] The anode of the light-emitting element (LD) can be connected to the first transistor M1 via a sixth transistor M6, and the cathode can be connected to the second power supply ELVSS. The LD produces light of a predetermined brightness corresponding to the amount of current supplied from the first transistor M1. The voltage of the first power supply ELVDD can be set to be higher than the voltage of the second power supply ELVSS, allowing current to flow to the LD.

[0179] On the other hand, the structure of the pixel PXL is not limited to Figure 14 The embodiments shown are illustrated. For example, various known pixel circuit structures can be applied to the pixel PXL.

[0180] Figure 15 It is shown Figure 14 A plan view of an exemplary embodiment of the pixel layout shown. Specifically, Figure 15 The setting is shown Figure 1 and Figure 2 The display area AA contains pixels PXL, including Figures 8 to 12C The layout of pixels PXL of the first light-transmitting hole LTH1 shown in the figure. Figure 16 It is along Figure 15 A sectional view taken by line I-I'. Figure 17 It is along Figure 15 The sectional view taken from line II-II'. For ease of description, Figures 15 to 17 Only shown Figure 4A and Figure 4B The circuit element layer BPL, light-emitting element layer LDL, and first protective layer PTL1 in the display device 10 shown are used to avoid redundancy.

[0181] In description Figures 15 to 17 In the embodiments, for convenience, the scan lines of the (i-1), i, and i+1 rows are called "scan lines Si-1, Si, and Si+1", the light emission control line of the i row is called "light emission control line Ei", the data line of the j column is called "data line Dj", and the power line of the j column (e.g., the power line of the j column to which the first power supply ELVDD is applied) is called "power line PL".

[0182] Referring to the embodiments described above Figures 15 to 17 The display device 10 may include a pixel PXL disposed in the display area AA and a wiring portion for supplying drive signals and / or power to the pixel PXL. The wiring portion may include scan lines Si-1, Si and Si+1, data line Dj, light emission control line Ei, power line PL and initialization power line IPL.

[0183] Scan lines Si-1, Si, and Si+1 may extend along a first direction DR1 within the display area AA. Scan lines Si-1, Si, and Si+1 may include an (i-1)th scan line Si-1, an ith scan line Si, and an (i+1)th scan line Si+1 arranged sequentially along a second direction DR2 intersecting the first direction DR1. Scan lines Si-1, Si, and Si+1 may receive scan signals. For example, the (i-1)th scan line Si-1 may receive the (i-1)th scan signal, the ith scan line Si may receive the ith scan signal, and the (i+1)th scan line Si+1 may receive the (i+1)th scan signal.

[0184] The light emission control line Ei can extend in the first direction DR1, parallel to the scan lines Si-1, Si, and Si+1 in the display area AA. The light emission control line Ei can receive the light emission control signal.

[0185] Data line Dj can extend along the second direction DR2 within the display area AA. That is, data line Dj can extend in a direction intersecting with control lines Si-1, Si, Si+1, and Ei, which include scan lines Si-1, Si, and Si+1, and light emission control line Ei. Data line Dj can receive data signals.

[0186] The power line PL may extend along the second direction DR2 within the display area AA, but is not limited thereto. The power line PL may be configured to be spaced apart from the data line Dj and may receive the first power supply ELVDD.

[0187] The initialization power line IPL can extend along the first direction DR1 in the display area AA, but is not limited thereto. The initialization power line IPL can receive the initialization power Vint.

[0188] In an embodiment, the pixel PXL may include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0189] The first transistor M1 may include a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0190] In an embodiment, the first gate electrode GE1 may be stacked with the first channel CH1 of the active pattern, and at least one insulating layer (e.g., gate insulating layer 113) may be disposed between the first gate electrode GE1 and the first channel CH1. The first gate electrode GE1 may be connected to the third drain electrode DE3 (including DE3a and DE3b) of the third transistor M3 and the fourth source electrode SE4 (including SE4a and SE4b) of the fourth transistor M4.

[0191] The first gate electrode GE1 can be connected to the third drain electrode DE3 and the fourth source electrode SE4 via the connecting wire CNL. One end of the connecting wire CNL can be connected to the first gate electrode GE1 via the first contact hole CT1, and the other end can be connected to the third drain electrode DE3 and the fourth source electrode SE4 via the second contact hole CT2.

[0192] In an embodiment, the first channel CH1, the first source electrode SE1, and the first drain electrode DE1 can be formed from semiconductor patterns that are undoped or doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 can be formed from semiconductor patterns that are doped with impurities, and the first channel CH1 can be formed from semiconductor patterns that are undoped with impurities.

[0193] The first channel CH1 has a shape extending in a random direction and may have a shape that bends several times along its length. When viewed in a plan view, the first channel CH1 may be stacked with the first gate electrode GE1. By forming the first channel CH1 as long, the channel region of the first transistor M1 can be formed as long. Therefore, the driving range of the gate voltage applied to the first transistor M1 is widened. Therefore, the grayscale of the light emitted from the light-emitting element LD can be precisely controlled.

[0194] The first source electrode SE1 can be connected to one end of the first channel CH1. The first source electrode SE1 can be connected to the second drain electrode DE2 of the second transistor M2 and the fifth drain electrode DE5 of the fifth transistor M5. In an embodiment, the first drain electrode DE1 can be connected to the other end of the first channel CH1. The first drain electrode DE1 can be connected to the third source electrode SE3 (including SE3a and SE3b) of the third transistor M3 and the sixth source electrode SE6 of the sixth transistor M6.

[0195] The second transistor M2 may include a second gate electrode GE2, a second channel CH2, a second source electrode SE2, and a second drain electrode DE2.

[0196] The second gate electrode GE2 may be stacked with the second channel CH2, and at least one insulating layer (e.g., gate insulating layer 113) may be disposed between the second gate electrode GE2 and the second channel CH2. The second gate electrode GE2 may be connected to the i-th scan line Si.

[0197] The second channel CH2, the second source electrode SE2, and the second drain electrode DE2 can be formed from semiconductor patterns that are undoped or doped. For example, the second source electrode SE2 and the second drain electrode DE2 can be formed from semiconductor patterns that are doped, and the second channel CH2 can be formed from a semiconductor pattern that is undoped. The second channel CH2 can correspond to the portion superimposed on the second gate electrode GE2.

[0198] One end of the second source electrode SE2 can be connected to the second channel CH2, and the other end of the second source electrode SE2 can be connected to the data line Dj through the sixth contact hole CT6. In the embodiment, one end of the second drain electrode DE2 can be connected to the second channel CH2, and the other end of the second drain electrode DE2 can be connected to the first source electrode SE1 of the first transistor M1 and the fifth drain electrode DE5 of the fifth transistor M5.

[0199] The third transistor M3 may have a dual-gate structure to prevent leakage current. That is, the third transistor M3 may include a third transistor M3a and a third transistor M3b. The third transistor M3a may include a third gate electrode GE3a, a third active pattern, a third source electrode SE3a, and a third drain electrode DE3a. The third transistor M3b may include a third gate electrode GE3b, a third active pattern, a third source electrode SE3b, and a third drain electrode DE3b. In the following text, the third gate electrode GE3a and the third gate electrode GE3b are referred to as the third gate electrode GE3, the third active pattern and the third active pattern are referred to as the third channel CH3, the third source electrode SE3a and the third source electrode SE3b are referred to as the third source electrode SE3, and the third drain electrode DE3a and the third drain electrode DE3b are referred to as the third drain electrode DE3.

[0200] The third gate electrode GE3 (including GE3a and GE3b) may be stacked with the third channel CH3, and at least one insulating layer (e.g., gate insulating layer 113) may be disposed between the third gate electrode GE3 and the third channel CH3. The third gate electrode GE3 may be connected to the i-th scan line Si.

[0201] The third channel CH3, the third source electrode SE3, and the third drain electrode DE3 can be formed from semiconductor patterns that are undoped or doped. For example, the third source electrode SE3 and the third drain electrode DE3 can be formed from semiconductor patterns that are doped, and the third channel CH3 can be formed from a semiconductor pattern that is undoped. The third channel CH3 corresponds to the portion superimposed on the third gate electrode GE3.

[0202] One end of the third source electrode SE3 can be connected to the third channel CH3 (including CH3a and CH3b), and the other end of the third source electrode SE3 can be connected to the first drain electrode DE1 of the first transistor M1 and the sixth source electrode SE6 of the sixth transistor M6. In an embodiment, one end of the third drain electrode DE3 can be connected to the third channel CH3, and the other end of the third drain electrode DE3 can be connected to the fourth source electrode SE4 of the fourth transistor M4. Furthermore, the third drain electrode DE3 can be connected to the first gate electrode GE1 of the first transistor M1 via the connecting wiring CNL, the second contact hole CT2, and the first contact hole CT1.

[0203] The fourth transistor M4 may be configured with a dual-gate structure to prevent leakage current. That is, the fourth transistor M4 may include a fourth transistor M4a and a fourth transistor M4b. The fourth transistor M4a may include a fourth gate electrode GE4a, a fourth active pattern, a fourth source electrode SE4a, and a fourth drain electrode DE4a. The fourth transistor M4b may include a fourth gate electrode GE4b, a fourth active pattern, a fourth source electrode SE4b, and a fourth drain electrode DE4b. In the following text, the fourth gate electrode GE4a and the fourth gate electrode GE4b are referred to as the fourth gate electrode GE4 (including GE4a and GE4b), the fourth active pattern and the fourth active pattern are referred to as the fourth channel CH4 (including CH4a and CH4b), the fourth source electrode SE4a and the fourth source electrode SE4b are referred to as the fourth source electrode SE4, and the fourth drain electrode DE4a and the fourth drain electrode DE4b are referred to as the fourth drain electrode DE4.

[0204] The fourth gate electrode GE4 may be stacked with the fourth channel CH4, and at least one insulating layer (e.g., gate insulating layer 113) may be disposed between the fourth gate electrode GE4 and the fourth channel CH4. The fourth gate electrode GE4 may be connected to the (i-1)th scan line Si-1.

[0205] The fourth channel CH4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed from semiconductor patterns that are undoped or doped. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 can be formed from semiconductor patterns that are doped, and the fourth channel CH4 can be formed from a semiconductor pattern that is undoped. The fourth channel CH4 corresponds to the portion superimposed on the fourth gate electrode GE4.

[0206] One end of the fourth source electrode SE4 can be connected to the fourth channel CH4, and the other end of the fourth source electrode SE4 can be connected to the third drain electrode DE3 of the third transistor M3. Furthermore, the fourth source electrode SE4 can be connected to the first gate electrode GE1 of the first transistor M1 via the connecting wiring CNL, the second contact hole CT2, and the first contact hole CT1. One end of the fourth drain electrode DE4 can be connected to the fourth channel CH4, and the other end of the fourth drain electrode DE4 can be connected to the seventh drain electrode DE7 of the seventh transistor M7. The fourth drain electrode DE4 can be connected to the initialization power line IPL via the auxiliary connecting wiring AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0207] The fifth transistor M5 may include a fifth gate electrode GE5, a fifth channel CH5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0208] The fifth gate electrode GE5 may be stacked with the fifth channel CH5, and at least one insulating layer (e.g., gate insulating layer 113) may be disposed between the fifth gate electrode GE5 and the fifth channel CH5. The fifth gate electrode GE5 may be connected to the light emission control line Ei.

[0209] The fifth channel CH5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed from semiconductor patterns that are undoped or doped. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed from semiconductor patterns that are doped, and the fifth channel CH5 can be formed from a semiconductor pattern that is undoped. The fifth channel CH5 corresponds to the portion superimposed on the fifth gate electrode GE5.

[0210] One end of the fifth source electrode SE5 can be connected to the fifth channel CH5, and the other end of the fifth source electrode SE5 can be connected to the power line PL through the fifth contact hole CT5. In the embodiment, one end of the fifth drain electrode DE5 can be connected to the fifth channel CH5, and the other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor M1 and the second drain electrode DE2 of the second transistor M2.

[0211] The sixth transistor M6 may include a sixth gate electrode GE6, a sixth channel CH6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0212] The sixth gate electrode GE6 may be stacked with the sixth channel CH6, and at least one insulating layer (e.g., gate insulating layer 113) may be disposed between the sixth gate electrode GE6 and the sixth channel CH6. The sixth gate electrode GE6 may be connected to the light emission control line Ei.

[0213] The sixth channel CH6, the sixth source electrode SE6, and the sixth drain electrode DE6 are formed from semiconductor patterns that are either undoped or doped. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 can be formed from semiconductor patterns that are doped, while the sixth channel CH6 can be formed from an undoped semiconductor pattern. The sixth channel CH6 corresponds to the portion superimposed on the sixth gate electrode GE6.

[0214] One end of the sixth source electrode SE6 can be connected to the sixth channel CH6, and the other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor M1 and the third source electrode SE3 of the third transistor M3. In an embodiment, one end of the sixth drain electrode DE6 can be connected to the sixth channel CH6, and the other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor M7.

[0215] The seventh transistor M7 may include a seventh gate electrode GE7, a seventh channel CH7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0216] The seventh gate electrode GE7 can be stacked with the seventh channel CH7, and at least one insulating layer (e.g., gate insulating layer 113) is disposed between the seventh gate electrode GE7 and the seventh channel CH7. The seventh gate electrode GE7 can be connected to the (i+1)th scan line Si+1.

[0217] The seventh channel CH7, the seventh source electrode SE7, and the seventh drain electrode DE7 can be formed from semiconductor patterns that are undoped or doped. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 can be formed from semiconductor patterns that are doped, and the seventh channel CH7 can be formed from a semiconductor pattern that is undoped. The seventh channel CH7 corresponds to the portion superimposed on the seventh gate electrode GE7.

[0218] One end of the seventh source electrode SE7 can be connected to the seventh channel CH7, and the other end of the seventh source electrode SE7 can be connected to the sixth drain electrode DE6 of the sixth transistor M6. In an embodiment, one end of the seventh drain electrode DE7 can be connected to the seventh channel CH7, and the other end of the seventh drain electrode DE7 can be connected to the initialization power line IPL through auxiliary connection wiring AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0219] The storage capacitor Cst may include a first capacitor electrode LE and a second capacitor electrode UE. In one embodiment, the first capacitor electrode LE may be the lower electrode of the storage capacitor Cst and may be integrally formed with the first gate electrode GE1 of the first transistor M1. In another embodiment, the second capacitor electrode UE may be the upper electrode of the storage capacitor Cst and may be stacked with the first gate electrode GE1. Furthermore, as seen in the plan view, the second capacitor electrode UE may cover at least one area of ​​the first capacitor electrode LE. The capacitance of the storage capacitor Cst can be increased by increasing the stacking area of ​​the first capacitor electrode LE and the second capacitor electrode UE.

[0220] The second capacitor electrode UE may extend along the first direction DR1. In an embodiment, a voltage at the same level as the first power supply ELVDD may be applied to the second capacitor electrode UE. The second capacitor electrode UE may have an opening portion OPN in the region where the first contact hole CT1 is formed, wherein the first gate electrode GE1 and the connection wiring CNL are in contact in the first contact hole CT1.

[0221] A light-emitting element (LD) may include a first electrode (e.g., an anode electrode) AD, a second electrode (e.g., a cathode electrode) CD, and a light-emitting element layer (LDL) disposed between the first electrode AD and the second electrode CD. In an embodiment, the first electrode AD and the second electrode CD are arranged to overlap each other in the light-emitting region of the light-emitting element layer LDL, and the light-emitting element layer LDL may be formed in the light-emitting region. That is, the light-emitting region of each pixel PXL may be the region where the first electrode AD, the light-emitting element layer LDL, and the second electrode CD of the light-emitting element LD overlap each other.

[0222] The first electrode AD can be disposed in a predetermined light-emitting area. The first electrode AD can be connected to the seventh source electrode SE7 of the seventh transistor M7 and the sixth drain electrode DE6 of the sixth transistor M6 through the fourth contact hole CT4 and the seventh contact hole CT7. The bridging pattern BRP can be disposed between the fourth contact hole CT4 and the seventh contact hole CT7. The bridging pattern BRP can connect the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD.

[0223] In the following, the stacked structure (cross-sectional structure) of the pixel PXL and the display area AA including the pixel PXL according to the embodiment will be described.

[0224] First, the buffer layer 112 can be disposed on the first surface of the first substrate SUB1.

[0225] An active pattern ACT can be disposed on the buffer layer 112. In an embodiment, the active pattern ACT may include a first channel CH1 to a seventh channel CH7. The first channel CH1 to the seventh channel CH7 may be formed of a semiconductor material.

[0226] The gate insulating layer 113 may be disposed on a buffer layer 112 on which the first channel CH1 to the seventh channel CH7 are disposed. In an embodiment, the gate insulating layer 113 may be a gate insulating film disposed between the active patterns ACT1 to ACT7 of the transistors M1 to M7 included in the pixel PXL and the gate electrodes GE1 to GE7.

[0227] The gate insulating layer 113 may include at least one inorganic film and / or an organic film. For example, the gate insulating layer 113 may be composed of SiO2. x SiN x Inorganic films such as, but not limited to, can be formed. For example, the gate insulating layer 113 may include, for example, SiO2. x SiN x SiON, SiOF or AlO x It is an inorganic or organic insulating material, and may be a single-layer or multilayer film including at least one of these materials.

[0228] A first conductive layer may be disposed on the gate insulating layer 113. In an embodiment, the first conductive layer may be a first gate layer. The first conductive layer may be provided with control lines Si-1, Si, Si+1, and Ei, and gate electrodes GE1 to GE7. Furthermore, one electrode of the storage capacitor Cst (e.g., the first capacitor electrode LE) may be disposed on the first conductive layer. Specifically, the (i-1)th scan line Si-1, the ith scan line Si, the (i+1)th scan line Si+1, the light emission control line Ei, and the first gate electrodes GE1 to the seventh gate electrodes GE7 may be disposed. In an embodiment, the first gate electrode GE1 may also be the first capacitor electrode LE of the storage capacitor Cst. That is, the first gate electrode GE1 and the first capacitor electrode LE may be integrally formed.

[0229] The control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE, which serves as the lower electrode of the storage capacitor Cst, disposed on the first conductive layer, can be formed of the same material. For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE, which serves as the storage capacitor Cst, can be formed of a predetermined first gate metal.

[0230] Examples of materials capable of forming the first gate metal include Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, Pb, etc., and various other metals can be used as materials capable of forming the first gate metal. Examples of alloys capable of forming the first gate metal include MoTi, AlNiLa, etc., and various other alloys can be used as alloys capable of forming the first gate metal. Examples of multilayer films capable of forming the first gate metal include Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, TiN / Ti / Cu / Ti, etc., and various other conductive materials for multilayer film structures can be used as multilayer films capable of forming the first gate metal.

[0231] On the other hand, the structural materials of the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE are not limited to metals. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for forming the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE.

[0232] For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE can be formed from a conductive polymer or a conductive metal oxide. Examples of conductive polymers capable of constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polyphenylene compounds, mixtures thereof, etc. In particular, among polythiophene compounds, PEDOT / PSS compounds can be used. Examples of conductive metal oxides capable of constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE include ITO, IZO, AZO, ITZO, ZnO, SnO2, etc.

[0233] The first interlayer insulating layer 114 may be disposed on the first conductive layer. In an embodiment, the first interlayer insulating layer 114 may be a first interlayer insulating film disposed between the first capacitor electrode LE and the second capacitor electrode UE. In an embodiment, the first interlayer insulating layer 114 may have a thickness limited to a predetermined range to sufficiently ensure the capacity of the storage capacitor Cst within a limited area.

[0234] The first interlayer insulating layer 114 may include one or more inorganic and / or organic films. For example, the first interlayer insulating layer 114 may be composed of SiO2. x SiN x Inorganic films such as, but not limited to, can be formed. For example, the first interlayer insulating layer 114 may include, for example, SiO2. x SiN x SiON, SiOF or AlO x It is an inorganic or organic insulating material, and may be a single-layer or multilayer film including at least one of these materials.

[0235] The second conductive layer can be disposed on the first interlayer insulating layer 114. In an embodiment, the second conductive layer can be a second gate layer.

[0236] The second conductive layer may be provided with a second capacitor electrode UE and an initialization power line IPL. In an embodiment, the second capacitor electrode UE may cover the first capacitor electrode LE. The second capacitor electrode UE is stacked with the first capacitor electrode LE, and a first interlayer insulating layer 114 is placed between the second capacitor electrode UE and the first capacitor electrode LE to form a storage capacitor Cst together with the first capacitor electrode LE.

[0237] The second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer can be made of the same material. For example, the second capacitor electrode UE and the initialization power line IPL can be formed of a predetermined second gate metal. In embodiments, the second gate metal can be one of the metal materials given above as examples of the first gate metal, but is not limited thereto. Furthermore, the construction material of the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer is not necessarily limited to metal. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for constructing the second capacitor electrode UE and the initialization power line IPL. For example, the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer can be made of a conductive polymer or a conductive metal oxide.

[0238] The second interlayer insulating layer 115 may be disposed on the second conductive layer. In an embodiment, the second interlayer insulating layer 115 may be a second interlayer insulating film.

[0239] The second interlayer insulating layer 115 may include one or more inorganic and / or organic films. For example, the second interlayer insulating layer 115 may be composed of SiO2. x SiN x It can be made of inorganic films, but is not limited to them. For example, the second interlayer insulating layer 115 may include, for example, SiO2. x SiN x SiON, SiOF or AlO x It is an inorganic or organic insulating material, and may be a single-layer or multilayer film including at least one of these materials.

[0240] The third conductive layer can be disposed on the second interlayer insulating layer 115. In an embodiment, the third conductive layer can be a source / drain layer.

[0241] The third conductive layer can be configured with data lines (Dj), power lines (PL), connection wiring (CNL), bridging patterns (BRP), and auxiliary connection wiring (AUX).

[0242] The data line Dj can be electrically connected to the second source electrode SE2 through the sixth contact hole CT6 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0243] The power line PL can be connected to the second capacitor electrode UE, which serves as the upper electrode of the storage capacitor Cst, via the third contact hole CT3 passing through the second interlayer insulating layer 115. Furthermore, the power line PL can be connected to the fifth source electrode SE5 via the fifth contact hole CT5 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0244] The connection wiring CNL can be connected to the first gate electrode GE1 through the first contact hole CT1 passing through the first interlayer insulating layer 114 and the second interlayer insulating layer 115. In addition, the connection wiring CNL can be electrically connected to the third drain electrode DE3 and the fourth source electrode SE4 through the second contact hole CT2 passing through the gate insulating layer 113, the first interlayer insulating layer 114 and the second interlayer insulating layer 115.

[0245] The bridging pattern BRP can be a pattern configured to connect the sixth drain electrode DE6 and the first electrode AD through a dielectric material. This bridging pattern BRP can be electrically connected to the sixth drain electrode DE6 and the seventh source electrode SE7 via a fourth contact hole CT4 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0246] The auxiliary connection wiring AUX can be connected to the initialization power line IPL through the eighth contact hole CT8 passing through the second interlayer insulation layer 115. Furthermore, the auxiliary connection wiring AUX can be connected to the seventh drain electrode DE7 through the ninth contact hole CT9 passing through the gate insulation layer 113, the first interlayer insulation layer 114, and the second interlayer insulation layer 115.

[0247] The data line Dj, power line PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX disposed in the third conductive layer can be made of the same material. For example, the data line Dj, power line PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX can be formed from a predetermined source-drain metal.

[0248] The source / drain metal can be one of the metallic materials presented earlier as examples of the first gate metal and / or the second gate metal, but is not limited thereto. Furthermore, the construction materials for the data line Dj, power line PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX disposed in the third conductive layer are not necessarily limited to metals. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for constructing the data line Dj, power line PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX. For example, the data line Dj, power line PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX can be made of conductive polymers or conductive metal oxides.

[0249] At least two of the first gate metal, the second gate metal, and the source / drain metal can be formed of the same material. For example, even if the first gate metal and the second gate metal are disposed on different layers, the first gate metal and the second gate metal can still be formed of the same material. However, exemplary embodiments of the invention are not limited thereto. For example, in another embodiment, all of the first gate metal, the second gate metal, and the source / drain metal can be formed of different materials.

[0250] In various exemplary embodiments of the invention, when light incident on each of the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer is reflected by each of the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer, reflected again by the upper layer, and incident again, the distance between the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer can be limited to prevent such re-reflected light from acting as noise. For example, the distance between the active pattern ACT, the first conductive layer, or the second conductive layer, and the third conductive layer can be limited to approximately 300 μm or less. The thicknesses of the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115 can be determined based on the distance between the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer, which, as described above, is limited.

[0251] The protective layer 116 may be disposed on the third conductive layer. In an embodiment, the protective layer 116 may include a passivation film and / or a planarization film. The protective layer 116 may include a seventh contact hole CT7 that exposes a portion of the bridging pattern BRP.

[0252] The light-emitting element LD can be disposed on the protective layer 116. The light-emitting element LD may include a first electrode AD, a second electrode CD, and a light-emitting element layer LDL disposed between the first electrode AD and the second electrode CD.

[0253] In an embodiment, the protective layer 116 may have approximately up to approximately Thickness (e.g., approximately) However, the thickness of the protective layer 116 is not limited to this.

[0254] At least one of the first electrode AD and the second electrode CD can be a transmission electrode. For example, when the light-emitting element LD is a back-surface emitting organic light-emitting display element, the first electrode AD can be a transmission electrode, and the second electrode CD can be a reflection electrode. On the other hand, when the light-emitting element LD is a front-surface emitting organic light-emitting display element, the first electrode AD can be a reflection electrode, and the second electrode CD can be a transmission electrode. Furthermore, when the light-emitting element LD is a double-sided emitting organic light-emitting display element, both the first electrode AD and the second electrode CD can be transmission electrodes. In the following description, the case where the light-emitting element LD is a front-surface emitting organic light-emitting display element and the first electrode AD is an anode electrode will be used as an example. Furthermore, in the illustrated embodiment, the light-emitting element LD is used as a light source, but exemplary embodiments of the invention are not limited thereto. For example, the light-emitting element LD can be replaced with another type of light-emitting element.

[0255] The first electrode AD can be disposed on the protective layer 116. The first electrode AD can be connected to the bridging pattern BRP through the seventh contact hole CT7 passing through the protective layer 116. Because the bridging pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the fourth contact hole CT4, the first electrode AD can ultimately be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the bridging pattern BRP.

[0256] The first electrode AD may include a reflective film capable of reflecting light and a transparent conductive film disposed above or below the reflective film. At least one of the transparent conductive film and the reflective film may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0257] The reflective film may include materials capable of reflecting light. For example, the reflective film may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and alloys thereof.

[0258] Transparent conductive films may include transparent conductive oxides. For example, a transparent conductive film may include at least one transparent conductive oxide selected from indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc aluminum oxide (“AZO”), gallium-doped zinc oxide (“GZO”), zinc tin oxide (“ZTO”), gallium tin oxide (“GTO”), and fluorine-doped tin oxide (“FTO”).

[0259] The light-emitting element layer (LDL) can be disposed on the exposed surface of the first electrode (AD). The LDL can have a multilayer thin film structure including a light-generating layer (“LGL”). For example, the LDL may include: a hole injection layer (“HIL”) for injecting holes; a hole transport layer (“HTL”) for increasing the chance of hole recombination by suppressing the movement of electrons not bound in the light-generating layer, and having excellent hole transport capability; a light-generating layer for emitting light by recombination of injected electrons and holes; a hole blocking layer (“HBL”) for suppressing the movement of unbound holes in the light-generating layer; an electron transport layer (“ETL”) for smoothly transporting electrons to the light-generating layer; and / or an electron injection layer (“EIL”) for injecting electrons.

[0260] The color of the light generated in the light-generating layer can be one of red, green, blue, and white, but exemplary embodiments of the invention are not limited thereto. For example, the color of the light generated in the light-generating layer of the light-emitting element layer (LDL) can be one of magenta, cyan, and yellow.

[0261] The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer can be a common film that is connected to each other in adjacent light-emitting regions.

[0262] The second electrode CD can be a transmissive and reflective film. For example, the second electrode CD can be a thin film metal layer with a thickness sufficient to transmit light emitted from the light-emitting element layer LDL. For example, the second electrode CD can transmit some of the light emitted from the light-emitting element layer LDL and reflect the remainder of the light emitted from the light-emitting element layer LDL.

[0263] In an embodiment, the second electrode CD may comprise a material having a work function lower than that of the transparent conductive film. For example, the second electrode CD may comprise at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0264] Some of the light emitted from the LDL (Light Emitting Diode) layer may not transmit through the second electrode CD, and the light reflected from the second electrode CD can be reflected again in the reflective film. That is, the light emitted from the LDL layer can resonate between the reflective film and the second electrode CD. The light extraction efficiency of the LDL can be improved through optical resonance.

[0265] A pixel defining film (or dam) 117 for dividing the light-emitting area of ​​each pixel PXL can be disposed on a first substrate SUB1 on which a first electrode AD is disposed. The pixel defining film 117 can expose the upper surface of the first electrode AD and can protrude from the first substrate SUB1 along the outer periphery of each light-emitting area.

[0266] A light-emitting element region or light-emitting element layer LDL can be disposed in the light-emitting region of each pixel PXL surrounded by the pixel defining film 117, and a second electrode CD can be disposed on the light-emitting element layer LDL. One of the first electrode AD and the second electrode CD can be an anode electrode, and the other can be a cathode electrode. For example, the first electrode AD can be an anode electrode, and the second electrode CD can be a cathode electrode.

[0267] Pixel defining film 117 may include an organic insulating material. For example, pixel defining film 117 may include at least one of polystyrene, polymethyl methacrylate (“PMMA”), polyacrylonitrile (“PAN”), polyamide (“PA”), polyimide (“PI”), polyaryl ether (“PAE”), heterocyclic polymer, chemical vapor deposition polymer sold by Specialty Coating Systems, Inc. of Indianapolis, Indiana, under the trade name PARYLENE, epoxy resin, benzocyclobutene (“BCB”), siloxane resin, and silane resin.

[0268] A first protective layer PTL1 covering the second electrode CD can be disposed as layer 118 on the second electrode CD. The first protective layer PTL1 can be formed of a thin film encapsulation layer. In embodiments, the thin film encapsulation layer can be replaced by at least one layer of another type of encapsulation film, encapsulation substrate, protective film, etc.

[0269] The thin-film encapsulation layer prevents oxygen and moisture from penetrating into the light-emitting element (LD). For this purpose, the thin-film encapsulation layer may include an inorganic film. The inorganic film may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0270] Each of the circuit elements and wirings disposed on the first surface of the first substrate SUB1 from the buffer layer 112 to the protective layer 116 can constitute the circuit element layer BPL of the display device 10 and / or the fingerprint sensor. Furthermore, the light-emitting element LD disposed in each pixel PXL from the first electrode AD to the second electrode CD and the thin film encapsulation layer disposed between the light-emitting elements LD can constitute the light-emitting element layer LDL of the display device 10 and / or the fingerprint sensor.

[0271] Further reference Figures 11 to 13Pixel PXL may include a first light-transmitting aperture LTH1 formed in at least one conductive layer of the circuit element layer BPL. Sensing region SA may include a plurality of pixels PXL including the first light-transmitting aperture LTH1.

[0272] The first light-transmitting aperture LTH1 may include a multilayer opening portion MLO formed to be stacked with multiple conductive layers that constitute the circuit element layer BPL. For example, the first light-transmitting aperture LTH1 may include a multilayer opening portion MLO, which is formed to be stacked with at least two of the following layers: a semiconductor layer in which an active pattern ACT is disposed, a first conductive layer in which gate electrodes GE1 to GE7 are disposed, a second conductive layer in which second capacitor electrodes UE are disposed, etc., and a third conductive layer in which power lines PL and bridging patterns BRP are disposed.

[0273] According to the above embodiments, a light-transmitting aperture array for receiving reflected light can be integrally formed with the light-emitting element layer (LDL) and the circuit element layer (BPL), without forming an additional layer in the circuit element layer (BPL). Therefore, the module thickness of the display device 10 can be reduced.

[0274] On the other hand, in various exemplary embodiments of the invention, the position and form of the first light-transmitting hole LTH1 are not limited to... Figures 15 to 17 The location and form are shown. That is, in various other embodiments, the first light-transmitting aperture LTH1 may be formed in another region (e.g., including the region of the opening portion OPN formed in the first gate electrode GE1). In such embodiments, various modifications can be made to the layout structure so that the conductive layer is not disposed in the first light-transmitting aperture LTH1.

[0275] The dimensions (width or diameter) of the first light-transmitting aperture LTH1 can be determined by the dimensions of the multi-layer opening portion MLO. For example, the width w' of the first light-transmitting aperture LTH1 can be determined as the minimum width among the widths of the multi-layer opening portion MLO.

[0276] At least a portion of the multi-layered opening portion MLO forming the first light-transmitting aperture LTH1 can be connected with a reference. Figures 7 to 12C The described light-shielding layer PHL has pinhole PIH stacks. In such an embodiment, the width w' of the first light-transmitting hole LTH1 may be the same as or different from the width w of the pinhole PIH.

[0277] In an embodiment, the width w' of the first light-transmitting aperture LTH1 can be smaller than the width w of the pinhole PIH. For example, the pinhole PIH and the first light-transmitting aperture LTH1 can have widths ranging from approximately 5 μm to approximately 20 μm, and the width w' of the first light-transmitting aperture LTH1 can be set to be smaller than the width w of the pinhole PIH.

[0278] In an embodiment, when the pinhole PIH and the first light-transmitting aperture LTH1 have a generally rectangular shape, the length of the first side of the pinhole PIH can be approximately 8.5 μm, and the length of the second side perpendicular to the first side can be approximately 9.4 μm. Furthermore, in such an embodiment, the length of the first side of the first light-transmitting aperture LTH1 can be approximately 4.5 μm, and the length of the second side perpendicular to the first side can be approximately 5.4 μm. These values ​​are merely examples, and exemplary embodiments of the invention are not limited thereto.

[0279] In embodiments where the first light-transmitting aperture LTH1 has a size smaller than that of the pinhole PIH, the first light-transmitting aperture array layer LTHL1 can perform the function of a light control layer LBL that controls the path of light (e.g., limiting the field of view of reflected light to a predetermined angular range), and the light-shielding layer PHL can perform the function of blocking light.

[0280] However, exemplary embodiments of the invention are not limited thereto. That is, in another embodiment, the width w' of the first light-transmitting aperture LTH1 can be larger than the width w of the pinhole PIH. In such an embodiment, the first light-transmitting aperture array layer LTHL1 can perform a light-blocking function, and the light-shielding layer PHL can perform the function of a light control layer LBL that controls the path of light.

[0281] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and the various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising: The substrate has a first surface and a second surface; A light-emitting element layer is disposed on the first surface of the substrate and has at least one light-emitting element; as well as A circuit element layer is disposed between the substrate and the light-emitting element layer, and includes circuit elements to control the light emission of the at least one light-emitting element. The circuit element layer includes a semiconductor layer and a conductive layer. Each of the semiconductor layer and the conductive layer constitutes at least a portion of the circuit element. The circuit element layer has a first opening, and In the plan view, each of the first openings has a closed-loop shape defined by at least one of the conductive layers and the semiconductor layer.

2. The display device according to claim 1, in, The semiconductor layer includes an active pattern of the circuit elements, and The conductive layer includes: A first gate layer includes a gate electrode superimposed on the active pattern; and The source / drain layer includes a source electrode and a drain electrode connected to the active pattern.

3. The display device according to claim 2, wherein, The conductive layer further includes: A second gate layer is disposed between the first gate layer and the source / drain layer, and includes at least one capacitor electrode.

4. The display device according to claim 3, wherein, The distance between the semiconductor layer and the source / drain layer is 300 μm or less.

5. The display device according to claim 3, wherein, The first gate layer includes light-emitting control lines to supply light-emitting control signals to the circuit elements. The second gate layer includes an initialization power line to supply initialization power to the circuit elements, and The source / drain layer includes power lines to apply power to the circuit elements.

6. The display device according to claim 5, wherein, In the plan view, the closed-loop shape is defined by the semiconductor layer, the first gate layer, the second gate layer, and the source / drain layer.

7. The display device according to claim 6, wherein, In the plan view, the closed-loop shape is defined by the active pattern, the light-emitting control line, the initialization power line, and the power line.

8. The display device according to claim 1, further comprising: A sensor layer is disposed on the second surface of the substrate and has a light sensor.

9. The display device according to claim 8, further comprising: A light-shielding layer is disposed between the sensor layer and the circuit element layer, and has a second opening. Wherein, at least a portion of the first opening and at least a portion of the second opening are at least partially overlapped and have different sizes.

10. The display device according to claim 9, wherein, The first opening and the second opening have a width or diameter between 5 μm and 20 μm.

11. The display device according to claim 9, wherein, The first opening and the second opening have a quadrilateral shape, wherein the width in the first direction and the width in the second direction perpendicular to the first direction are the same or different.

12. The display device according to claim 9, wherein, The width of the first opening is greater than the width of the second opening.

13. The display device according to claim 8, further comprising: A protective layer is disposed between the substrate and the sensor layer; as well as An adhesive layer is disposed between the substrate and the protective layer.

Images