Phase-shifted full-bridge PWM (Pulse Width Modulation) output method based on XOR operation

Abstract

The invention relates to the technical field of DC conversion, and discloses a phase-shifted full-bridge PWM output method based on XOR operation, which comprises a PWM unit, a half-bridge phase difference 180-degree signal unit, a full-bridge phase difference event regulator, a mode selection switch, a level XOR phase-shifting unit, a full-bridge dead time unit and a synchronous rectification unit. The half-bridge phase difference 180-degree signal unit and the level XOR phase shift unit are arranged, so that level XOR operation can be carried out on upper and lower bridge signals of a leading bridge arm output by the half-bridge phase difference 180-degree signal unit and overlapping signals output by a synchronous rectification unit diagonal overlapping detection unit respectively; therefore, lagging bridge arm upper and lower bridge signals after phase shifting are obtained; the phase-shifted full-bridge peak current mode control of the DCDC converter is realized, the voltage mode control is realized, and the cost of a chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of DC-DC conversion technology, and more specifically to a phase-shifted full-bridge PWM output method based on XOR operation. Background Technology

[0002] A phase-shifted full-bridge converter is a highly efficient power electronic converter topology widely used in DC-DC conversion, inverters, and high-frequency power supplies. It achieves phase regulation of the output voltage and power transfer by controlling the on and off times of the switching devices in the full-bridge circuit. The core of the phase-shifted full-bridge converter lies in utilizing the junction capacitance of the power devices and the leakage inductance of the transformer as resonant elements, enabling the switching transistors to conduct at zero voltage (ZVS), thereby achieving soft switching. Figure 1 As shown, QA and QB are the leading arm switches, and QC and QD are the lagging arm switches. QA and QD are simultaneously turned on as one diagonal pair of switches, and QB and QC are simultaneously turned on as another diagonal pair of switches. QE and QF are the two switches for secondary synchronous rectification, which are turned on as much as possible, but cannot be turned on simultaneously when transferring energy from the primary to the secondary side to prevent transformer short circuit.

[0003] Currently, software-controlled voltage loop (PI) and current loop (PI) switches are commonly used to control the phase shift angle of the switches and achieve stable output voltage control. However, at high switching frequencies (200-500kHz), software control suffers from high CPU load. In such cases, the software current loop can be implemented in hardware. Specifically, the current-limiting signal is obtained by combining the ILr circuit with the DAC comparator circuit, and then the full-bridge control signal is obtained through the chip's phase-shifting module. Some existing MCU chip peripherals, such as GTM, can implement phase-shifted full-bridge peak current mode control signals through the dead-time module (DTM). However, implementing the synchronous rectification signal and its dead time is relatively complex or requires software integration. Integrating GTM IP involves licensing, increasing chip cost.

[0004] In view of this, this application proposes a phase-shifted full-bridge PWM output method based on XOR operation to solve the above problems. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, this invention provides a phase-shifted full-bridge PWM output method based on XOR operation to solve the problems existing in the background art.

[0006] This invention provides the following technical solution: a phase-shifted full-bridge PWM output method based on XOR operation, comprising:

[0007] A PWM signal is generated by the PWM unit;

[0008] The signal unit with a 180-degree phase difference between the half-bridge and the output signal of the PWM unit generates a signal with a 180-degree phase difference between the half-bridge and no dead time insertion.

[0009] The rising and falling edges of the output signal of the PWM unit are delayed by a full-bridge phase difference event regulator.

[0010] Select between phase-shifted full-bridge peak current mode and voltage mode using the mode selection switch;

[0011] The signal output from the half-bridge phase difference 180-degree signal unit is processed by the level XOR phase shift unit to process the upper and lower bridge signals of the leading bridge arm.

[0012] By inserting a dead time unit into the full-bridge dead time unit, a PWM signal controlling the full-bridge switching transistors with a dead time is output.

[0013] The final synchronous rectifier switch control signal is obtained through the synchronous rectifier unit.

[0014] Preferably, the PWM unit generates one PWM signal with a settable period and duty cycle; the half-bridge phase difference 180-degree signal unit generates a signal with a half-bridge phase difference of 180 degrees and no dead time insertion from the output signal of the PWM unit, which is used for the processing of the upper and lower bridge signals of the advanced bridge arm and the upper and lower bridge arm of the lagging bridge arm respectively.

[0015] Preferably, the full-bridge phase difference event regulator delays the rising and falling edges of the output signal of the PWM unit for a delay time equal to the expected full-bridge phase angle control amount, thereby obtaining a phase difference event; the mode selection switch selects either the phase-shifted full-bridge peak current mode or the voltage mode.

[0016] Preferably, the level XOR phase shifting unit processes the leading bridge arm up and down bridge signals output by the half-bridge phase difference 180-degree signal unit, and performs a level XOR operation with the overlapping signal output by the synchronous rectification unit and the diagonal overlap detection unit, respectively, to obtain the phase-shifted lagging bridge arm up and down bridge signals.

[0017] Preferably, the full-bridge dead-time unit is formed by inserting the leading bridge arm up and down bridge signals output by the half-bridge phase difference 180-degree signal unit and the lagging bridge arm up and down bridge signals output by the level XOR phase shift unit into the dead time, and outputting the full-bridge switching transistor control PWM signal with dead time.

[0018] Preferably, the synchronous rectification unit includes a diagonal overlap detection unit, a synchronous rectification delay unit, and a level flipping unit.

[0019] Preferably, the diagonal overlap detection unit uses the output signal of the PWM unit and the phase difference event output by the current limiting signal edge event or the full-bridge phase difference event regulator to identify the diagonal overlap portion, and outputs the overlap signal of the VAB positive voltage and the overlap signal of the VAB negative voltage, and simultaneously outputs the overlap signal of the VAB positive voltage or the negative voltage.

[0020] Preferably, the synchronous rectification delay unit delays the rising and falling edges of the positive voltage overlap signal and the negative voltage overlap signal respectively, so that the synchronous rectification signal and the primary side conduction switch have a dead zone, ensuring that when energy is transferred from the primary side to the secondary side, the two synchronous rectifiers on the secondary side will not conduct at the same time, thus preventing the transformer from short-circuiting.

[0021] Preferably, the level-flipping unit flips the level of the delayed synchronous rectified signal to obtain the final synchronous rectified switch control signal. The synchronous rectified enable input signal can disable the synchronous rectified unit, which is suitable for applications where diode rectification is used on the secondary side.

[0022] Preferably, in specific implementation, the PWM unit can be replaced by an external PWM module, which only needs to input a PWM that satisfies a fixed duty cycle of 50%.

[0023] The technical effects and advantages of this invention are as follows:

[0024] This invention, by incorporating a half-bridge phase difference 180-degree signal unit and a level XOR phase shifting unit, facilitates the generation of a half-bridge phase difference 180-degree signal with no dead-time insertion from the output signal of the PWM unit. These signals are used for processing the leading and lagging bridge arm up / down signals in the subsequent stage. The leading bridge arm up / down signals output by the half-bridge phase difference 180-degree signal unit are processed and XORed with the overlapping signal output by the diagonal overlap detection unit of the synchronous rectification unit to obtain the phase-shifted lagging bridge arm up / down signals. This enables phase-shifted full-bridge peak current mode control of the DC-DC converter, while also achieving voltage mode control. The input interface is simple and easily integrated into the chip's PWM module, simplifying application integration. It eliminates the need for complex IPs like GTM IPs requiring licensing, reducing chip costs. Attached Figure Description

[0025] Figure 1 This is a flowchart of the phase-shifted full-bridge PWM output method based on XOR operation of the present invention.

[0026] Figure 2 This is a schematic diagram of the phase-shifted full-bridge DC-DC converter topology of the present invention.

[0027] Figure 3 This is a schematic diagram of the technical solution in this invention.

[0028] Figure 4 This is a schematic diagram of the timing waveforms of the main signals in the peak current mode of this invention.

[0029] Figure 5 This is a timing waveform diagram of the main signals in the voltage mode of this invention. Detailed Implementation

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. In addition, the forms of the various structures described in the following embodiments are merely illustrative. The phase-shifted full-bridge PWM output method based on XOR operation involved in the present invention is not limited to the structures described in the following embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] like Figure 1-5 As shown, this invention provides a phase-shifted full-bridge PWM output method based on XOR operation, including:

[0032] A PWM signal is generated by the PWM unit;

[0033] The signal unit with a 180-degree phase difference between the half-bridge and the output signal of the PWM unit generates a signal with a 180-degree phase difference between the half-bridge and no dead time insertion.

[0034] The rising and falling edges of the output signal of the PWM unit are delayed by a full-bridge phase difference event regulator.

[0035] Select between phase-shifted full-bridge peak current mode and voltage mode using the mode selection switch;

[0036] The signal output from the half-bridge phase difference 180-degree signal unit is processed by the level XOR phase shift unit to process the upper and lower bridge signals of the leading bridge arm.

[0037] By inserting a dead time unit into the full-bridge dead time unit, a PWM signal controlling the full-bridge switching transistors with a dead time is output.

[0038] The final synchronous rectifier switch control signal is obtained through the synchronous rectifier unit.

[0039] In this embodiment, it should be specifically explained that the PWM unit generates one PWM signal with a settable period and duty cycle; the half-bridge phase difference 180-degree signal unit generates a half-bridge phase difference 180-degree signal with no dead time insertion from the output signal of the PWM unit, which is used for processing the upper and lower bridge signals of the leading and lagging bridge arms respectively; in specific implementation, the PWM unit can be replaced by an external PWM module, which only needs to input a PWM with a fixed duty cycle of 50%; the full-bridge phase difference event regulator delays the rising and falling edges of the output signal of the PWM unit, and the delay time is the expected full-bridge phase angle control amount to obtain the phase difference event; the mode selection switch selects either the phase-shifted full-bridge peak current mode or the voltage mode; the level XOR phase-shifting unit processes the upper and lower bridge signals of the leading bridge arm output by the half-bridge phase difference 180-degree signal unit, and performs a level XOR operation with the overlapping signal output by the synchronous rectification unit and the diagonal overlap detection unit to obtain the phase-shifted upper and lower bridge signals of the lagging bridge arm.

[0040] In this embodiment, it should be specifically noted that the phase-shifted full-bridge peak current mode and voltage mode can be used independently in practical applications. Therefore, any one or a combination of two of the phase-shifted full-bridge peak current mode and voltage mode can be selected according to the actual situation. This embodiment does not limit the specific mode.

[0041] In this embodiment, it should be specifically explained that the full-bridge dead time unit is composed of the leading bridge arm up / down bridge signals output by the half-bridge phase difference 180-degree signal unit and the lagging bridge arm up / down bridge signals output by the level XOR phase shift unit, which are respectively inserted into the dead time to output the full-bridge switching transistor control PWM signal with dead time; the synchronous rectification unit includes a diagonal overlap detection unit, a synchronous rectification delay unit, and a level flipping unit; the diagonal overlap detection unit uses the output signal of the PWM unit and the phase difference event output by the current limiting signal edge event or the full-bridge phase difference event regulator to identify the diagonal overlap part, and outputs the overlap signal of VAB positive voltage and the overlap signal of VAB negative voltage, and simultaneously outputs the overlap signal of VAB positive voltage or negative voltage.

[0042] In this embodiment, it should be specifically noted that the synchronous rectification delay unit delays the rising and falling edges of the positive voltage overlap signal and the negative voltage overlap signal, respectively, so that the synchronous rectification signal and the primary side conduction switch have a dead zone, ensuring that when energy is transferred from the primary side to the secondary side, the two synchronous rectifications on the secondary side will not conduct simultaneously, preventing transformer short circuit; the level flipping unit flips the level of the delayed synchronous rectification signal to obtain the final synchronous rectification switch control signal, and the synchronous rectification enable input signal can disable the synchronous rectification unit, which is suitable for applications using diode rectification on the secondary side.

[0043] In this embodiment, it should be specifically explained that the reference signal (or an externally input PWM with a 50% duty cycle) generated by the PWM unit is divided into complementary signals for the upper and lower bridge arms that are alternately conducting by the half-bridge phase difference 180-degree signal unit; the full-bridge phase difference event regulator generates a phase-shift control quantity based on the preset angle delay of the PWM edge; after the mode selection switch switches the peak current or voltage mode according to the load characteristics, the level XOR phase-shift unit receives the hysteresis bridge arm signal output by the half-bridge phase difference 180-degree signal unit, and performs level flipping operation on the current limiting signal edge event or the phase difference event output by the full-bridge phase difference event regulator, respectively. The flipped level continues until the next edge of the hysteresis bridge arm signal and then the hysteresis bridge arm signal is restored, thereby obtaining the phase-shifted hysteresis bridge arm upper and lower bridge signals.

[0044] Subsequently, the full-bridge dead-time unit inserts lead and lag bridge arm signals into the dead time to prevent bridge arm shoot-through, ultimately outputting four phase-shifted PWM drive signals. The synchronous rectification unit detects the primary and secondary energy transfer windows (diagonal conduction process) and uses delay and level-flipping logic to generate rectification control signals that are staggered from the primary bridge arm actions. This avoids secondary-side short circuits and improves energy efficiency, and can be adapted to diode rectification scenarios through the enable terminal. In typical applications, the system achieves zero-voltage switching (ZVS) through dynamic phase adjustment, improving high-frequency inverter efficiency, while optimizing performance under different loads through mode switching and dead-time management.

[0045] The synchronous rectification unit captures the VAB voltage polarity transition interval (positive voltage overlap during the conduction of the lead arm) in real time through diagonal overlap detection. Combined with current limiting events or phase shift events, it generates a synchronous rectification enable window. The synchronous rectification delay unit delays this window by the rising / falling edge (usually 1% to 5% of the switching cycle) to ensure that the primary-side switch is fully turned on before triggering the secondary-side synchronous rectifier, avoiding the risk of short circuit caused by reverse current. Finally, the level flipping unit generates a rectification control signal that is complementary to the main bridge arm action, and this function can be turned off through the enable pin to adapt to traditional diode rectification (low-power scenarios). In practical applications, this system achieves zero-voltage switching (ZVS) through phase shift control, reducing the switching losses of high-frequency inverters. Combined with mode switching and dead-time optimization, it significantly improves efficiency and EMI characteristics over a wide load range, making it suitable for high-power density power supplies and new energy converters.

[0046] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0047] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A phase-shifted full-bridge PWM output method based on XOR operation, characterized in that: include: A PWM signal is generated by the PWM unit; The signal unit with a 180-degree phase difference between the half-bridge and the output signal of the PWM unit generates a signal with a 180-degree phase difference between the half-bridge and no dead time insertion. The rising and falling edges of the output signal of the PWM unit are delayed by a full-bridge phase difference event regulator. Select between phase-shifted full-bridge peak current mode and voltage mode using the mode selection switch; The signal output from the half-bridge phase difference 180-degree signal unit is processed by the level XOR phase shift unit to process the upper and lower bridge signals of the leading bridge arm. By inserting a dead time unit into the full-bridge dead time unit, a PWM signal controlling the full-bridge switching transistors with a dead time is output. The final synchronous rectifier switch control signal is obtained through the synchronous rectifier unit.

2. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 1, characterized in that: The PWM unit generates a PWM signal with a settable period and duty cycle. The half-bridge phase difference 180-degree signal unit generates a signal with a half-bridge phase difference of 180 degrees and no dead time insertion from the output signal of the PWM unit. These signals are used for processing the upper and lower bridge signals of the leading and lagging bridge arms, respectively.

3. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 1, characterized in that: The full-bridge phase difference event regulator delays the rising and falling edges of the output signal of the PWM unit for a delay time equal to the expected full-bridge phase angle control value, thereby obtaining a phase difference event; the mode selection switch selects either the phase-shifted full-bridge peak current mode or the voltage mode.

4. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 1, characterized in that: The level XOR phase shifting unit processes the leading bridge arm up and down bridge signals output by the half-bridge phase difference 180-degree signal unit, and performs level XOR operation with the overlapping signal output by the synchronous rectification unit and the diagonal overlap detection unit, respectively, to obtain the phase-shifted lagging bridge arm up and down bridge signals.

5. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 1, characterized in that: The full-bridge dead-time unit is formed by inserting the leading bridge arm up and down bridge signals output from the half-bridge phase difference 180-degree signal unit and the lagging bridge arm up and down bridge signals output from the level XOR phase shift unit into the dead time, and outputting the full-bridge switching transistor control PWM signal with dead time.

6. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 1, characterized in that: The synchronous rectification unit includes a diagonal overlap detection unit, a synchronous rectification delay unit, and a level flipping unit.

7. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 6, characterized in that: The diagonal overlap detection unit uses the output signal of the PWM unit and the phase difference event output by the current limiting signal edge event or the full-bridge phase difference event regulator to identify the diagonal overlap part, and outputs the overlap signal of VAB positive voltage and the overlap signal of VAB negative voltage, and simultaneously outputs the overlap signal of VAB positive voltage or negative voltage.

8. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 6, characterized in that: The synchronous rectification delay unit delays the rising and falling edges of the positive voltage overlap signal and the negative voltage overlap signal respectively, so that there is a dead time between the synchronous rectification signal and the primary side conduction switch, ensuring that when energy is transferred from the primary side to the secondary side, the two synchronous rectifications on the secondary side will not conduct at the same time, thus preventing the transformer from short-circuiting.

9. A phase-shifted full-bridge PWM output method based on XOR operation according to claim 6, characterized in that: The level-flipping unit flips the level of the delayed synchronous rectified signal to obtain the final synchronous rectified switch control signal. The synchronous rectified enable input signal can disable the synchronous rectified unit, which is suitable for applications where diode rectification is used on the secondary side.

10. The phase-shifted full-bridge PWM output method based on XOR operation according to claim 2, characterized in that: In practice, the PWM unit can be replaced by an external PWM module, requiring only the input of a PWM module with a fixed duty cycle of 50%.

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