Display device

Abstract

A display device includes a first sub-pixel including a first light emitting element configured to emit light of a first color and a first driving transistor configured to drive the first light emitting element, a second sub-pixel including a second light emitting element configured to emit light of a second color and a second driving transistor configured to drive the second light emitting element, at least one first dummy hole disposed in the first driving transistor, and at least one second dummy hole disposed in the second driving transistor. Further, a total aperture area of at least one first dummy hole of the first driving transistor is different from a total aperture area of at least one second dummy hole of the second driving transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0055681, filed on April 25, 2024, the entire contents of which are expressly incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device capable of reducing changes in brightness and color coordinates caused by temperature variations. Background Technology

[0004] Electroluminescent display devices have the advantages of high brightness, low operating voltage, ultra-thin film, and the ability to achieve free shape by utilizing self-emissive elements.

[0005] Because electroluminescent display devices have the characteristic that the brightness of the light-emitting element changes with temperature, the brightness may vary depending on temperature.

[0006] The background art described above is part of the design of this disclosure or is technical information obtained through the process of designing this disclosure. However, it should not be considered prior art disclosed to the public prior to this disclosure simply because it is mentioned in or in connection with the discussion in the background art section. The description in the background art section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit the invention. Summary of the Invention

[0007] The inventors have recognized that in electroluminescent display devices, red, green, and blue light-emitting elements with different light-emitting materials have different temperature-dependent brightness variation characteristics, and therefore, differences in brightness variation may occur between the three color sub-pixels depending on temperature fluctuations. As a result, the white coordinate of the electroluminescent display device may fluctuate depending on temperature fluctuations, which may degrade optical quality.

[0008] Therefore, this disclosure aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0009] In one aspect, this disclosure provides a display device that improves upon luminance and color coordinate variations caused by temperature changes.

[0010] The purposes of this disclosure are not limited to those described above. Other purposes not mentioned in this disclosure can be understood based on the following description and will become clearer based on exemplary embodiments according to this disclosure. Furthermore, it will be readily understood that the purposes of this disclosure can be achieved using the means shown in the claims or a combination thereof.

[0011] Additional advantages and features of this disclosure will be set forth in part in the following description, and in part will become apparent to those skilled in the art upon review of the following, or may be learned from practice of this disclosure. The technical benefits and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and its claims, and in the accompanying drawings.

[0012] To achieve these and other benefits, and in accordance with the purposes of this disclosure, as embodied and broadly described herein, this disclosure provides a display device having: a first sub-pixel including a first light-emitting element configured to emit light of a first color and a first driving transistor configured to drive the first light-emitting element; and a second sub-pixel including a second light-emitting element configured to emit light of a second color and a second driving transistor configured to drive the second light-emitting element, wherein the area of ​​the dummy aperture of the first driving transistor and the area of ​​the dummy aperture of the second driving transistor have different area ratios.

[0013] According to another aspect of this disclosure, a display device is provided, the display device comprising: a first sub-pixel, the first sub-pixel including a first light-emitting element configured to emit light of a first color, a first driving transistor configured to drive the first light-emitting element, and a first dummy aperture overlapping a first gate electrode of the first driving transistor; a second sub-pixel, the second sub-pixel including a second light-emitting element configured to emit light of a second color, a second driving transistor configured to drive the second light-emitting element, and a second dummy aperture overlapping a second gate electrode of the second driving transistor; and a third sub-pixel including a third light-emitting element configured to emit light of a third color, a third driving transistor configured to drive the third light-emitting element, and a third dummy aperture overlapping a third gate electrode of the third driving transistor, wherein the area of ​​the first dummy aperture has a different area ratio than each of the area of ​​the second dummy aperture and the area of ​​the third dummy aperture, and wherein the area of ​​the second dummy aperture is the same as or different from the area of ​​the third dummy aperture.

[0014] According to another aspect of this disclosure, a display device is provided, the display device having: a first sub-pixel, the first sub-pixel including a first light-emitting element configured to emit light of a first color, a first driving transistor configured to drive the first light-emitting element, and a first dummy aperture overlapping the first driving transistor; and a second sub-pixel, the second sub-pixel including a second light-emitting element configured to emit light of a second color, a second driving transistor configured to drive the second light-emitting element, and a second dummy aperture overlapping the second driving transistor, wherein the first driving transistor and the second driving transistor have different dummy aperture area ratios depending on the brightness variation characteristics of the first light-emitting element and the second light-emitting element with temperature.

[0015] According to another aspect of this disclosure, a display device is provided, the display device having: a first sub-pixel, the first sub-pixel including a first light-emitting element configured to emit light of a first color, a first driving transistor configured to drive the first light-emitting element, and a first dummy aperture overlapping the first driving transistor; and a second sub-pixel, the second sub-pixel including a second light-emitting element configured to emit light of a second color, a second driving transistor configured to drive the second light-emitting element, and a second dummy aperture overlapping the second driving transistor, wherein the first driving transistor and the second driving transistor have different dummy aperture area ratios depending on the aperture ratio of the first light-emitting element and the second light-emitting element.

[0016] It should be understood that both the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of this disclosure. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate exemplary embodiments of this disclosure and, together with the specification, serve to illustrate the principles of this disclosure. In the drawings:

[0018] Figure 1 This is a block diagram schematically illustrating the configuration of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2A and Figure 2B This is a diagram illustrating a drive transistor structure with a dummy hole according to an exemplary embodiment of the present disclosure.

[0020] Figure 3A and Figure 3B This is a diagram illustrating a drive transistor structure with a dummy hole according to an exemplary embodiment of the present disclosure.

[0021] Figures 4A to 4C This is a diagram illustrating a drive transistor structure with a dummy hole according to an exemplary embodiment of the present disclosure.

[0022] Figure 5 This is a diagram illustrating a portion of the pixel array of a display device according to an exemplary embodiment of the present disclosure.

[0023] Figure 6 This is a diagram illustrating a portion of the pixel array of a display device according to an exemplary embodiment of the present disclosure.

[0024] Figure 7 This is an equivalent circuit diagram illustrating a subpixel configuration according to an exemplary embodiment of the present disclosure.

[0025] Figures 8A to 8D This is a diagram illustrating the layout structure of subpixels according to a comparative example and an exemplary embodiment of the present disclosure.

[0026] Figure 9 This is a cross-sectional view illustrating the structure of a sub-pixel according to an exemplary embodiment of the present disclosure;

[0027] Figure 10 This is a graph comparing the temperature and brightness sensitivity of a display device based on exemplary embodiments and comparative examples of this disclosure.

[0028] Figure 11 This is a graph comparing the temperature color sensitivity of a display device based on exemplary embodiments and comparative examples of this disclosure.

[0029] Figures 12A to 12D This is a graph comparing the white coordinate changes of a display device according to temperature changes, based on an exemplary embodiment and comparative example of this disclosure.

[0030] Through the accompanying drawings and detailed embodiments, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and descriptions of these elements may be exaggerated for clarity, illustration, and convenience.

[0031] Specific exemplary implementation methods

[0032] The advantages and features of this disclosure, and their implementation, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0033] The shapes, dimensions (e.g., size, ratio, width, thickness, length, diameter, radius, area, etc.), angles, and numbers disclosed in the accompanying drawings for describing exemplary embodiments of this disclosure are merely examples and may be exaggerated for the purpose of effective description of the technical content; therefore, this disclosure is not limited to the details shown. Throughout the text, similar reference numerals refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted or simplified where such detailed descriptions are determined to unnecessarily obscure the essential points of this disclosure.

[0034] When using the terms “comprising,” “containing,” “having,” and “including” as described in this specification, other parts may also exist unless terms such as “only” or “just” are used. Singular terms may include plural forms unless otherwise indicated.

[0035] When interpreting a component, it is interpreted as including an error region or tolerance region, even though there is no explicit description of it.

[0036] When describing positional relationships, for example, when the positional order is described as “on top of,” “above,” “on the top of,” “upper,” “lower,” “below,” “below,” “beside,” or “adjacent,” situations in which they do not touch may be included unless terms such as “exactly” or “directly” are used.

[0037] When it is mentioned that the first element is "above" the second element, this does not mean that the first element must be above the second element in the drawing. The upper and lower parts of the object of interest can change depending on the orientation of the object. As a result, the case of the first element being "above" the second element includes the case where the first element is "below" the second element in the drawing or in the actual configuration, as well as the case where the first element is "above" the second element.

[0038] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “after,” “next,” and “before,” discontinuous situations may be included unless terms such as “immediately,” “following immediately,” or “directly” are used.

[0039] It should be understood that although the terms “first,” “second,” “A,” “B,” “a,” “b,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0040] It should be understood that the term "at least one" includes all combinations associated with any one of them. For example, "at least one of the first element, the second element, and the third element" can include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0041] Features of the various exemplary embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven. The exemplary embodiments of this disclosure may be performed independently of each other or may be performed together in a mutually dependent relationship.

[0042] In the following description, aspects of this disclosure will be described with reference to the accompanying drawings. Since the scale of each element shown in the drawings differs from the actual scale for ease of description, this disclosure is not limited to the scales shown. Furthermore, all components of each display device, display apparatus, and display panel according to all aspects of this disclosure are operatively coupled and configured.

[0043] Figure 1 This is a block diagram schematically illustrating the configuration of a display device according to an exemplary embodiment of the present disclosure.

[0044] A display device according to one exemplary embodiment may be an electroluminescent display device. Electroluminescent display devices may include, but are not limited to, organic light-emitting diode (OLED) display devices, quantum dot light-emitting diode (QD) display devices, micro LEDs, mini LEDs, and inorganic light-emitting diode (ILD) display devices.

[0045] Reference Figure 1 A display device 1000 according to an exemplary embodiment may include, but is not limited to, a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, a gamma voltage generation unit 500, and a power management circuit 700. The display device may include more or fewer components. The gate driver 200 and the data driver 300 may be integrated and represented as a panel driver driving the display panel 100. Alternatively, the gate driver 200 and the data driver 300 may be separate. The gate driver 200, the data driver 300, the timing controller 400, the gamma voltage generation unit 500, and the power management circuit 700 may be collectively referred to as a display driver.

[0046] Display panel 100 can be a rigid display panel or a flexible display panel that can change shape, such as a bendable, foldable, flexible, rollable, or stretchable display panel.

[0047] The display panel 100 can display images via a pixel array, in which subpixels SP are arranged in a matrix in a display area DA. In one exemplary embodiment, the display panel 100 may further include a touch sensor array arranged in the display area DA to sense a user's touch.

[0048] Pixels arranged in the display area DA may include multiple sub-pixels SP, which may be configured to emit light of different colors to achieve white light. Sub-pixels SP may include red sub-pixels emitting red light (hereinafter referred to as R sub-pixels), green sub-pixels emitting green light (hereinafter referred to as G sub-pixels), blue sub-pixels emitting blue light (hereinafter referred to as B sub-pixels), and may also include white sub-pixels emitting white light (hereinafter referred to as W sub-pixels). Alternatively, sub-pixels SP may emit light of other color systems such as CMYK.

[0049] The sub-pixel SP may have pixel circuitry, which includes a light-emitting element EL and a driving transistor DT that independently drives the light-emitting element EL. The light-emitting element EL may include, but is not limited to, organic light-emitting diodes, quantum dot light-emitting diodes, micro LEDs, mini LEDs, and inorganic light-emitting diodes. The pixel circuitry may have various circuit configurations, including, but is not limited to, the driving transistor DT, transistors connected to at least one of nodes N1, N2, N3 connected to the driving transistor DT, and capacitors. The pixel circuitry of the sub-pixel SP may be connected to signal lines, including gate lines (e.g., scan lines), data lines, power lines, etc., arranged on the display panel 100.

[0050] Light-emitting elements (ELs) can exhibit temperature-dependent brightness variation characteristics, and therefore can possess high temperature-sensitive brightness sensitivity (TLS). R, G, and B ELs, which utilize different types of luminescent materials, exhibit varying temperature-dependent brightness variation characteristics, and thus can possess high temperature-sensitive color sensitivity (TCS).

[0051] According to an exemplary embodiment, the display panel 100 can control the temperature-dependent brightness variation of the light-emitting element EL by controlling the temperature-dependent threshold voltage variation ΔVth of the driving transistor DT.

[0052] According to an exemplary embodiment, a display panel 100 can alter the temperature-dependent threshold voltage variation ΔVth of a driving transistor DT by applying dummy vias to multiple insulating layers of the driving transistor DT in a sub-pixel SP. The dummy vias of the driving transistor DT can be disposed in the multiple insulating layers in the same process as contact vias to reduce process steps and simplify the manufacturing process. The dummy vias of the driving transistor DT can also be used, along with contact vias, as channels to release hydrogen atoms in the multiple insulating layers during a heat treatment process to increase the degree of dehydrogenation, thereby increasing the temperature-dependent threshold voltage variation ΔVth of the driving transistor DT.

[0053] Therefore, the display panel 100 can suppress the temperature-dependent brightness change of the light-emitting element EL by increasing the temperature-dependent threshold voltage change ΔVth of the driving transistor DT, thereby reducing or minimizing the temperature-dependent brightness sensitivity TLS and temperature-dependent color sensitivity TCS of the sub-pixel SP.

[0054] According to an exemplary embodiment, the display panel 100 may differentially control the threshold voltage change ΔVth of the driving transistor DT by applying the number or area ratio of dummy holes (i.e., aperture ratio or aperture area) to the driving transistor DT based on the aperture ratio (aperture area) or light-emitting area of ​​the light-emitting element EL or the temperature-dependent brightness variation characteristics of the light-emitting element EL. A detailed description of this will be provided later.

[0055] Therefore, the display panel 100 can reduce or minimize the difference in brightness variation caused by temperature changes between sub-pixels SP by differentially controlling the threshold voltage change ΔVth of the driving transistor DT in at least two sub-pixels SP of different colors. Thus, it can reduce or minimize the change in white coordinates caused by temperature changes, thereby improving optical quality.

[0056] The gate driver 200 can be configured to be controlled according to a plurality of gate control signals supplied from the timing controller 400, and can be individually configured to drive the gate lines of the display panel 100. The gate driver 200 can be configured to supply a gate on-state voltage to each gate line during a driving period for each gate line, and can be configured to supply a gate off-state voltage to the corresponding gate line during a non-driving period for each gate line. Depending on the type of transistor (N-type or P-type) of the gate driver 200, the gate on-state voltage can be a gate high voltage or a gate low voltage, and the gate off-state voltage can be a gate high voltage or a gate low voltage different from the gate on-state voltage. The gate driver 200 can be integrated into the bezel region of the display panel 100 in the form of an in-panel gate (GIP) formed together with the thin-film transistors of the display area DA.

[0057] In one exemplary embodiment, the gate driver 200, integrated in the display panel 100, can be configured to receive a plurality of gate control signals from the timing controller 400 via a level shifter. The level shifter can be configured to receive timing control signals from the timing controller 400 and can be configured to level-shift or perform logic processing on these timing control signals to generate a plurality of gate control signals for supply to the gate driver 200.

[0058] The gamma voltage generation unit 500 can be configured to generate multiple reference gamma voltages with different gamma voltage levels and supply the multiple reference gamma voltages to the data driver 300. The gamma voltage generation unit 500 can be configured, under the control of the timing controller 400, to generate multiple reference gamma voltages corresponding to the gamma characteristics of the display device 1000 and supply the multiple reference gamma voltages to the data driver 300. The gamma voltage generation unit 500 can be configured to adjust the reference gamma voltage level according to gamma data supplied from the timing controller 400 and output the reference gamma voltage level to the data driver 300. The gamma voltage generation unit 500 can be configured to adjust, for example, a high-potential power supply voltage that can serve as the maximum gamma voltage, according to peak brightness control from the timing controller 400, and can be configured to adjust the multiple reference gamma voltages according to the adjusted high-potential power supply voltage and output the multiple reference gamma voltages to the data driver 300.

[0059] The data driver 300 can be configured to be controlled according to multiple data control signals supplied from the timing controller 400, and can be configured to convert digital data supplied from the timing controller 400 into analog data signals using a digital-to-analog converter circuit. The data driver 300 can be configured to divide or convert multiple reference gamma voltages supplied from the gamma voltage generation unit 500 into gamma voltages, and can be configured to use the divided gamma voltages to convert digital data into analog data signals. The data driver 300 can be configured to supply the converted data signals to the data lines of the display panel 100.

[0060] In one exemplary embodiment, the data driver 300 may be further configured to supply a reference voltage to the reference line of the display panel 100 under the control of the timing controller 400. The data driver 300 may be configured to supply reference voltages for display and sensing respectively under the control of the timing controller 400.

[0061] In one exemplary embodiment, the data driver 300 may further include a sensing unit to sense signals reflecting the driving characteristics of the sub-pixel SP via a reference line or power line in a voltage sensing manner and / or a current sensing manner under the control of the timing controller 400, and to send the sensing results to the timing controller 400. Alternatively, the data driver 300 may be separate from the sensing unit.

[0062] The timing controller 400 can be configured to receive source image data and timing control signals from an external host system. The host system may include computers such as laptops, netbooks, TV systems, set-top boxes, portable terminals such as PDAs (personal digital assistants), electronic tablets (e.g., tablet computers), or mobile phones (e.g., smartphones), computer monitors, automotive devices, wearable devices, and vehicle interior systems, but embodiments of this disclosure are not limited thereto. Timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0063] The timing controller 400 can be configured to control the gate driver 200 and the data driver 300 using timing control signals supplied from the host system and internally stored timing setting information. The timing controller 400 can be configured to generate a plurality of gate control signals for controlling the drive timing of the gate driver 200 and supply the plurality of gate control signals to the gate driver 200. The timing controller 400 can be configured to generate a plurality of data control signals for controlling the drive timing of the data driver 300 and supply the plurality of data control signals to the data driver 300. In one exemplary embodiment, the timing controller 400 can be represented as a controller.

[0064] The timing controller 400 can be configured to perform at least one of various image processing operations on input image data supplied from the host system, including brightness correction, degradation correction, image quality correction, image scaling, color adjustment, effects addition, and image compositing for reducing power consumption.

[0065] In one exemplary embodiment, the timing controller 400 may be further configured to compensate for characteristic deviations of sub-pixels SP stored in memory before or during the supply of image processing data to the data driver 300.

[0066] In one exemplary embodiment, the timing controller 400 can be configured to periodically or irregularly execute a sensing mode based on a drive sequence requested or set from a host system or user. The timing controller 400 can be configured to control the system drivers 200, 300 and power management circuitry 700 to drive the display panel 100 and update compensation data stored in memory during the sensing mode. In the sensing mode, the timing controller 400 can be configured to sense the threshold voltage and mobility of the driving transistor DT, reflecting the characteristics or degradation of the sub-pixels SP of the display panel 100, via the data driver 300, and can also be configured to sense the threshold voltage of the light-emitting element EL. The timing controller 400 can be configured to process the sensing results and update the compensation data of the sub-pixels SP.

[0067] In one exemplary embodiment, the timing controller 400 may be configured to accumulate image data of the subpixel SP to predict the degradation of the subpixel SP, and update the compensation data by sensing the threshold voltage of the light-emitting element EL of the subpixel SP with relatively large degradation.

[0068] The power management circuit 700 can be configured to generate and supply various drive voltages necessary for the operation of all components of the display device 1000 (including the display panel 100, gate driver 200, data driver 300, timing controller 400, and gamma voltage generator 500, etc.) by using input voltage.

[0069] Figures 2A to 4C This is a diagram illustrating a drive transistor structure with a dummy hole according to an exemplary embodiment of the present disclosure.

[0070] Reference Figure 2A and Figure 3A According to an exemplary embodiment, the first driving transistor DT_SP1 of the first sub-pixel may include an active layer ACT on a substrate SUB, a gate insulating layer GI on the active layer ACT, a gate electrode GE1 on the gate insulating layer GI, a first source / drain electrode SD11 and a second source / drain electrode SD12 disposed facing each other as conductive regions in the active layer ACT, with a channel CH1 between them. The first driving transistor DT_SP1 is disposed on a plurality of insulating layers including an interlayer insulating layer ILD on the gate electrode GE1, and may further include a first source / drain connection electrode SD14 connected to the first source / drain electrode SD11 through a contact hole 11, and a second source / drain connection electrode SD15 connected to the second source / drain electrode SD12 through a contact hole 12.

[0071] Reference Figure 2B and Figure 3BAccording to an exemplary embodiment, the second driving transistor DT_SP2 or DTa_SP2 of the second sub-pixel may include an active layer ACT on the substrate SUB, a gate insulating layer GI on the active layer ACT, a gate electrode GE2 on the gate insulating layer GI, a first source / drain electrode SD21 and a second source / drain electrode SD22 disposed facing each other as conductive regions in the active layer ACT, with a channel CH2 between them. The second driving transistor DT_SP2 or DTa_SP2 may also include a first source / drain connection electrode SD23 disposed on the interlayer insulating layer ILD and connected to the first source / drain electrode SD21 through a contact hole 21, and a second source / drain connection electrode SD24 connected to the second source / drain electrode SD22 through a contact hole 22.

[0072] The gate electrode GE1 of the first driving transistor DT_SP1 can be connected to the second node N2 of the first sub-pixel. The first source / drain electrode SD11 can be connected to the first node N1 of the first sub-pixel through the first source / drain connection electrode SD14, and the second source / drain electrode SD12 can be connected to the third node N3 of the first sub-pixel through the second source / drain connection electrode SD15. The gate electrode GE2 of the second driving transistor DT_SP2 or DT_SP2 can be connected to the second node N2 of the second sub-pixel. The first source / drain electrode SD21 can be connected to the first node N1 of the corresponding (i.e., second) sub-pixel through the first source / drain connection electrode SD23, and the second source / drain electrode SD22 can be connected to the third node N3 of the second sub-pixel through the second source / drain connection electrode SD24.

[0073] The contact holes 11 and 12 of the first driving transistor DT_SP1 and the contact holes 21 and 22 of the second driving transistor DT_SP2 or DT_SP2 can be configured through multiple insulating layers including the interlayer insulating layer ILD and the gate insulating layer GI.

[0074] According to an exemplary embodiment, the first driving transistor DT_SP1 may further include a dummy via 13 disposed in a plurality of insulating layers including an interlayer insulating layer ILD on a gate electrode GE1. According to an exemplary embodiment, the second driving transistor DT_SP2 or DT_SP2 may further include a dummy via 23 or 23a disposed in a plurality of insulating layers including an interlayer insulating layer ILD on a gate electrode GE2.

[0075] The dummy vias 13 and 23 or 23a of the driving transistors DT_SP1 and DT_SP2 or DTa_SP2 can be disposed in multiple insulating layers, including the interlayer insulating layer (ILD), using the same process as the contact vias 11, 12, 21, and 22. The dummy vias 13 and 23 or 23a, together with the contact vias 11, 12, 21, and 22, can be used as degassing channels in a heat treatment process following the contact via process by releasing hydrogen atoms from the insulating layers, including the ILD. Therefore, according to an exemplary embodiment, the driving transistors DT_SP1 and DT_SP2 or DTa_SP2 can increase the temperature-dependent threshold voltage change ΔVth by increasing the degree of hydrogen removal via dummy vias 13 and 23 or 23a, resulting in a reduction in the temperature-sensitive luminance sensitivity (TLS) and temperature-sensitive color sensitivity (TCS) of the first and second sub-pixels.

[0076] Furthermore, in a display device according to an exemplary embodiment, the aperture ratio, aperture area, or number of dummy holes 13 and 23 or 23a can be applied differently to the first driving transistor DT_SP1 and the second driving transistor DT_SP2 or DT_SP2 based on the aperture ratio or light-emitting area of ​​the light-emitting element or the temperature-dependent brightness variation characteristics of the light-emitting element, thereby controlling the temperature-dependent threshold voltage variation (ΔVth) of the first driving transistor DT_SP1 and the second driving transistor DT_SP2 or DT_SP2 differently.

[0077] Reference Figure 2A and Figure 2B In one exemplary embodiment, the number of dummy holes 13 of the first driving transistor DT_SP1 of the first sub-pixel and the number of dummy holes 23 of the second driving transistor DT_SP2 of the second sub-pixel may be different. Each of the dummy holes 13 and 23 may have the same width W1 and the same area as each of the contact holes 11, 12, 21, and 22.

[0078] Figure 2B The number of dummy vias 23 in the second driving transistor DT_SP2 shown can be greater than [number missing]. Figure 2B The number of dummy vias 13 shown is as follows: For example, the first driving transistor DT_SP1 may include one dummy via 13, while the second driving transistor DT_SP2 may include two dummy vias 23.

[0079] See Figure 3A and Figure 3B In one exemplary embodiment, the width W1 and area of ​​the dummy hole 13 of the first driving transistor DT_SP1 of the first sub-pixel may be different from the width W2 and area of ​​the dummy hole 23a of the second driving transistor DT_SP2 of the second sub-pixel.

[0080] Figure 3B The width W2 and area of ​​the dummy via 23a of the second driving transistor DTa_SP2 shown in the figure can be greater than 100 mm. Figure 3A The width W1 and area of ​​the dummy hole 13 of the first driving transistor DT_SP1 are shown. The width W2 and area of ​​the dummy hole 23a of the second driving transistor DT_SP2 can be greater than the width and area of ​​each of the contact holes 21 and 22 of the second driving transistor DT_SP2.

[0081] Reference Figures 2A to 3B According to an exemplary embodiment, the driving transistors DT_SP1, DT_SP2, and DT_SP2 may further include dummy electrodes SD16 and SD25 disposed on a plurality of insulating layers including an interlayer insulating layer (ILD) and connected to gate electrodes GE1 and GE2 via dummy vias 13, 23, and 23a. The dummy electrodes SD16 and SD25 are electrically floating and may be represented as floating electrodes. The dummy electrodes SD16 and SD25 cover the dummy vias 13, 23, and 23a, thereby preventing or reducing defects that may be caused by the dummy vias 13, 23, and 23a in subsequent processes after the heat treatment process. In an exemplary embodiment, the dummy electrodes SD16 and SD25 may be omitted.

[0082] Reference Figures 4A to 4C In one exemplary embodiment, the dummy via 13b disposed in the first driving transistor DTb_SP1 of the first sub-pixel and the dummy vias 23b and 23c disposed in the second driving transistors DTb_SP2 and DTc_SP2 of the second sub-pixel can have the following structure: these dummy vias are buried in the insulating material of the planarization layer PLN disposed on the source / drain connection electrodes SD14, SD15, SD23 and SD24.

[0083] A second driving transistor DT_SP2, DTTa_SP2, DTb_SP2, or DTc_SP2 having dummy holes 23, 23a, 23b, or 23c larger than the dummy holes 13 or 13b of the first driving transistor DT_SP1 or DTb_SP1 in terms of aperture ratio, aperture area, or number, can have a larger temperature-dependent threshold voltage variation ΔVth than the first driving transistor DT_SP1 or DTb_SP1. In such cases... Figure 4BIn cases involving multiple dummy holes, the aperture ratio and aperture area can refer to the total aperture ratio and total aperture area of ​​the multiple dummy holes, respectively. In an exemplary embodiment, a first driving transistor DT_SP1 or DTb_SP1 can be applied to a first sub-pixel, which has relatively low brightness variation characteristics depending on the temperature of the light-emitting element. Simultaneously, a second driving transistor DT_SP2, DTTa_SP2, DTb_SP2, or DTc_SP2 can be applied to a second sub-pixel, which has relatively high brightness variation characteristics depending on the temperature of the light-emitting element.

[0084] Therefore, the temperature-luminance sensitivity TLS of the second sub-pixel can be further reduced by the second driving transistor DT_SP2, DTTa_SP2, DTb_SP2 or DTc_SP2, and as a result, the temperature-dependent luminance variation difference between the first and second sub-pixels is reduced or minimized, thereby reducing or minimizing the temperature-color sensitivity TCS of the sub-pixel, thereby reducing or minimizing the white coordinate fluctuation according to temperature fluctuation.

[0085] In one exemplary embodiment, the dummy vias 13, 13b, 23, 23a, 23b, and 23c of the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, and DTc_SP2 can be arranged to overlap with the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, and DTc_SP2, or they can be arranged in the insulating layer of adjacent regions that do not overlap with the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, and DTc_SP2.

[0086] In one exemplary embodiment, the dummy vias 13, 13b, 23, 23a, 23b, or 23c of the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, or DTc_SP2 can be arranged in an insulating layer in a region adjacent to the gate electrode GE1 or GE2.

[0087] In one exemplary embodiment, the dummy vias 13, 13b, 23, 23a, 23b, or 23c of the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, or DTc_SP2 may be arranged to overlap or not overlap with at least one of the gate electrode GE1 or GE2 and the active layer ACT.

[0088] In one exemplary embodiment, at least some of the dummy vias 13, 13b, 23, 23a, 23b and 23c of the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2 and DTc_SP2 may be arranged so as not to overlap with the gate electrode GE1 or GE2 or the active layer ACT.

[0089] In one exemplary embodiment, the closer the dummy holes 13, 13b, 23, 23a, 23b, and 23c in the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, and DTc_SP2 are to the active layer ACT or channels CH1 and CH2, the greater the increase in the emission of hydrogen atoms in the insulating layer near the active layer ACT, thereby further increasing the temperature-dependent threshold voltage change ΔVth. Therefore, in a display device according to an exemplary embodiment, the temperature luminance sensitivity TLS and temperature chromaticity sensitivity TCS of the sub-pixels can be further reduced, thereby improving optical quality.

[0090] Figure 5 and Figure 6 This is a diagram illustrating a portion of the pixel array of a display device according to an exemplary embodiment of the present disclosure.

[0091] Reference Figure 5 According to an exemplary embodiment, a display panel 100a may include a pixel matrix in which pixels PXa, including R / G / B sub-pixels Ra, Ga, and Ba, are repeatedly arranged in a first direction X and a second direction Y. G sub-pixels Ga and R sub-pixels Ra may be arranged adjacent to each other in the second direction Y, and B sub-pixels Ba may be arranged adjacent to G sub-pixels Ga and R sub-pixels Ra in the first direction X, but this arrangement is not limited to this configuration.

[0092] Reference Figure 6 According to an exemplary embodiment, a display panel 100b may include a pixel matrix in which first-type pixels PXb, including R / G sub-pixels Rb and Gb, and second-type pixels PXc, including B / G sub-pixels Bb and Gb, are arranged alternately and repeatedly in a first direction X and a second direction Y. R sub-pixels Rb and B sub-pixels Bb may be arranged adjacent to each other in the first direction X and the second direction Y, G sub-pixels Gb may be arranged adjacent to R sub-pixels Rb in a first diagonal direction, and G sub-pixels Gb may be arranged adjacent to B sub-pixels Bb in a second diagonal direction, but are not limited to this arrangement.

[0093] R / G / B subpixels Ra / Ga / Ba or Rb / Gb / Bb / Gb can have a light-emitting region in which the R / G / B light-emitting elements emit light, and the remaining region other than the light-emitting region can be a non-light-emitting region arranged with a black matrix.

[0094] In R / G / B sub-pixels Ra / Ga / Ba or Rb / Gb / Bb / Gb, considering the efficiency and lifetime of the B light-emitting element, the light-emitting area (aperture ratio) of the B light-emitting element in the B sub-pixels Ba and Bb can be the largest. The light-emitting area (aperture ratio) of the R light-emitting element in the R sub-pixels Ra and Rb or the G light-emitting element in the G sub-pixels Ga and Gb can be the smallest. In one exemplary embodiment, such as... Figure 5 As shown, the light-emitting area of ​​the G light-emitting element of the G sub-pixel Ga can be larger than the light-emitting area of ​​the R light-emitting element of the R sub-pixel Ra, or in an exemplary embodiment, as... Figure 6 As shown, the light-emitting area of ​​the R light-emitting element of the R sub-pixel Rb can be greater than the light-emitting area of ​​the G light-emitting element of the G sub-pixel Gb.

[0095] Reference Figures 2A to 6 Each of the R / G / B sub-pixels Ra / Ga / Ba, Rb / Gb / Bb / Gb according to an exemplary embodiment may include either a first driving transistor DT_SP1 or DTb_SP1 having a dummy hole 13 or 13b, or any of a second driving transistor DT_SP2, DTTa_SP2, DTb_SP2 and DTc_SP2 having dummy holes 23, 23a, 23b or 23c.

[0096] Therefore, according to an exemplary embodiment, the display panel 100a or 100b can reduce the temperature luminance sensitivity TLS and temperature color sensitivity TCS of the R / G / B sub-pixels Ra / Ga / Ba or Rb / Gb / Bb / Gb by increasing the temperature-dependent threshold voltage change ΔVth of the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2 or DTc_SP2.

[0097] In an R / G / B sub-pixel Ra / Ga / Ba or Rb / Gb / Bb / Gb according to an exemplary embodiment, at least one of the R / G sub-pixels Ra / Ga or Rb / Gb may include a first driving transistor DT_SP1 or DTb_SP1 having a dummy aperture 13 or 13b. A B sub-pixel Ba or Bb having a relatively high aperture ratio of the B light-emitting element or a large temperature-dependent brightness variation may include a second driving transistor DT_SP2, DT_SP2, DTb_SP2, or DTc_SP2 having dummy apertures 23, 23a, 23b, or 23c.

[0098] Therefore, for the first driving transistor DT_SP1 or DTb_SP1 and the second driving transistors DT_SP2, DTTa_SP2, DTb_SP2 or DTc_SP2, the display panel 100a or 100b according to an exemplary embodiment has different temperature-dependent threshold voltage variations ΔVth, thereby reducing or minimizing the temperature-dependent brightness variation differences between R / G / B sub-pixels Ra / Ga / Ba or Rb / Gb / Bb / Gb, thereby reducing or minimizing the temperature-dependent color sensitivity (TCS) of the R / G / B sub-pixels Ra / Ga / Ba or Rb / Gb / Bb / Gb, and thus reducing or minimizing the temperature-dependent white coordinate variation. For example, the number, shape, or size of dummy holes can be configured for the B sub-pixels to produce, for example, a larger threshold voltage variation ΔVth than that of the R or G sub-pixels, so that the temperature-dependent brightness variation differences between the R / G / B sub-pixels can be reduced. Forming dummy holes of different depths can also be used to adjust the threshold voltage variation (dummy holes formed near the ACT layer increase the threshold voltage variation).

[0099] Figure 7 This is an equivalent circuit diagram illustrating the configuration of sub-pixels according to an exemplary embodiment of the present disclosure.

[0100] Reference Figure 7 According to one exemplary embodiment, a sub-pixel SPa may include a light-emitting element (OLED) and pixel circuitry independently driving the OLED. The pixel circuitry may include a driving transistor DT, multiple transistors T2 to T8, and a storage capacitor Cst, but this disclosure is not limited thereto. The sub-pixel may include other numbers of transistors and / or capacitors and / or [other components]. Figure 7 The circuit configurations shown are different.

[0101] Each of the transistors DT, T2 to T8 in the pixel circuit can be made of any of the following materials: polycrystalline silicon semiconductors such as low-temperature polycrystalline silicon semiconductors (LTPS), amorphous silicon semiconductors, and oxide semiconductors such as IZO (indium zinc oxide), IGO (indium gallium oxide), ITO (indium tin oxide), IGZO (indium gallium zinc oxide), IGZTO (indium gallium zinc tin oxide), GZTO (gallium zinc tin oxide), GZO (gallium zinc oxide), and ITZO (indium tin zinc oxide). In one exemplary embodiment, some or all of the transistors DT, T2 to T8 in the pixel circuit can be formed as P-type transistors such as P-type polycrystalline silicon transistors or P-type oxide transistors. In one exemplary embodiment, some or all of the transistors DT, T2 to T8 in the pixel circuit can be formed as N-type transistors such as N-type polycrystalline silicon transistors or N-type oxide transistors. In one exemplary embodiment, the transistors DT, T2 to T8 in the pixel circuit can be formed by mixing P-type transistors and N-type transistors. For example, the transistors DT, T2 to T8 of the pixel circuit can be formed by mixing P-type polysilicon transistors and N-type oxide transistors.

[0102] In one exemplary embodiment, some of transistors T2, T5-T8 and the driving transistor DT may be formed of a P-type low-temperature polysilicon LTPS transistor with high mobility, and at least one of transistors T3 and T4 may be formed of an N-type oxide transistor with a smaller off-state leakage current than that of an LTPS transistor.

[0103] The sampling transistor (third transistor) T3 can be configured to be controlled by the first gate line 31 and can be configured to connect the second node N2 and the third node N3, wherein the gate electrode of the driving transistor DT is connected to the second node N2, and the second source / drain electrode of the driving transistor DT is connected to the third node N3. The sampling transistor T3 can be turned on by the gate on-state voltage of the first scan signal Scan1 supplied through the first gate line 31, and can connect the gate electrode and the second source / drain electrode of the driving transistor DT during the sampling period, thereby connecting the driving transistor DT in a diode structure.

[0104] The switching transistor (second transistor) T2 can be configured to be controlled by the second gate line 32 and can be configured to connect the first node N1 connected to the data line 53 and the first source / drain electrode of the driving transistor DT. The switching transistor T2 can be configured to be turned on by the gate on-state voltage of the second scan signal Scan2 supplied through the second gate line 32 and can be configured to supply the data voltage Vdata supplied through the data line 53 to the driving transistor DT during the data programming period.

[0105] The operation control transistor (fifth transistor) T5 can be configured to be controlled by the fifth gate line 35, and can be configured to connect the first power line 51 supplying the first power voltage VDD and the first node N1 of the driving transistor DT. The operation control transistor T5 can be configured to be turned on by the gate turn-on voltage of the light emission control signal EM supplied through the fifth gate line 35, and can be configured to supply the first power voltage VDD supplied through the first power line 51 to the first node N1 of the driving transistor DT during the light emission period.

[0106] The light-emitting control transistor (sixth transistor) T6 can be configured to be controlled by the fifth gate line 35, and can be configured to connect the third node N3 of the driving transistor DT and the fourth node N4 connected to the anode electrode of the light-emitting element OLED. The light-emitting control transistor T6 can be configured to be turned on by the gate on-state voltage of the light-emitting control signal EM supplied through the fifth gate line 35, and can be configured to connect the third node N3 of the driving transistor DT and the anode electrode of the light-emitting element OLED during the light-emitting period.

[0107] The first initialization transistor (fourth transistor) T4 can be configured to be controlled by the fourth gate line 34 and can be configured to connect the second node N2 of the driving transistor DT and the first initialization voltage line 41. The first initialization transistor T4 can be configured to be turned on by the gate on-state voltage of the fourth scan signal Scan4 supplied through the fourth gate line 34 and can be configured to supply the first initialization voltage Vinit supplied through the first initialization voltage line 41 to the second node N2 of the driving transistor DT during the initialization period.

[0108] The second initialization transistor (seventh transistor) T7 can be configured to be controlled by the third gate line 33, and can be configured to connect the second initialization voltage line 42 and the fourth node N4 connected to the anode of the light-emitting element OLED. The second initialization transistor T7 can be configured to be turned on by the gate on-state voltage of the third scan signal Scan3 supplied through the third gate line 33, and can be configured to supply the second initialization voltage VAR supplied through the second initialization voltage line 42 to the fourth node N4 connected to the anode electrode of the light-emitting element OLED during the initialization period.

[0109] The second initialization voltage VAR can be represented as the anode reset voltage.

[0110] The third initialization transistor (eighth transistor) T8 can be configured to be controlled by the third gate line 33 and can be configured to connect the third initialization voltage line 43 and the first node N1 of the driving transistor DT. The third initialization transistor T8 can be turned on by the gate on-state voltage of the third scan signal Scan3 supplied through the third gate line 33, and can be configured to supply the third initialization voltage Vobs supplied through the third initialization voltage line 43 to the first node N1 connected to the first source / drain electrode of the driving transistor DT during the initialization period. The third initialization voltage Vobs can be expressed as a conduction bias stress voltage that suppresses threshold voltage offset of the driving transistor DT.

[0111] The storage capacitor Cst can be configured to be connected between the first power line 51 and the second node N2 of the driving transistor DT. The storage capacitor Cst can be configured to charge the differential voltage between the first power voltage VDD supplied through the first power line 51 and the data voltage Vdata supplied from the data line 53 to the second node N2 via the switching transistor T2, the driving transistor DT, and the sampling transistor T3. During the sampling period when the driving transistor DT is connected in a diode configuration via the sampling transistor T3, the storage capacitor Cst can be configured to sample and store the threshold voltage Vth of the driving transistor DT, and can be configured to provide a data voltage with a compensated threshold voltage to the second node N2 of the driving transistor DT. The storage capacitor Cst can be configured to charge and maintain the differential voltage between the first power voltage VDD and the data voltage Vdata compensated by the threshold voltage Vth of the driving transistor DT as a target voltage, and can be configured to supply the maintained target voltage as the driving voltage of the driving transistor DT.

[0112] The driving transistor (first transistor) DT may have a gate electrode connected to the second node N2, a first source / drain electrode connected to the first node N1, and a second source / drain electrode connected to the third node N3. The driving transistor DT may be configured to control the amount of current flowing through the light-emitting control transistor T6 to the light-emitting element OLED according to the target voltage charged in the storage capacitor Cst, thereby controlling the light emission intensity of the light-emitting element EL.

[0113] According to an exemplary embodiment, any one of the driving transistors DT_SP1, DTb_SP1, DT_SP2, DTTa_SP2, DTb_SP2, and DTc_SP2 with the aforementioned dummy via can be applied to the driving transistor DT, such that the temperature-dependent threshold voltage variation ΔVth can be large.

[0114] An OLED (Optical Light Emitting Device) may include an anode connected to a third node of a driving transistor DT via a light-emitting control transistor T6, a cathode connected to a second power line 52 supplying a second power voltage VSS, and an organic light-emitting layer between the anode and the cathode. The OLED may be configured to emit light with a brightness proportional to the amount of driving current supplied from the driving transistor DT via the light-emitting control transistor T6.

[0115] Reference Figure 1 and Figure 7 The first to fourth gate lines (“scan lines”) 31, 32, 33, and 34 can be driven by a scan driver included in the gate driver 200, and the fifth gate line 35 can be driven by a light-emitting control driver included in the gate driver 200. A data voltage Vdata can be supplied from the data driver 300, and a first power voltage VDD, a second power voltage VSS, a first initialization voltage Vinit, a second initialization voltage VAR, and a third initialization voltage Vobs can be supplied from the power management circuit 700.

[0116] Figures 8A to 8D This is a diagram illustrating the layout structure of subpixels according to an exemplary embodiment and comparative example of this disclosure.

[0117] Specifically, Figures 8A to 8D The sub-pixels shown illustrate the layout of a first active layer, a first gate metal layer, an upper metal layer, a second active layer, a second gate metal layer, and a first source / drain metal layer arranged on the circuit element layer in the display panel, and omit the layout of the second source / drain metal layer of the circuit element layer and the light-emitting element layer arranged on the circuit element layer.

[0118] Reference Figures 8A to 8D The pixel circuitry of a sub-pixel according to a comparative example and an exemplary embodiment may include, for example: Figure 7 The driving transistor DT and multiple transistors T2 to T8, as well as the storage capacitor Cst, are shown.

[0119] The first initialization voltage line 41, configured to supply the first initialization voltage Vini; the fourth gate line 34, configured to supply the fourth scan signal Scan4; the second gate line 32, configured to supply the second scan signal Scan2; the first gate line 31, configured to supply the first scan signal Scan1; the first power line 51, configured to supply the first power voltage VDD; the fifth gate line 35, configured to supply the light emission control signal EM; the third scan line 33, configured to supply the third scan signal Scan3; the third initialization voltage line 43, configured to supply the third initialization voltage Vobs; and the second-first initialization voltage line 42r and the second-second initialization voltage line 42gb, configured to supply the second-first initialization voltage VARr and the second-second initialization voltage VARgb respectively, can be arranged to extend in the first direction X and be spaced apart from each other in the second direction Y. A redundant line WDR extending in the first direction X can be additionally arranged between the fifth gate line 35 and the third scan line 33 for dark spot repair. The first direction X is not limited to the horizontal as shown in the figure, and the second direction Y is not limited to the vertical as shown in the figure. They can be any direction, as long as the first direction X and the second direction Y intersect.

[0120] In one exemplary embodiment, the driving transistor DT, the switching transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 may include a first active layer ACT formed by LTPS and integrally connected.

[0121] In one exemplary embodiment, the sampling transistor T3 and the first initialization transistor T4 may include a second active layer OACT made of oxide semiconductor and integrally connected.

[0122] In one exemplary embodiment, the driving transistor DT and the plurality of transistors T2 to T8 of the pixel circuit may include an active layer made of LTPS, or may include an active layer made of oxide semiconductor.

[0123] The gate electrode GE1 of the driving transistor DT, the first capacitor electrode C1 of the storage capacitor Cst, the gate electrode GE5 of the operation control transistor T5, the gate electrode GE6 of the light emission control transistor T6, and the third scan line 33 including the gate electrode GE7 of the second initialization transistor T7 and the gate electrode GE8 of the third initialization transistor T8 can be disposed on the first active layer ACT as the first gate metal layer.

[0124] The second capacitor electrode C2 of the storage capacitor Cst, the light-shielding electrodes 112 and 114 of the sampling transistor T3 and the first initialization transistor T4 can be disposed on the first gate metal layer as an upper metal layer.

[0125] The lower line 103 of the first gate line 31 of the gate electrode GE3 of the sampling transistor T3 and the gate electrode GE4 of the first initialization transistor T4 can be disposed as the second gate metal layer on the second active layer OACT.

[0126] The first initialization voltage line 41, the fourth gate line 34, the second gate line 32, the upper line 104 of the first gate line 31, the first power line 51, the fifth gate line 35, the third scan line 33 supplying the third scan signal Scan3, the third initialization voltage line 43, the second-first initialization voltage line 42r and the second-second initialization voltage line 42gb, and the connecting electrodes 102, 105, 106 and 107 can be disposed on the second gate metal layer as the first source / drain metal layer.

[0127] The driving transistor DT and the storage capacitor Cst can be placed between the fourth gate line 34 and the fifth gate line 35. The driving transistor DT and the storage capacitor Cst can overlap in the third direction Z, and the first power line 51 can overlap with the driving transistor DT and the storage capacitor Cst in the third direction Z.

[0128] The driving transistor DT (first transistor) may include a first channel CH1, a first-first source / drain electrode SD11, and a first-second source / drain electrode SD12 disposed in the first active layer ACT, and a first gate electrode GE1 overlapping the first channel CH1 in the third direction Z. The first gate electrode GE1 can be connected to the connection electrode 105 through the second node N2 and the contact hole 64. The connection electrode 105 can be connected to the sampling transistor T3 (third transistor) and the first initialization transistor T4 (fourth transistor) through the contact hole 65. The first-first source / drain electrode SD11 can be connected to the fifth-first source / drain electrode SD51 of the operation control transistor T5 (fifth transistor) and the second-second source / drain electrode SD22 of the switching transistor T2 (second transistor) through the first node N1. The first-second source / drain electrode SD12 can be connected to the sampling transistor T3 and the light-emitting control transistor T6 (sixth transistor) through the third node N3.

[0129] The storage capacitor Cst may include a first capacitor electrode C1 integrally disposed with the first gate electrode GE1 of the driving transistor DT, and a second capacitor electrode C2 overlapping the first capacitor electrode C1 in the third direction Z. The second capacitor electrode C2 may be connected to the first power line 51 through a contact hole 70.

[0130] The switching transistor T2 (second transistor) may include a second channel CH2 disposed in the first active layer ACT, a second-first source / drain electrode SD21 and a second-second source / drain electrode SD22, and a second gate electrode GE2 overlapping the second channel CH2 in the third direction Z. The second gate electrode GE2 can be connected to the second gate line 32 overlapping in the third direction Z through a contact hole 62. The second-first source / drain electrode SD21 can be connected to the second source / drain metal layer disposed in the second source / drain metal layer through a contact hole 61 and a connecting electrode 102. Figure 7 The data line 53 is shown. The second-second source / drain electrode SD22 can be connected to the first-first source / drain electrode SD11 of the driving transistor DT through the first node N1.

[0131] The operation control transistor T5 (the fifth transistor) may include a fifth channel CH5, a fifth-first source / drain electrode SD51, and a fifth-second source / drain electrode SD52 disposed in the first active layer ACT, and a fifth gate electrode GE5 overlapping the fifth channel CH5 in the third direction Z. The fifth gate electrode GE5 can be connected to the fifth gate line 35 through contact hole 72. The fifth-first source / drain electrode SD51 can be connected to the first-first source / drain electrode SD11 of the driving transistor DT through the first node N1. The second-second source / drain electrode SD22 can be connected to the first power line 51 through contact hole 71.

[0132] The light-emitting control transistor T6 (sixth transistor) may include a sixth channel CH6, a sixth-first source / drain electrode SD61, and a sixth-second source / drain electrode SD62 disposed in the first active layer ACT, and a sixth gate electrode GE6 overlapping the sixth channel CH6 in the third direction Z. The sixth gate electrode GE6 can be connected to the fifth gate line 35 through contact hole 72. The sixth-first source / drain electrode SD61 can be connected to the first-second source / drain electrode SD12 of the driving transistor DT through the third node N3. The sixth-second source / drain electrode SD62 can be connected to the first-second source / drain electrode SD12 of the driving transistor DT through contact hole 73 and connection electrode 107. Figure 7 The anode electrode of the OLED light-emitting element shown.

[0133] The third initialization transistor T8 (eighth transistor) may include an eighth channel CH8, an eighth-first source / drain electrode SD81, and an eighth-second source / drain electrode SD82 disposed in the first active layer ACT, and an eighth gate electrode GE8 overlapping the eighth channel CH8 in the third direction Z. The eighth gate electrode GE8 may be integrally connected with the third gate line 32. The eighth-first source / drain electrode SD81 may be connected to the fifth-second source / drain electrode SD52 of the operation control transistor T5. The eighth-second source / drain electrode SD82 may be connected to the third initialization voltage line 43 through the contact hole 74.

[0134] The second initialization transistor T7 (seventh transistor) may include a seventh channel CH7, a seventh-first source / drain electrode SD71, and a seventh-second source / drain electrode SD72 disposed in the first active layer ACT, and a seventh gate electrode GE7 overlapping the seventh channel CH7 in the third direction Z. The seventh gate electrode GE7 may be integrally connected with the third gate line 32. The seventh-first source / drain electrode SD71 may be connected to the sixth-second source / drain electrode SD62 of the light-emitting control transistor T6. The seventh-second source / drain electrode SD72 may be connected to the second-second initialization voltage line 42gb through the contact hole 75.

[0135] The sampling transistor T3 may include a third channel CH3, a third-first source / drain electrode SD31, and a third-second source / drain electrode SD32 disposed in the second active layer OACT, and a third gate electrode GE3 overlapping the third channel CH3 in the third direction Z. The third gate electrode GE3 may be integrally connected to the lower line 103 of the first gate line 31, and may be connected to the upper line 104 of the first gate line 31 through contact hole 63. The third-first source / drain electrode SD31 may be connected to the third node N3 of the driving transistor DT through contact holes 68, 69 and connection electrode 106. The third-second source / drain electrode SD32 may be connected to the second node N2 of the driving transistor DT through contact holes 64, 65 and connection electrode 105. The first light-shielding electrode 112 overlapping the sampling transistor T3 in the third direction Z may be connected to the upper line 104 of the first gate line 31 through contact hole 163.

[0136] The first initialization transistor T4 (fourth transistor) may include a fourth channel CH4, a fourth-first source / drain electrode SD41, and a fourth-second source / drain electrode SD42 disposed in the second active layer OACT, and a fourth gate electrode GE4 overlapping the fourth channel CH4 in the third direction Z. The fourth gate electrode GE4 can be connected to the fourth gate line 34 through contact hole 66. The fourth-first source / drain electrode SD41 can be connected to the second node N2 of the driving transistor DT through contact holes 64, 65 and connection electrode 105. The fourth-second source / drain electrode SD42 can be connected to the first initialization voltage line 41 through contact hole 67. The third light-shielding electrode 114 overlapping the first initialization transistor T4 in the third direction Z can be connected to the fourth gate line 34 through contact hole 166.

[0137] Reference Figure 8A According to the comparative example, the driving transistor DT of the sub-pixel can have a structure without dummy holes.

[0138] Reference Figure 8BAccording to an exemplary embodiment, the driving transistor DT of a sub-pixel may include a dummy hole 120 and a dummy electrode 122 overlapping the gate electrode GE1 in the third direction Z.

[0139] Reference Figure 8C According to an exemplary embodiment, the driving transistor DT of a subpixel may include two dummy holes 124 and a dummy electrode 126 that overlaps with the gate electrode GE1 in the third direction Z.

[0140] Reference Figure 8D According to an exemplary embodiment, the driving transistor DT of a sub-pixel may include two dummy holes 124 and a dummy electrode 126 overlapping the gate electrode GE1 in the third direction Z, and may include a plurality of contact holes (dummy holes) 69a, 73a, and 77 additionally arranged in a region adjacent to the driving transistor DT. For example, the number of contact holes 69a of the connection electrode 106 connecting the sampling transistor T3 and the third node N3 of the driving transistor DT may be increased to two, and the number of contact holes 73a of the connection electrode 107 connecting the light-emitting control transistor T6 may be increased to two. Two dummy holes 77 may also be arranged in a protruding region protruding from the third initialization voltage line 43 along the second direction Y.

[0141] according to Figure 8A The comparative examples shown and Figures 8B to 8D The subthreshold swing factor S, threshold voltage Vth, and temperature-dependent threshold voltage variation ΔVth of the driving transistor DT in the subpixels of the various exemplary embodiments shown are presented in Table 1 below.

[0142]

[0143]

[0144]

[0145] Referring to Table 1 above, and Figure 8A Compared to the driving transistor DT without dummy holes shown, it can be seen that as the number of dummy holes 120, 124, 69a, 73a, and 77 increases, the S-factor value and the temperature-dependent threshold voltage change ΔVth increase, while the threshold voltage Vth decreases.

[0146] Figure 9 This is a cross-sectional view illustrating the structure of a sub-pixel according to an exemplary embodiment of the present disclosure.

[0147] Specifically, Figure 9 It shows along Figure 8C The cross-sectional structure of the sub-pixels of the I-I' and II-II' cutting lines is shown.

[0148] Reference Figure 8C and Figure 9 According to an exemplary embodiment, a sub-pixel may include a circuit element layer comprising pixel circuitry disposed on a substrate SUB, a light-emitting element layer comprising light-emitting elements disposed on the circuit element layer, and an encapsulation layer ENCAP disposed on the light-emitting element layer. The circuit element layer may include a driving transistor DT, a switching transistor T2, a sampling transistor T3, a first initialization transistor T4, an operation control transistor T5, a light-emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, and a storage capacitor Cst.

[0149] In one exemplary embodiment, a touch sensor array including multiple touch electrodes may also be arranged on the encapsulation layer ENCAP. A color filter array including a color filter and a black matrix may also be arranged on the touch sensor array, or a lens array may also be arranged.

[0150] Figure 9 A representative cross-sectional structure of the light-emitting control transistor T6, the driving transistor DT, the storage capacitor Cst, and the sampling transistor T3 is shown.

[0151] In one exemplary embodiment, the light-emitting control transistor T6 and the driving transistor DT may include a first active layer ACT made of LTPS.

[0152] In one exemplary embodiment, the sampling transistor T3 may include a second active layer OACT made of oxide semiconductor. For example, the second active layer OACT may be made of oxide semiconductor, including but not limited to at least one of the following: IZO (indium zinc oxide), IGO (indium gallium oxide), ITO (indium tin oxide), ZTO (zinc tin oxide), IGZO (indium gallium zinc oxide), IGZTO (indium gallium zinc tin oxide), GZTO (gallium zinc tin oxide), GZO (gallium zinc oxide), and ITZO (zinc tin zinc oxide). In one exemplary embodiment, the sampling transistor T3 may include an active layer made of LTPS.

[0153] The substrate SUB may include a plastic substrate or a glass substrate. The plastic substrate may be formed of a flexible material. For example, the substrate SUB may include at least one organic insulating material selected from acrylic resin, epoxy resin, silicone resin, polyimide resin, polyamide resin, polymethyl methacrylate (PMMA), polycarbonate (PC), polyvinyl alcohol (PVA), acrylonitrile-butadiene-styrene (ABS), polyethylene terephthalate (PET), silicone resin, or polyurethane (PU), but this disclosure is not limited thereto.

[0154] A lower buffer layer (MBF) may be disposed on the substrate SUB. The lower buffer layer (MBF) can prevent or reduce the inflow of impurities such as hydrogen through the substrate SUB into the first active layer ACT. The lower buffer layer (MBF) may include an inorganic insulating material. For example, the lower buffer layer (MBF) may include an oxide-based insulating material, such as silicon oxide (SiOx), silicon nitride (SiOxNy), or aluminum oxide (Al2O3). In an exemplary embodiment, a barrier layer capable of preventing particle inflow may also be disposed between the substrate SUB and the lower buffer layer (MBF). The barrier layer may consist of multiple barrier layers, in which at least one organic insulating layer, such as acrylic resin, epoxy resin, polyimide, polyethylene, and silicon carbide (SiOC), and at least one inorganic insulating layer are alternately laminated.

[0155] The driving transistor DT may include a first channel CH1, a first-first source / drain electrode SD11 and a first-second source / drain electrode SD12 disposed in a first active layer ACT, a first gate electrode GE1 overlapping the first channel CH1 in the third direction Z, and a first gate insulating layer GI1 between them.

[0156] The light-emitting control transistor T6 may include a sixth channel CH6, a sixth-first source / drain electrode SD61 and a sixth-second source / drain electrode SD62 disposed in the first active layer ACT, a sixth gate electrode GE6 overlapping the sixth channel CH6 in the third direction Z, and a first gate insulating layer GI1 between them.

[0157] The first-second source / drain electrode SD12 of the driving transistor DT and the sixth-first source / drain electrode SD61 of the light-emitting control transistor T6 can be connected through the first active layer ACT. The first gate electrode GE1 of the driving transistor DT can be integrally formed with the first capacitor electrode C1 of the storage capacitor Cst.

[0158] The driving transistor DT may also include a dummy via 124 penetrating multiple insulating layers, including a first upper buffer layer ABF1, a second upper buffer layer ABF2, a second gate insulating layer GI2, and an interlayer insulating layer ILD stacked on the first gate electrode GE1, and a dummy electrode 126 disposed on the interlayer insulating layer ILD and connected to the first gate electrode GE1 through the dummy via 124.

[0159] The gate insulating layers GI1 and GI2, the upper buffer layers ABF1 and ABF2, and the interlayer insulating layer ILD may include inorganic insulating materials, such as silicon oxide SiO2, silicon nitride SiNx, silicon nitride SiOxNy, etc.

[0160] The storage capacitor Cst may include a first capacitor electrode C1 connected to a first gate electrode GE1 of the driving transistor DT, and a second capacitor electrode C2 overlapping a first upper buffer layer ABF1 in the third direction Z, wherein the first upper buffer layer ABF1 is located between the first capacitor electrode C1 and the second capacitor electrode C2. A second upper buffer layer ABF2 may be disposed on the second capacitor electrode C2.

[0161] The sampling transistor T3 disposed on the second upper buffer layer ABF2 may include a third channel CH3, a third-first source / drain electrode SD31, and a third-second source / drain electrode SD32 of the second active layer OACT disposed in the second upper buffer layer ABF2, a third gate electrode GE3 overlapping the third channel CH3 in the third direction Z, and a second gate insulating layer GI2 between them. The sampling transistor T3 may also include a light-shielding electrode 112 disposed between the first upper buffer layer ABF1 and the second upper buffer layer ABF2, and overlapping the third channel CH3 of the second active layer OACT in the third direction Z.

[0162] An interlayer insulating layer (ILD) can be disposed on the sampling transistor T3. The third-first source / drain electrode SD31 of the sampling transistor T3 can be connected to the connection electrode 106 disposed on the ILD via contact hole 68. The third-second source / drain electrode SD32 of the sampling transistor T3 can be connected to the connection electrode 105 disposed on the ILD via contact hole 65, and the connection electrode 105 can be connected to the first capacitor electrode C1 via contact hole 64. The gate electrode GE3 of the sampling transistor T3 can overlap with the upper line 104 of the first gate line 31 in the third direction Z.

[0163] The first gate line 31 may include a lower line 103 on the second gate insulating layer GI2 and an upper line 104 disposed on the interlayer insulating layer ILD and overlapping the lower line 103 in the third direction Z.

[0164] The sixth-second source / drain electrode SD62 of the light-emitting control transistor T6 can be connected to the connection electrode 107 disposed on the interlayer insulating layer ILD through the contact hole 73.

[0165] The connection electrode 107 of the light-emitting control transistor T6 can be connected to the connection electrode 92-3 disposed on the first planarization layer PLN1 through the contact hole 83-2, and to the anode electrode AE3 disposed on the second planarization layer PLN2 through the contact hole 84-3.

[0166] The light-emitting element layer, including the light-emitting element, the dam layer BK, and the spacer SP, can be arranged on the second planarization layer PLN2.

[0167] The light-emitting element may include an anode electrode AE3, a light-emitting stack EML3, and a cathode electrode (second electrode) CE disposed on the second planarization layer PLN2. The anode electrode AE3 can be disposed independently for each sub-pixel. The anode electrode AE3 can be formed from a multi-conductive layer structure with high reflectivity. For example, the anode electrode AE3 can be formed from a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), a stacked structure of silver (Ag) and molybdenum-titanium alloy (Ag / MoTi), or a stacked structure of APC and ITO (ITO / APC / ITO), but is not limited thereto. APC is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0168] The anode electrode AE3 may have an opening exposed on the second planarization layer PLN2, and a dam layer BK may be disposed covering the end of the anode electrode AE3. The opening of the dam layer BK may be defined as the light-emitting region EA3, and the area where the dam layer BK is disposed may be defined as the non-light-emitting region. The dam layer BK surrounding the light-emitting region may be formed as a single-layer, double-layer, or multi-layer structure. A spacer SP having an opening wider than the opening of the dam layer BK may also be disposed on the dam layer BK. When the light-emitting stack EML3 is formed, the spacer SP may support the fine metal mask FMM, which serves as a deposition mask. The dam layer BK and the spacer SP may be formed of an organic insulating material, such as acrylic resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, benzocyclobutene, polystyrene resin, and polyphenylene sulfide resin. The dam layer BK may contain a light-blocking material to block light leakage between adjacent pixels and reduce or prevent external light reflection.

[0169] The light-emitting stack EML3 can be formed by stacking a hole control layer, a light-emitting layer, and an electron control layer in this order or the reverse order. The hole control layer may include at least a hole transport layer from a hole injection layer and a hole transport layer, and the electron control layer may include at least an electron transport layer from an electron injection layer and an electron transport layer.

[0170] The cathode electrode CE can be a common electrode disposed on the light-emitting stack EML3 and connected along the surfaces of the embankment layer BK and the spacer SP. The cathode electrode CE can be formed of a semi-transparent conductive material or a conductive material with high light transmittance. For example, the cathode electrode CE can be formed of a transparent conductive material such as ITO, IZO, or ITZO. The cathode electrode CE can also be formed of a semi-transparent metallic material such as magnesium (Mg), silver (Ag), or alloys thereof. A capping layer can also be disposed on the cathode electrode CE to improve the optical resonance and luminous efficiency of the light-emitting element.

[0171] An encapsulation layer ENCAP is provided on the light-emitting element layer to seal the light-emitting element layer, thereby preventing or reducing the penetration of impurities such as moisture or oxygen into the light-emitting element and covering particles to prevent or reduce flow. The encapsulation layer ENCAP may have a laminated structure of a first inorganic encapsulation layer PAS1, a second inorganic encapsulation layer PAS2, and an organic encapsulation layer PCL disposed between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The inorganic encapsulation layers PAS1 and PAS2 can prevent or reduce the penetration of impurities such as moisture or oxygen from the outside. The organic encapsulation layer PCL can cover particles and is used to buffer the stress between the layers when the display panel is bent.

[0172] Figure 10 This is a graph comparing the temperature and brightness sensitivity of a display device based on comparative examples and an exemplary embodiment of this disclosure. Figure 11 This is a graph comparing the temperature and color sensitivity of a display device based on comparative examples and exemplary embodiments.

[0173] exist Figure 10 In the diagram, the vertical axis represents the temperature-luminosity sensitivity (TLS). Figure 11 In the diagram, the vertical axis represents the offset Δu'v' of the white coordinate corresponding to the temperature color sensitivity (TCS).

[0174] Reference Figure 10 and Figure 11 The display device according to the comparative example may include a driving transistor DT without a dummy hole for the R / G / B sub-pixels, such as Figure 8A As shown in the comparative example. In the comparative example, the temperature-dependent threshold voltage variation ΔVth of the driving transistor DT for each R / G / B sub-pixel may be relatively low, for example, about 7.7mV / ℃. Therefore, in the display device according to the comparative example, it can be seen that the temperature luminance sensitivity TLS 1.19, 1.34 and 4.50 for each R / G / B sub-pixel and the temperature luminance sensitivity TLS 1.62 for white light W are relatively high. In particular, the temperature luminance sensitivity TLS of the B sub-pixel has a relatively high value of 4.50, and the white coordinate offset Δu'v' = 0.044 is also relatively high.

[0175] The display device according to the first exemplary embodiment may include a driving transistor DT having a dummy hole 120 for each sub-pixel in the R / G / B sub-pixels, as in Figure 8BAs shown in the exemplary embodiment. In the first exemplary embodiment, the temperature-dependent threshold voltage change ΔVth of the driving transistor DT of each sub-pixel in the R / G / B sub-pixels can be increased to about 10.6 mV / ℃, which is higher than the ΔVth of 7.7 mV / ℃ in the comparative example. Therefore, it can be seen that, compared with the comparative example, the temperature luminance sensitivity TLS 0.92, 1.10, and 2.20 of each sub-pixel in the R / G / B sub-pixels and the temperature luminance sensitivity TLS 1.22 of white light W are reduced in the display device according to the first exemplary embodiment. Furthermore, it can be seen that, in the display device according to the first exemplary embodiment, the difference between the temperature luminance sensitivity TLS 0.92 and 1.10 of the R / G sub-pixels and the temperature luminance sensitivity TLS 2.20 of the B sub-pixels is reduced, and the white coordinate offset Δu'v' = 0.018 is also reduced compared with Δu'v' = 0.044 in the comparative example.

[0176] In the display device according to the second exemplary embodiment, the R / G sub-pixel may include a driving transistor DT having a dummy hole 120, such as Figure 8C As shown in the exemplary embodiment, the B sub-pixel may include a driving transistor DT having two dummy holes 124, such as Figure 8C As shown in the exemplary embodiment. The temperature-dependent threshold voltage change ΔVth of the driving transistor DT of the B sub-pixel can be approximately 11.5 mV / ℃, which may be increased compared to the comparative example's ΔVth of 7.7 mV / ℃ and the temperature-dependent threshold voltage change 10.6 mV / ℃ of the driving transistor of the R / G sub-pixel. Therefore, it can be seen that, compared to the comparative example, the temperature luminance sensitivity TLS1.44, 1.59, 2.04 of each sub-pixel in the R / G / B sub-pixels and the temperature luminance sensitivity TLS1.71 of the white light W are reduced in the display device according to the second exemplary embodiment. Furthermore, it can be seen that, in the display device according to the second exemplary embodiment, compared to the first exemplary embodiment, the difference between the temperature luminance sensitivity TLS1.44, 1.59 of the R / G sub-pixels and the temperature luminance sensitivity TLS2.04 of the B sub-pixel is reduced, and the white coordinate offset Δu'v' = 0.009 is also reduced compared to Δu'v' = 0.044 in the comparative example and Δu'v' = 0.018 in the first exemplary embodiment.

[0177] The display device according to the third exemplary embodiment may include, for example, R / G sub-pixels. Figure 8D The exemplary embodiment shown has a driving transistor DT with a dummy hole 120, and the B sub-pixel may include, for example, Figure 8DThe exemplary embodiment shown has a driving transistor DT with two dummy holes 124, and may also include six dummy holes 69a, 73a, 77 in the region of the driving transistor DT. The temperature-dependent threshold voltage variation ΔVth of the driving transistor DT of the B sub-pixel can be approximately 11.8 mV / ℃, which may be increased compared to the comparative example's ΔVth 7.7 mV / ℃ and the temperature-dependent threshold voltage variation 10.6 mV / ℃ of the driving transistor of the R / G sub-pixel. Therefore, it can be seen that in the display device according to the third exemplary embodiment, compared to the comparative example, the temperature luminance sensitivity TLS1.18, 1.22, 1.87 of each sub-pixel in the R / G / B sub-pixels and the temperature luminance sensitivity TLS1.36 of white light W are reduced. Furthermore, it can be seen that in the display device according to the third exemplary embodiment, compared with the first exemplary embodiment, the difference between the temperature and brightness sensitivity TLS1.18 and 1.22 of the R / G sub-pixels and the temperature and brightness sensitivity TLS1.87 of the B sub-pixels is reduced, and the white coordinate offset Δu'v' = 0.010 is also reduced compared with Δu'v' = 0.044 in the comparative example and Δu'v' = 0.018 in the first exemplary embodiment.

[0178] Figures 12A to 12D This is a graph comparing the white coordinate changes of a display device according to a comparative example and an exemplary embodiment of the present disclosure with respect to temperature changes.

[0179] exist Figures 12A to 12D In the diagram, the horizontal axis represents the u' chromaticity, the vertical axis represents the v' chromaticity, and the white coordinates according to temperature are shown in the u'v' chromaticity coordinate system.

[0180] Reference Figure 12A According to the comparative example, the display device can include a driving transistor DT without a dummy hole for the R / G / B sub-pixels, such as... Figure 8A As shown in the comparative example, the temperature-dependent threshold voltage variation ΔVth of the driving transistor DT for each R / G / B sub-pixel can be relatively low, for example, about 7.7mV / ℃. Therefore, in the display device according to the comparative example, the temperature luminance sensitivity TLS and temperature chromaticity sensitivity TCS of the R / G / B sub-pixels are relatively low, resulting in a relatively large range of white coordinate variation depending on temperature changes. Thus, it can be seen that the range of white coordinate variation is also large at room temperature (20℃) and high temperature (40℃), and also large at room temperature (20℃) and low temperature (10℃).

[0181] Reference Figure 12B The display device according to the first exemplary embodiment may include a driving transistor DT having a dummy hole 120 for each of the R / G / B sub-pixels, such as Figure 8B As shown in the exemplary embodiment, and compared to the comparative example's ΔVth of 7.7 mV / ℃, the temperature-dependent threshold voltage change ΔVth of the driving transistor DT in each sub-pixel of the R / G / B sub-pixel can be increased to approximately 10.6 mV / ℃. Therefore, it can be seen that in the display device according to the first exemplary embodiment, the temperature luminance sensitivity TLS and temperature color sensitivity TCS of the R / G / B sub-pixels are reduced compared to the comparative example in terms of the range of white coordinate changes depending on temperature. Consequently, compared to the comparative example, the range of white coordinate changes at room temperature (20℃) and high temperature (40℃), as well as the range of white coordinate changes at room temperature (20℃) and low temperature (10℃), are both reduced.

[0182] Reference Figure 12C In the display device according to the second exemplary embodiment, the R / G sub-pixel may include, for example: Figure 8B The exemplary embodiment shown has a driving transistor DT with a dummy hole 120, and the B sub-pixel may include, for example, Figure 8C The exemplary embodiment shown has a driving transistor DT with two dummy holes 124. The temperature-dependent threshold voltage variation ΔVth of the driving transistor DT for the B sub-pixel can be approximately 11.5 mV / ℃, which is increased compared to the comparative example's ΔVth of 7.7 mV / ℃ and the temperature-dependent threshold voltage variation ΔVth of the driving transistor for the R / G sub-pixel of 10.6 mV / ℃. Therefore, in the display device according to the second exemplary embodiment, compared to the comparative example and the first exemplary embodiment, the temperature luminance sensitivity TLS and temperature chromaticity sensitivity TCS of the R / G / B sub-pixels are reduced in terms of the white coordinate fluctuation range caused by temperature changes, resulting in a reduction in the white coordinate fluctuation range at room temperature (20℃) and high temperature (40℃) as well as the white coordinate fluctuation range at room temperature (20℃) and low temperature (10℃) compared to the comparative example and the first exemplary embodiment.

[0183] Reference Figure 12D In the display device according to the third exemplary embodiment, the R / G sub-pixel may include, for example: Figure 8B The exemplary embodiment shown has a driving transistor DT with a dummy hole 120, and the B sub-pixel may include, for example, Figure 8DThe exemplary embodiment shown has a driving transistor DT with two dummy holes 124, and may also include six dummy holes 69a, 73a, and 77 located in the peripheral region of the driving transistor DT. The temperature-dependent threshold voltage variation ΔVth of the driving transistor DT of the B sub-pixel can be increased to about 11.8 mV / ℃, which is higher than the ΔVth of 7.7 mV / ℃ in the comparative example and the temperature-dependent threshold voltage variation ΔVth of 10.6 mV / ℃ in the driving transistor of the R / G sub-pixel. Therefore, in the display device according to the third exemplary embodiment, compared with the comparative example and the first exemplary embodiment, the temperature luminance sensitivity TLS and temperature color sensitivity TCS of the R / G / B sub-pixels are reduced. Thus, it can be seen that compared with the comparative example and the first exemplary embodiment, the variation range of the white coordinate at room temperature 20℃ and high temperature 40℃, as well as the variation range of the white coordinate at room temperature 20℃ and low temperature 10℃, are both reduced.

[0184] As described above, a display device according to an exemplary embodiment can control the temperature-dependent threshold voltage variation of the driving transistor by applying a dummy hole to the insulating layer of the driving transistor, thereby reducing or minimizing the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the sub-pixel.

[0185] A display device according to an exemplary embodiment can minimize the difference in brightness variation between sub-pixels due to temperature variations by differentially applying the number or area ratio of dummy holes in the insulating layer of sub-pixels, based on the aperture ratio (area) of the light-emitting element or the temperature-dependent brightness variation characteristics of the light-emitting element. As a result, the change in white coordinates due to temperature variations can be reduced or minimized, thereby improving optical quality.

[0186] A display device according to an exemplary embodiment can control temperature-dependent threshold voltage variations of the driving transistors to reduce or minimize the temperature-dependent luminance and color-dependent sensitivity of subpixels, thereby improving optical quality. As a result, it can provide improved image quality with lower power consumption.

[0187] As described above, a display device according to embodiments of the present disclosure may include a first sub-pixel comprising a first light-emitting element configured to emit light of a first color and a first driving transistor configured to drive the first light-emitting element, a second sub-pixel comprising a second light-emitting element configured to emit light of a second color and a second driving transistor configured to drive the second light-emitting element, at least one first dummy hole disposed in the first driving transistor, and at least one second dummy hole disposed in the second driving transistor, wherein the total aperture area of ​​the at least one first dummy hole of the first driving transistor may be different from the total aperture area of ​​the at least one second dummy hole of the second driving transistor.

[0188] Furthermore, the total aperture area of ​​the at least one first dummy hole of the first driving transistor may be greater than the total aperture area of ​​the at least one second dummy hole of the second driving transistor. Additionally, the number of the at least one first dummy hole of the first driving transistor may be greater than the number of the at least one second dummy hole of the second driving transistor. Moreover, the first sub-pixel may further include at least one peripheral dummy hole disposed in an insulating layer surrounding the first driving transistor.

[0189] The display device according to some embodiments of the present disclosure may further include a third light-emitting element configured to emit light of a third color, a third sub-pixel configured to drive the third light-emitting element, and at least one third dummy hole disposed in the third driving transistor, wherein the total aperture area of ​​the at least one third dummy hole of the third driving transistor may be the same as or different from the total aperture area of ​​the at least one first dummy hole of the first driving transistor and the total aperture area of ​​the at least one second dummy hole of the second driving transistor.

[0190] Furthermore, the first driving transistor may further include a first dummy electrode connected to the gate electrode of the first driving transistor through the at least one first dummy via. The second driving transistor may further include a second dummy electrode connected to the gate electrode of the second driving transistor through the at least one second dummy via. The third driving transistor may further include a third dummy electrode connected to the gate electrode of the third driving transistor through the at least one third dummy via.

[0191] In a display device according to some embodiments, the at least one first dummy hole of the first driving transistor, the at least one second dummy hole of the second driving transistor, and the at least one third dummy hole of the third driving transistor can be embedded by an upper insulating layer disposed above the first driving transistor, the second driving transistor, and the third driving transistor.

[0192] Furthermore, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may also include at least one contact hole. The aperture area of ​​each of the at least one first dummy hole of the first sub-pixel, the at least one second dummy hole of the second sub-pixel, and the at least one third dummy hole of the third sub-pixel may be the same as the aperture area of ​​each of the at least one contact hole of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0193] In a display device according to some embodiments, the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a red sub-pixel. The total aperture area of ​​the at least one first dummy hole of the first driving transistor in the blue sub-pixel may be greater than the total aperture area of ​​the at least one second dummy hole of the second driving transistor in the green sub-pixel, and greater than the total aperture area of ​​the at least one third dummy hole of the third driving transistor in the red sub-pixel. The total aperture area of ​​the at least one second dummy hole of the second driving transistor may be the same as the total aperture area of ​​the at least one third dummy hole of the third driving transistor.

[0194] In a display device according to some embodiments, the first sub-pixel can be a blue sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a red sub-pixel. The number of at least one first dummy holes of the first driving transistor in the blue sub-pixel can be greater than the number of at least one second dummy holes of the second driving transistor in the green sub-pixel, and greater than the number of at least one third dummy holes of the third driving transistor in the red sub-pixel. The number of at least one second dummy holes of the second driving transistor can be the same as the number of at least one third dummy holes of the third driving transistor.

[0195] A display device according to some embodiments of the present disclosure may include a first sub-pixel comprising a first light-emitting element configured to emit light of a first color, a first driving transistor configured to drive the first light-emitting element, and at least one first dummy aperture overlapping with the first gate electrode of the first driving transistor; a second sub-pixel comprising a second light-emitting element configured to emit light of a second color, a second driving transistor configured to drive the second light-emitting element, and at least one second dummy aperture overlapping with the second gate electrode of the second driving transistor; and a third sub-pixel comprising a third light-emitting element configured to emit light of a third color, a third driving transistor configured to drive the third light-emitting element, and at least one third dummy aperture overlapping with the third gate electrode of the third driving transistor.

[0196] Furthermore, the total aperture area of ​​the at least one first dummy hole may have a different aperture ratio than the total aperture area of ​​each of the at least one second dummy hole and the at least one third dummy hole, and the total aperture area of ​​the at least one second dummy hole may be the same as or different from the total aperture area of ​​the at least one third dummy hole.

[0197] Furthermore, the number of at least one first dummy vias of the first driving transistor may be greater than the number of at least one second dummy vias of the second driving transistor, and also greater than the number of at least one third dummy vias of the third driving transistor. The total aperture area of ​​the at least one first dummy vias of the first driving transistor may be greater than the total aperture area of ​​the at least one second dummy vias of the second driving transistor, and also greater than the total aperture area of ​​the at least one third dummy vias of the third driving transistor. The total aperture area or number of the at least one second dummy vias of the second driving transistor may be the same as or different from the total aperture area or number of the at least one third dummy vias of the third driving transistor.

[0198] Furthermore, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may also include at least one contact hole disposed in a plurality of insulating layers, and the aperture area of ​​each of the at least one first dummy hole of the first sub-pixel, the at least one second dummy hole of the second sub-pixel, and the at least one third dummy hole of the third sub-pixel may be the same as the aperture area of ​​each of the at least one contact hole.

[0199] The display device according to embodiments of the present disclosure may further include a first dummy electrode connected to the first gate electrode via at least one first dummy hole of the first driving transistor, a second dummy electrode connected to the second gate electrode via at least one second dummy hole of the second driving transistor, and a third dummy electrode connected to the third gate electrode via at least one third dummy hole of the third driving transistor, wherein the area of ​​the first dummy electrode may be different from the area of ​​the second dummy electrode and the area of ​​the third dummy electrode, and wherein the area of ​​the second dummy electrode may be the same as or different from the area of ​​the third dummy electrode.

[0200] Furthermore, the at least one first dummy hole, the at least one second dummy hole, and the at least one third dummy hole can be embedded through an upper insulating layer above the first gate electrode of the first driving transistor, the second gate electrode of the second driving transistor, and the third gate electrode of the third driving transistor. Additionally, the first sub-pixel may also include a plurality of peripheral dummy holes disposed in a plurality of insulating layers surrounding the first driving transistor.

[0201] Furthermore, the aperture area of ​​each of the first, second, and third light-emitting elements may be different from each other. In a display device according to some embodiments, the temperature-dependent brightness variation characteristics of each of the first, second, and third light-emitting elements may be different from each other.

[0202] Furthermore, the temperature-dependent threshold voltage change of the first driving transistor may be different from the temperature-dependent threshold voltage change of the second driving transistor and the temperature-dependent threshold voltage change of the third driving transistor, and the temperature-dependent threshold voltage change of the second driving transistor may be the same as or different from the temperature-dependent threshold voltage change of the third driving transistor.

[0203] Furthermore, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may also include a plurality of transistors connected to each of the first driving transistor, the second driving transistor, and the third driving transistor, and the first driving transistor, the second driving transistor, the third driving transistor, and the plurality of transistors may include an active layer of at least one of a polycrystalline silicon semiconductor layer and an oxide semiconductor layer.

[0204] In each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the plurality of transistors and at least one of the first driving transistor, the second driving transistor, and the third driving transistor may be a polysilicon transistor comprising a polysilicon semiconductor layer. At least another transistor among the plurality of transistors may be an oxide transistor comprising an oxide semiconductor layer. The oxide transistor may be disposed on at least one lower insulating layer disposed on the polysilicon transistor. Each of the at least one first dummy via, the at least one second dummy via, and the at least one third dummy via may be formed through at least one insulating layer of the polysilicon transistor, the at least one lower insulating layer on the polysilicon transistor, and at least one upper insulating layer on the oxide transistor.

[0205] Furthermore, the first driving transistor may further include a first dummy electrode connected to the first gate electrode through the at least one first dummy via, the second driving transistor may further include a second dummy electrode connected to the second gate electrode through the at least one second dummy via, and the third driving transistor may further include a third dummy electrode connected to the third gate electrode through the at least one third dummy via, wherein the first dummy electrode, the second dummy electrode, and the third dummy electrode are disposed on at least one upper insulating layer on the oxide transistor.

[0206] A display device according to an embodiment of the present disclosure may include a first sub-pixel comprising a first light-emitting element configured to emit light of a first color, a first driving transistor configured to drive the first light-emitting element, and at least one first dummy aperture overlapping the first driving transistor, and a second sub-pixel comprising a second light-emitting element configured to emit light of a second color, a second driving transistor configured to drive the second light-emitting element, and at least one second dummy aperture overlapping the second driving transistor, wherein the first driving transistor and the second driving transistor have different total aperture areas of dummy apertures depending on the brightness variation characteristics of the first light-emitting element and the second light-emitting element with temperature.

[0207] Furthermore, the first driving transistor and the second driving transistor may have different total dummy aperture areas depending on the aperture areas of the first light-emitting element and the second light-emitting element.

[0208] The display device according to one or more exemplary embodiments of this disclosure can be applied to a variety of electronic devices. For example, the display device according to one or more exemplary embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, flexible devices, electronic diaries, e-books, electronic boards (e.g., tablets), portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigators, vehicle navigators, vehicle display devices, televisions, set-top boxes, wallpaper display devices, signage devices, gaming devices, laptop computers, monitors, camera devices, camcorders, and home appliances, but is not limited thereto.

[0209] The features, structures, and effects described above in this disclosure are included in at least one exemplary embodiment of this disclosure, but are not limited to only one exemplary embodiment. Furthermore, the features, structures, and effects described in at least one exemplary embodiment of this disclosure can be implemented by those skilled in the art through combinations or modifications of other exemplary embodiments. Therefore, anything associated with combinations and modifications should be interpreted as being within the scope of this disclosure.

[0210] It will be apparent to those skilled in the art that various substitutions, modifications, and variations can be made within the scope of this disclosure without departing from its spirit and scope. Therefore, the scope of this disclosure includes those expressed in the appended claims, and all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as including within the scope of this disclosure.

[0211] The various exemplary embodiments described above can be combined to provide other exemplary embodiments. Aspects of the exemplary embodiments can be modified as necessary to employ the concepts of various exemplary embodiments to provide other exemplary embodiments.

[0212] Based on the detailed description above, these and other changes can be made to the exemplary embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific exemplary embodiments disclosed in the specification and claims, but should be understood to include all possible exemplary embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A display device, comprising: The first sub-pixel includes a first light-emitting element configured to emit light of a first color and a first driving transistor configured to drive the first light-emitting element; The second sub-pixel includes a second light-emitting element configured to emit light of a second color and a second driving transistor configured to drive the second light-emitting element; At least one first dummy hole is disposed in the first driving transistor; as well as At least one second dummy hole is disposed in the second driving transistor. Wherein, the total aperture area of ​​the at least one first dummy hole of the first driving transistor is different from the total aperture area of ​​the at least one second dummy hole of the second driving transistor.

2. The display device according to claim 1, in, The total aperture area of ​​the at least one first dummy hole of the first driving transistor is greater than the total aperture area of ​​the at least one second dummy hole of the second driving transistor.

3. The display device according to claim 1, in, The number of the at least one first dummy via of the first driving transistor is greater than the number of the at least one second dummy via of the second driving transistor.

4. The display device according to claim 1, in, The first sub-pixel also includes at least one peripheral dummy hole disposed in an insulating layer surrounding the first driving transistor.

5. The display device according to claim 1, further comprising: The third sub-pixel includes a third light-emitting element configured to emit light of a third color and a third driving transistor configured to drive the third light-emitting element; as well as At least one third dummy hole is disposed in the third driving transistor. Wherein, the total aperture area of ​​the at least one third dummy hole of the third driving transistor is the same as, or different from, any one of the total aperture areas of the at least one first dummy hole of the first driving transistor and the at least one second dummy hole of the second driving transistor.

6. The display device according to claim 5, in, The first driving transistor further includes a first dummy electrode connected to the gate electrode of the first driving transistor through the at least one first dummy via. The second driving transistor further includes a second dummy electrode connected to the gate electrode of the second driving transistor through the at least one second dummy via, and The third driving transistor further includes a third dummy electrode that is connected to the gate electrode of the third driving transistor through the at least one third dummy hole.

7. The display device according to claim 5, in, Each of the first, second, and third sub-pixels further includes at least one contact hole, and Wherein, the aperture area of ​​each of the at least one first dummy hole of the first sub-pixel, the at least one second dummy hole of the second sub-pixel, and the at least one third dummy hole of the third sub-pixel is the same as the aperture area of ​​each of the at least one contact hole of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

8. The display device according to claim 5, in, The first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel. Wherein, the total aperture area of ​​the at least one first dummy hole of the first driving transistor in the blue sub-pixel is greater than the total aperture area of ​​the at least one second dummy hole of the second driving transistor in the green sub-pixel, and greater than the total aperture area of ​​the at least one third dummy hole of the third driving transistor in the red sub-pixel, and Wherein, the total aperture area of ​​the at least one second dummy hole of the second driving transistor is the same as the total aperture area of ​​the at least one third dummy hole of the third driving transistor.

9. The display device according to claim 5, in, The first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel. Wherein, the number of at least one first dummy holes of the first driving transistor in the blue sub-pixel is greater than the number of at least one second dummy holes of the second driving transistor in the green sub-pixel, and greater than the number of at least one third dummy holes of the third driving transistor in the red sub-pixel, and The number of at least one second dummy hole in the second driving transistor is the same as the number of at least one third dummy hole in the third driving transistor.

10. A display device, comprising: The first sub-pixel includes a first light-emitting element configured to emit light of a first color, a first driving transistor configured to drive the first light-emitting element, and at least one first dummy hole overlapping with the first gate electrode of the first driving transistor. The second sub-pixel includes a second light-emitting element configured to emit light of a second color, a second driving transistor configured to drive the second light-emitting element, and at least one second dummy hole overlapping with the second gate electrode of the second driving transistor. as well as The third sub-pixel includes a third light-emitting element configured to emit light of a third color, a third driving transistor configured to drive the third light-emitting element, and at least one third dummy hole overlapping with the third gate electrode of the third driving transistor.

11. The display device according to claim 10, in, The total aperture area of ​​the at least one first dummy hole is different from each of the total aperture areas of the at least one second dummy hole and the at least one third dummy hole, and The total aperture area of ​​the at least one second dummy hole is the same as or different from the total aperture area of ​​the at least one third dummy hole.

12. The display device according to claim 11, in, The number of at least one first dummy holes of the first driving transistor is greater than the number of at least one second dummy holes of the second driving transistor, and is greater than the number of at least one third dummy holes of the third driving transistor.

13. The display device according to claim 11, in, The total aperture area of ​​the at least one first dummy hole of the first driving transistor is greater than the total aperture area of ​​the at least one second dummy hole of the second driving transistor, and is greater than the total aperture area of ​​the at least one third dummy hole of the third driving transistor.

14. The display device according to claim 11, in, The total aperture area or number of the at least one second dummy hole of the second driving transistor is the same as the total aperture area or number of the at least one third dummy hole of the third driving transistor.

15. The display device according to claim 11, in, Each of the first, second, and third sub-pixels further includes at least one contact hole disposed in a plurality of insulating layers, and Wherein, the aperture area of ​​each of the at least one first dummy hole of the first sub-pixel, the at least one second dummy hole of the second sub-pixel, and the at least one third dummy hole of the third sub-pixel is the same as the aperture area of ​​each of the at least one contact hole.

16. The display device according to claim 11, further comprising: The first dummy electrode is connected to the first gate electrode through the first dummy hole of the first driving transistor; The second dummy electrode is connected to the second gate electrode through the at least one second dummy hole of the second driving transistor; as well as The third dummy electrode is connected to the third gate electrode through at least one third dummy hole of the third driving transistor. The area of ​​the first dummy electrode is different from the areas of the second and third dummy electrodes. The area of ​​the second dummy electrode may be the same as or different from the area of ​​the third dummy electrode.

17. The display device according to claim 11, in, The at least one first dummy via, the at least one second dummy via, and the at least one third dummy via are embedded through an upper insulating layer above the first gate electrode of the first driving transistor, the second gate electrode of the second driving transistor, and the third gate electrode of the third driving transistor.

18. The display device according to claim 11, in, The first sub-pixel also includes a plurality of peripheral dummy holes disposed in a plurality of insulating layers surrounding the first driving transistor.

19. The display device according to claim 11, in, The aperture area of ​​each of the first, second, and third light-emitting elements is different from that of the others.

20. The display device according to claim 11, in, The temperature-dependent brightness variation characteristics of each of the first, second, and third light-emitting elements are different from each other, or The temperature-dependent threshold voltage change of the first driving transistor differs from that of the second and third driving transistors. The temperature-dependent threshold voltage change of the second driving transistor may be the same as or different from the temperature-dependent threshold voltage change of the third driving transistor.

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