Photonic integrated circuit and method of manufacturing photonic integrated circuit
By introducing a tilted surface transition region into photonic integrated circuits, waveguides can be smoothly connected at different height levels, overcoming the limitations of existing waveguide connection methods and improving signal transmission quality and space utilization efficiency.
Patent Information
- Application Number
- CN202480014972.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-04-06
- Filing Date
- 2024-03-26
- Publication Date
- 2025-10-28
AI Technical Summary
The existing waveguide connection methods in photonic integrated circuits limit their flexibility and signal transmission efficiency at different height levels, resulting in poor signal quality and low space utilization efficiency.
By employing a transition region with a tilted surface, the waveguide extends between different surfaces of the substrate. By combining the release layer and the cladding layer, a tilted surface transition region is formed, enabling a smooth connection of the waveguide at different height levels.
This enables flexible connection of waveguides at different height levels, improving signal transmission quality and space utilization efficiency, while reducing signal interference and optical loss.
Smart Images
Figure CN120858307A_ABST
Abstract
Description
[0001] This invention relates to photonic integrated circuits and methods for manufacturing photonic integrated circuits.
[0002] This patent application claims priority to German patent application 102023108967.6, the disclosure of which is incorporated herein by reference.
[0003] Photonic integrated circuits, including waveguides for the transmission of photonic signals, are known in the prior art.
[0004] The purpose of this application is to provide an improved photonic integrated circuit and an improved method for manufacturing the photonic integrated circuit.
[0005] The objective is achieved by the photonic integrated circuit and method of the independent claim. Further embodiments are the subject of the dependent claims.
[0006] According to one aspect of the present invention, a photonic integrated circuit is provided, the photonic integrated circuit including a substrate having a first surface, a cladding layer having a second surface, and at least one waveguide disposed on the first surface and the second surface, wherein the first surface is partially covered by the cladding layer, wherein the cladding layer includes a transition region having a sloping surface, and wherein the waveguide extends from the first surface to the second surface of the cladding layer via the sloping surface of the transition region.
[0007] This allows for the provision of improved photonic integrated circuits. Due to the transition region with its sloping surface, the waveguide can extend at two different height levels relative to the substrate. A 3D photonic integrated circuit can be provided, comprising stacked waveguides on top of each other, with a portion of each waveguide level transitioning to the same plane.
[0008] According to one embodiment, an additional waveguide is disposed on the first surface and is at least partially covered by a cladding layer.
[0009] This allows for the technical advantage of providing an improved photonic integrated circuit with at least two different waveguides. Due to the transition region with tilted surfaces, the two waveguides can be positioned side-by-side at one height level and on top of each other at two different height levels with a vertical interval between them. This allows for horizontal connection ports where the waveguides are positioned side-by-side at the same height level, and for vertical connection ports where the waveguides are positioned at different height levels with a vertical interval between them.
[0010] The terms vertical and horizontal are used with reference to the normal direction of the substrate.
[0011] The term height level refers to the normal direction of the substrate. Two different height levels can be defined by a first surface and a second surface that are perpendicularly spaced from each other with respect to the normal direction.
[0012] According to the implementation method, the waveguide and other waveguides are at least partially parallel oriented.
[0013] This allows for the technical advantage that two waveguides can be included in a single vertical connection port.
[0014] According to the embodiment, the tilt angle α of the inclined surface of the transition region is less than or equal to 30°, preferably less than or equal to 20°, and most preferably less than or equal to 10°.
[0015] This allows for the realization of technical advantages, namely, optimal signal transmission through the waveguide. Too steep an angle will result in a significant loss of signal quality.
[0016] According to the embodiment, the length of the inclined surface in the inclined direction is between 5 μm and 200 μm, preferably between 10 μm and 50 μm.
[0017] This allows for a technological advantage: further improvement in signal transmission within the waveguide. Too short a tilted surface leads to drastic changes in height, resulting in a degraded signal quality.
[0018] According to the embodiment, the spacing between waveguides and other waveguides with respect to the normal direction of the substrate is between 50 nm and 5 μm, preferably between 100 nm and 1 μm.
[0019] This allows for technical advantages, namely, avoiding signal interference between signals from two waveguides. Furthermore, it provides a space-saving solution, allowing waveguides to be installed on more than two vertically spaced surfaces and at different heights.
[0020] According to an embodiment, the first surface is the surface of another covering layer disposed on the substrate.
[0021] This allows for the realization of technical advantages, namely, the waveguide being mounted on a solid substrate using an additional cladding layer. The additional cladding layer improves the deposition of the material to form the waveguide. This results in better waveguide quality, and consequently, better signal transmission. When the substrate has a higher refractive index than the waveguide material, a cladding layer with a lower refractive index can be advantageous.
[0022] According to the implementation method, the thickness of the additional coating layer is greater than or equal to 2 μm.
[0023] This allows for the realization of technical advantages, namely, the provision of a solid substrate for the waveguide. This enables robust and efficient photonic integrated circuits.
[0024] According to the embodiment, the height step between the inclined surface of the transition region and the first surface is less than or equal to 100 nm, preferably less than or equal to 50 nm, and most preferably less than or equal to 10 nm.
[0025] This allows for the achievement of technical advantages, namely, minimizing the variation in the waveguide cross-section at the input and output of the tilted region, and thus resulting in minimal optical loss.
[0026] According to the implementation, the width of the waveguide on the inclined surface of the transition region is greater than the width of the waveguide on the first surface and / or the second surface.
[0027] This allows for technological advantages, namely, improved signal transmission due to the increased width of the waveguide in the tilted surface, and ensures photolithographic manufacturability in the tilted region.
[0028] According to the embodiments, the width of the waveguide on the first surface and / or the second surface is between 50 nm and 10 μm, preferably between 300 nm and 1 μm, and / or wherein the width of the waveguide on the inclined surface of the transition region is 0.5 μm, 1 μm or greater than 3 μm.
[0029] This allows for technological advantages, namely, the ability to achieve optimal signal transmission via the waveguide.
[0030] According to an embodiment, the photonic integrated circuit includes a plurality of waveguides and / or a plurality of additional waveguides, wherein the plurality of waveguides and / or the plurality of additional waveguides are oriented parallel to each other.
[0031] This allows for the realization of technical advantages, namely, improved performance and / or functionality of photonic integrated circuits due to multiple waveguides and multiple additional waveguides.
[0032] According to an aspect of the present invention, a method for manufacturing a photonic integrated circuit according to any of the foregoing embodiments is provided, the method comprising:
[0033] - Provide a substrate having a first surface;
[0034] - Apply a peeling layer to a predefined area of the first surface, wherein the peeling layer includes an edge region having an undercut portion, and wherein the edge region having the undercut portion is adjacent to an area of the first surface not covered by the peeling layer.
[0035] - Apply a coating layer with a second surface to the area of the first surface not covered by the peeling layer and the first surface, and form a transition region with an inclined surface between the first surface and the second surface by applying a coating layer with a gradually decreasing thickness to the area of the first surface below the undercut portion of the peeling layer.
[0036] -Remove the peeling layer from the first surface, and
[0037] - A waveguide is formed on the first and second surfaces, which extends through the inclined surface of the transition layer.
[0038] This allows for a technological advantage: an improved method for manufacturing photonic integrated circuits. The method includes applying a release layer with an undercut portion to a predefined region on a first surface. In a subsequent step, a cladding layer is applied to the release layer and to a region not covered by the release region. This deposits a cladding layer material in the region below the undercut portion. Due to deposition probability, the cladding layer in the region below the undercut portion has a gradually decreasing thickness and forms a transition region with the sloping surface. Therefore, the use of the release layer with an undercut portion provides a technically easy method for generating a transition region with a sloping surface, where the transition region provides a smooth transition between two height levels of the first and second surfaces. This allows waveguides to extend between two different height levels.
[0039] According to an implementation method, the method further includes:
[0040] - Before applying the release layer and the cladding layer, an additional waveguide is formed on the first surface, wherein applying the cladding layer on the release layer and the first surface includes:
[0041] - Apply a cladding layer to at least a portion of the other waveguide.
[0042] This allows for the technological advantage of manufacturing photonic integrated circuits with multiple waveguides at different height levels. Furthermore, waveguides can be connected between different height levels via a transitional slope.
[0043] According to an implementation method, the method further includes:
[0044] - Before applying the release layer and the coating layer, an additional coating layer is applied to the substrate, wherein the first surface is formed by the surface of the additional coating layer.
[0045] This allows for technological advantages, namely providing a robust foundation for waveguides that can be optically transparent.
[0046] According to an embodiment, the coating layer and / or additional coating layers are formed by silica deposition, wherein the deposition includes physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), and low-pressure chemical vapor deposition (LPCVD).
[0047] This allows for a technical advantage: a simple method for applying the coating layer via deposition. Due to the deposition of the coating material, a sloping transition region can be formed below the undercut portion of the release layer.
[0048] According to an implementation method, the method further includes:
[0049] - Planarize the cladding and / or additional cladding before applying the waveguide and / or additional waveguide.
[0050] This allows for the technical advantage of providing a smooth surface, which is beneficial to waveguide performance. Furthermore, the smooth surface improves the stacking of multiple waveguide layers.
[0051] According to an embodiment, planarization includes chemical mechanical polishing of the coating layer.
[0052] This allows for the realization of technical advantages, namely, precise flattening.
[0053] According to the implementation method, the release layer is stabilized by temperature treatment.
[0054] This allows for the achievement of technical advantages, namely, providing a stable release layer.
[0055] According to an embodiment, the waveguide and / or additional waveguides are formed by nitride film deposition, and / or wherein the waveguide and / or additional waveguides are formed as ribbed waveguides.
[0056] This allows for the realization of technical advantages, namely, the provision of high-quality waveguides.
[0057] The above-described properties, features, and advantages of the invention, as well as the ways in which they are realized, become clearer and more readily understood in conjunction with the following description of embodiments illustrated in conjunction with the accompanying drawings. The drawings show:
[0058] Figure 1 A schematic diagram of a photonic integrated circuit according to an embodiment;
[0059] Figure 2 A further schematic diagram of a photonic integrated circuit according to a further embodiment;
[0060] Figure 3 A schematic diagram of the method steps for manufacturing a photonic integrated circuit according to an embodiment;
[0061] Figure 4 A schematic diagram of further method steps for manufacturing photonic integrated circuits;
[0062] Figure 5 Further schematic diagrams of method steps for manufacturing a photonic integrated circuit according to a further embodiment; and
[0063] Figure 6 A schematic diagram of further method steps for manufacturing photonic integrated circuits.
[0064] Figure 1 A schematic diagram of a photonic integrated circuit 100 according to an embodiment is shown.
[0065] As shown in the embodiment, the photonic integrated circuit 100 includes a substrate 101 having one set of waveguides 109 and another set of additional waveguides 115. The waveguides 109 and the additional waveguides 115 form two sets of largely parallel waveguides in each set. The number of waveguides 109, 115 and the corresponding paths of each of the waveguides 109, 115 shown are merely exemplary and should not limit the invention.
[0066] In the current embodiment, the additional waveguide 115 is positioned entirely on the first surface 103. The first surface 103 defines a first height level relative to the substrate 101. In the illustrated embodiment, an additional cladding layer 123 is applied to the substrate 101. The surface of the additional cladding layer 123 defines the first surface 103.
[0067] In the first region 161, a plurality of waveguides 109 are positioned on a first surface 103 defining a first height level relative to the substrate 101. In the second region 163, the photonic integrated circuit 101 includes an overlay layer 105. The overlay layer 105 defines a second surface 107. The second surface 107 defines a second height level relative to the substrate 101 and includes vertical spacing to the first surface 103.
[0068] The covering layer 105 includes a transition region 111 having an inclined surface 113. The inclined surface 113 provides a transition between a first surface 103 in a first region 161 and a second surface 107 of the covering layer 105 in a second region 163.
[0069] In the illustrated embodiment, a plurality of waveguides 109 extend from the first surface 103 to the second surface 107 of the cladding layer 105 via the inclined surface 113 of the transition region 111.
[0070] When multiple additional waveguides 115 are positioned on the first surface 103 and thus at the first height level, including the vertical distance to multiple waveguides 109 in the second region 163, wherein the waveguides 109 are positioned on the second surface 107 of the cladding layer 105 and thus at the second height level.
[0071] Figures a) and b) show cross-sectional views of the photonic integrated circuit 100 of Figure b) along two cutting axes A and C.
[0072] In Figure a), waveguide 109 and another waveguide 115 are shown positioned on the first surface 103 and at a corresponding first height level, respectively. In contrast, in Figure c), waveguide 109 and the other waveguide 115 are shown positioned at different height levels with a vertical distance between them. The other waveguide 115 is positioned on the first layer 103 and at a corresponding first height level, while waveguide 109 is positioned on the second surface 107 of the cladding layer 105 and thus at a corresponding second height level.
[0073] On the first edge 167 of the photonic integrated circuit 100, a plurality of waveguides 109 are included in a first terminal region 171. An additional waveguide 115 is included in a second terminal region 173. Both the first terminal region 171 and the second terminal region 173 are located on the first surface 103 and at a corresponding first height level. On the second edge 169 of the photonic integrated circuit 100, a plurality of waveguides 109 and a plurality of waveguides 115 are combined into a third terminal region 175. In the third terminal region 175, the respective waveguides 109 are perpendicularly spaced relative to the other waveguides 115.
[0074] Figure 2 A further schematic diagram of a photonic integrated circuit 100 according to a further embodiment is shown.
[0075] The implementation shown is based on Figure 1 The implementation methods described herein include... Figure 1 All the features shown. Figure 2 In one embodiment, the photonic integrated circuit 100 includes an additional cladding layer 145 positioned on top of the cladding layer 105. The additional cladding layer 145 defines a third surface 143 perpendicularly spaced from the second surface 107 of the cladding layer 105, and thus defines a third height level. The additional cladding layer 145 is positioned in a third region 165 and includes an additional transition region 147 having an additional inclined surface 149. The additional transition region 147, and in particular the additional inclined surface 149, provides a transition within a first region 161 between the third surface 143 of the additional cladding layer 145 and the second surface 107 of the cladding layer 105, or between the third surface 143 of the additional cladding layer 145 and the first surface 103 of the additional cladding layer 123.
[0076] In the illustrated embodiment, the photonic integrated circuit 100 includes another set of multiple additional waveguides 151. In a first region 161, the additional waveguides 151 are positioned on a first surface 103 of an additional cladding layer 123. In a second region 163, the additional waveguides 151 are positioned on a second surface 107 of a cladding layer 105. In a third region 165, the additional waveguides 151 are positioned on a third surface 143 of an additional cladding layer 145. Thus, the additional waveguides 151 extend from the first surface 103 to the second surface 107 of the cladding layer 105 via a sloped surface 113 of a transition region 111, and extend to the third surface 143 of the additional cladding layer 145 via a further sloped surface 149 of a further transition region 147.
[0077] On the first edge 167, an additional waveguide 151 is incorporated into the fourth terminal region 177. The first terminal region 171, the second terminal region 173, and the fourth terminal region 177 are positioned on the first surface 103. On the second edge 169, waveguide 109, an additional waveguide 115, and the additional waveguide 151 are all incorporated into the third terminal region 175. In the third terminal region 175, all waveguides 109, 115, and 151 are positioned on three different surfaces 103, 107, and 143 and at three different height levels, respectively.
[0078] Figure b) shows a cross-sectional view of the photonic integrated circuit 100 along the cutting axis C. It shows that in the third terminal region 175, three sets of waveguides 109, 115, and 151 are perpendicularly spaced apart with respect to the normal direction 121 of the substrate 101. In the embodiment of Figure b), the additional waveguide 151 is further covered by a fourth cladding layer 153. Each of the aforementioned sets of waveguides 109, 115, and 151 can be spaced apart from each other in the plane, for example, by about 3 μm. The waveguides of the entire set can be spaced apart, for example, by about 21 μm. Different spacings of waveguides 109, 115, and 151 are also possible.
[0079] The number of waveguides 109, 115, and 151 in different groups and the number of waveguides in each group are merely exemplary and should not limit the scope of the invention.
[0080] In terminal regions 171, 173, 175, and 177, waveguides 109, 115, and 151 of each group are oriented to be mostly parallel to the waveguides of the corresponding group. This allows for easy and efficient connection of the photonic integrated circuit 100 to other components.
[0081] Figure 3 A schematic diagram of the method steps for manufacturing a photonic integrated circuit 100 according to an embodiment is shown.
[0082] Figures a), b), and c) show the methods for manufacturing according to Figure 1 and Figure 2 The three steps of the method of the present invention for the photonic integrated circuit 100 in the embodiment are described.
[0083] In FIG. a), a substrate 101 having a first surface 103 is provided. In the illustrated embodiment, the first surface 103 is defined by the surface of a further covering layer 123 applied to the substrate 101.
[0084] According to an embodiment, an additional coating layer is formed by silica deposition. The deposition may include physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PEDVD), or low-pressure chemical vapor deposition (LPCVD).
[0085] If an additional cladding layer 123 is applied directly to the substrate 101, the additional cladding layer 123 can be grown as thermally heated silicon dioxide. Thermal oxides have the advantages of a very smooth surface and a very uniform thickness distribution.
[0086] According to a further embodiment, the thickness 125 of the additional cladding layer 123 is greater than or equal to 2 μm. This minimizes leakage loss due to the interaction between the evanescent field of the propagation mode in the waveguide and the bare silicon of the substrate 101.
[0087] According to Figure b), in a further method step, a release layer 129 is applied to a predefined region 131 on the first surface 103. The predefined region 131 is only a small portion of the entire region of the first surface 103, such that a large portion 139 of the first surface 103 is not covered by the release layer 129. The release layer 129 includes an edge region 133 adjacent to the uncovered region 139 of the first surface 103. In the edge region 133, the release layer 129 includes an undercut portion 135 having a length 155 and a height 157, and defines a region 141 of the first surface 103 positioned below the undercut portion 135.
[0088] The undercut portion 135 of the peeling layer 129 can be produced according to the method disclosed in EP 2835687 A1.
[0089] The release layer 129 can be made of spin-coated negative release resin.
[0090] According to the embodiment, the release layer 129 is stabilized by temperature treatment before the deposition of the coating layer 105.
[0091] In a further method step, as shown in Figure c), a covering layer 105 is applied to the peeling layer 129 and the region 139 of the first surface 103 that is not covered by the peeling layer 129.
[0092] According to the embodiment, the coating layer 105 is formed by silica deposition, preferably using physical vapor deposition (PVD) or any low-temperature deposition technique.
[0093] Due to the deposition process of the silica material in the cladding layer 105, the silica material is deposited on a region 141 of the first surface 103 located below the undercut portion 135. Due to the deposition probability of the silica material in the region 141 below the undercut portion 135, the cladding layer 105 includes a transition region 111 located in the region 141 below the undercut portion 135. The transition region 111 includes a gradually decreasing thickness and therefore has a sloped surface 113.
[0094] The tilt angle α of the transition region 111 and the length of the tilted surface 113 can be varied by changing the length 155 and height 157 of the undercut portion 135.
[0095] Figure 4 A schematic diagram of further method steps for manufacturing a photonic integrated circuit 100 is shown.
[0096] Figures d), e), and f) illustrate three further method steps of the present invention for manufacturing photonic integrated circuits. The method steps in Figures d), e), and f) are... Figure 3 The method steps in Figures a), b), and c) are a continuation.
[0097] In the method steps shown in Figure d), the peeling layer 129 is removed from the first surface 103 of the additional coating layer 123. The removal of the peeling layer 129 is achieved by washing it off from the additional coating layer 123 using various liquids in a two-step method. The coating layer 105 is removed along with the peeling layer 129. Removal can be achieved by washing away the corresponding layer.
[0098] In Figure d), the inclined surface 113 of the transition region 111 is further shown to have an inclination angle α relative to the first surface 103 of the additional covering layer 123. According to an embodiment, the inclination angle α of the inclined surface 113 is less than or equal to 30°. Preferably, the inclination angle α is less than or equal to 20°. Most preferably, the inclination angle α is less than or equal to 10°.
[0099] In the next method step shown in Figure e), planarization of cladding layer 105 and / or additional cladding layer 123 is performed. Planarization may include chemical mechanical polishing of cladding layers 105, 123. Through planarization, the first surface 103 and the second surface 107 are defined or at least formed as uniform surfaces that can be parallel to the surface orientation of the substrate 101. The inclined surface 113 of the transition region 111 of cladding layer 107 may be further included in the planarization process. Waveguide loss can be limited due to the smooth surface of the cladding layers. Planarization must be optimal to minimize the number and size of defects on the one hand, and to prevent dielectric erosion that may occur during excessively long planarization times on the other.
[0100] According to a further embodiment, the length 117 of the inclined surface 113 of the transition region 111 is between 5 μm and 200 μm, preferably between 10 μm and 15 μm. The length 117 is oriented in the inclined direction of the inclined surface 113.
[0101] In a further method step, as shown in FIG. f), waveguide 109 is formed on a first surface 103 and a second surface 107, and waveguide 109 extends via an inclined surface 113 of transition layer 111. According to an embodiment, waveguide 109 is formed by nitride film deposition. According to a further embodiment, waveguide 109 may be formed as a ribbed waveguide.
[0102] The deposition of the nitride film used to create the waveguide 109 can be applied via PECVD or LPCVD. The structuring of the ribs 159 can be achieved in a two-step process. First, the ribs are constructed to a defined height of, for example, approximately 350 nm via reactive ion etching in a constant-time etching step. Then, the first multi-ridge structure is etched via successive reactive ion etching steps, wherein an etch stop is present on the cladding layer 105.
[0103] According to a further embodiment, the rib 159 of the waveguide 109 on the inclined surface 113 of the transition region 111 is larger than the rib 159 of the waveguide 109 on the first surface 103 and / or the second surface 107. According to a further embodiment, the height of the rib 159 of the waveguide 109 on the first surface 103 and / or the second surface 107 is between 50 nm and 10 μm, preferably between 300 nm and 1 μm. The width of the waveguide 109 on the inclined surface 113 of the transition region 111 can be greater than 3 μm.
[0104] Figure 5 A further schematic diagram of the method steps for manufacturing a photonic integrated circuit 100 according to a further embodiment is shown.
[0105] Figure 5 The embodiment of the method for manufacturing the photonic integrated circuit 100 shown is based on Figure 3 and Figure 4 The embodiments of the method shown are described, and include all the method steps shown in the figures.
[0106] Similar to the first method step Figure 3 and Figure 4 The implementation method is shown in Figure a), according to Figure 3 One embodiment provides a substrate 101 having an additional covering layer 123 defining a first surface 103.
[0107] exist Figure 5 and Figure 6 In the embodiments shown, with Figure 3 and Figure 4 Compared to the embodiment shown, an additional waveguide 115 is provided on the first surface 103 of the additional cladding layer 123. This is done in the method steps shown in FIG. b). FIG. b1) shows a bird's-eye view of a substrate 101 having the additional cladding layer 123 applied to the first surface 103 and the additional waveguide 115. FIG. b2) shows a cross-sectional view of the substrate 101 of FIG. b1) along the first direction D1.
[0108] Similar to waveguide 109, another waveguide 115 is produced by nitride film deposition.
[0109] In the method step of Figure c), a release layer 129 is applied in a predefined region 131. The release layer 129 does not cover the additional waveguide 115 disposed on the first surface 103. Even the spacing between the release layer 129 and the additional waveguide 115 is possible. The release layer 129 again includes an undercut portion 135 in the edge region 133 adjacent to the region 137 not covered by the release layer 129. Figure c2) again shows a cross-sectional view of the photonic integrated circuit 100 along the first direction D1.
[0110] In the method step of Figure d), a covering layer 105 is applied to the release layer 129 and the region 137 not covered by the release layer 129. Figure d) shows a cross-sectional view of the photonic integrated circuit 100 along the second direction D2.
[0111] Figure e) shows the deposition steps of the coating layer 105 shown in Figure d) along the first direction D1.
[0112] In the following method steps shown in Figures f) and g), the release layer 129 is removed from a predefined region 131 of the first surface 103, and a cladding layer 105 is applied to the release layer 129. As shown in Figure g), an additional waveguide 115 disposed on the first surface 103 of the additional cladding layer 123 is covered by the cladding layer 105. Similar to Figure 3 and Figure 4In the illustrated embodiment, the cladding layer 105 includes a transition region 111 with a sloping surface 113. The sloping surface 113 provides a transition between the first surface 103 of the additional cladding layer 123 and the second surface 107 of the cladding layer 105. In Figure g), the second surface 107 of the cladding layer 105 is shown as a roughened surface prior to the planarization process. The roughened surface includes kinks and steps originating from the underlying waveguide topography.
[0113] Figure 6 A schematic diagram of further method steps for manufacturing a photonic integrated circuit 100 is shown.
[0114] The method steps shown in Figures h) to m) are Figure 5 The method steps shown in Figures a) to g) are a continuation.
[0115] Planarization of the first surface 103 and / or the second surface 107 and / or the inclined surface 113 of the transition region 111 is shown in Figures H and I. Similar to Figures f) and g), Figures h) and i) show cross-sectional views of the photonic integrated circuit 100 along the second and first directions, respectively. In the method steps of Figures H and I, the planarization of surfaces 103, 107, 113 can be achieved by chemical mechanical polishing.
[0116] In a further step of the method, as shown in FIG. j), waveguide 109 is formed on a first surface 103 and a second surface 107, and extends via an inclined surface 113 of a transition region 111. As shown in FIG. k), waveguide 109, positioned on the second surface 107 of cladding layer 105, is positioned above another waveguide 115 located on the first layer 103 of another cladding layer 123. In the first region 161, both waveguides 109 and 115 are positioned on the first surface 103 of the other cladding layer 123 and are positioned at similar height levels relative to the substrate 101. In the second region 163, waveguide 109 is positioned on the second surface 107 of cladding layer 105 and is therefore positioned at a second height level, while the other waveguide 115 is positioned on the first surface 103 and is therefore positioned at a first height level relative to the substrate 101. The two waveguides 109 and 115 are perpendicularly spaced apart relative to the substrate 101.
[0117] In Figures 1) and 2) it is shown that waveguides 109 and 115 can be formed as ribbed waveguides. According to an embodiment, waveguide 109 can be formed by nitride film deposition.
[0118] In Figure m), waveguide 109 and another waveguide 115 have the same width 127. As mentioned above, the width 127 of waveguide 109 on the inclined surface 113 may be greater than the width 127 on the first surface 103 or the second surface 107. Alternatively, the widths of waveguides 109 and 115 may be different.
[0119] The invention has been described and illustrated in more detail with the aid of preferred embodiments. However, the invention is not limited to the disclosed examples. Other variations can be derived by those skilled in the art.
[0120] List of reference numerals
[0121] 100 Photonic Integrated Circuits
[0122] 101 substrate
[0123] 103 First Surface
[0124] 105 Coating Layer
[0125] 107 Second Surface
[0126] 109 Waveguide
[0127] 111 Transition Zone
[0128] 113 Inclined surface
[0129] 115 Other waveguides
[0130] 117 Length
[0131] 119 interval
[0132] 121 Normal direction
[0133] 123 Other coating layers
[0134] 125mm thickness
[0135] 127 width
[0136] 129 Peel Layer
[0137] 131 Predefined region
[0138] 133 Edge Region
[0139] 135 Undercut section
[0140] 137 Areas not covered by the stripping layer
[0141] 139mm thickness
[0142] 141 The area below the undercut portion
[0143] 143 Third Surface
[0144] 145 Additional Covering Layer
[0145] 147 Other transitional areas
[0146] 149 Other inclined surfaces
[0147] 151 Additional waveguide
[0148] 153 Fourth Coating Layer
[0149] 155 Length
[0150] 157 meters high
[0151] 159 Ribs
[0152] 161 First Region
[0153] 163 Second Region
[0154] 165 Third Region
[0155] 167 First Edge
[0156] 169 Second Edge
[0157] 171 First Terminal Area
[0158] 173 Second Terminal Area
[0159] 175 Third Terminal Area
[0160] 177 Fourth Terminal Area
[0161] α tilt angle
[0162] D1 First Direction
[0163] D2 Second Direction
[0164] A cutting axis
[0165] C-cutting axis
Claims
1. A photonic integrated circuit (100) comprising a substrate (101) having a first surface (103), a cladding layer (105) having a second surface (107), and at least one waveguide (109) disposed on the first surface and the second surface (103, 107), wherein, The first surface (103) is partially covered by the cladding layer (105), wherein the cladding layer (105) includes a transition region (111) having an inclined surface (113), and wherein the waveguide (109) extends from the first surface (103) to a second surface (107) of the cladding layer (105) via the inclined surface (113) of the transition region (111), wherein the width (127) of the waveguide (109) on the inclined surface (113) of the transition region (111) is greater than the width (127) of the waveguide (109) on the first surface and / or the second surface (103, 107).
2. The photonic integrated circuit (100) according to claim 1, wherein, Another waveguide (115) is disposed on the first surface (103) and is at least partially covered by the cladding layer (105).
3. The photonic integrated circuit (100) according to claim 1 or 2, wherein, The waveguide (109) is at least partially parallel to the other waveguide (115).
4. The photonic integrated circuit (100) according to any one of claims 1 to 3, wherein, The tilt angle (α) of the inclined surface (113) of the transition region (111) is less than or equal to 30°, preferably less than or equal to 20°, and most preferably less than or equal to 10°.
5. The photonic integrated circuit (100) according to any one of claims 1 to 4, wherein, The length (117) of the inclined surface (113) in the inclined direction is between 5 μm and 200 μm, preferably between 10 μm and 50 μm.
6. The photonic integrated circuit (100) according to any one of claims 1 to 5, wherein, The spacing (119) between the waveguide (109) and the other waveguide (115) with respect to the normal direction (121) of the substrate (101) is between 50 nm and 5 μm, preferably between 100 nm and 1 μm.
7. The photonic integrated circuit (100) according to any one of claims 1 to 6, wherein, The first surface (103) is the surface of another covering layer (123) disposed on the substrate (101).
8. The photonic integrated circuit (100) according to claim 7, wherein, The thickness (125) of the additional covering layer (123) is greater than or equal to 2 μm.
9. The photonic integrated circuit (100) according to any one of claims 1 to 8, wherein, The height step between the inclined surface (113) of the transition region (111) and the first surface (103) is less than or equal to 100 nm, preferably less than or equal to 50 nm, and most preferably less than or equal to 10 nm.
10. The photonic integrated circuit (100) according to any one of claims 1 to 9, wherein, The width (127) of the waveguide (109) on the first surface and / or the second surface (103, 107) is between 50 nm and 10 μm, preferably between 300 nm and 1 μm, and / or wherein, The width of the waveguide (109) on the inclined surface (113) of the transition region (111) is 0.5 μm, 1 μm or greater than 3 μm.
11. The photonic integrated circuit (100) according to any one of claims 1 to 9, wherein, The photonic integrated circuit (100) includes a plurality of waveguides (109) and / or a plurality of additional waveguides (115), wherein the plurality of waveguides (109) and / or the plurality of additional waveguides (115) are oriented parallel to each other.
12. A method for manufacturing a photonic integrated circuit (100) according to any one of claims 1 to 11, comprising: - Provide a substrate (101) having a first surface (103); - Apply a peeling layer (129) to a predefined area (131) of the first surface (103), wherein the peeling layer (129) includes an edge region (133) having an undercut portion (135), and wherein the edge region (133) having the undercut portion (135) is adjacent to an area (137) of the first surface (103) not covered by the peeling layer (129); - A covering layer (105) having a second surface (107) is applied to the area (137) of the peeling layer (129) and the first surface (103) not covered by the peeling layer (129), and a transition region (111) having an inclined surface (113) is formed between the first surface and the second surface (103, 107) by applying a covering layer (105) having a gradually decreasing thickness (139) to the area (141) of the first surface (103) below the undercut portion (135) of the peeling layer (129); - Remove the peeling layer (129) from the first surface and the second surface (103, 107), and - A waveguide (109) is formed on the first surface and the second surface (103, 107), the waveguide (109) extending via the inclined surface (113) of the transition layer.
13. The method of claim 12, further comprising: - Before applying the release layer (129) and the cladding layer (105), an additional waveguide (115) is formed on the first surface (103), wherein applying the cladding layer (105) on the release layer (129) and the first surface (103) includes: - The cladding layer (105) is applied to at least a portion of the additional waveguide (115).
14. The method according to claim 12 or 13, further comprising: - Before applying the release layer (129) and the cover layer (105), an additional cover layer (123) is applied to the substrate (101), wherein the first surface (103) is formed by the surface of the additional cover layer (123).
15. The method according to any one of claims 12, 13 or 14, wherein, The coating layer (105) and / or the additional coating layer (123) are formed by silica deposition, wherein the deposition includes physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), and low-pressure chemical vapor deposition (LPCVD).
16. The method according to any one of claims 12 to 15, further comprising: - Planarize the cladding layer (105) and / or the additional cladding layer (123) before applying the waveguide (109) and / or the additional waveguide (115).
17. The method according to claim 16, wherein, The planarization includes chemical mechanical polishing of the overlay layers (105, 123).
18. The method according to any one of claims 12 to 17, wherein, The release layer (129) is stabilized by temperature treatment.
19. The method according to any one of claims 12 to 18, wherein, The waveguide (109) and / or the additional waveguide (115) are formed by nitride film deposition, and / or wherein the waveguide and / or the additional waveguide are formed as ribbed waveguides.
Citation Information
Patent Citations
Method of producing a resist structure with undercut sidewall
EP2835687A1