Two-way communication for allowing consistent per-frame configuration updates

Abstract

An electronic device uses a dominant synchronization signal generator to synchronize clock signal generators used by multiple components in the electronic device to a common time base. A processor core complex of the electronic device sends a per-frame configuration to a timing controller for a corresponding frame before the frame to be displayed on the electronic display begins.

Description

Background Technology

[0001] This disclosure relates to systems, methods, and apparatus for synchronizing gamma settings of an electronic device having one or more electronic displays and for transmitting frame configurations for the electronic device on a per-frame basis.

[0002] This section is intended to introduce the reader to various aspects of the art that may be related to the aspects of this disclosure, which are described below and / or protected by the claims. This discussion is intended to help provide the reader with background information to better understand the aspects of this disclosure. Accordingly, it should be understood that these statements should be read in this regard and not as an endorsement of prior art.

[0003] Many electronic devices, including televisions, mobile phones, computers, wearable devices, vehicle dashboards, virtual reality glasses, and so on, display images on electronic displays. To display images, electronic displays can control the light emission of their display pixels, at least in part, based on corresponding image data. In electronic devices, multiple components may use clock signals generated by different clock signal generators. The clock signals generated by different clock signal generators may not be exactly the same, and clock drift may occur between different components after a certain period of time, which may result in frame duplication or loss from the electronic display. Summary of the Invention

[0004] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects that may not be set forth below.

[0005] As previously mentioned, in electronic devices, multiple components may use clock signals generated by more than one clock signal generator (e.g., a crystal). Clock signals generated by different clock signal generators may not be identical, and clock drift may occur between different components after a certain time period, which could cause frames to be repeated on or lost from the electronic display. Some electronic devices may define a time base to manage time-related operations in components associated with the electronic display. For example, the time base can be used to determine whether it is time to display a frame. For example, a global time base (GTB) can be used as the time base in an electronic device. For example, the computing system of an electronic device (e.g., processing circuitry, processor) may implement a Universal Precision Time Protocol (gPTP) time base based on the IEEE 802.1AS precision time protocol. The GTB time may be periodically broadcast to a subset or all components within the computing system, and timers (e.g., clock signal generators) in each component may be synchronized to the GTB time. For example, a component of an electronic device may have a clock signal generator and use that clock signal generator to generate clock signals for time-related operations within that component. Clock drift can occur between the clock signal generator in a component and the gPTP time base used by the computing system because they are not generated from the same clock generator, and the systems may be out of sync. The computing system of an electronic device can use a dominant synchronization signal generator to synchronize the clock signal generators used by these multiple components, so that the generated clock signals are synchronized to a common time base, such as the gPTP time base.

[0006] This disclosure provides a technique for synchronizing a clock signal generator used by multiple components using a dominant synchronization signal generator, such that the clock signals generated by these components are synchronized to a common time base (e.g., gPTP time base). By utilizing the dominant synchronization signal generator, the computing system of an electronic device can send a frame configuration to a timing controller via a bidirectional communication channel before the start of each frame to be displayed on an electronic display, for that corresponding frame. Each frame configuration may include frame information such as foveation rendering information, intra-frame pause (IFP) position and duration, transmit rate, frame duration, luminance, active link power management (ALPM), etc., as described in more detail herein. Additionally, the computing system and the timing controller can maintain gamma settings synchronization. When the timing controller detects a temperature-induced current / voltage (I / V) drift, it can calculate the relevant gamma settings based on the temperature-induced I / V drift and send them to the electronic display. Furthermore, the timing controller can calculate updated gamma correlation coefficients and interrupt the computing system to read these updated gamma correlation coefficients from the timing controller via another bidirectional communication channel. The computing system can use the updated gamma correlation coefficients to update the relevant gamma settings. These two communication channels can form a closed loop, which allows for maintaining a consistent gamma setting.

[0007] Various modifications to the features described above may be possible with respect to the various aspects of this disclosure. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, the various features discussed below with respect to one or more embodiments of the illustrated embodiments may be incorporated individually or in any combination into any of the foregoing aspects of this disclosure. The brief summary presented above is intended only to familiarize the reader with certain aspects and context of embodiments of this disclosure and does not limit the claimed subject matter. Attached Figure Description

[0008] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram of an electronic device according to one embodiment of the present disclosure;

[0010] Figure 2 It means Figure 1 A perspective view of a notebook computer, representing one embodiment of an electronic device;

[0011] Figure 3 It means Figure 1 A front view of a handheld device in another embodiment of an electronic device;

[0012] Figure 4 It means Figure 1 A front view of another handheld device in another embodiment of an electronic device;

[0013] Figure 5 It means Figure 1 A front view and a side view of another embodiment of a wearable electronic device;

[0014] Figure 6 It means Figure 1 A front view of a desktop computer in another embodiment of an electronic device;

[0015] Figure 7 This is an example of an implementation scheme according to this disclosure. Figure 1 A schematic block diagram of closed-loop communication in electronic devices;

[0016] Figure 8 This is an example of an implementation scheme according to this disclosure. Figure 1 A timing diagram of a synchronization implementation scheme in electronic devices;

[0017] Figure 9 This is an example of an implementation scheme according to this disclosure. Figure 1 A timing diagram of another implementation scheme for synchronization in electronic devices;

[0018] Figure 10 This is an example of an implementation scheme according to this disclosure. Figure 1 A timing diagram of an implementation scheme for command flow in an electronic device;

[0019] Figure 11 This is a timing diagram illustrating a frame rate variation mechanism according to an embodiment of the present disclosure; and

[0020] Figure 12 This is a block diagram illustrating an active frame with dynamically rendered content according to an embodiment of this disclosure. Detailed Implementation

[0021] When describing elements of various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to mean one or more elements present in the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that additional elements may be present in addition to those listed. Furthermore, it should be understood that references to “an embodiment,” “an embodiment,” or “some embodiments” of this disclosure are not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. The use of the terms “approximately” or “close to” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.).

[0022] In view of the foregoing and for ease of explanation, Figure 1 An electronic device 10, including an electronic display 12, is shown. As detailed below, the electronic device 10 can be any suitable electronic device, such as a computer, mobile phone, portable media device, tablet computer, television, virtual reality headset, wearable device (such as a watch), vehicle dashboard, etc. Therefore, it should be noted that... Figure 1 This is merely an example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0023] Electronic device 10 includes an electronic display 12, one or more input devices 14, one or more input / output (I / O) ports 16, a processor core complex 18 having one or more processing circuits or processing circuit cores, local memory 20, main memory storage device 22, network interface 24, and power supply 26 (e.g., power source). Figure 1The various components described herein may include hardware elements (e.g., circuitry), software elements (e.g., a tangible, non-transitory computer-readable medium storing executable instructions), or a combination of both hardware and software elements. It should be noted that the various depicted components may be combined into fewer components or separated into additional components. For example, local memory 20 and main memory storage device 22 may be included in a single component.

[0024] The processor core complex 18 is operatively coupled to local memory 20 and main memory storage device 22. Therefore, the processor core complex 18 can execute instructions stored in local memory 20 or main memory storage device 22 to perform operations such as generating and / or transmitting image data for display on electronic display 12. Accordingly, the processor core complex 18 may include one or more general-purpose microprocessors, one or more application-specific integrated circuits (ASICs), one or more field-programmable logic arrays (FPGAs), or any combination thereof.

[0025] In addition to program instructions, local memory 20 or main memory storage device 22 may store data to be processed by processor core complex 18. Therefore, local memory 20 and / or main memory storage device 22 may include one or more tangible, non-transitory computer-readable media. For example, local memory 20 may include random access memory (RAM), and main memory storage device 22 may include read-only memory (ROM), rewritable non-volatile memory such as flash memory, hard disk drive, optical disk, etc.

[0026] Network interface 24 can communicate data with another electronic device or network. For example, network interface 24 (e.g., a radio frequency system) can enable electronic device 10 to communicatively couple to a personal area network (PAN) (such as a Bluetooth network), a local area network (LAN) (such as an 802.11x Wi-Fi network), and / or a wide area network (WAN) (such as a 4G, LTE, or 5G cellular network). Power supply 26 can provide power to one or more components in electronic device 10, such as processor core complex 18 or electronic display 12. Therefore, power supply 26 can include any suitable energy source, such as a rechargeable lithium polymer (Li-poly) battery or an alternating current (AC) power converter. I / O port 16 can enable electronic device 10 to interact with other electronic devices. For example, when a portable storage device is connected, I / O port 16 can enable processor core complex 18 to communicate data with the portable storage device.

[0027] Input device 14 can enable user interaction with electronic device 10 by receiving user input, for example, via buttons, keyboard, mouse, touchpad, touch sensor, etc. Input device 14 may include touch sensing components (e.g., touch control circuitry, touch sensing circuitry) in electronic display 12. Touch sensing components can receive user input by detecting the frequency or location of an object touching the surface of electronic display 12.

[0028] In addition to enabling user input, the electronic display 12 may be a display panel having one or more display pixels. For example, the electronic display 12 may include a self-emitting pixel array having an array of one or more self-emitting pixels or liquid crystal pixels. The electronic display 12 may include any suitable circuitry (e.g., display driver circuitry) to drive the self-emitting pixels, including, for example, row drivers and / or column drivers (e.g., display drivers). Each self-emitting pixel may include any suitable light-emitting element, such as an LED (e.g., an OLED or microLED). However, any other suitable type of pixel may also be used, including non-self-emitting pixels (e.g., liquid crystals used in liquid crystal displays (LCDs), digital micromirror devices (DMDs) used in DMD displays). The electronic display 12 may control the light emission from the display pixels to present a visual representation of information, such as a graphical user interface (GUI) of an operating system, an application interface, still images, or video content, by displaying image data frames. To display images, the electronic display 12 may include display pixels implemented on the display panel. Display pixels may represent subpixels, each subpixel controlling the luminance of a color component (e.g., red, green, or blue for an RGB pixel arrangement, or red, green, blue, or white for an RGBW arrangement).

[0029] The electronic display 12 can display an image by controlling pulse emission (e.g., light emission) from its display pixels based on pixel or image data associated with corresponding image pixels (e.g., dots) in an image. In some embodiments, the pixel or image data may be generated by an image source (e.g., image data, digital code), such as processor core complex 18, graphics processing unit (GPU), or image sensor. Additionally, in some embodiments, image data may be received from another electronic device 10, for example, via network interface 24 and / or I / O port 16. Similarly, the electronic display 12 may display image frames of content based on pixel or image data generated by processor core complex 18, or the electronic display 12 may display frames based on pixel or image data received via network interface 24, input devices, or I / O port 16.

[0030] Electronic device 10 can be any suitable electronic device. For illustrative purposes, Figure 2An example of electronic device 10 is shown: a handheld device 10A. Handheld device 10A can be a portable phone, media player, personal data manager, handheld gaming platform, etc. For illustrative purposes, handheld device 10A can be a smartphone, such as any device available from Apple Inc. model.

[0031] The handheld device 10A includes a housing 30 (e.g., a casing). The housing 30 protects internal components from physical damage or shields them from electromagnetic interference, such as by surrounding the electronic display 12. The electronic display 12 can display a graphical user interface (GUI) 32 with an array of icons. When an icon 34 is selected via the input device 14 or the touch-sensing component of the electronic display 12, an application can be launched.

[0032] The input device 14 can be accessed through an opening in the housing 30. The input device 14 enables the user to interact with the handheld device 10A. For example, the input device 14 enables the user to activate or deactivate the handheld device 10A, navigate the user interface to the home screen, navigate the user interface to a user-configurable application screen, activate voice recognition feature structures, provide volume control, or switch between vibration and ring modes.

[0033] Figure 3 Another example of a suitable electronic device 10 is shown, specifically a tablet device 10B. The tablet device 10B can be any device available from Apple Inc. model. Figure 4 Another example of a suitable electronic device 10 is shown, specifically a computer 10C. For illustrative purposes, computer 10C can be any device available from Apple Inc. or Model. Another example of a suitable electronic device 10, especially a wearable electronic device 10D, is in Figure 5 As shown in the image. For illustrative purposes, the wearable electronic device 10D can be any Apple Inc. device. Model. As depicted, the tablet device 10B, computer 10C, and watch 10D each also include an electronic display 12, an input device 14, an I / O port 16, and a housing 30. The electronic display 12 can display a GUI 32. Here, the GUI 32 displays a visualization of a clock. When the visualization is selected via the input device 14 or the touch-sensitive component of the electronic display 12, an application can be launched, such as transforming the GUI 32 into a presentation. Figure 2 and Figure 3 Icon 34 is discussed in the text.

[0034] See Figure 6 Computer 10E can represent Figure 1 Another embodiment of the electronic device 10. The computer 10E can be any computer, such as a desktop computer, server, or laptop, but can also be a standalone media player or video game console. For example, the computer 10E could be Apple Inc. of Cupertino, California. Or other similar devices. It should be noted that computer 10E may also refer to a personal computer (PC) from another manufacturer. A similar housing 36 may be provided to protect and enclose the internal components of computer 10E, such as electronic display 12. In some embodiments, the user of computer 10E may interact with computer 10E using various peripheral input structures 14 that can be connected to computer 10E, such as keyboard 14A or mouse 14B (e.g., input structure 14).

[0035] In view of the above, Figure 7This is a schematic block diagram illustrating closed-loop communication 90 between processor core complex 18, electronic display panel 92 of electronic display 12, and timing controller (TCON) 102 in electronic display 12. Electronic display panel 92 may include reference array 94, active area 96, and associated driver circuitry (e.g., scan driver, data driver). Reference array 94 may include a display pixel array for monitoring parameters on display panel 92 (e.g., pixel drive current / voltage (I / V)). Processor core complex 18 may send information associated with display settings (such as display brightness value (DBV) and frame configuration (e.g., foveation rendering information, intra-frame pause (IFP) position and duration, transmit rate, frame duration, brightness)) to TCON 102 to control the display of image frames on active area 96 of display panel 92. In electronic device 10, multiple components (such as processor core complex 18 and TCON 102) may use clock signals generated by more than one clock signal generator to control some time-related operations. For example, a clock signal generator (CSG) 98 in processor core complex 18 can generate clock signals for time-dependent operations within processor core complex 18, and a clock signal generator (CSG) 103 in TCON 102 can generate clock signals for time-dependent operations within TCON 102. Clock signals generated by different clock signal generators may not be identical, and clock drift may occur between different components after a certain time period, and the system may become out of sync. For example, clock signals generated by clock signal generators 98 and 103 may not be identical, and clock drift between processor core complex 18 and TCON 102 may cause frames to be repeated on display panel 92 or lost from the display panel. Therefore, a dominant synchronization signal generator (LSSG) 100 in processor core complex 18 can be used to synchronize clock signals generated in multiple components (e.g., by clock signal generators 98 and 103) to a common time base (e.g., the IEEE 802.1-based Universal Precision Time Protocol (gPTP) time base or Global Time Base (GTB)). For example, in some implementations, the clock signal generated by the clock signal generator 103 in TCON 102 can follow the dominant synchronization signal generated by the dominant synchronization signal generator 100 in the processor core complex 18, so that TCON 102 can remain synchronized with the dominant synchronization signal on a frame-by-frame basis. Therefore, by utilizing the dominant synchronization signal generator 100, the processor core complex 18 can send a frame configuration to TCON 102 on a frame-by-frame basis before the start of each frame to be displayed on the display panel 92, for that corresponding frame, such as... Figure 11As illustrated. In some embodiments, when multiple frames use the same frame configuration, the processor core complex 18 may send the frame configuration to TCON 102 on a multi-frame basis (e.g., on a two-frame basis, on a three-frame basis, etc.). In some embodiments, the processor core complex 18 may send the frame configuration to TCON 102 on demand (e.g., when the frame configuration is updated). The frame configuration may include frame information such as foveated rendering information, intra-frame pause (IFP) position and duration, transmit rate, frame duration, luminance, ALPM, etc.

[0036] In some embodiments, a clock signal generated by a clock signal generator in a component of electronic device 10 (e.g., clock signal generator 103 in TCON 102) may follow a dominant synchronization signal generated by a dominant synchronization signal generator 100 in processor core complex 18, such that the component (e.g., TCON 102) may be synchronized with processor core complex 18 on a per-frame or multi-frame basis (e.g., on a two-frame basis, on a three-frame basis, etc.) in relation to time-dependent operations in the component. For example, synchronization on a multi-frame basis (e.g., on a two-frame basis, on a three-frame basis, etc.) may be sufficient for time-dependent operations in the component. For example, in some embodiments, processor core complex 18 may implement two dedicated fractional timers (e.g., 80-bit) with programmable increments and offsets to track common gPTP times. Processor core complex 18 may implement multiple (e.g., 32) programmable pulse waveforms for multiple components (such as cameras, display pipelines, external audio phase-locked loops (PLLs), etc.). Therefore, a subset or all of the components in electronic device 10 can be synchronized to a common time base (e.g., gPTP time base). Processor core complex 18 can implement multiple gPTP timers (e.g., two) to allow switching from one timer master to another.

[0037] like Figure 7As illustrated, a bidirectional communication channel exists between the processor core complex 18 and the TCON 102 via two interfaces: a System Power Management Interface (SPMI) interface 104 and a Low Power Display Port (LPDP) interface 106. Communication via SPMI 104 and communication via LPDP 106 form a closed-loop communication mechanism. This closed-loop communication mechanism allows for consistent gamma settings between the processor core complex 18 and the TCON 102. SPMI interface 104 can be used for communication between the processor core complex 18 and the TCON 102 to synchronize information associated with the gamma settings (e.g., spline coefficients defining the relationship between the drive voltage (V) and drive current (I) of the display pixels). An example procedure for synchronizing gamma settings between the processor core complex 18 and the TCON 102 via SPMI interface 104 is described in detail below and in [the following text is incomplete and requires further context]. Figure 8 and Figure 9 As illustrated in the example. Additionally, the processor core complex 18 can implement auxiliary data packet (SDP) command packets in the LPDP protocol to convey information associated with display brightness values ​​(DBV) and frame configurations (e.g., transmit rate, frame duration, brightness, foveated rendering information, IFP (intra-frame pause) position and duration) via the LPDP interface 106 and TCON 102. Figure 10 An example procedure is illustrated for a DBV (Display Brightness Value) command stream generated using SDP packets via LPDP interface 106 between processor core complex 18 and TCON 102.

[0038] TCON 102 can communicate with display panel 92 via System Programming Interface (SPI) interface 108, such as reading from display panel 92 (SPI (read)) or writing to display panel 92 (SPI (write)). For example, processor core complex 18 can read initial temperature parameters and initial spline coefficients generated by TCON 102 from TCON 102 via SPMI interface 104. Spline coefficients can be used to define the relationship between the drive voltage (V) and drive current (I) of display pixels. Display brightness value (DBV) commands can be transmitted to processor core complex 18 and TCON 102 via signal line 110 via LPDP interface 106. At block 112, processor core complex 18 can calculate grayscale-to-voltage conversion (G2V) and voltage-to-digital code conversion (V2D) LUTs by using lookup table (LUT) interpolation, and TCON 102 can calculate the tap voltage (Vtap) associated with gamma setting at block 114 and send it to display panel 92 via SPI interface 108. The G2V LUT is a global LUT that maps grayscale code / grayscale level (target light under the current DBV) to the voltage of pixels in the display panel 92. As temperature changes, the G2V characteristics also change; therefore, the G2V LUT can be periodically regenerated to track temperature-induced I / V shifts in the pixel drivers, which can be measured by the reference array 94 in the display panel 92. At block 116, the TCON 102 tracks the reference array I / V sensing to periodically (e.g., every 1 second) detect temperature-induced I / V drift and calculates updated spline coefficients based on the detected temperature-induced I / V drift. The TCON 102 can send interrupt requests to the processor core complex 18 via the SPMI interface 104. In some embodiments, the TCON 102 can generate and update the Vtap based on I / V sensing and write it to the display panel 92 via the SPI interface 108, such as... Figure 8 As illustrated. In other embodiments, TCON 102 may wait for the processor core complex 18 to send a signal for an I / V update (e.g., via an SDP command), then TCON 102 may calculate the Vtap and write it to the display panel 92 via the SPI interface 108, as shown. Figure 9 As illustrated, after receiving an interrupt request from TCON 102, processor core complex 18 can read updated spline coefficients (e.g., 40 floating-point spline coefficients) from TCON 102 via SPMI interface 104, and processor core complex 18 can perform I / V evaluation at block 118, and update or construct new G2V and V2D LUTs with the updated spline coefficients.

[0039] The display pixel pipeline 120 in the processor core complex 18 can be used to prepare pixel data 122 to be displayed on the display panel 92, such as... Figure 7 As illustrated, in the display pixel pipeline 120, pixel data 122 is input to the processor core complex 18. At block 124, the processor core complex 18 converts the grayscale level of the pixel data 122 into voltage codes in a G2V LUT, and at block 126, subpixel uniformity compensation (SPUC) is performed in the voltage domain. At block 128, the processor core complex 18 uses a V2D LUT to convert the output of the SPUC from voltage data into digital codes. At block 130, the processor core complex 18 uses dithering to compensate for errors in the digital codes and sends the compensated digital codes to TCON 102 via data line 132. TCON 102 then sends the compensated digital codes to the display panel 92 via address line ADDR 134. The display panel 92 uses the compensated digital codes to calculate a digital code-to-voltage (D2V) LUT that maps the digital codes to display pixel voltages. The display pixel voltages can then be sent to the active pixels on the display panel 92. Display pixel voltages can also be sent to reference array 94 on display panel 92. As previously mentioned, processor core complex 18 can send frame configuration to TCON 102 on a per-frame basis before the start of each frame to be displayed on display panel 92 for that corresponding frame. Frame configuration may include frame information such as foveation rendering information, intra-frame pause (IFP) position and duration, transmit rate, frame duration, brightness, ALPM, etc. Therefore, display pixel pipeline 120 can use the clock signal generated by clock signal generator 98 and TCON 102 can use the clock signal generated by clock signal generator 103 to perform time-related operations during the frame duration, which does not affect the display of the frame, because the dominant synchronization signal generated by dominant synchronization signal generator 100 can be used to keep processor core complex 18 and TCON 102 synchronized for each frame.

[0040] Figure 8This is a timing diagram 150 illustrating an implementation of synchronizing gamma settings between processor core complex 18 and TCON 102 via SPMI interface 104. Processor core complex 18 can synchronize its gamma settings with TCON 102 via SPMI interface 104, addressing I / V drift caused by temperature. TCON 102 can periodically (e.g., once per second) read I / V measurements from display panel 92 (e.g., from reference array 94) to detect gamma curve (e.g., spline coefficient) drift due to temperature variations. At time t1, when the temperature-induced I / V drift detected by TCON 102 on active frame 152 displayed on active region 96 exceeds a threshold (e.g., a percentage or a value), TCON 102 can determine to update the gamma settings, which can be determined by TCON 102 based on the content of the active frame. For example, when temperature-induced I / V drift causes perceptible image artifacts in the image displayed on active frame 152, TCON 102 can determine to update the gamma settings to correct such artifacts. TCON 102 can calculate updated spline coefficients based on the detected temperature-induced I / V drift. At time t2, TCON 102 can calculate an updated Vtap based on the updated spline coefficients and send the updated Vtap to display panel 92. Display panel 92 can apply the updated Vtap to active frame 154 immediately following active frame 152. At time t3, TCON 102 can send an interrupt signal to processor core complex 18 via SPMI interface 104. In some embodiments, processor core complex 18 can monitor the interrupt bit associated with the interrupt signal every frame to detect the presence of new data to be read. At time t4, processor core complex 18 can read the updated spline coefficients (e.g., 40 floating-point spline coefficients) from TCON 102 via SPMI interface 104. At time t5, processor core complex 18 can perform I / V evaluation and update the G2V and V2D LUTs using updated spline coefficients. Processor core complex 18 can prepare the updated G2V / V2D LUTs for the SPUC in the display pixel pipeline 120 before time t'5. Processor core complex 18 can apply the updated G2V / V2D LUTs to the display pixel pipeline 120 for use in the next active frame. The duration between time t3 and time t'5 can be less than a threshold T. th-1 (For example, several frame durations), allowing the updated gamma settings to be applied to the target active frame (e.g., the active frame immediately following active frame 156). Therefore, in Figure 8In the illustrated implementation, updated gamma settings (e.g., Vtap, G2V / V2D LUT) can be applied to the display panel 92 at different times, which allows the software in the processor core complex 18 more time to update the LUT. For example, an updated Vtap can be applied to the display panel 92 at active frame 154, while an updated G2V / V2D LUT can be prepared for the SPUC in the display pixel pipeline 120 during active frame 156 and applied to pixels on active frames after active frame 156.

[0041] Figure 9 This is timing diagram 180 illustrating another implementation of synchronizing gamma settings between processor core complex 18 and TCON 102 via SPMI interface 104. Figure 9 In this configuration, TCON 102 can periodically (e.g., once per second) read I / V measurements from display panel 92 (e.g., from reference array 94) to detect any drift in the gamma curve (e.g., spline coefficients) due to temperature variations. At time t1, when the temperature-induced I / V drift detected by TCON 102 on active frame 182 displayed on effective area 96 exceeds a threshold (e.g., a percentage or a specific value), TCON 102 determines to update the gamma setting. TCON 102 can calculate the updated spline coefficients based on the detected temperature-induced I / V drift. Unlike... Figure 8 The implementation scheme illustrated herein, in Figure 9In this process, Vtap may not be calculated and may not be applied to active frame 184 immediately following active frame 182. At time t2, TCON 102 may send an interrupt signal to processor core complex 18 via SPMI interface 104. In some implementations, processor core complex 18 may monitor the interrupt bit associated with the interrupt signal every frame to detect the presence of new data to be read. At time t3, processor core complex 18 may read the updated spline coefficients (e.g., 40 floating-point spline coefficients) from TCON 102 via SPMI interface 104. At time t4, processor core complex 18 may perform I / V evaluation and update G2V and V2DLUT using the updated spline coefficients. Processor core complex 18 may prepare the updated G2V / V2D LUT for SPUC in display pixel pipeline 120 before time t'4 (which may be within active frame 186). At time t5 (which may occur during the VBLACK between active frames 186 and 188), processor core complex 18 may set an I / V update synchronization flag in an SDP command packet. This SDP command packet can be used to send the corresponding frame configuration (e.g., transmit rate, frame duration, brightness, foveation rendering information, IFP (intra-frame pause) position and duration) to TCON 102 during the VBLACK cycle of each frame for each frame. The duration between time t2 and time t'4 may be less than a threshold T. th-2 (For example, several frame durations), allowing the updated gamma settings to be applied to the target active frame (e.g., active frame 188). At time t6, TCON 102 can calculate the updated Vtap based on the updated spline coefficients and send the updated Vtap to display panel 92. At time t7, processor core complex 18 can apply the updated G2V / V2D LUT to display pixel pipeline 120 for pixels on active frame 188, and display panel 92 can apply the updated Vtap to active frame 188. Therefore, in Figure 9 In the illustrated implementation, the updated gamma settings (e.g., Vtap, G2V / V2D LUT) can be applied to the display panel 92 simultaneously (e.g., during active frame 188).

[0042] In some implementations, the processor core complex 18 may receive DBV commands for changing the brightness of the display panel 92 periodically (e.g., per frame) or on demand, and as discussed above, the processor core complex 18 may apply DBV commands on a per-frame basis using the dominant synchronization signal generator 100. For example, the processor core complex 18 may send frame configurations (e.g., transmit rate, frame duration, brightness, foveation rendering information, IFP (intra-frame pause) position and duration) to the TCON 102 before the start of each frame to be displayed on the display panel 92 for that corresponding frame. Additionally, some display pixel pipelines in the display pixel pipeline may be brightness-dependent and may change at the same frame when updating the G2V / V2D LUT. Figure 10 This is a timing diagram 200 illustrating an implementation of a DBV command flow generated via SDP packets between processor core complex 18 and TCON 102 through interface 106. At time t1 (during a VBLANK cycle after active frame 202 and before active frame 204), processor core complex 18 can send an updated DBV to TCON 102 via SDP packets using LPDP interface 106. Therefore, the DBV data in TCON 102 is updated (e.g., from DBV:B to DBV:C). At time t2 (which may be the same as t1), processor core complex 18 can prepare an updated G2V / V2D LUT for the SPUC in the display pixel pipeline 120 based on the updated DBV before the start of active frame 204. At time t3, TCON 102 can calculate an updated Vtap based on the updated DBV data (e.g., DBV:C) in TCON 102 and send the updated Vtap to display panel 92. At time t4, the processor core complex 18 can apply the updated G2V / V2D LUT to the display pixel pipeline 120 for pixels on active frame 204, and the display panel 92 can apply the updated Vtap at active frame 204.

[0043] The processor core complex 18 can also support frame rate (e.g., 90Hz, 120Hz) variations by utilizing the dominant synchronization signal generator 100. Figure 11 This is timing diagram 300 illustrating the frame rate variation mechanism. Figure 11In the illustrated implementation, the display line time (e.g., 3.2 microseconds) can be fixed, the vertical blanking period (VBLANK) can be a fixed time period, and the vertical active frame (VACTIVE) duration can be determined by the corresponding resolution and inter-frame pause (IFP). Frame duration can include periods for VBLANK, VACTIVE, and vertical wait (VWAIT). The duration of VWAIT for a frame can vary based on the corresponding frame rate. Therefore, the duration of VWAIT in a frame can be a flexible time period that can increase or decrease according to changes in the frame rate. Corresponding dominant synchronization signals (e.g., dominant synchronization signal 302, dominant synchronization signal 304, dominant synchronization signal 306, dominant synchronization signal 308, dominant synchronization signal 310) can be generated by dominant synchronization signal generator 100 and used to synchronize TCON 102 with processor core complex 18 based on the corresponding target frame duration for each frame (e.g., frame 312, frame 314, frame 316, frame 318). For example, a dominant synchronization signal can be received by the processor core complex 18 and TCON 102 to indicate the end of a frame. For example, dominant synchronization signal 302 can indicate the end of a frame preceding frame 312, dominant synchronization signal 304 can indicate the end of frame 312, dominant synchronization signal 306 can indicate the end of frame 314, and so on. The processor core complex 18 can send a new frame duration in the frame configuration (e.g., transmit rate, frame duration, brightness, foveation rendering information, IFP (intra-frame pause) position and duration) to TCON 102 via a corresponding SDP command at some time before the start of the corresponding VACTIVE frame. For example, at time t1 (which may be during the VBLANK of frame 314), the processor core complex 18 can send the frame configuration of frame 314 (e.g., target frame duration, foveation rendering information, IFP position and duration, brightness) to TCON 102 via SDP command S314. Time t1 may be earlier than time t2 (when the VACTIVE frame of frame 314 begins) by a time period Dt (e.g., several rows). Dt may be the minimum time period for which the frame configuration included in SDP command S314 is applied to the VACTIVE frame of frame 314. The value of the time period Dt may be different for frames (e.g., frames 314, 316, 318), which may be related to the corresponding frame configuration, TCON 102, and display panel 92. If the frame configuration associated with a frame is sent to TCON 102 at a time period less than the corresponding minimum time period Dt before the frame begins to be displayed (e.g., due to clock drift), that frame configuration may not be used to display the frame on display panel 92 in subsequent vertically active frames. For example, if SDP command S314 is sent to TCON 102 after time t1, the frame configuration included in SDP command S314 may not be applied to the VACTIVE frame of frame 314.Since the dominant synchronization signal generated by the dominant synchronization signal generator 100 can be used to keep the processor core complex 18 and TCON 102 synchronized for each frame, for each frame, the frame configuration associated with the frame (e.g., target frame duration, foveation rendering information, IFP position and duration, brightness) can be sent to TCON 102 at a time equal to or greater than the corresponding minimum time period Dt before the frame begins to play on display panel 92. In some embodiments, TCON 102 can be kept synchronized with processor core complex 18 on a per-frame basis or on a multi-frame basis (e.g., on a two-frame basis, on a three-frame basis, etc.), so that the frame configuration associated with the frame (e.g., target frame duration, foveation rendering information, IFP position and duration, brightness) can be sent to TCON 102 via SDP commands on a per-frame basis or on a multi-frame basis, such that the minimum time period Dt is satisfied, and the frame configuration can be used to display the frame on display panel 92 in the vertically active frame following the SDP command.

[0044] A VWAIT with duration W1 can be added to frame 314 to achieve the target frame duration. Therefore, various VWAIT durations can be used for frames with various frame durations / rates. For example, W2 is the VWAIT duration of frame 316 with a first frame rate (e.g., 96Hz), and W3 is the VWAIT duration of frame 318 with a second frame rate (e.g., 90Hz). Since the vertical active frame (VACTIVE) duration can be determined by the corresponding resolution and IFP (inter-frame pause), the method described above can also be used to change the resolution and IFP (e.g., IFP position and duration) and foveated rendering on a per-frame basis. In some implementations, frame configurations can be sent to TCON 102 on a multi-frame basis (e.g., on a two-frame basis, on a three-frame basis) or on demand (e.g., when the frame configuration is updated).

[0045] As mentioned above, the processor core complex 18 can also support frame-by-frame foveated rendering variations (e.g., foveated position or gaze point, foveated rendering region coordinates) by utilizing the dominant synchronization signal generator 100. Foveated rendering means that the image resolution of the image can vary depending on the fixed gaze point (e.g., the gaze point). Foveated rendering can be used to reduce the number of pixels to be processed by grouping pixels in non-foveated regions. For dynamic foveated rendering, the display pixel pipeline 120 can process frame data at a fixed foveated resolution / region whose coordinates depend on the dynamically changing fixed gaze point position (e.g., based on eye tracking). Figure 12 This is a block diagram illustrating an active frame 400 with dynamically rendered content. Figure 12In this context, region 402 corresponds to the gaze point and does not contain pixel groups. The position of region 402 can change between frames (e.g., based on eye tracking). In region 402, the resolution is 1×1. Region 404 corresponds to a grouping of 2×2 regions (2 rows of pixels and 2 columns of pixels), and region 406 corresponds to a grouping of 4×4 regions (4 rows of pixels and 4 columns of pixels). In regions with pixel groups (e.g., regions 404 and 406), the scan driver and data driver of display panel 92 can concurrently update the pixel groups. For example, four pixels (2×2) in the same group in region 404 can use the same image data and be updated concurrently. The gaze point location or gaze point information can be included in the metadata sent to processor core complex 18 for each frame. The processor core complex 18 can send foveation rendering information (e.g., foveation position, grouping information, region coordinates) to the TCON 102 via the LPDP interface 106 using SDP commands before the VACTIVE of the corresponding frame, enabling the VACTIVE to display the foveation rendering information. Therefore, real-time eye tracking can be achieved by updating foveation rendering changes (e.g., foveation position or gaze point, foveation rendering region coordinates) on a per-frame basis to improve dynamic image display.

[0046] The processor core complex 18 can also support ALPM (Active Link Power Management) to reduce power during VBLACK and IFP (Inter-Frame Pause). For example, the processor core complex 18 can send ALPM to TCON 102 via LPDP interface 106 during each VBLACK between frames.

[0047] The techniques presented and claimed herein are referenced and applied to specific examples of physical and practical nature that significantly improve the art and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements designated as “means for [performing] [function]…” or “steps for [performing] [function]…”, it is intended that such elements should be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be interpreted in accordance with 35U.SC112(f).

[0048] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. An electronic device, comprising: An electronic display configured to display frames of image data; and Processing circuit, the processing circuit being configured to: A dominant synchronization signal is generated to synchronize the timing controller to the processing circuitry, wherein the timing controller is configured to control the electronic display; as well as Before the frame begins to be displayed on the electronic display, a configuration associated with the frame is sent to the timing controller at a specific time based on the dominant synchronization signal, wherein the frame is configured to be displayed on the electronic display based on the configuration.

2. The electronic device of claim 1, wherein the configuration includes the duration of the frame, foveation rendering information, intra-frame pause position and duration, luminance data, or any combination thereof.

3. The electronic device according to claim 1, wherein the time period from the specific time to the display time is within the vertical blanking time of the electronic display.

4. The electronic device of claim 1, wherein the dominant synchronization signal is used to indicate the end of the duration of the frame.

5. The electronic device of claim 4, wherein the duration of the frame includes a flexible time period, wherein the flexible time period is related to the frame rate of the frame.

6. The electronic device of claim 4, wherein the duration of the frame comprises a fixed time period, wherein the fixed time period is a common value for each frame displayed on the electronic display.

7. The electronic device of claim 4, wherein a common line time is used for each frame displayed on the electronic display.

8. An electronic device, comprising: Control circuit, the control circuit being configured to: Monitor changes in parameters associated with temperature on an electronic display; In response to the change of the parameter being greater than a threshold, a coefficient is calculated based on the temperature, the coefficient indicating the relationship between the driving voltage and driving current of the display pixels on the electronic display; as well as Send an interrupt signal; and Processing circuit, the processing circuit being configured to: Receive the interrupt signal from the control circuit; as well as Within a threshold period following the receipt of the interrupt signal, the coefficient is read from the control circuit.

9. The electronic device of claim 8, wherein the change in the parameter is detected by a reference array on the electronic display.

10. The electronic device of claim 8, wherein the control circuit synchronizes with the processing circuit for each frame displayed on the electronic display by utilizing a dominant synchronization signal generated by a dominant synchronization signal generator of the processing circuit.

11. The electronic device of claim 8, wherein the control circuit is configured to: The first gamma setting is calculated based on the coefficients; and The first gamma setting is applied to the first active frame of the electronic display.

12. The electronic device of claim 11, wherein the processing circuit is configured to: The second gamma setting is calculated based on the coefficient within the threshold time period; and The second gamma setting is applied to the second active frame of the electronic display.

13. The electronic device of claim 12, wherein the first active frame is displayed on the electronic display earlier than the second active frame.

14. The electronic device of claim 8, wherein the processing circuit is configured to: The third gamma setting is calculated based on the coefficients within the threshold time period; and The third gamma setting is applied to the active frame of the electronic display.

15. The electronic device of claim 14, wherein the control circuit is configured to: After receiving a signal from the processing circuit, a fourth gamma setting is calculated based on the coefficients, wherein the signal is transmitted during the vertical blanking period; and The fourth gamma setting is applied to the active frame of the electronic display.

16. A method comprising: A dominant synchronization signal for synchronizing a timing controller to the processing circuitry is generated via a dominant synchronization signal generator in the processing circuitry of the electronic device, wherein the timing controller is configured to control an electronic display. as well as Before the frame begins to be displayed on the electronic display, a configuration associated with the frame is sent to the timing controller via the processing circuit through a communication interface at a specific time based on the dominant synchronization signal, wherein the timing controller is configured to display the frame on the electronic display based on the configuration.

17. The method of claim 16, wherein the configuration includes the duration of the frame, foveation rendering information, intra-frame pause position and duration, luminance data, or any combination thereof.

18. The method of claim 16, wherein the time period from the specific time to the display time is within the vertical blanking time of the electronic display.

19. The method of claim 16, comprising: The timing controller detects changes in parameters associated with the temperature displayed on the electronic display. In response to the change of the parameter being greater than a threshold, a coefficient is calculated based on the temperature via the timing controller, the coefficient indicating the relationship between the driving voltage and driving current of the display pixels on the electronic display; An interrupt signal is sent to the processing circuit via the timing controller through the second communication interface; as well as Within a threshold period after the processing circuit receives the interrupt signal, the coefficient is read from the timing controller via the processing circuit.

20. The method of claim 19, comprising: During the threshold period following the receipt of the interrupt signal by the processing circuit, the coefficient is used to update the mapping relationship in the processing circuit.

21. A system comprising: A device for generating a dominant synchronization signal for synchronizing a timing controller, wherein the timing controller is configured to control an electronic display; and A device for performing the following operation: before the display time of a frame of image data begins to be displayed on the electronic display, sending a configuration associated with the frame to a timing controller at a specific time based on the dominant synchronization signal, wherein the timing controller is configured to cause the frame to be displayed on the electronic display based on the configuration.

22. The system of claim 21, wherein the means for generating the dominant synchronization signal comprises a dominant synchronization signal generator in the processing circuitry of an electronic device.

Images