A current-controlled resistance module based on ldo zero-pole tracking compensation and use thereof

Abstract

The application discloses a flow control resistance module based on LDO zero-pole tracking compensation, which comprises an operational transconductance amplifier, a PMOS tube PM1 and a PMOS tube PM2; the noninverting terminal of the operational transconductance amplifier is connected with the drain of the PMOS tube PM1, and the inverting terminal is connected with a first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected with the gate of the PMOS tube PM1 and the gate of the PMOS tube PM2; the drain of the PMOS tube PM1 is connected with an ideal current source Isense; the source of the PMOS tube PM1 and the drain of the PMOS tube PM2 are connected with an ideal voltage source VCC; the source S2 of the PMOS tube PM2 is connected with a capacitor C1, and the other end of the capacitor C1 is connected with a second ideal voltage source. The flow control resistance module can generate an equivalent resistance which is inversely proportional to a sampling current, can make the equivalent flow control resistance R ds be linearly related to 1 / I Isense , solves the problem that a traditional flow control resistance module cannot follow the linear change of 1 / I sense , and the control is not accurate; meanwhile, the flow control resistance is less affected by process errors and temperature, and the generated error is small.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a flow control resistance module based on LDO zero-pole tracking compensation and application thereof. BACKGROUND

[0002] With the increasingly small process size and high integration of integrated circuits, power management chips develop very rapidly. For the power supply of high-performance chips, multi-phase control circuits combined with DrMOS have become the mainstream development direction. However, the DrMOS with high current output has high requirements for the stability of the output of the LDO (Low Dropout Regulator) under heavy load.

[0003] The classic structure of the LDO includes a first-stage error amplifier, a second-stage buffer, a third-stage output power tube, a resistance dividing feedback network, an off-chip load capacitor, and a compensation structure. The classic compensation structure includes traditional Miller compensation, Ahuja compensation based on Miller compensation, unit gain bandwidth compensation, and pseudo-ESR power stage compensation. The above compensation structures are used to provide stable transient response characteristics for the LDO under different loads. However, when the load current of the LDO is large, the Ahuja compensation based on Miller compensation will generate a pair of conjugate poles. The conjugate poles will cause the transient response of the LDO to oscillate at certain frequencies, resulting in abnormal output voltage. By using zero-pole tracking, the flow control resistance needs to accurately follow the load current to control the Q value of the conjugate poles to maintain between 0.5-0.7, reducing its impact on stability. When the load current of the LDO changes, the pseudo-ESR power stage compensation structure will change the position of the poles, and even in some cases, the phase margin will decrease due to the in-band entering, affecting the stability of the transient response of the LDO. By using zero-pole tracking, the flow control resistance needs to accurately follow the load current to control the position of the zero point to accurately follow the change of the position of the poles. SUMMARY

[0004] The purpose of the present application is to provide a flow control resistance module based on LDO zero-pole tracking compensation capable of accurately controlling the equivalent resistance of the PMOS tube and application thereof.

[0005] The present application provides a flow control resistance module based on LDO zero-pole tracking compensation, comprising an operational transconductance amplifier, a PMOS tube PM1, and a PMOS tube PM2.

[0006] The non-inverting terminal of the operational transconductance amplifier is connected to the drain of the PMOS tube PM1, and the inverting terminal is connected to a first ideal voltage source. The output terminal G1_2 of the operational transconductance amplifier is connected to the gate of the PMOS tube PM1 and the gate of the PMOS tube PM2.

[0007] The drain of the PMOS transistor PM1 is connected to an ideal current source I. sense The source of PMOS transistor PM1 and the drain of PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of PMOS transistor PM2 is connected to capacitor C1, and the other end of capacitor C1 is connected to a second ideal voltage source.

[0008] The ideal current source I sense To simulate the LDO sampling load current, the PMOS transistor PM1 can convert the load current into a gate drive voltage. The ideal current source I... sense The signal is converted into a voltage signal V by PMOS transistor PM1. GS1 The drain of the PMOS transistor PM1 is clamped to 3.2V by an operational transconductance amplifier, thereby controlling the drain-source voltage of the PMOS transistor PM1 to be constant.

[0009] The capacitor C1 is a simulated Miller compensation capacitor. The source of the PMOS transistor PM2 is connected to capacitor C1 to simulate the current path of LDO Miller compensation, controlling the source voltage and drain voltage to be approximately equal.

[0010] Furthermore, in the current-controlled resistor module of the present invention, the positive power supply pin of the operational transconductance amplifier is connected to the power supply VDD, and the negative power supply pin is grounded. The power supply VDD supplies power to the operational transconductance amplifier.

[0011] Furthermore, the operational transconductance amplifier of the current-controlled resistor module described in this invention is a differential amplifier with differential input and single-ended output.

[0012] Furthermore, the first ideal voltage source of the current-controlled resistor module of the present invention is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

[0013] Furthermore, the source-drain voltages of PMOS transistors PM1 and PM2 in the current-controlled resistor module of the present invention are controlled to be less than 100mV, and both PMOS transistors PM1 and PM2 are in the deep linear region.

[0014] Since PMOS transistors PM1 and PM2 are located in the deep linear region, the equivalent drain-source resistance of PMOS transistors PM1 and PM2 is inversely proportional to the absolute value of the gate-source voltage.

[0015] Furthermore, the equivalent resistance of the PMOS transistor PM1 in the current-controlled resistor module of the present invention is R. ds1 And it satisfies Formula I, and when the PMOS transistor PM1 is in the deep linear region, it satisfies Formula II:

[0016] ,

[0017] ,

[0018] The equivalent resistance of the PMOS PM2 is R ds2 , and satisfies the formula III,

[0019] ,

[0020] ,

[0021] ,

[0022] Wherein μ P is the hole mobility, C ox is the gate oxide capacitance, (W / L) PM1 is the width-length ratio of the PMOS PM1, (W / L) PM2 is the width-length ratio of the PMOS PM2, V GS is the gate-source voltage of the PMOS PM1, V th is the threshold voltage;

[0023] The R ds1 and R ds2 are linearly related to 1 / I sense .

[0024] Since the drain-source voltage of the PMOS PM1 is clamped, the current flowing through the PMOS PM1 is inversely proportional to the equivalent resistance of the source-drain.

[0025] Further, the equivalent resistance R ds2 of the PMOS PM2 of the flow control resistance module of the present application is in the range of -40℃ to 125℃, and the error rate is ±10%;

[0026] And the equivalent resistance R ds2 of the PMOS PM2 is in any process angle of tt or ff or ss or snfp or fnsp, and the error rate is ±10%.

[0027] A use based on any of the above-mentioned flow control resistance modules, the flow control resistance module is used for a low dropout linear regulator.

[0028] Further, the use of the flow control resistance module of the present application, the compensation structure of the low dropout linear regulator is ahuja compensation, by controlling the equivalent resistance R ds2 of the PMOS PM2, the Q value of the conjugate pole under heavy load is reduced to 0.5-0.7, no frequency spike appears, the phase margin is above 45°, the load is stepped from 0 to 250mA, and the response time is less than or equal to 5us.

[0029] Furthermore, regarding the application of the current-controlled resistor module described in this invention, the compensation structure of the low-dropout linear regulator is pseudo-ESR compensation, which is achieved by controlling the equivalent resistance R of the PMOS transistor PM2. ds2 This allows the zero point position to follow the pole position change, achieving stable transient response of the LDO under full load, with a phase margin of over 45°, and a response time of less than or equal to 7µs when the load changes from 0 to 250mA step.

[0030] The present invention discloses a current-controlled resistor module based on LDO zero-pole tracking compensation and its application, the advantages of which are as follows:

[0031] First, the current-controlled resistor module based on LDO zero-pole tracking compensation described in this invention, through its unique circuit structure (operational transconductance amplifier + dual PMOS transistors) and deep linear region operating design, achieves for the first time the equivalent resistance R. ds The reciprocal of the sampling current 1 / Isense Strict linear correlation. Significantly improved equivalent resistance R compared to existing technologies. ds The precision of control is improved. In particular, it solves the core challenges of Q-value control with conjugate poles in Ahuja compensation and dynamic zero-point tracking poles in pseudo-ESR compensation.

[0032] Since the drain-source voltage of PMOS transistor PM1 is clamped, and the current comes from the load current sampling current, the equivalent resistance of PMOS transistor PM1 is inversely proportional to the load current sampling current. Furthermore, because both PMOS transistors PM1 and PM2 are in the linear region, their gate-source voltages are approximately equal. Therefore, the equivalent resistances of PMOS transistors PM1 and PM2 are only inversely proportional to their gate-source voltages. Following this logic, the equivalent resistance of PMOS transistor PM2 is inversely proportional to the load current sampling current. This solves the problem of previous controlled resistances being inversely proportional to the square root of the load current sampling current, leading to inaccurate resistance control under heavy loads. This makes it more suitable for Ahuja compensation and pseudo-ESR compensation.

[0033] Since the ratio of the equivalent resistances of PMOS transistors PM1 and PM2 is only related to the ratio of their width to length, and their source voltages are approximately equal, the equivalent resistance of PM2 is minimally affected by threshold voltage and process variations, minimally affected by mobility variations under different processes, and minimally affected by temperature variations.

[0034] In summary, the current-controlled resistor module of this invention can generate an equivalent resistance that is inversely proportional to the sampling current. This module can not only make the equivalent current-controlled resistance R ds With 1 / Isense It exhibits linear correlation, solving the problem that traditional current-controlled resistor modules cannot follow 1 / I. senseThe linear change solves the problem of inaccurate control, and the flow control resistance is less affected by process error and temperature, so that the error is small. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A circuit schematic diagram of the flow control resistance module based on LDO zero-pole tracking compensation according to Embodiment 1 of the present application;

[0036] Figure 2 A graph of the relationship between the flow control resistance of the flow control resistance module according to the present application and the sampling current of the load current;

[0037] Figure 3 A simulation change graph of the process affecting the flow control resistance of the flow control resistance module according to the present application;

[0038] Figure 4 A simulation change graph of the temperature affecting the flow control resistance of the flow control resistance module according to the present application;

[0039] Figure 5 A circuit topology diagram of the flow control resistance applied to ahuja compensation according to Embodiment 2 of the present application;

[0040] Figure 6 A circuit topology diagram of the flow control resistance applied to pseudo-ESR compensation according to Embodiment 3 of the present application. DETAILED DESCRIPTION

[0041] In order to have a more clear understanding of the technical features, objectives and effects of the present application, the specific embodiments of the present application will be described in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application. The specific conditions are not specified in the specific embodiments, and the conventional conditions or the conditions provided by the manufacturer are used.

[0042] The following description refers to the accompanying drawings. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present disclosure. The terms used in the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Specific embodiment one:

[0044] A flow control resistance module based on LDO zero-pole tracking compensation, comprising an operational transconductance amplifier, a PMOS tube PM1 and a PMOS tube PM2;

[0045] The non-inverting terminal of the operational transconductance amplifier is connected to the drain of PMOS PM1, and the inverting terminal is connected to a first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected to the gate of PMOS PM1 and the gate of PMOS PM2 simultaneously;

[0046] The drain of PMOS PM1 is connected to an ideal current source I sense ; the source of PMOS PM1 and the drain of PMOS PM2 are connected to an ideal voltage source VCC simultaneously; the source S2 of PMOS PM2 is connected to a capacitor C1, and the other terminal of the capacitor C1 is connected to a second ideal voltage source.

[0047] In other embodiments, the positive power supply pin of the operational transconductance amplifier is connected to a power supply VDD, and the negative power supply pin is connected to ground.

[0048] In other embodiments, the operational transconductance amplifier is a differential amplifier with differential input and single-ended output.

[0049] In other embodiments, the first ideal voltage source is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

[0050] In other embodiments, the source-drain voltage of PMOS PM1 and PMOS PM2 is controlled to be less than 100mV, and PMOS PM1 and PMOS PM2 are both in deep linear region.

[0051] In other embodiments, the equivalent resistance of PMOS PM1 is R ds1 , and formula I is satisfied, and formula II is satisfied when PMOS PM1 is in deep linear region:

[0052] ,

[0053] ,

[0054] The equivalent resistance of PMOS PM2 is R ds2 , and formula III is satisfied,

[0055] ,

[0056] ,

[0057] ,

[0058] where μ P is the hole mobility, C ox is the gate oxide capacitance, and (W / L) PM1width-to-length ratio of the PMOS transistor PM1, (W / L) PM2 width-to-length ratio of the PMOS transistor PM2, V GS gate-to-source voltage of the PMOS transistor PM1, V th threshold voltage;

[0059] The R ds1 and R ds2 are linearly related to 1 / I sense .

[0060] In other embodiments, the equivalent resistance R ds2 of the PMOS transistor PM2 has an error rate of ±10% in a temperature range of -40°C to 125°C;

[0061] and the equivalent resistance R ds2 of the PMOS transistor PM2 has an error rate of ±10% in any process corner of tt or ff or ss or snfp or fnsp. Specific Implementation Two:

[0063] A use of the flow control resistance module based on any of the above embodiments, the flow control resistance module is used for a low dropout linear regulator.

[0064] In other embodiments, the compensation structure of the low dropout linear regulator is ahuja compensation, by controlling the equivalent resistance R ds2 of the PMOS transistor PM2, the Q value of the conjugate pole under heavy load is reduced to 0.5-0.7, no frequency spike appears, the phase margin is above 45°, the load is stepped from 0 to 250mA, and the response time is less than or equal to 5us.

[0065] In other embodiments, the compensation structure of the low dropout linear regulator is pseudo ESR compensation, by controlling the equivalent resistance R ds2 of the PMOS transistor PM2, the zero point position follows the change of the pole position, and the stability of the LDO transient response is realized under full load, the phase margin is above 45°, the load is stepped from 0 to 250mA, and the response time is less than or equal to 7us. Example 1:

[0066] A flow control resistance module based on LDO zero-pole tracking compensation, as Figure 1 shown, comprising an operational transconductance amplifier, a PMOS transistor PM1 and a PMOS transistor PM2;

[0067] The non-inverting terminal of the operational transconductance amplifier is connected with the drain of the PMOS PM1, and the inverting terminal is connected with a first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected with the gate of the PMOS PM1 and the gate of the PMOS PM2; the positive power supply pin of the operational transconductance amplifier is connected with a power supply VDD, and the negative power supply pin is grounded.

[0068] The drain of the PMOS PM1 is connected with an ideal current source I sense ; the source of the PMOS PM1 and the drain of the PMOS PM2 are connected with an ideal voltage source VCC; the source S2 of the PMOS PM2 is connected with a capacitor C1, and the other end of the capacitor C1 is connected with a second ideal voltage source.

[0069] In the embodiment 1, the operational transconductance amplifier is a differential amplifier with differential input and single-ended output. The first ideal voltage source is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

[0070] The source-drain voltage of the PMOS PM1 and the PMOS PM2 is controlled to be less than 100mV, and the PMOS PM1 and the PMOS PM2 are both in deep linear region.

[0071] In the embodiment 1, the design requirement of the PMOS PM1 is that the drain voltage of the PMOS PM1 is clamped by the operational amplifier to 3.2V (which can be output by a voltage dividing resistor in the LDO), and the source voltage of the PMOS PM1 is input as 3.3V (LDO output 3.3V), so that the PMOS PM1 works in linear region, and the clamp of the drain-source voltage is 100mV; at the same time, the current flowing through the PMOS PM1 is the load sampling current I sense , so that the equivalent resistance of the PMOS PM1 is R ds1 , and the formula I is satisfied, and the formula II is satisfied when the PMOS PM1 is in deep linear region:

[0072] ,

[0073] ,

[0074] The design requirement of the PMOS PM2 is that the drain voltage of the PMOS PM2 is input as 3.3V (LDO output 3.3V), and the source voltage is connected with one end of the capacitor C1, so that the current flowing through the PMOS PM2 is very small, which is almost equal to no ground path, so that the source voltage of the PMOS PM2 is slightly lower than 3.3V, the PMOS PM2 is in deep linear region, the equivalent resistance of the PMOS PM2 is R ds2 , and the formula III is satisfied,

[0075] ,

[0076] The design requirements of the operational transconductance amplifier are: the operational transconductance amplifier is a two-stage differential amplifier of differential input and single output; the non-inverting terminal of the operational transconductance amplifier is connected with the drain terminal of the PMOS tube PM1; the inverting terminal of the operational transconductance amplifier is connected with the first ideal voltage source, and the voltage is 3.2V (from the LDO voltage dividing resistor output); the output terminal G1_2 of the operational transconductance amplifier is connected with the gate of the PMOS tube PM1 and the PMOS tube PM2, so as to realize closed-loop control: when the load current sampling current I sense becomes larger, the voltage of the non-inverting input terminal of the operational transconductance amplifier decreases, and the output terminal voltage decreases accordingly, causing the |V GS | of the PMOS tube PM1 and the PMOS tube PM2 to rise, and the equivalent resistance of the PMOS tube PM1 to decrease, so as to pull up the drain voltage of the PMOS tube PM1 and maintain the stability of the non-inverting input voltage.

[0077] ,

[0078] (V GS -V th ) can be offset, because the source voltages of the PMOS tube PM1 and the PMOS tube PM2 are approximately equal, although in actual situations, the source voltages of the PMOS tube PM1 and the PMOS tube PM2 have some differences, causing the threshold voltages to be different, but the error is small and has little effect on the equivalent resistance:

[0079] ,

[0080] Where μ P is the hole mobility, C ox is the gate oxide capacitance, (W / L) PM1 is the width-length ratio of the PMOS tube PM1, (W / L) PM2 is the width-length ratio of the PMOS tube PM2, V GS is the gate-source voltage of the PMOS tube PM1, V th is the threshold voltage;

[0081] As Figure 2 shown, the R ds1 and R ds2 are linearly related to 1 / I sense . The equivalent resistance of the PMOS tube PM2 is a current control resistance, which is only affected by the width-length ratio of the PMOS tube PM1 and the PMOS tube PM2 and the load current sampling current, and compared with the prior art, the equivalent resistance of the PMOS tube PM2 can follow 1 / IsensePrecise variation, zero position easier to control: not only that, the equivalent resistance of PMOS PM2 is almost independent of the mobility, oxide capacitance and threshold voltage of PMOS, so the equivalent current-controlled resistance of PMOS PM2 is less affected by errors caused by process variation and temperature.

[0082] As shown in Figure 3 , the equivalent resistance R ds2 In any process angle of tt or ff or ss or snfp or fnsp, the variation is small, and the error rate is ± 10%.

[0083] As shown in Figure 4 , and the equivalent resistance R ds2 The error rate is ± 10% in the temperature range of -40℃ to 125℃; the variation is small. Example 2:

[0084] The current-controlled resistance module is used in a low-dropout linear regulator, and the compensation structure of the low-dropout linear regulator is ahuja compensation, as shown in Figure 5 The ahuja compensation structure of the low-dropout linear regulator comprises three stages; the first stage is an error amplifier EA, which inputs a reference voltage and a feedback voltage V FB , and outputs a second stage Buffer circuit; the output of the second stage Buffer circuit is connected to the gate of a power transistor PM; the drain of the power transistor PM is connected to a series of voltage dividing resistors R1, R2 and R3, and then grounded. The gate of the power transistor PM is connected to the gate of a mirror transistor PMs, and the mirror transistor PMs provides a sampling current to the PMOS PM1 of the current-controlled resistance module through a current mirror; the drain voltage of the power transistor PM serves as the source of the PMOS PM1 and the output voltage, and the voltage dividing resistors R1, R2 and R3 divide the output voltage to 3.2V and input it to the inverting terminal of the operational transconductance amplifier of the current-controlled resistance module. The drain of the power transistor PM is connected to the drain of the PMOS PM2, and the source of the PMOS PM2 is connected to a capacitor C1, and the other end of the capacitor C1 is connected to an NMOS transistor in the error amplifier EA, forming an ahuja compensation structure. In this embodiment 2, the capacitor C1 is a Miller capacitor.

[0085] The feedback signal VFB is input to the error amplifier EA, and is clamped with the Vref voltage, and drives the power transistor PM through the second stage Buffer circuit, controls the on-resistance of the power transistor PM to change with the load current, and makes the output voltage stable at 3.3V. The PMOS PM2 of the current-controlled resistance module and the capacitor C1 form a compensation structure, introduce a zero point, and split the main pole and secondary pole positions, improving the phase margin.

[0086] At light load, the control current resistance increases with the decrease of the load, so that the feedforward zero point generated by the ahuja compensation structure tracks the secondary point position of the output end of the second stage Buffer circuit; at heavy load, the resistance value of the control current resistance can be accurately controlled with the load current, the Q value of the conjugate pole point is accurately controlled at 0.5-0.7, the frequency peak generated by the conjugate pole point is controlled, and the stability of the transient output is prevented from being affected; finally, under the condition of the output current of 0-250 mA, the phase margin is above 45°, the bandwidth is maximum 650 kHz, and the response time is less than or equal to 5 us. Example 3

[0087] The control current resistance module is used in a low dropout linear regulator, and a compensation structure of the low dropout linear regulator is a pseudo ESR compensation, as shown in the figure. Figure 6 The low dropout linear regulator with the pseudo ESR compensation structure comprises three stages of circuits, the first stage is an error amplifier EA1, an input end is connected with a reference voltage and a feedback voltage VFB1, and an output end is connected with a second stage Buffer1 circuit; an output of the second stage Buffer1 circuit is connected with a power tube PMr; the power tube PMr is connected with series-connected voltage dividing resistors R4, R5 and R6. The power tube PMr is connected with gate electrodes of mirror tubes PMs1 and PMs2, the mirror tube PMs2 provides a sampling current to a PMOS tube PM1 of the control current resistance module through a current mirror; a drain voltage of the power tube PMr is used as a source electrode of the PMOS tube PM1 and an output voltage, the voltage dividing resistors R4, R5 and R6 divide the output voltage into 3.2 V and input the voltage into an inverting terminal of an operational transconductance amplifier of the control current resistance module. The drain electrode of the power tube PMr is connected with a drain electrode of a PMOS tube PM2, the source electrode of the drain electrode of the PMOS tube PM2 is connected with a capacitor C2, the other end of the capacitor C2 is connected with a drain electrode of the mirror tube PMs1, and a pseudo ESR compensation structure is formed. In the embodiment 3, the capacitor C2 is a clamping capacitor.

[0088] The feedback signal VFB1 is input into the error amplifier EA1, is clamped with the Vref voltage, drives the power tube PMr through the second stage Buffer1 circuit, controls the on-resistance of the power tube PMr to change with the load current, and makes the output voltage stable at 3.3 V. The PMOS tube PM2, the mirror tube PMs1 and the capacitor C2 of the control current resistance module form a compensation structure, two zero points and one pole point are introduced, one of the zero points is a dynamic zero point, and the other zero point and the pole point are close to each other and can be cancelled out.

[0089] Under light load and heavy load, the value of flow control resistance can be accurately controlled, so that the position of zero point changes with the position of pole, and the stability of LDO transient response is realized under full load. Finally, under the condition of output current 0-250mA, the phase margin is above 45°, the maximum bandwidth is 1.7MHz, and the response time is less than or equal to 7us.

Claims

1. A current steering resistive module based on LDO zero-pole tracking compensation, characterized in that, The operational transconductance amplifier, a PMOS tube PM1 and a PMOS tube PM2 are included; The non-inverting terminal of the operational transconductance amplifier is connected with the drain of the PMOS tube PM1, and the inverting terminal is connected with a first ideal voltage source; the output terminal G1_2 of the operational transconductance amplifier is connected with the gate of the PMOS tube PM1 and the gate of the PMOS tube PM2 simultaneously; The drain of the PMOS transistor PM1 is connected to an ideal current source I sense The source of the PMOS transistor PM1 and the drain of the PMOS transistor PM2 are simultaneously connected to an ideal voltage source VCC; the source S2 of the PMOS transistor PM2 is connected to a capacitor C1, and the other end of the capacitor C1 is connected to a second ideal voltage source.

2. The fluidic resistance module of claim 1, wherein: The positive power pin of the operational transconductance amplifier is connected with a power supply VDD, and the negative power pin is grounded.

3. The fluidic resistance module of claim 1, wherein: The operational transconductance amplifier is a differential amplifier with differential input and single-end output.

4. The fluidic resistance module of claim 1, wherein, The first ideal voltage source is 3.2V, the ideal voltage source VCC is 3.3V, and the second ideal voltage source is 0.88V.

5. The fluidic resistance module of claim 1, wherein: The source-drain voltage of the PMOS tube PM1 and the PMOS tube PM2 is controlled to be less than 100mV, and the PMOS tube PM1 and the PMOS tube PM2 are both in deep linear region.

6. The fluidic resistance module of claim 5, wherein: The equivalent resistance of the PMOS transistor PM1 is R ds1 and satisfies the formula I, and the formula II when the PMOS transistor PM1 is in deep linear region. ， ， The equivalent resistance of the PMOS transistor PM2 is R ds2 and satisfies the equation III, ， ， ， where μ P is the hole mobility, C ox is the gate oxide capacitance, (W / L) PM1 is the width-to-length ratio of PMOS transistor PM1, (W / L) PM2 is the width-to-length ratio of PMOS transistor PM2, V GS is the gate-to-source voltage of PMOS transistor PM1, V th is the threshold voltage; The R ds1 and R ds2 are linearly dependent on 1 / I sense .

7. The fluidic resistance module of claim 6, wherein: The equivalent resistance R of the PMOS tube PM2 ds2 The error rate is ±10% in the temperature range of -40℃ to 125℃. and the equivalent resistance R of the PMOS transistor PM2 ds2 The error rate is ±10% at any process corner of tt or ff or ss or snfp or fnsp.

8. Use of a flow-controlled resistive module according to any one of claims 1 to 7, characterized in that: The flow control resistance module is used for a low-dropout linear voltage regulator.

9. Use of a flow-controlled resistive module according to claim 8, characterized in that: The compensation structure of the low dropout linear regulator is ahuja compensation, and the equivalent resistance R of the PMOS tube PM2 is controlled ds2 The Q value of the control heavy load conjugate pole is reduced to 0.5-0.7, no frequency peak appears, the phase margin is above 45°, the load is stepped from 0 to 250mA, and the response time is less than or equal to 5us.

10. Use of a flow-controlled resistive module according to claim 8, characterized in that: The compensation structure of the low dropout linear regulator is pseudo ESR compensation, and the equivalent resistance R of the PMOS tube PM2 is controlled ds2 The zero point position follows the pole position change, the stability of the LDO transient response is realized under full load, the phase margin is above 45°, the load changes by 0-250mA step, and the response time is less than or equal to 7us.

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