Signal recording method and device, electronic equipment and medium

Abstract

The invention discloses a signal recording method and device, electronic equipment and a medium, and relates to the technical field of computers.The method comprises the steps that first-class signal values corresponding to all signals in a first signal set in a to-be-detected chip at the current moment and second-class signal values corresponding to all signals in the first signal set at the previous moment are obtained; and determining to record all the first-class signal values or all the second-class signal values according to the first-class signal values and the second-class signal values respectively corresponding to all the signals and a pre-configured trigger recording condition. According to the signal detection method and device, the time sequence incidence relation between the signals is established according to the first-class signal value at the current moment and the second-class signal value at the previous moment, dynamic comparison of the signals is achieved, the first-class signal value or the second-class signal value is automatically recorded based on the trigger recording condition, and the signal detection efficiency, flexibility and real-time performance are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a signal recording method, apparatus, electronic device and medium. Background Technology

[0002] In the field of integrated circuit design and verification, with the continuous increase in chip functional complexity, accurate and efficient monitoring and evaluation of the execution efficiency of key functional modules has become a core aspect of optimizing circuit design, troubleshooting hardware faults, and verifying the functional integrity of the system. This process typically requires real-time tracking of the behavioral characteristics of key signals, such as signal trigger frequency, trigger interval, and signal value changes, to quantitatively analyze the operational efficiency of key functions. Currently, signal monitoring relies on the traditional method of waveform data packet capture, data packet to waveform file conversion, and waveform file viewing. However, this method suffers from drawbacks such as low signal detection efficiency and long processing time. Summary of the Invention

[0003] This application provides a signal recording method, apparatus, electronic device, and medium to at least solve the problems of low signal detection efficiency and long detection time.

[0004] This application provides a signal recording method applied to a signal recording device, the method comprising: Obtain the first type of signal values ​​corresponding to all signals in the first signal set of the chip under test at the current time, and the second type of signal values ​​corresponding to each signal at the previous time. Based on the first and second type signal values ​​corresponding to all signals, and the pre-configured trigger recording conditions, determine whether to record all first type signal values ​​or all second type signal values.

[0005] This application also provides a signal recording device, comprising: The acquisition module is used to acquire the first type of signal values ​​corresponding to all signals in the first signal set in the chip under test at the current time, and the second type of signal values ​​corresponding to them at the previous time. The determination module is used to determine whether to record all first-type signal values ​​or all second-type signal values ​​based on the first-type signal values ​​and second-type signal values ​​corresponding to all signals, as well as pre-configured trigger recording conditions.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above signal recording methods.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described signal recording methods.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described signal recording methods.

[0009] This application utilizes the ability to analyze signal values ​​at the current and previous moments to compare signal value changes across different time periods, thereby obtaining the trend and timing relationships of signal changes. By combining this with pre-configured trigger recording conditions, the correlation between signal changes can be recorded more accurately, providing a basis for analyzing the chip's operating status. Furthermore, the pre-configured trigger recording conditions can be flexibly set according to different application scenarios and needs. For example, customized trigger recording conditions can be set based on the chip's specific functions and testing requirements, enabling targeted detection and recording of different types of signals and improving the flexibility of signal detection. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A flowchart illustrating a signal recording method provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the structure between the signal recording device and the Zebu hardware emulator provided in this embodiment of the application; Figure 3 This is a schematic diagram illustrating the application of a signal recording device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a signal recording device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] First, the application scenarios of the embodiments of this application will be introduced by way of example.

[0016] In the process of integrated circuit design and verification, the execution efficiency of the module under test is mainly verified by detecting and statistically analyzing the behavior of key signals. For example, the execution efficiency of the module under test for key functions can be determined by the trigger frequency, trigger interval, and changes in signal values ​​of key signals. This information is particularly important for optimizing circuit design, debugging hardware problems, and verifying system functionality.

[0017] In related technologies, taking the verification process based on the Zebu hardware emulator as an example, it relies on waveform capture and analysis tools, mainly through three core steps: data packet capture, conversion of data packets to waveform files, and finally, using tools such as Verdi for waveform viewing and analysis. However, when facing large-scale circuit designs, this signal detection method exposes many problems: First, the entire detection process is cumbersome. The step of converting data packets to waveform files requires calling specific tools, which not only consumes a lot of computing resources but also takes up a lot of time, seriously affecting verification efficiency. Second, there is a lack of real-time performance. Signal-related data can often only be obtained after the entire testing process is completed, leading to delays in debugging and optimization work and increasing the development cycle. Third, there is a lack of flexibility. Once the hardware design is finalized, the signals monitored in the waveform are difficult to adjust flexibly, failing to adapt to the dynamic needs of focusing on monitoring different signals during the verification process. These limitations make it difficult for traditional methods to meet the requirements of modern integrated circuit design for efficient, real-time, and flexible signal monitoring. Therefore, how to achieve efficient and accurate detection of signals in chips is a current focus.

[0018] In view of this, embodiments of this application provide a signal recording method to solve the problems of cumbersome and inefficient signal detection processes.

[0019] It should be noted that the signal recording method provided in this embodiment of the invention can be executed by a signal recording device. This device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. The electronic device can be a server or a terminal. In this embodiment, the server can be a single server or a server cluster composed of multiple servers. The terminal in this embodiment can be a smartphone, personal computer, tablet computer, wearable device, or other intelligent hardware device such as an intelligent robot. The following method embodiments will use an electronic device as an example for explanation.

[0020] According to an embodiment of the present invention, a signal recording method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0021] Figure 1 This is a flowchart of a signal recording method according to an embodiment of the present invention, which is executed by a signal recording device. Figure 1 As shown, the process includes: S101, respectively acquire the first type of signal value corresponding to all signals in the first signal set in the chip to be detected at the current time, and the second type of signal value corresponding to each signal at the previous time.

[0022] Specifically, the chip under test refers to an integrated circuit chip that needs to undergo functional verification, performance testing, or fault diagnosis, such as a graphics processing unit (GPU) or an application-specific integrated circuit (ASIC).

[0023] The first set of signals refers to the signals generated by the chip under test during operation, including but not limited to control signals, data signals, and clock signals. Examples include register read / write signals within the chip, bus transmission signals (such as the valid and ready signals of the Advanced eXtensible Interface (AXI) bus), and enable signals for inter-module interaction within the chip.

[0024] The first type of signal value refers to the specific numerical value or state of the signal at the current moment, such as high or low level, binary data, decimal data, hexadecimal data, etc. Similarly, the second type of signal value refers to the specific numerical value or state of the signal at the previous moment.

[0025] In this embodiment, by acquiring the first type of signal value and the second type of signal value in real time, there is no need to wait for the waveform file to be converted after the test, thus increasing the real-time performance of the detection and accelerating the detection process. Furthermore, by associating the signal values ​​at the current moment with those at the previous moment, the timing relationship between signals can be captured, such as the sequential logic of control signals and data signals. This helps in analyzing the execution efficiency of the functions of the chip under test, such as data transmission delay.

[0026] S102, based on the first type signal value and the second type signal value corresponding to each signal, and the pre-configured trigger recording conditions, determine to record all first type signal values ​​or all second type signal values.

[0027] Pre-configured trigger recording conditions refer to signal recording conditions preset according to the test objective, used to determine whether specific signal values ​​need to be recorded. For example, recording is triggered when the write enable signal is high at the current moment and the read data signal is not zero at the previous moment. For instance, the trigger recording conditions can be determined based on the test objective of the chip under test. Taking a System-on-Chip (SoC) chip as an example, the write address (awaddr), write address valid signal (awvalid), write address ready signal (aweady), and write response valid signal (bvalid) of the AXI host interface of the central processing unit (CPU) in the chip are used to determine the write transfer efficiency of the host interface accessing a certain address range. Another example is the finite state machine of a functional module in the chip under test, used to determine the order and time consumption of each working stage. The trigger recording conditions can be dynamically configured according to the actual situation. The signal type and signal recording rules of the detection signal can be adjusted without modifying the hardware design, which can flexibly adapt to different test scenarios, such as functional verification scenarios and fault location scenarios.

[0028] In this embodiment, by analyzing the signal value at the current moment and the signal value at the previous moment, the changes in signal values ​​at different times can be compared to obtain the trend and timing relationship of the signal changes. Combined with recording signal values ​​using pre-configured trigger recording conditions, the correlation between changes in signals can be recorded more accurately, providing a basis for analyzing the chip's operating status. Furthermore, the pre-configured trigger recording conditions can be flexibly set according to different application scenarios and needs. For example, customized trigger recording conditions can be set according to the specific functions of the chip and testing requirements, thereby achieving targeted detection and recording of different types of signals and improving the flexibility of signal detection.

[0029] In some embodiments, the signal recording device, a hardware device or module for acquiring, filtering, and recording signals from a chip under test, is typically integrated into an emulator, logic analyzer, or test instrument. For example, it is integrated into a Zebu hardware emulator.

[0030] The signal recording device includes at least one port, which is used to acquire all signals in the corresponding signal set of the chip under test.

[0031] Specifically, in a signal recording device, a port refers to a physical interface or logical channel used to access signals in the chip under test. Each port corresponds to a set of related signals in the chip under test. A port address is the address information used to uniquely identify each port in the signal recording device, and is used to identify and manage different ports within the device.

[0032] Here, a port can also be understood as a detection channel, which receives a signal (trig) from the chip under test.

[0033] The method provided in this application embodiment also includes the following: First, obtain the port address corresponding to the first signal set, as well as the preset configuration information in the signal recording device.

[0034] The preset configuration information includes the port address and trigger record conditions corresponding to at least one port.

[0035] Specifically, the preset configuration information is the configuration data pre-set in the signal recording device. The preset configuration information is used to indicate the trigger conditions for the signal recording device to record information related to the signal set. For example, the configuration information table records "Trigger condition corresponding to port 0 (port address 0x0001): record when the current write enable is 1 and the previous read data is not 0", and "Trigger condition corresponding to port 1 (port address 0x0002): record when the current clock frequency is greater than 1GHz".

[0036] Then, the port whose port address in the preset configuration information matches the port address corresponding to the first signal set is taken as the target port.

[0037] Specifically, the target port refers to the port selected from multiple ports of the signal recording device that matches the port address of the first signal set of the chip under test. For example, the signal recording device compares the port address corresponding to the first signal set with all port addresses in the preset configuration information and selects the port with the matching address as the target port.

[0038] Finally, the trigger record conditions corresponding to the target port are determined as the trigger record conditions corresponding to the first signal set.

[0039] In this way, by associating port addresses with preset configuration information, manual setting of trigger recording conditions is eliminated, reducing operational errors. Multiple ports can work simultaneously, each matching its own trigger recording conditions to record the corresponding signal set. This meets the needs of parallel verification of multiple modules in large-scale chips, improving overall test coverage and making it suitable for complex chip testing scenarios involving multiple modules and signals. Furthermore, different ports correspond to different module signal sets. The preset configuration information can be flexibly modified, allowing the signal recording device to adapt to various chip testing scenarios.

[0040] In some embodiments, based on any of the foregoing embodiments, the triggering recording conditions include a first type of reference value corresponding to all first type of signal values, a second type of reference value corresponding to all second type of signal values, a first matching identifier, and a second matching identifier. The first matching identifier is used to indicate whether all first type of signal values ​​match their respective first type of reference values, and the second matching identifier is used to indicate whether all second type of signal values ​​match their respective second type of reference values.

[0041] Specifically, the first type of reference value refers to the reference value preset for the current moment in the trigger recording conditions, used to determine whether the actual value of the signal at the current moment meets the trigger recording conditions. If the signal is a "write enable signal", the corresponding first type of reference value can be set to the corresponding valid value (such as a high level). Similarly, the second type of reference value refers to the reference value preset for the previous moment in the trigger recording conditions for each signal, used to determine whether the actual value of the signal at the previous moment meets the trigger recording conditions.

[0042] The first matching identifier indicates the result of the judgment (e.g., binary state) regarding whether the signal values ​​of all signals match their respective first-type reference values. "Valid" (e.g., 1) indicates that all signals match their corresponding first-type reference values, while "invalid" (e.g., 0) indicates that at least one signal does not match its corresponding first-type reference value. The second matching identifier indicates the result of the judgment regarding whether the signal values ​​of all signals at the previous time step were equal to their respective second-type reference values. "Valid" indicates that all signals match their corresponding second-type reference values, while "invalid" indicates that at least one signal does not match its corresponding second-type reference value.

[0043] In this way, by setting the first matching identifier, the second matching identifier, and the corresponding reference value for each signal, the trigger recording condition is set. When all signals match the first matching identifier and all signals match the second matching identifier, it is determined that the first signal set meets the trigger recording condition, and only then is the recording of the first type of signal value or the second type of signal value triggered.

[0044] In one possible implementation, s102 specifically includes the following steps: a1, based on the first type of signal value and the first type of reference value corresponding to each signal, determine whether each signal matches the first matching identifier.

[0045] Optionally, in a1 above, based on the first type of signal value and the first type of reference value corresponding to each signal, it is determined whether each signal matches the first matching identifier, specifically including the following steps: b1, according to the preset signal sorting, concatenate the first type of signal values ​​corresponding to all signals in sequence to generate the first signal value sequence.

[0046] Specifically, the preset signal sorting refers to the order in which the signals are ordered, ensuring consistency when comparing signals. For example, the preset signal sorting can be stored in the trigger recording conditions to determine the order of the signals. The preset signal sorting can be set according to actual conditions and is not limited here.

[0047] b2, according to the preset signal sorting, sequentially concatenate the first type of reference values ​​corresponding to all signals to generate the second signal value sequence.

[0048] Similarly, the second signal value sequence obtained by splicing the first type of reference values ​​can refer to the first signal value sequence mentioned above, and will not be repeated here.

[0049] b3, based on the first signal value sequence and the second signal value sequence, determine whether all signals match the first matching identifier.

[0050] In one possible scenario, the first signal value sequence is compared bit by bit or byte by byte with the second signal value sequence. If all bits are consistent, the sequence is considered a match; if at least one bit is inconsistent, the sequence is considered a mismatch.

[0051] In another possible scenario, calculate the corresponding hash value (such as CRC check) for each of the two signal value sequences, and determine whether the two signal value sequences match by comparing whether the hash values ​​are consistent.

[0052] In this way, by transforming the comparison of multiple signals into a holistic comparison of two sequences, the judgment speed of the signal recording device is accelerated, making it suitable for multi-signal scenarios.

[0053] In another possible implementation, for each signal, the current value of the first type of signal is compared with the corresponding first type of reference value to obtain the comparison result for each signal. After obtaining the comparison result for each signal, the comparison results of all signals are counted. If the comparison results of all signals satisfy the first matching identifier, then all signals are determined to match the first matching identifier. Compared with the signal value sequence method, checking each signal one by one is more intuitive and suitable for detection scenarios with a small number of signals and simple logic.

[0054] Optionally, each signal includes multiple bits, and the triggering recording condition also includes the first type of mask bit corresponding to each signal at the current time. Besides the specific implementation in b3 above, determining whether all signals match the first matching identifier can also be achieved in the following way: First, based on the first signal value sequence and the first type of mask bits corresponding to each signal, the masked first signal value sequence is determined.

[0055] Specifically, the first type of mask bit is a binary mask configured for each signal, used to filter out the bits of interest in the signal value. For example, the binary identifier "1" indicates that the bit should be kept, and "0" indicates that the bit should be ignored.

[0056] Then, based on the second signal value sequence and the first type of mask bits corresponding to each signal, the masked second signal value sequence is determined.

[0057] Finally, based on the first signal value sequence after masking and the second signal value sequence after masking, it is determined whether all signals match the first matching identifier at the current moment.

[0058] For example, the first signal set includes signal A, signal B, and signal C. If the first type of mask bits corresponding to signals A, B, and C are 0xFF, 0xF0, and 0x0F respectively, it means that when determining whether signal A matches the first matching identifier, the first signal value corresponding to signal A is compared with all 8 bits of the first type of reference value. When determining whether signal B matches the first matching identifier, only the high 4 bits of the first signal value corresponding to signal B are compared with the high 4 bits of the first type of reference value. When determining whether signal C matches the first matching identifier, only the low 4 bits of the first signal value corresponding to signal C are compared with the low 4 bits of the first type of reference value. When the first signal value corresponding to signal A is equal to all 8 bits in the first type of reference value, and the high 4 bits in the first signal value corresponding to signal B are equal to the values ​​corresponding to the high 4 bits in the first type of reference value, and the first signal value corresponding to signal C is equal to the values ​​corresponding to the low 4 bits in the first type of reference value, it is determined that all signals match the first matching identifier at the current time; otherwise, it is determined that all signals do not match the first matching identifier at the current time.

[0059] In this way, by filtering the signals using mask bits to select the bits of interest, such as only detecting the high 4 bits of voltage stability while ignoring irrelevant bits, such as noise fluctuations in the low 4 bits, invalid data can be avoided from interfering with the judgment results. For example, in the process of logic chip testing, this can be used to verify key timing-related bits, improving judgment accuracy and reducing computational resource consumption. Furthermore, by configuring independent mask bits for each signal, each signal can be processed specifically, flexibly adapting to the detection needs of different signals.

[0060] a2, based on the second type of signal value and the second type of reference value corresponding to each signal, determine whether each signal matches the second matching identifier.

[0061] Determining whether all signals match the second matching identifier is similar to determining whether signals match the first matching identifier; you can refer to the specific implementation of this method, which will not be elaborated here.

[0062] a3, when all signals match the first matching identifier and all signals match the second matching identifier, it is determined that the first signal set satisfies the trigger recording condition.

[0063] For example, in a signal recording device, by setting up a logical AND gate or setting up a software script for AND operation, the device can make a combined judgment on whether the signals match the first matching identifier and the second matching identifier respectively. If all signals match the first matching identifier and all signals match the second matching identifier, a recording signal that meets the triggering recording condition is output. This recording signal triggers subsequent recording operations, such as recording the first type of signal value or the second type of signal value. If the signal does not match the corresponding identifier, the signal recording device is not triggered to perform a recording operation.

[0064] a4, based on the first matching identifier and the second matching identifier in the trigger recording condition, determine to record all first-type signal values ​​or all second-type signal values.

[0065] In this way, by comparing each signal individually to determine whether to trigger the signal recording device to record, the recorded data is ensured to be strongly correlated with the target event (such as "normal data transmission completed" or "before the abnormal operation occurs"), thus reducing interference from invalid data.

[0066] In one possible implementation, based on any of the foregoing embodiments, the recording of all first-type signal values ​​or all second-type signal values ​​is determined according to the first matching identifier and the second matching identifier in the trigger recording condition, specifically including the following: When the first matching identifier indicates that at least one signal corresponds to a first type of signal value and a first reference value that do not match, and the second matching identifier indicates that all signals correspond to second type of signal values ​​that match second type of reference values, then all second type of signal values ​​are determined to be recorded.

[0067] Specifically, when the first matching identifier indicates that at least one signal value does not match the corresponding first type of reference value, and the second matching identifier indicates that all signal values ​​match the corresponding second type of reference value, it can be understood that the signal is abnormal or changed at the current moment, while the signal was normal at the previous moment, i.e., the "old value leaves" scenario, indicating that the chip under test has transitioned from the normal state at the previous moment to the abnormal or changed state at the current moment.

[0068] For example, the "old value departure" scenario can be used to capture the last normal state before an anomaly occurs, enabling fault location of the chip under test. An abnormal state often evolves gradually from the normal state of the previous moment, and the "old value" (the normal signal of the previous moment) may contain key information that led to the current anomaly (such as parameter settings, configuration status, etc.). Recording the old value can establish a causal relationship of "normal → abnormal", avoiding the situation of only observing the current anomaly while ignoring the preceding conditions.

[0069] In one possible implementation, based on any of the foregoing embodiments, determining to record all first-type signal values ​​or all second-type signal values ​​according to the first matching identifier and the second matching identifier in the trigger recording condition includes: When the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all signals match respectively, and the second matching identifier indicates that at least one signal corresponds to a second type of signal value that does not match the second type of reference value, or, When the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all signals match, and the second matching identifier indicates that the second type of signal value and the second type of reference value corresponding to all signals match, or, When the first matching identifier indicates that at least one signal corresponds to a first type of signal value and a first reference value that do not match, and the second matching identifier indicates that at least one signal corresponds to a second type of signal value that does not match a second type of reference value, Record all Type I signal values.

[0070] Specifically, when the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all signals are matched, and the second matching identifier indicates that the second type of signal value corresponding to at least one signal does not match the second type of reference value, it can be understood as the "new value arrives" scenario. The current signal values ​​all meet the corresponding reference values ​​(the first matching identifier is "all equal"), that is, the chip to be detected enters the expected "new state".

[0071] For example, the "new value arrives" scenario can be the initialization of the chip under test, such as when the configuration signal value reaches a reference value after the chip is powered on. The "new value arrives" scenario can also be a state transition during the normal operation of the chip under test, such as transitioning from an idle state to a data transmission state, where the data transmission enable signal at the current moment meets a preset signal value. The "new value arrives" scenario can also be the chip under test returning to a normal state after an anomaly, for example, when the signal value was abnormal at a previous moment and has now returned to normal.

[0072] In this implementation, by recording the first type of signal value corresponding to the "new value arrives" scenario, it can be used to verify whether the chip enters the target state as expected, and at the same time, it can provide benchmark information for subsequent state changes.

[0073] Specifically, when the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all signals are matched, and the second matching identifier indicates that the second type of signal value and the second type of reference value corresponding to all signals are matched, it can be understood as a "specific value change" scenario, that is, the signal has completed a specific correct value change.

[0074] For example, the "specific value change" scenario can be a time-sequential state switch, such as a signal value that was in preparation at the previous moment being converted to a signal value that is ready at the current moment. The "specific value change" scenario can also be a chip fault automatic repair scenario, such as a signal value that was used to indicate a verification error at the previous moment, and a signal value that was used to indicate that the verification was successful at the current moment, thus completing the fault repair.

[0075] Specifically, when the first matching identifier indicates that at least one signal corresponds to a first type of signal value that does not match the first reference value, and the second matching identifier indicates that at least one signal corresponds to a second type of signal value that does not match the second reference value, it can be understood that the chip under test is in an "arbitrary change tracking" scenario, indicating that the chip under test is in a continuous abnormal state, and the current value has changed arbitrarily relative to the abnormal value at the previous moment.

[0076] For example, the "arbitrary change tracking" scenario can be a fault propagation scenario (such as a bus error in the previous moment, and an address error in the current moment, neither of which meets the corresponding reference value), an unstable state fluctuation scenario (such as the clock signal frequency in the chip under test being too low in the previous moment, and the current frequency deviating further from the corresponding reference value), or a failure to repair errors in the chip under test (such as attempting to correct the data error in the previous moment, but the current data still does not meet the corresponding reference value).

[0077] In this implementation, three scenarios are covered: "new value arrival," "specific value change," and "arbitrary change tracking," ensuring that any scenario triggering the recording condition can be recorded, providing a comprehensive inspection of the chip under test. Simultaneously, by recording the current first-type signal value and combining it with the previous state (such as the second matching identifier), a cause-and-effect temporal relationship is established, facilitating the tracing of the logical chain of signal changes in the chip under test. Furthermore, the three scenarios enable problem localization of the chip under test: the "new value arrival" scenario verifies the correctness of the chip's function; the "specific value change" scenario verifies the effectiveness of the chip's repair function; and the "arbitrary change tracking" scenario captures the fault propagation path, significantly shortening the debugging cycle.

[0078] In one possible implementation, the previous moment is the trigger moment when the signal value corresponding to the first preset signal in the chip to be detected is converted into the corresponding reference value. The first preset signal is a signal other than the signals in the first signal set. The first signal is a response signal of the first preset signal, wherein the first signal is any signal in the first signal set.

[0079] Specifically, the first preset signal is not a signal in the first signal set, but serves as a trigger signal in the chip under test to induce signals in the first signal set. Taking the detection of access to a certain address range as an example, the first preset signal can be the address range selection signal received by the chip under test. The first signal set includes signals related to write transfer efficiency, such as write instruction enable signals (used to indicate whether to start write transfer), etc.

[0080] The first preset signal can be a signal that is pre-indicated in the trigger recording conditions, and the first preset signal associated with the signal is recorded in the trigger recording conditions.

[0081] The method provided in this application embodiment also includes the following: First, obtain the reference value of the first preset signal at the previous moment.

[0082] Then, the reference value of the first preset signal at the previous moment is determined as the first type of reference value corresponding to the first signal.

[0083] In this implementation, the first type of reference value of the first signal is automatically determined by the reference value of the first preset signal, avoiding errors from manual settings and adapting to dynamic changes in signal logic. For example, when the reference value of the first preset signal changes in different scenarios, the first type of reference value of the first signal can be automatically synchronized with the first preset signal. Furthermore, a causal relationship is established between the first preset signal and the first signal, so that when an anomaly occurs in the first signal, the state of the first preset signal can be quickly traced back, enabling rapid fault location.

[0084] In some embodiments, based on any of the foregoing embodiments, the method provided in this application further includes the following: b1, When the first signal set meets the trigger recording condition, count the number of times the first signal set meets the trigger recording condition within a preset historical time period based on the current time.

[0085] Specifically, the preset instance time period serves as the time window for limiting the technology and can be set according to the actual situation, such as the number of triggers in the 10 minutes before the current moment.

[0086] Optionally, the signal recording device includes at least one counter; the preset configuration information also includes at least one counter identifier corresponding to each port. When the first signal set meets the trigger recording condition, the number of times the first signal set meets the trigger recording condition within a preset historical time period is counted, based on the current time. Specifically, this includes the following steps: First, based on the counter identifier corresponding to the target port, determine the target counter corresponding to the first signal set from at least one counter.

[0087] The target counter is used to perform an accumulation counting operation when the first set of signals meets the trigger recording condition within a preset historical time period.

[0088] Then, the count value in the target counter is used as the number of times.

[0089] Specifically, the counters in the signal recording device are distinguished by counter identifiers. For example, the counter identifier can be the counter name, register address, etc.

[0090] b2, based on the number of times, generates the record information for the first signal set.

[0091] Specifically, the recording information of the first signal set includes the count value in the target counter. Furthermore, the recording information also includes the first type of signal value corresponding to each of the signals determined in S102 above, or the second type of signal value corresponding to each of the signals.

[0092] In this way, based on the counter identifier corresponding to the target port, it is ensured that each port has an independent counter for its corresponding signal set, avoiding interference between the trigger times of different ports and making the counting results more accurate.

[0093] In one possible implementation, the signal recording device includes at least one clock; the preset configuration information also includes at least one clock identifier corresponding to each port; the method provided in this application embodiment further includes the following: First, based on the clock identifier corresponding to the target port, determine the target clock corresponding to the first signal set from at least one clock.

[0094] Then, when the first set of signals meets the trigger recording condition, the timestamp corresponding to the first set of signals is recorded by the target clock.

[0095] In one possible implementation, the recorded information also includes the signal value corresponding to the second preset signal at the current moment, wherein the second preset signal is a signal in the chip to be detected other than the signals in the first signal set, and the second signal is the trigger signal of the second preset signal, wherein the second signal is any signal in the first signal set.

[0096] Specifically, changes in the state of the second signal (such as high / low level, pulse transitions, etc.) trigger changes in the state of the second preset signal, establishing a causal triggering relationship between the two signals. For example, the chip under test includes a transmit enable signal to control the activation or deactivation of the data transmission function. The second preset signal is a transmit bandwidth signal used to determine the bandwidth used for data transmission. The transmit enable signal acts as the trigger signal for the second preset signal. When the transmit enable signal changes from 0 to 1, i.e., the data transmission function changes from deactivated to activated, it triggers the second preset signal to change from 1Gbps to 10Gbps. In this case, the recorded information also includes the signal value of the second preset signal at the current moment, i.e., 10Gbps.

[0097] Since the second preset signal has a triggering relationship with the second signal, recording the signal value of the second preset signal at the current moment can supplement the correlation information between the signals, which helps to trace the entire process of signal changes in the chip under test. Recording the signal value of the second preset signal can verify whether the triggering logic in the chip under test is normal (e.g., whether the transmission bandwidth signal changes as expected after the transmit enable signal is activated), thereby improving the comprehensiveness of chip function verification. In addition, when the second signal is abnormal, the signal value of the second preset signal can also provide additional information for anomaly analysis. Continuing with the example of the second preset signal as the response signal to the transmit enable signal, the signal value of the second preset signal at the current moment can be used to determine whether the data transmission anomaly is related to the signal value corresponding to the second preset signal.

[0098] In some embodiments, based on any of the foregoing embodiments, the method provided in this application further includes the following: First, the preset configuration information is modified to obtain the modified configuration information.

[0099] Then, based on the modified configuration information, the trigger record conditions corresponding to the first signal set are adjusted.

[0100] Optionally, continuing with the signal recording device as a submodule in Zebu as an example, the submodule includes three preset ports, used to acquire the trigger recording conditions, the corresponding port information (such as port addresses), and the recording content (such as the first or second type of signal value, or the count value in the counter) from the preset configuration information. The trigger recording conditions, port information, and recording content are controlled by entering relevant ToolCommand Language Instruction (Tcl) commands through an interactive command line. For example, the configuration toggle (cfg_toggle) port, configuration address (cfg_addr) port, and configuration data input (cfg_datain) port in the submodule are used to configure the trigger recording condition behavior, port address, and recording content, respectively. When compiling the Zebu project, a force function is added to these three ports. When running the Zebu project, these three ports can be controlled to transmit the preset configuration information within the submodule.

[0101] In this way, considering that the working scenario of the chip under test may change with the application requirements, the trigger recording conditions can be adjusted by modifying the configuration information, such as dynamically adding or deleting signals or reference values ​​in the trigger recording conditions, so that the information recording device can quickly adapt to new test scenarios and improve the flexibility of signal recording.

[0102] In some embodiments, the method provided in this application further includes the following: c1 acquires the functional information, trigger information, and dependency information between multiple signals in the chip under test.

[0103] Specifically, the multiple signals in the chip under test refer to electrical or logical signals used for data transmission, control logic, or status indication; they are the basic units for chip function implementation. Examples include clock signals, data read / write signals, and address signals.

[0104] Functional information describes the specific function or role a signal plays within a chip. For example, a write enable signal is used to indicate an enable operation for writing data. Exemplarily, the functional information of each signal can be analyzed from the hardware description code, design document, or datasheet of the chip under test to determine its purpose.

[0105] Trigger information describes the conditions under which a signal is activated (e.g., a level transition or numerical change). Taking a chip under test that includes signals indicating whether a write command is valid (awvalid) and whether the receiver has acknowledged receiving the write command (awready) as an example, when the receiver detects awvalid is high (i.e., the write command is valid) and is ready to receive the command (e.g., internal registers are free), awready is triggered to a high level. For example, the conditions and timing for each signal to be triggered are determined through logical expressions (e.g., "tx_start=data_valid&addr_ready") or timing constraints (e.g., "addr is latched on the rising edge of clk") in the hardware description of the chip under test.

[0106] The dependency relationship between signals refers to the causal or temporal correlation between signals, which reflects the interaction logic between signals. For example, signal A causes a change in signal B. For instance, code morphology analysis tools can be used to identify the causal relationship between various signals, such as signal A being the input to signal B, and signal B fluctuating after a change in signal A, thereby obtaining the dependency relationship between the signals.

[0107] c2, based on the functional information and trigger information corresponding to each signal, as well as the dependency information between the signals, groups the signals to obtain multiple signal sets in the chip to be tested.

[0108] In one possible implementation, the signals are grouped according to their respective functional and triggering information, as well as the dependency information between them, to obtain multiple signal sets in the chip under test. This includes the following steps: First, based on the functional information corresponding to each signal, the signals are grouped to obtain at least one candidate set.

[0109] For example, based on the functional information corresponding to each signal, signals with a similarity to the functional information exceeding a preset threshold are grouped together to form a candidate set. For instance, if the signals in the chip to be tested include: write address signal (awaddr), write command valid signal (awvalid), write data signal (wdata), write completion feedback signal (bvalid), read address signal (rdaddr), and read data signal (rdata), then the signals "awaddr, awvalid, wdata, bvalid" related to the write operation are grouped together to obtain the candidate set related to the write operation, and the signals "rdaddr, rdata" related to the read operation are grouped together to obtain the candidate set related to the read operation.

[0110] Then, based on the triggering information corresponding to each signal in the first candidate set, the signals in the first candidate set are grouped to obtain at least one candidate subset corresponding to the first candidate set.

[0111] The first candidate set is any one of at least one candidate set.

[0112] For example, based on the trigger information corresponding to each signal, signals sharing the same pre-signal or timing characteristics are grouped into a candidate subset. For instance, taking signals related to write operations as the candidate subset, assume that the trigger information for awaddr is "effective when the sender prepares the address". The trigger information for awvalid is "awvalid is high when awaddr is valid". The trigger information for wdata is "effective one clock cycle after awvalid is high". The trigger information for bvalid is "effective after the receiver completes the write operation". awaddr, awvalid, and wdata share the trigger timing of the "write command initiation phase", therefore awaddr, awvalid, and wdata are grouped into a candidate subset. bvalid belongs to the trigger timing of the "write operation completion phase", therefore bvalid is grouped into a candidate subset.

[0113] Finally, based on the dependency information between the signals in the first candidate subset, the signals in the first candidate subset are grouped to obtain at least one signal set corresponding to the first candidate subset.

[0114] The first candidate subset is any one of at least one candidate subset.

[0115] Optionally, signals with dependencies in the first candidate subset can be used to form a signal set corresponding to the first candidate subset.

[0116] Taking the candidate subset including awaddr, awvalid, and wdata as an example, the dependencies between the signals in the candidate subset are as follows: awvalid depends on awaddr (if awaddr is invalid, awvalid cannot be set high); wdata depends on awvalid (if awvalid is not set high, wdata will not take effect). awaddr, awvalid, and wdata form a complete data chain from the initiation of the write command to the data transmission. Therefore, awaddr, awvalid, and wdata are considered as a set of signals.

[0117] For example, a signal is randomly selected from the first candidate subset as the starting signal. All subsequent signals that depend on this signal are searched. Then, the dependencies of the subsequent signals are recursively traced until there are no new dependent signals. Then, the preceding signals that the starting signal depends on are searched. The dependencies of the preceding signals are recursively traced. When there are no new preceding signals, a signal set is formed.

[0118] In this embodiment, by grouping the signals in the chip under test according to functional information, trigger information, and dependency information, key signals are avoided during signal detection, making the signal logic in the chip clearer. For example, the data transmission set can intuitively reflect the complete signal chain of chip read and write operations. Furthermore, the signal set is a prerequisite for setting trigger recording conditions. Grouping ensures that the trigger recording conditions cover all related signals, avoiding inaccurate signal detection and analysis due to isolated signals.

[0119] In another possible implementation, the signals are grouped according to their respective functional and triggering information, as well as the dependency information between them, to obtain multiple signal sets in the chip under test. This includes the following steps: First, based on the functional information corresponding to each signal, the first semantic similarity between each pair of signals is determined.

[0120] Then, based on the trigger information corresponding to each signal, the second semantic similarity between each pair of signals is determined.

[0121] Next, based on the dependency information corresponding to each signal, the third semantic similarity between each pair of signals is determined.

[0122] Finally, based on the first semantic similarity, second semantic similarity, and third semantic similarity between each pair of signals, the signals are divided to obtain multiple signal sets.

[0123] For example, for a pair of signals, the first semantic similarity, the second semantic similarity, and the third semantic similarity are weighted and summed to obtain the comprehensive similarity of the pair of signals. Signals with a comprehensive similarity greater than a preset threshold are grouped into one group, thereby obtaining multiple signal sets.

[0124] The signal recording device can be used for circuit performance monitoring and statistics in Zebu and Electronic Design Automation Simulation (EDA). In the following embodiments, Zebu will be used as an example for illustrative purposes.

[0125] Figure 2 This is a schematic diagram showing the structure between the signal recording device and the Zebu hardware emulator. Figure 2 In this system, the signal recording device is a submodule of the Zebu hardware emulator. The Zebu hardware emulator acquires the hardware design program corresponding to the chip under test, automatically compiles the hardware design program into hardware units, and tests the chip under test based on test cases. During the test, the signal recording device records key signal values ​​(such as first-type signal values ​​and second-type signal values) and their related information (total number of triggers), generating a log. The recording operation relies on functions supported by Zebu that are allowed in hardware code, such as $fdisplay, $fwrite, $fopen, and $fclose.

[0126] The preset configuration information in the signal recording device can be determined by the tester based on the test objectives of the chip under test. The tester can determine the configuration table according to the performance testing requirements, and then convert the configuration table into a configuration data stream that the signal recording device can recognize, thereby enabling the signal recording device to generate the preset configuration information.

[0127] For example, the configuration table is shown in Table 1.

[0128] Table 1

[0129] In Table 1, the "Signals" column lists the signals that need to be monitored in the chip under test. To better organize and utilize the monitoring logic for numerous signals, each signal can be implemented in multiple instances. The number here is the instance number where the current row of signals is located after organization.

[0130] As shown in Table 1, the signals top.dut.cpu.awaddr, top.dut.cpu.awid, top.dut.cpu.awvalid, and top.dut.cpu.awready belong to the signal set cpu-aw. The signals top.dut.cpu.bid, top.dut.cpu.bvalid, and top.dut.cpu.bready belong to the signal set cpu-b. The signals top.dut.uart.cur_state and top.dut.dma.core.cur_state belong to the signal set state1. The signal top.dut.cpu.dbg_state belongs to the signal set state0. Bit width refers to the number of bits in a signal. The most significant bit (MSB) refers to the position of the most significant bit in the signal value sequence when all the signal values / reference values ​​are concatenated sequentially. The least significant bit (LSB) refers to the position of the least significant bit in the signal value sequence when all the signal values / reference values ​​corresponding to each signal are concatenated sequentially. During signal recording, in addition to recording the first type of signal value, the second type of signal value, and the number of times, the recording device also records a timestamp. The clock flags corresponding to signal sets cpu-a and cpu-b are both 0, while the clock flags corresponding to signal sets state1 and state0 are both 1. That is, signal sets cpu-a and cpu-b use a clock flag of 0 for timestamp recording, while signal sets state1 and state0 use a clock flag of 1 for timestamp recording.

[0131] In Table 1, the trigger record type is raise, which is the "new value arrives" scenario; the trigger record type is shift, which is the "specific value changes" scenario; and the trigger record type is trace, which is the "arbitrary change tracking" scenario.

[0132] Based on the above configuration table, the port of the signal recording device is connected to the hardware unit corresponding to the chip under test. The connection relationship can be represented as follows: ".trig0( / / cpu-aw top.dut.cpu.awaddr, / / [73:10] top.dut.cpu.awid, / / [9:2] top.dut.cpu.awvalid, / / [1:1] top.dut.cpu.awready / / [0:0] ), .trig1( / / cpu-b top.dut.cpu.bid, / / [9:2] top.dut.cpu.bvalid, / / [1:1] top.dut.cpu.bready / / [0:0] ), trig2( / / state1 top.dut.uart.cur_state, / / [7:4] top.dut.dma.core.cur_state / / [3:0] ), trig3( / / stateθ top.dut.cpu.dbg_state / / [5:0] )".

[0133] Based on the above configuration table, the testers converted it into a format that the signal recording device could recognize, resulting in the configuration data stream shown in Table 2.

[0134] Table 2

[0135] A signal recording device may contain multiple monitoring channels, each requiring its own configuration information. In this embodiment, this configuration information is organized into a unified format, referred to as a configuration data stream, as shown in the table above. Each monitoring channel's configuration segment consists of TW_MAX*4 bits, where TW_MAX is the maximum value of all port widths. The explanations of each part of the configuration data stream are as follows.

[0136] targ_value_old corresponds to the second type of benchmark value in the configuration table. In this embodiment, the various second type of benchmark values ​​can be concatenated to obtain a signal value sequence.

[0137] targ_value_new corresponds to the first type of baseline value in the configuration table.

[0138] targ_igno_old or last_trig_sel corresponds to the second type of mask bit in the configuration table.

[0139] targ_igno_new corresponds to the first type of mask bit in the configuration table.

[0140] timer_rcd(timer record) controls message recording, determining whether to print timestamps to the log, i.e., whether to record timestamps.

[0141] payld_rcd (payload record) controls information recording and determines whether to print the payload data (i.e., the signal value corresponding to the second preset signal at the current moment) attached to the channel to the log.

[0142] trig_rcd (trigger record) controls information logging, determining whether to print the first or second type of signal value to the log when triggered.

[0143] chng_trc (change trace), or change trace, is a trigger record type control that indicates the trigger record type for this channel when it is working in trace mode.

[0144] timer_sel (timer selection) determines the timer number to use when printing timestamps.

[0145] crs_targ (cross target) is a special trigger record type control, indicating that the first type of reference value of this channel comes from the reference value of the first preset signal of the record of the previous channel at the previous moment.

[0146] Each line of the above configuration data stream is accompanied by a valid bit in its main data portion. Depending on the combination of valid values ​​accompanying `targ_value_new` and `targ_value_old`, the channel will exhibit different trigger record types. Specifically: targ_value_new valid, targ_value_old invalid, the trigger record type is raise; `targ_value_new invalid`, `targ_value_old valid`, triggering the record type as `drop`; targ_value_new valid, targ_value_old valid, the trigger record type is shift; If `targ_value_new` is invalid or `targ_value_old` is invalid, the record will be closed. targ_value_new invalid, targ_value_old invalid, chng_trc valid, triggering a record type of trace.

[0147] The information recording device uses an array to store the configuration segments of all channels.

[0148] The monitoring path has three inputs: a port for constantly monitoring and triggering event logging; a configuration section for comparison and control; and a data input port for additional printing to the log file, specifically for obtaining the signal value of the second preset signal at the current moment. The monitoring path compares the first type of signal value with the configured first type of reference value at each clock cycle, and compares the registered second type of signal value from the previous cycle with the configured second type of reference value. Depending on whether these two parts are equal, different trigger logging types may be met. The first type of signal value is equal to the first type of reference value, while the second type of signal value is not equal to the second type of reference value. At this time, the raise condition is met, that is, the signal value reaches the target value for the first time. If this channel is configured to raise, the event log will be triggered. The first type of signal value is not equal to the first type of reference value, while the second type of signal value is equal to the second type of reference value. At this time, the drop condition is met, that is, the signal value leaves the target value. If this channel is configured to drop, the event log will be triggered. The first type of signal value is equal to the first type of reference value, and the second type of signal value is also equal to the second type of reference value. At this time, the shift condition is hit, that is, the signal value has changed to a specific value. If this channel is configured to shift, the event logging can be triggered. If the first type of signal value is not equal to the first type of reference value, and the second type of signal value is not equal to the second type of reference value, then the trace condition is met, that is, the signal value has changed by any value. If this channel is configured to trace, the event recording will be triggered.

[0149] When comparing signal values ​​with corresponding reference values, both will be filtered by the mask bits in the configuration segment.

[0150] Generally, if the valid bit accompanying targ_igno_new is high (i.e., the mask bit is high), the signal value will be bit-flipped and then bitwise ANDed with the value of targ_value_new. The resulting bitwise ANDed data will then be compared.

[0151] In another scenario, the first reference value for a channel should be derived from the reference value (also the signal value) of a preset signal recorded by another channel at the previous moment. For example, to test the response speed of an AXI write transaction, it's necessary to wait for the specific ID to be returned as a BID in another channel after an AXI write command for a specific AWID is issued in one trigger channel. This feature is called cross-target in zsigmon. If the crs_targ control bit in the configuration section is valid, the portion of targ_value_new ultimately used for that monitoring channel that is selected by last_trig_sel will be replaced by the corresponding portion of the reference value (also the signal value) recorded by the previous monitoring channel. This allows a portion of the bit field of one signal to be used as the trigger target for another signal, enabling complex signal correlation monitoring and supporting more complex verification scenarios.

[0152] Because Zebu supports adding system functions such as $fdisplay, $fwrite, $fopen, and $fclose to a project and these functions take effect when the Zebu project is running, logs can be output to text files in a timely manner.

[0153] Each record is a line in the Log file, and it mainly consists of three parts: <TRIGN_M=0xVALUE> This indicates that the Mth event has occurred on channel N, and the trigger value (signal value) is 0xVALUE. Whether the =0xVALUE part of this field is printed or not is controlled by trigger_rcd. <TIMEN_M=TIMESTAMP@CLKA> This indicates the time when the Mth event occurs on channel N. The timer value is TIMESTAMP driven by clock A. Whether this field is printed or not is controlled by the timer_rcd enable function.

[0154] <PAYLOADN_M=0xVALUE> This indicates that when the Mth event occurs on channel N, the payload port value of that channel is 0xVALUE. Whether this field is printed or not is controlled by the payld_rcd enable function.

[0155] After different conditions are met, the signal values ​​printed to the Log file will vary depending on the relevant control bits in the configuration section. After triggering `raise`, if `trig_rcd` is enabled, the first type of signal value will be printed; after triggering `drop`, if `trig_rcd` is enabled, the second type of signal value will be printed; after triggering `shift`, if `trig_rcd` is enabled, the first type of signal value will be printed; after triggering `trace`, if `trig_rcd` is enabled, the first type of signal value will be printed.

[0156] Figure 3This is a schematic diagram illustrating the application of a signal recording device. Figure 3 In this process, the signal recording device receives a first type of signal value and a second type of signal value, compares the first type of signal value with a first type of reference value, and compares the second type of signal value with the second type of reference value. When the comparison result meets the trigger recording condition, if the counting function is enabled, a counter is used to count the number of signals that meet the trigger recording condition; if the function to record a preset signal value (i.e., the signal value corresponding to the second preset signal at the current time) is enabled, the preset signal value is recorded; if the timestamp function is enabled, a clock corresponding to the signal set is selected to obtain the timestamp of the current time. Thus, a log is generated based on the count value in the counter, the preset signal value, the timestamp, etc.

[0157] In this embodiment, firstly, signal monitoring is achieved through a hardware module, avoiding the cumbersome process of traditional waveform capture and analysis tools, significantly reducing monitoring time and improving verification efficiency. Secondly, it can record relevant information instantly when a signal is triggered, facilitating real-time monitoring and debugging by engineers, and enabling timely identification and resolution of problems. Thirdly, monitoring conditions can be dynamically adjusted during simulation runtime, flexibly adapting to different testing requirements without recompiling or modifying the hardware design. The signal recording device records detailed log information, including but not limited to the number of times the trigger recording conditions are met, timestamps, and corresponding data (such as first-type signal values ​​and second-type signal values), facilitating subsequent analysis and optimization, and providing strong support for circuit design improvements. Fourthly, it is applicable to various signal monitoring scenarios, including the arrival of new values, the departure of old values, changes in specific values, and tracking of arbitrary changes, meeting different design and verification requirements.

[0158] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0159] This application also provides a signal recording device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0160] This embodiment provides a signal recording device, such as... Figure 4 As shown, it includes: The acquisition module 401 is used to acquire the first type of signal values ​​corresponding to all signals in the first signal set in the chip under test at the current time, and the second type of signal values ​​corresponding to them at the previous time. The determining module 402 is used to determine whether to record all first-type signal values ​​or all second-type signal values ​​based on the first-type signal values ​​and second-type signal values ​​corresponding to all signals, as well as pre-configured trigger recording conditions.

[0161] In one possible implementation, the signal recording device includes at least one port, which is used to acquire all signals in the signal set corresponding to the chip under test; the acquisition module 401 is also used to acquire the port address corresponding to the first signal set, as well as the preset configuration information in the signal recording device, wherein the preset configuration information includes the port address and trigger recording conditions corresponding to at least one port respectively. The port whose port address in the preset configuration information matches the port address corresponding to the first signal set is taken as the target port; The trigger record conditions corresponding to the target port are determined as the trigger record conditions corresponding to the first signal set.

[0162] In one possible implementation, the trigger recording conditions include a first reference value corresponding to all first type signal values, a second reference value corresponding to all second type signal values, a first matching identifier, and a second matching identifier. The first matching identifier is used to indicate whether all first type signal values ​​match their respective first type reference values, and the second matching identifier is used to indicate whether all second type signal values ​​match their respective second type reference values.

[0163] In one possible implementation, the determining module 402 is specifically used to determine whether all signals match the first matching identifier based on the first type of signal value and the first type of reference value corresponding to all signals respectively. Based on the second type of signal value and the second type of reference value corresponding to each signal, determine whether each signal matches the second matching identifier. When all signals match the first matching identifier and all signals match the second matching identifier, it is determined that the first signal set satisfies the trigger recording condition. Based on the first and second matching identifiers in the trigger recording conditions, determine whether to record all first-type signal values ​​or all second-type signal values.

[0164] In one possible implementation, the determining module 402 is specifically used to sort all signals according to a preset signal order, and then sequentially concatenate the first type of signal values ​​corresponding to all signals to generate a first signal value sequence. According to the preset signal sorting, the first type of reference values ​​corresponding to all signals are sequentially concatenated to generate the second signal value sequence; Based on the first signal value sequence and the second signal value sequence, determine whether all signals match the first matching identifier.

[0165] In one possible implementation, each signal includes multiple bits, and the triggering recording condition also includes the first type of mask bit corresponding to each signal at the current time; the device also includes a judgment module for determining the masked first signal value sequence based on the first signal value sequence and the first type of mask bit corresponding to each signal. Based on the second signal value sequence and the first type of mask bits corresponding to each signal, determine the masked second signal value sequence; Based on the first signal value sequence after masking and the second signal value sequence after masking, determine whether all signals match the first matching identifier at the current time.

[0166] In one possible implementation, the determining module 402 is specifically used to determine and record all second-type signal values ​​when the first matching identifier indicates that there is a mismatch between the first type signal value and the first reference value corresponding to at least one signal, and the second matching identifier indicates that the second type signal values ​​corresponding to all signals match the second type reference value.

[0167] In one possible implementation, the determining module 402 is specifically configured to determine the match when the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all signals match, and the second matching identifier indicates that at least one signal corresponds to a second type of signal value that does not match the second type of reference value. or, When the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all signals match, and the second matching identifier indicates that the second type of signal value and the second type of reference value corresponding to all signals match, or, When the first matching identifier indicates that at least one signal corresponds to a first type of signal value and a first reference value that do not match, and the second matching identifier indicates that at least one signal corresponds to a second type of signal value that does not match a second type of reference value, Record all Type I signal values.

[0168] In one possible implementation, the previous moment is the trigger moment when the signal value corresponding to the first preset signal in the chip under test is converted into a corresponding reference value. The first preset signal is a signal other than the signals in the first signal set. The first signal is a response signal of the first preset signal, wherein the first signal is any signal in the first signal set. The device further includes: acquiring the reference value of the first preset signal at the previous moment. The reference value of the first preset signal at the previous moment is determined as the first type of reference value corresponding to the first signal.

[0169] In one possible implementation, the device further includes a statistics module, which is used to count the number of times the first signal set meets the trigger recording condition within a preset historical time period based on the current time when the first signal set meets the trigger recording condition. Based on the number of occurrences, generate the record information for the first signal set.

[0170] In one possible implementation, the signal recording device includes at least one clock; the preset configuration information also includes at least one clock identifier corresponding to each port; the device is further configured to determine a target clock corresponding to the first signal set from at least one clock based on the clock identifier corresponding to the target port. When the first set of signals meets the trigger recording condition, the timestamp corresponding to the first set of signals is recorded by the target clock.

[0171] In one possible implementation, the recorded information also includes the signal value corresponding to the second preset signal at the current moment, wherein the second preset signal is a signal in the chip to be detected other than the signals in the first signal set, and the second signal is the trigger signal of the second preset signal, wherein the second signal is any signal in the first signal set.

[0172] In one possible implementation, the device further includes a modification module for modifying preset configuration information to obtain modified configuration information; Adjust the trigger record conditions corresponding to the first signal set based on the modified configuration information.

[0173] In one possible implementation, the acquisition module 401 is further used to acquire the functional information, trigger information, and dependency information between the signals corresponding to the multiple signals in the chip under test. Based on the functional and triggering information corresponding to each signal, as well as the dependency information between signals, the signals are grouped to obtain multiple signal sets in the chip under test.

[0174] In one possible implementation, the acquisition module 401 is specifically used to group the signals according to the functional information corresponding to each signal to obtain at least one candidate set. Based on the triggering information corresponding to each signal in the first candidate set, the signals in the first candidate set are grouped to obtain at least one candidate subset corresponding to the first candidate set, wherein the first candidate set is any one of the at least one candidate set; Based on the dependency information between signals in the first candidate subset, the signals in the first candidate subset are grouped to obtain at least one signal set corresponding to the first candidate subset, wherein the first candidate subset is any one of the at least one candidate subset.

[0175] In one possible implementation, the acquisition module 401 is specifically used to construct a signal set corresponding to the first candidate subset by taking the signals that have dependencies in the first candidate subset.

[0176] For a description of the features in the embodiment corresponding to the signal recording device, please refer to the relevant description of the embodiment corresponding to the signal recording method, which will not be repeated here.

[0177] Embodiments of this application also provide an electronic device, such as... Figure 5 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-described signal recording method embodiments.

[0178] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described signal recording method embodiments when it is run.

[0179] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0180] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described signal recording method embodiments.

[0181] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described signal recording method embodiments.

[0182] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0183] The signal recording method, apparatus, electronic device, and medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A signal recording method, characterized in that, Applied to a signal recording device, the method includes: Obtain the first type of signal values ​​corresponding to all signals in the first signal set of the chip under test at the current time, and the second type of signal values ​​corresponding to each signal at the previous time. Based on the first type of signal value and the second type of signal value corresponding to all the signals respectively, and the pre-configured trigger recording conditions, determine to record all the first type of signal values ​​or all the second type of signal values.

2. The method according to claim 1, characterized in that, The signal recording device includes at least one port, and the at least one port is respectively used to acquire all signals in the signal set corresponding to the chip under test; the method further includes: Obtain the port address corresponding to the first signal set, and the preset configuration information in the signal recording device, wherein the preset configuration information includes at least one port address and trigger recording condition corresponding to each of the ports; The port whose port address in the preset configuration information is consistent with the port address corresponding to the first signal set is taken as the target port; The trigger recording condition corresponding to the target port is determined as the trigger recording condition corresponding to the first signal set.

3. The method according to claim 1 or 2, characterized in that, The trigger recording conditions include a first reference value corresponding to all the first type of signal values, a second reference value corresponding to all the second type of signal values, a first matching identifier, and a second matching identifier. The first matching identifier is used to indicate whether all the first type of signal values ​​match their respective first reference values, and the second matching identifier is used to indicate whether all the second type of signal values ​​match their respective second reference values.

4. The method according to claim 3, characterized in that, The step of determining to record all first-type signal values ​​or all second-type signal values ​​based on the first-type signal values ​​and second-type signal values ​​corresponding to all the signals, and the pre-configured trigger recording conditions, includes: Based on the first type of signal value and the first type of reference value corresponding to all the signals, determine whether all the signals match the first matching identifier; Based on the second type of signal value and the second type of reference value corresponding to all the signals, determine whether all the signals match the second matching identifier; When all the signals match the first matching identifier and all the signals match the second matching identifier, it is determined that the first signal set satisfies the trigger recording condition; Based on the first matching identifier and the second matching identifier in the trigger recording conditions, determine to record all first type signal values ​​or all second type signal values.

5. The method according to claim 4, characterized in that, The step of determining whether all the signals match the first matching identifier based on the first type of signal value and the first type of reference value corresponding to all the signals includes: According to the preset signal sorting, the first type of signal values ​​corresponding to all the signals are sequentially concatenated to generate a first signal value sequence; According to the preset signal sorting, the first type of reference values ​​corresponding to all the signals are sequentially concatenated to generate a second signal value sequence; Based on the first signal value sequence and the second signal value sequence, determine whether all the signals match the first matching identifier.

6. The method according to claim 5, characterized in that, Each of the signals includes multiple bits, and the trigger recording condition further includes the first type of mask bits corresponding to each of the signals at the current time; the method further includes: Based on the first signal value sequence and the first type of mask bits corresponding to each signal, determine the masked first signal value sequence; Based on the second signal value sequence and the first type of mask bits corresponding to each signal, determine the masked second signal value sequence; Based on the first signal value sequence after the mask and the second signal value sequence after the mask, determine whether all the signals match the first matching identifier at the current time.

7. The method according to claim 4, characterized in that, The step of determining to record all first-type signal values ​​or all second-type signal values ​​based on the first matching identifier and the second matching identifier in the trigger recording condition includes: When the first matching identifier indicates that there is a mismatch between the first type of signal value and the first reference value corresponding to at least one of the signals, and the second matching identifier indicates that the second type of signal value corresponding to all the signals matches the second type of reference value, it is determined to record all the second type of signal values.

8. The method according to claim 4, characterized in that, The step of determining to record all first-type signal values ​​or all second-type signal values ​​based on the first matching identifier and the second matching identifier in the trigger recording condition includes: When the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all the signals match, and the second matching identifier indicates that there is at least one second type of signal value corresponding to a signal that does not match the second type of reference value, or, When the first matching identifier indicates that the first type of signal value and the first reference value corresponding to all the signals match, and the second matching identifier indicates that the second type of signal value corresponding to all the signals matches the second type of reference value, or, When the first matching identifier indicates that at least one of the signals corresponds to a first type of signal value that does not match the first reference value, and the second matching identifier indicates that at least one of the signals corresponds to a second type of signal value that does not match the second type of reference value, Record all values ​​of the first type of signal.

9. The method according to claim 4, characterized in that, The preceding moment is the trigger moment when the signal value corresponding to the first preset signal in the chip under test is converted into a corresponding reference value. The first preset signal is a signal other than the signals in the first signal set. The first signal serves as a response signal to the first preset signal, wherein the first signal is any signal in the first signal set. The method further includes: Obtain the reference value of the first preset signal at the previous moment; The reference value of the first preset signal at the previous moment is determined as the first type of reference value corresponding to the first signal.

10. The method according to claim 1, characterized in that, The method further includes: When the first signal set meets the trigger recording condition, count the number of times the first signal set meets the trigger recording condition within a preset historical time period based on the current time. Based on the number of times, record information for the first signal set is generated.

11. The method according to claim 2, characterized in that, The signal recording device includes at least one clock; the preset configuration information also includes at least one clock identifier corresponding to each of the ports; the method further includes: Based on the clock identifier corresponding to the target port, determine the target clock corresponding to the first signal set from at least one of the clocks; When the first signal set meets the trigger recording condition, the timestamp corresponding to the first signal set is recorded by the target clock.

12. The method according to claim 10, characterized in that, The recorded information also includes the signal value corresponding to the second preset signal at the current time, wherein the second preset signal is a signal in the chip to be detected other than the signals in the first signal set, and the second signal is the trigger signal of the second preset signal, wherein the second signal is any signal in the first signal set.

13. The method according to claim 2 or 11, characterized in that, The method further includes: The preset configuration information is modified to obtain the modified configuration information; Based on the modified configuration information, adjust the trigger record conditions corresponding to the first signal set.

14. The method according to any one of claims 1, 2, 10-12, characterized in that, The method further includes: Obtain the functional information, trigger information, and dependency information between the signals corresponding to the multiple signals in the chip under test; Based on the functional information and triggering information corresponding to each signal, as well as the dependency information between the signals, the signals are grouped to obtain multiple signal sets in the chip to be tested.

15. The method according to claim 14, characterized in that, The step of grouping the signals according to the functional information and triggering information corresponding to each signal, as well as the dependency information between the signals, to obtain multiple signal sets in the chip to be tested includes: Based on the functional information corresponding to each signal, the signals are grouped to obtain at least one candidate set; Based on the triggering information corresponding to each signal in the first candidate set, the signals in the first candidate set are grouped to obtain at least one candidate subset corresponding to the first candidate set, wherein the first candidate set is any one of at least one of the candidate sets; Based on the dependency information between the signals in the first candidate subset, the signals in the first candidate subset are grouped to obtain at least one set of signals corresponding to the first candidate subset, wherein the first candidate subset is any one of the at least one candidate subset.

16. The method according to claim 15, characterized in that, The step of grouping the signals in the first candidate subset according to the dependency information between the signals in the first candidate subset to obtain at least one set of signals corresponding to the first candidate subset includes: The signals that have dependencies in the first candidate subset are used to form the signal set corresponding to the first candidate subset.

17. A signal recording device, characterized in that, The device includes: The acquisition module is used to acquire the first type of signal values ​​corresponding to all signals in the first signal set in the chip under test at the current time, and the second type of signal values ​​corresponding to them at the previous time. The determining module is configured to determine whether to record all first-type signal values ​​or all second-type signal values ​​based on the first-type signal values ​​and second-type signal values ​​corresponding to all the signals, as well as pre-configured trigger recording conditions.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the signal recording method as described in any one of claims 1-16 when executing the computer program.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the signal recording method as described in any one of claims 1-16.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the signal recording method as described in any one of claims 1-16.

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