A signal recording method and device, electronic equipment and medium

Abstract

The application discloses a signal recording method and device, electronic equipment and medium, and relates to the technical field of computers. The method comprises the following steps: acquiring first type signal values corresponding to all signals in a first signal set in a to-be-detected chip at a current moment and second type signal values corresponding to all signals at a previous moment, respectively; and determining whether to record all first type signal values or all second type signal values according to the first type signal values and the second type signal values corresponding to all signals and a preconfigured trigger recording condition. According to the application, the time sequence correlation between signals is established according to the first type signal values at the current moment and the second type signal values at the previous moment, dynamic comparison of signals is realized, the first type signal values or the second type signal values are recorded automatically based on the trigger recording condition, and the signal detection efficiency, flexibility and real-time performance are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a signal recording method and device, electronic equipment and medium. BACKGROUND

[0002] In the field of integrated circuit design and verification, as the complexity of chip functions continues to increase, it is necessary to accurately and efficiently monitor and evaluate the execution efficiency of key function modules, which is the core link of optimizing circuit design, troubleshooting hardware faults and verifying system function integrity. This process usually needs to track the behavior characteristics of key signals in real time, such as signal trigger frequency, trigger interval and signal value change, to quantitatively analyze the running efficiency of key functions. At present, the traditional way of realizing the monitoring of signals is to rely on waveform capture data packets, data packet to waveform file conversion and waveform file viewing. However, this method has the defects of low signal detection efficiency and long time consumption. SUMMARY

[0003] The present application provides a signal recording method, device, electronic equipment and medium to at least solve the problems of low signal detection efficiency and long time consumption.

[0004] The present application provides a signal recording method applied to a signal recording device, the method comprising:

[0005] Respectively acquiring first type signal values corresponding to all signals in a first signal set in a chip to be detected at a current time and second type signal values corresponding to all signals in the first signal set at a previous time;

[0006] According to the first type signal values and the second type signal values corresponding to all signals and a preconfigured trigger recording condition, determining whether to record all first type signal values or all second type signal values.

[0007] The present application also provides a signal recording device, comprising:

[0008] An acquisition module is configured to respectively acquire first type signal values corresponding to all signals in a first signal set in a chip to be detected at a current time and second type signal values corresponding to all signals in the first signal set at a previous time;

[0009] A determination module is configured to determine whether to record all first type signal values or all second type signal values according to the first type signal values and the second type signal values corresponding to all signals and a preconfigured trigger recording condition.

[0010] The present application also provides an electronic equipment comprising a memory for storing a computer program and a processor for executing the computer program to realize the steps of any of the above signal recording methods.

[0011] The application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program.

[0012] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of any one of the signal recording methods.

[0013] According to the application, by analyzing the signal value of the signal at the current moment and the signal value of the signal at the previous moment, the change trend and the time sequence relationship of the signal can be obtained by comparing the signal values at different moments, and the change correlation between the signals can be recorded more accurately by recording the signal values in combination with the preconfigured trigger recording condition, thereby providing a basis for analyzing the working state of the chip. In addition, the preconfigured trigger recording condition can be flexibly set according to different application scenarios and requirements, such as customizing the trigger recording condition according to the specific function of the chip, the test requirement and the like, so as to realize the targeted detection and recording of different types of signals and improve the flexibility of signal detection. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the application, the drawings required to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0015] Figure 1 A flowchart of a signal recording method provided by the embodiments of the application;

[0016] Figure 2 A structural schematic diagram of a signal recording device provided by the embodiments of the application and a Zebu hardware emulator;

[0017] Figure 3 An application schematic diagram of a signal recording device provided by the embodiments of the application;

[0018] Figure 4 A structural schematic diagram of a signal recording device provided by the embodiments of the application;

[0019] Figure 5 A structural schematic diagram of an electronic device provided by the embodiments of the application. DETAILED DESCRIPTION

[0020] With reference to the drawings and specific embodiments described below, the technical solutions in the embodiments of the present application will be clearly and completely described, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0021] It should be noted that in the description of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0022] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0023] First, the application scenario of the embodiments of the present application is exemplarily introduced.

[0024] In the process of integrated circuit design and verification, the execution efficiency of the to-be-detected module is verified mainly by detecting and counting the behavior of the key signal, for example, the execution efficiency of the to-be-detected module for the key function is judged by the trigger frequency, trigger interval and signal value change of the key signal and the like. These information is particularly important for optimizing circuit design, debugging hardware problems and verifying system function.

[0025] In the related art, taking a verification process based on a Zebu hardware simulator as an example, a waveform capture and analysis tool is relied on, and three core steps of data packet capture, conversion of the data packet into a waveform file, and finally waveform viewing and analysis using a tool such as Verdi are mainly used. However, when facing a large-scale circuit design, this signal detection method exposes many problems: first, the entire detection process is tedious to operate, and the conversion of the data packet into a waveform file requires calling a specific tool, which not only consumes a large amount of computing resources but also occupies a lot of time, seriously affecting the verification efficiency. Second, the real-time performance is missing, and the signal-related data can only be obtained after the test process is completely finished, which causes the debugging and optimization work to lag behind and increases the development cycle. Third, the flexibility is insufficient, and once the hardware design is finalized, the signals monitored in the waveform cannot be flexibly adjusted, which cannot adapt to the dynamic needs of different signal monitoring in the verification process. These limitations make it difficult for the traditional method to meet the needs of efficient, real-time, and flexible signal monitoring in modern integrated circuit design. Therefore, how to realize efficient and accurate detection of signals in a chip is the focus of attention.

[0026] Therefore, the embodiment of the present application provides a signal recording method to solve the problems of the above-mentioned tedious and low-efficiency signal detection process.

[0027] It should be noted that the signal recording method provided by the embodiment of the present application can be executed by a signal recording device, which can be implemented by software, hardware or a combination of software and hardware to become part or all of an electronic device, wherein the electronic device can be a server or a terminal, wherein the server in the embodiment of the present application can be a server, or a server cluster composed of multiple servers, and the terminal in the embodiment of the present application can be a smart phone, a personal computer, a tablet computer, a wearable device, a smart robot and other smart hardware devices. In the following method embodiment, the execution subject is taken as an example to be explained.

[0028] According to the embodiment of the present application, a signal recording method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0029] Figure 1 is a flowchart of a signal recording method according to the embodiment of the present application, which is executed by a signal recording device. As shown in Figure 1 , the flowchart includes:

[0030] S101, respectively acquire the first type of signal value corresponding to the current time and the second type of signal value corresponding to the previous time of all signals in the first signal set of the chip to be detected.

[0031] Specifically, the chip to be detected refers to an integrated circuit chip that needs to be functionally verified, performance tested or fault diagnosed, for example, a graphics processing unit (GPU), an application-specific integrated circuit (ASIC) and the like.

[0032] The first signal set refers to signals generated by the chip to be detected in the running process, including but not limited to control signals, data signals, clock signals and the like. For example, register read-write signals in the chip, bus transmission signals (such as valid signals and ready signals of an advanced eXtensible interface (AXI) bus), and enable signals for interaction between modules in the chip.

[0033] The first type of signal value refers to the specific value or state of the signal at the current time, such as high and low levels, binary data, decimal data, hexadecimal data and the like. Similarly, the second type of signal value refers to the specific value or state of the signal at the previous time.

[0034] In the embodiments of the present application, by collecting the first type of signal value and the second type of signal value in real time, it is not necessary to wait for the waveform file to be converted after the test is completed, the real-time detection is increased, and the detection process is accelerated. In addition, by associating the signal values at the current time and the previous time, the timing relationship between the signals can be captured, such as the logic of the control signal and the data signal, which is helpful for analyzing the execution efficiency of the function of the chip to be detected, such as data transmission delay.

[0035] S102, according to the first type of signal value and the second type of signal value corresponding to all signals respectively, and the preconfigured trigger record condition, determine to record all first type of signal value or all second type of signal value.

[0036] The preconfigured trigger record condition refers to a signal record condition preset according to a test purpose, and is used to determine whether a specific signal value needs to be recorded. For example, in the case that the write enable signal is high at the current time and the read data signal is not 0 at the previous time, the trigger record is triggered. For example, the trigger record condition can be determined according to the test purpose of the chip to be detected. For example, the chip to be detected is a system on chip (SoC), and the write address (awaddr) of the AXI host interface of the central processing unit (CPU) in the chip, the write address valid signal (awvalid), the write address ready signal (awready), and the write response valid signal (bvalid) are used to determine the write transmission efficiency of the host interface accessing a certain address range. For another example, the finite state machine of a certain functional module in the chip to be tested is used to determine the sequence and time consumption of each working stage. The trigger record condition can be dynamically configured according to the actual situation, and the signal type and signal record rule of the detection signal can be adjusted without modifying the hardware design, and the detection signal can be flexibly adapted to different test scenarios, such as functional verification scenarios and fault positioning scenarios.

[0037] In the embodiments of the present application, by analyzing the signal value of the signal at the current time and the signal value of the signal at the previous time, the signal value changes at different times can be compared, the change trend and timing relationship of the signal can be obtained, and the signal value can be recorded by combining the preconfigured trigger record condition, so that the correlation between the changes of the signals can be more accurately recorded, and the working state of the chip can be analyzed. In addition, the preconfigured trigger record condition can be flexibly set according to different application scenarios and requirements, such as customizing the trigger record condition according to the specific function of the chip, the test requirement, and the like, so as to realize the targeted detection and record of different types of signals, and improve the flexibility of signal detection.

[0038] In some embodiments, the signal recording device is a hardware device or a module for collecting, screening and recording the signals of the chip to be detected, and is usually integrated in a simulator, a logic analyzer or a test instrument. For example, it is integrated in a Zebu hardware simulator.

[0039] The signal recording device includes at least one port, and the at least one port is respectively used to acquire all signals in a signal set corresponding to the at least one port in the chip to be detected.

[0040] Specifically, the port in the signal recording device refers to a physical interface or a logical channel for accessing the signal in the chip to be detected. Each port corresponds to a group of related signals in the chip to be detected. The port address is address information in the signal recording device for uniquely identifying each port, for identifying and managing different ports in the signal recording device.

[0041] Here, a port can also be understood as a detection channel that receives a signal (trig) from the chip to be detected.

[0042] The method provided by the embodiment of the present application further includes the following content:

[0043] First, the port address corresponding to the first signal set and the preset configuration information in the signal recording device are obtained.

[0044] The preset configuration information includes the port address and the trigger recording condition corresponding to at least one port.

[0045] Specifically, the preset configuration information is the configuration data in the signal recording device set in advance. The preset configuration information is used to indicate the trigger condition of the signal recording device recording the signal set related information. For example, the configuration information table records "port 0 (port address 0x0001) corresponds to the trigger condition: record in the case that the current write enable is 1 and the previous time reading data is not 0", "port 1 (port address 0x0002) corresponds to the trigger condition: record in the case that the current clock frequency is greater than 1GHz".

[0046] Then, the port in the preset configuration information whose port address is consistent with the port address corresponding to the first signal set is taken as the target port.

[0047] Specifically, the target port refers to the port matched with the port address of the first signal set of the chip to be detected from the multiple ports of the signal recording device. For example, the signal recording device compares the port address corresponding to the first signal set with all the port addresses in the preset configuration information, and selects the port with the matched address as the target port.

[0048] Finally, the trigger recording condition corresponding to the target port is determined as the trigger recording condition corresponding to the first signal set.

[0049] In this way, by associating the preset configuration information with the port address, manual setting of the trigger recording condition is not required, operation errors are reduced, multiple ports can work simultaneously, each port matches the trigger recording condition to record the corresponding signal set, the demand for parallel verification of multiple modules in a large-scale chip is met, the overall test coverage is improved, and the signal recording device is suitable for complex chip test scenarios of multiple modules and multiple signals. In addition, different ports correspond to different signal sets of different modules. The preset configuration information can be flexibly modified, so that the signal recording device can adapt to various chip test scenarios.

[0050] In some embodiments, on the basis of any of the preceding embodiments, the trigger recording condition includes first-type reference values corresponding to all first-type signal values respectively, second-type reference values corresponding to all second-type signal values respectively, a first matching identifier, and a second matching identifier, the first matching identifier is used to indicate whether all first-type signal values match the respective first-type reference values, and the second matching identifier is used to indicate whether all second-type signal values match the respective second-type reference values.

[0051] Specifically, the first-type reference value refers to a reference value of a current time preset for a signal in the trigger recording condition, and is used to determine whether an actual value of the signal at the current time meets the trigger recording condition. If the signal is a "write enable signal", the corresponding first-type reference value can be set as a corresponding valid value (such as a high level). Similarly, the second-type reference value refers to a reference value of a previous time preset for each signal in the trigger recording condition, and is used to determine whether an actual value of the signal at the previous time meets the trigger recording condition.

[0052] The first matching identifier is used to represent a determination result (such as a binary state) of whether all signal values of all signals match the respective first-type reference values. "Valid" (such as 1) indicates that all signals match the corresponding first-type reference values, and "invalid" (such as 0) indicates that at least one signal value does not match the corresponding first-type reference value. The second matching identifier is used to represent a determination result of whether all signal values of all signals at the previous time are equal to the respective second-type reference values. "Valid" indicates that all signals match the corresponding second-type reference values, and "invalid" indicates that at least one signal does not match the corresponding second-type reference value.

[0053] In this way, by setting the first matching identifier, the second matching identifier, and the reference value corresponding to each signal, the trigger recording condition is set. When all signals match the first matching identifier and all signals match the second matching identifier, it is determined that the first signal set meets the trigger recording condition, and the first-type signal value or the second-type signal value is recorded at this time.

[0054] In a possible implementation, the s102 specifically includes the following steps:

[0055] a1, based on the first type of signal value and the first type of reference value corresponding to each signal, determine whether each signal matches the first matching identifier.

[0056] Optionally, in a1 above, based on the first type of signal value and the first type of reference value corresponding to each signal, it is determined whether each signal matches the first matching identifier, specifically including the following steps:

[0057] b1, according to the preset signal sorting, concatenate the first type of signal values ​​corresponding to all signals in sequence to generate the first signal value sequence.

[0058] Specifically, the preset signal sorting refers to the order in which the signals are ordered, ensuring consistency when comparing signals. For example, the preset signal sorting can be stored in the trigger recording conditions to determine the order of the signals. The preset signal sorting can be set according to actual conditions and is not limited here.

[0059] b2, according to the preset signal sorting, sequentially concatenate the first type of reference values ​​corresponding to all signals to generate the second signal value sequence.

[0060] Similarly, the second signal value sequence obtained by splicing the first type of reference values ​​can refer to the first signal value sequence mentioned above, and will not be repeated here.

[0061] b3, based on the first signal value sequence and the second signal value sequence, determine whether all signals match the first matching identifier.

[0062] In one possible scenario, the first signal value sequence is compared bit by bit or byte by byte with the second signal value sequence. If all bits are consistent, the sequence is considered a match; if at least one bit is inconsistent, the sequence is considered a mismatch.

[0063] In another possible scenario, calculate the corresponding hash value (such as CRC check) for each of the two signal value sequences, and determine whether the two signal value sequences match by comparing whether the hash values ​​are consistent.

[0064] In this way, by transforming the comparison of multiple signals into a holistic comparison of two sequences, the judgment speed of the signal recording device is accelerated, making it suitable for multi-signal scenarios.

[0065] In another possible implementation, for each signal, the current value of the first type of signal is compared with the corresponding first type of reference value to obtain the comparison result for each signal. After obtaining the comparison result for each signal, the comparison results of all signals are counted. If the comparison results of all signals satisfy the first matching identifier, then all signals are determined to match the first matching identifier. Compared with the signal value sequence method, checking each signal one by one is more intuitive and suitable for detection scenarios with a small number of signals and simple logic.

[0066] Optionally, each signal includes a plurality of bits, and the trigger record condition further includes a first type mask bit corresponding to each signal at the current time. In addition to the specific implementation manner in b3 above, determining whether all signals match the first matching identifier can also be implemented in the following manner:

[0067] First, according to the first signal value sequence and the first type mask bit corresponding to each signal, a masked first signal value sequence is determined.

[0068] Specifically, the first type mask bit is a binary mask configured for each signal, which is used to filter the bits of the signal value that need to be paid attention to. For example, the binary identifier "1" indicates that the bit is retained, and "0" indicates that the bit is ignored.

[0069] Then, according to the second signal value sequence and the first type mask bit corresponding to each signal, a masked second signal value sequence is determined.

[0070] Finally, according to the masked first signal value sequence and the masked second signal value sequence, it is determined whether all signals match the first matching identifier at the current time.

[0071] For example, the first signal set includes signal A, signal B, and signal C. If the first type mask bits corresponding to signal A, signal B, and signal C are 0xFF, 0xF0, and 0x0F respectively, it indicates that when determining whether signal A matches the first matching identifier, the first signal value corresponding to signal A is compared with all 8-bit bits in the first type reference value. When determining whether signal B matches the first matching identifier, only the high 4-bit bits in the first signal value corresponding to signal B are compared with the high 4-bit bits in the first type reference value. When determining whether signal C matches the first matching identifier, only the first signal value corresponding to signal C is compared with the low 4-bit bits in the first type reference value. When the first signal value corresponding to signal A is equal to all 8-bit bits in the first type reference value, and the high 4-bit bits in the first signal value corresponding to signal B are equal to the corresponding values of the high 4-bit bits in the first type reference value, and the first signal value corresponding to signal C is equal to the corresponding values of the low 4-bit bits in the first type reference value, it is determined that all signals match the first matching identifier at the current time, otherwise, it is determined that all signals do not match the first matching identifier at the current time.

[0072] In this way, by screening the bit of interest in the signal through the mask bit, such as detecting only the high 4-bit voltage stability and ignoring irrelevant bit, such as the noise fluctuation of the low 4-bit, the invalid data interference on the judgment result can be avoided. For example, in the logic chip test process, the key bit related to the timing is verified, the judgment accuracy is improved, and the calculation resource consumption is reduced. In addition, by configuring an independent mask bit for each signal, each signal can be processed specifically, and the detection requirements of different signals can be flexibly adapted.

[0073] a2, according to the second type signal value corresponding to all signals respectively and the second type reference value, judging whether all signals match the second matching identifier.

[0074] Judging whether all signals match the second matching identifier is similar to the specific implementation manner of judging whether the signal matches the first matching identifier, which will not be described here.

[0075] a3, when all signals match the first matching identifier and all signals match the second matching identifier, it is determined that the first signal set meets the trigger recording condition.

[0076] For example, in the signal recording device, a logical AND gate is set, or a software script of "AND" operation is set, to make a combined judgment on whether the signal matches the first matching identifier and the second matching identifier respectively. If all signals match the first matching identifier and all signals match the second matching identifier, a recording signal meeting the trigger recording condition is output, which triggers the subsequent recording operation, such as recording the first type signal value or the second type signal value. If the signal does not match the corresponding identifier, the signal recording device does not trigger the recording operation.

[0077] a4, according to the first matching identifier and the second matching identifier in the trigger recording condition, determining to record all first type signal values or all second type signal values.

[0078] In this way, by comparing each signal to determine whether to trigger the signal recording device to record, it is ensured that the recorded data is strongly related to the target event (such as "normal data transmission completion" "before abnormal operation occurs"), and the invalid data interference is reduced.

[0079] In a possible implementation, based on any of the foregoing embodiments, according to the first matching identifier and the second matching identifier in the trigger recording condition, it is determined to record all first type signal values or all second type signal values, which specifically includes the following contents:

[0080] When the first matching identifier indicates that at least one signal respectively corresponding to the first type signal value and the first reference value does not match, and the second matching identifier indicates that all signals respectively corresponding to the second type signal value and the second reference value match, it is determined to record all second type signal values.

[0081] Specifically, when the first matching identifier indicates that at least one signal value does not match the corresponding first type reference value, and the second matching identifier indicates that all signal values match the corresponding second type reference value, it can be understood that the signal is abnormal or changes at the current moment, and the signal is normal at the previous moment, i.e., the "old value leaving" scenario, indicating that the chip under test transits from the normal state at the previous moment to the abnormal state or the change state at the current moment.

[0082] For example, the "old value leaving" scenario can be used to capture the last normal state before the abnormality occurs, and realize fault positioning of the chip under test. The abnormal state is often evolved from the normal state at the previous moment, and the "old value" (normal signal at the previous moment) may implicitly contain key information (such as parameter setting, configuration state, etc.) leading to the current abnormality. Recording the old value can establish the cause-effect relationship from "normal to abnormal", avoiding ignoring the precondition by only observing the current abnormality.

[0083] In a possible implementation, based on any of the foregoing embodiments, according to the first matching identifier and the second matching identifier in the trigger recording condition, it is determined to record all first type signal values or all second type signal values, including:

[0084] When the first matching identifier indicates that all signals respectively match the corresponding first type signal values and the first reference values, and the second matching identifier indicates that at least one signal does not match the corresponding second type signal value and the second type reference value,

[0085] Or,

[0086] When the first matching identifier indicates that all signals respectively match the corresponding first type signal values and the first reference values, and the second matching identifier indicates that all signals respectively match the corresponding second type signal values and the second type reference values,

[0087] Or,

[0088] When the first matching identifier indicates that at least one signal respectively does not match the corresponding first type signal value and the first reference value, and the second matching identifier indicates that at least one signal does not match the corresponding second type signal value and the second type reference value,

[0089] It is determined to record all first type signal values.

[0090] Specifically, when the first matching identifier indicates that all signals respectively match the corresponding first type signal values and the first reference values, and the second matching identifier indicates that at least one signal does not match the corresponding second type signal value and the second type reference value, it can be understood as a "new value arriving" scenario, in which all current signal values meet the corresponding reference values (the first matching identifier "all equal"), i.e., the chip under test enters the expected "new state".

[0091] An exemplary "new value arrival" scenario can be that the chip to be detected completes initialization, such as a signal value after power-on of the chip is configured to reach a reference value. The "new value arrival" scenario can be that the chip to be detected switches states in a normal operation process, such as from an idle state to a data transmission state, and the data transmission enable signal at the current time meets the preset signal value. The "new value arrival" scenario can also be that the chip to be detected recovers from an error to reach a normal state, for example, the signal value at the previous time is abnormal, and the signal value at the current time is normal.

[0092] In the present implementation, by recording the first type of signal value corresponding to the "new value arrival" scenario, it can be used to verify whether the chip enters the target state as expected, and also provide reference information for subsequent state changes.

[0093] Specifically, when the first matching identifier indicates that the first type of signal value corresponding to all signals and the first reference value are matched, and the second matching identifier indicates that the second type of signal value corresponding to all signals and the second reference value are matched, it can be understood as a "specific value change" scenario, that is, the signal completes a specific correct value change.

[0094] An exemplary "specific value change" scenario can be a timing state switch, for example, the signal value corresponding to the preparation at the previous time is converted to the signal value corresponding to the readiness at the current time. The "specific value change" scenario can also be a chip fault automatic repair scenario, for example, the signal value at the previous time is used to indicate a check error, and the signal value at the current time is used to indicate a check pass, completing fault repair.

[0095] Specifically, when the first matching identifier indicates that there is at least one signal respectively corresponding to the first type of signal value and the first reference value that do not match, and the second matching identifier indicates that there is at least one signal corresponding to the second type of signal value and the second reference value that do not match, it can be understood as a "arbitrary change tracking" scenario of the chip to be detected, indicating that the chip to be detected is in a continuous abnormal state, and the current value has an arbitrary change relative to the abnormal value at the previous time.

[0096] An exemplary "arbitrary change tracking" scenario can be a fault diffusion scenario (such as a bus error at the previous time and an address error at the current time, neither of which meets the corresponding reference value), an unstable state fluctuation scenario (such as a clock signal in the chip to be detected having a lower frequency at the previous time and a further deviation from the corresponding reference value at the current frequency), and a failed error repair of the chip to be detected (such as attempting to correct a data error at the previous time, but the current data still does not meet the corresponding reference value).

[0097] In the implementation mode, the three scenarios cover a "new value arrival" scenario, a "specific value change" scenario, and an "arbitrary change tracking" scenario, ensuring that any scenario that triggers a recording condition can be recorded, which is a comprehensive detection of the chip to be detected. At the same time, by recording the current first type signal value and combining the previous time state (such as the second matching identifier) to establish a cause-and-effect time sequence association, the logic chain of the signal change of the chip to be detected can be tracked. In addition, the three scenarios are used to locate the problem of the chip to be detected, such as the "new value arrival" scenario for verifying the correctness of the function of the chip to be detected, the "specific value change" scenario for verifying the effectiveness of the repair function of the chip to be detected, and the "arbitrary change tracking" scenario for capturing the fault propagation path, which greatly shortens the debugging period.

[0098] In a possible implementation mode, the previous time is a trigger time when a signal value corresponding to a first preset signal in the chip to be detected is converted into a reference value corresponding thereto, the first preset signal is a signal other than a signal in a first signal set, and the first signal is a response signal of the first preset signal, wherein the first signal is any signal in the first signal set.

[0099] Specifically, the first preset signal is not a signal in the first signal set and is a trigger signal that triggers a signal in the first signal set in the chip to be detected. Taking detection of access to a certain address range as an example, the first preset signal can be an address range selection signal received by the chip to be detected, and the first signal set includes signals related to write transmission efficiency, such as a write instruction enable signal (used to indicate whether to start write transmission) and the like.

[0100] The first preset signal can be a signal indicated in advance in the trigger recording condition, and the first preset signal associated with the signal is recorded in the trigger recording condition.

[0101] The method provided by the embodiment of the application further includes the following content:

[0102] First, a reference value of the first preset signal at a previous time is acquired.

[0103] Then, the reference value of the first preset signal at the previous time is determined as the first type reference value corresponding to the first signal.

[0104] In the implementation mode, the reference value of the first preset signal is used to automatically determine the first type reference value of the first signal, avoiding errors caused by manual setting, adapting to dynamic changes in signal logic, for example, in the case of changes in the reference value of the first preset signal in different scenarios, the first type reference value of the first signal can be automatically synchronized with the first preset signal. In addition, a cause-and-effect relationship is established between the first preset signal and the first signal, so that when the first signal is abnormal, the state of the first preset signal can be quickly traced back, and the fault can be quickly located.

[0105] In some embodiments, based on any of the foregoing embodiments, the method provided by the embodiments of the present application further includes the following content:

[0106] b1, when the first signal set meets the trigger recording condition, counting the number of times that the first signal set meets the trigger recording condition within a preset historical time period back to the current time.

[0107] Specifically, the preset instance time period is used as a time window for limiting technology, which can be set according to actual conditions, for example, the number of triggers in the last 10 minutes.

[0108] Optionally, the signal recording device includes at least one counter; and the preset configuration information further includes a counter identifier corresponding to each port. When the first signal set meets the trigger recording condition, the number of times that the first signal set meets the trigger recording condition within a preset historical time period back to the current time is counted, which specifically includes the following steps:

[0109] First, according to the counter identifier corresponding to the target port, a target counter corresponding to the first signal set is determined in the at least one counter.

[0110] The target counter is used to perform an accumulation counting operation when the first signal set meets the trigger recording condition within the preset historical time period.

[0111] Then, the counting value in the target counter is used as the number of times.

[0112] Specifically, the counters in the signal recording device are distinguished by counter identifiers. For example, the counter identifier can be a counter name, a register address, etc.

[0113] b2, according to the number of times, generating the recording information of the first signal set.

[0114] Specifically, the recording information of the first signal set includes the counting value in the target counter. In addition, the recording information further includes the first type signal value corresponding to all signals determined to be recorded in S102 or the second type signal value corresponding to all signals.

[0115] In this way, based on the counter identifier corresponding to the target port, it is ensured that each port corresponds to a signal set corresponding to an independent counter, avoiding interference between trigger times of different ports, so that the counting result is more accurate.

[0116] In one possible implementation, the signal recording device includes at least one clock; the preset configuration information further includes a clock identifier corresponding to each port; and the method provided by the embodiments of the present application further includes the following content:

[0117] First, according to the clock identifier corresponding to the target port, a target clock corresponding to the first signal set is determined in at least one clock.

[0118] Then, when the first signal set satisfies the trigger recording condition, a timestamp corresponding to the first signal set is recorded by the target clock.

[0119] In a possible implementation, the recording information further includes a signal value of a second preset signal corresponding to the current time, wherein the second preset signal is a signal in the chip to be detected other than the signals in the first signal set, and the second signal is a trigger signal of the second preset signal, and the second signal is any signal in the first signal set.

[0120] Specifically, the state (such as the high and low of the level, the pulse jump, etc.) change of the second signal will trigger the state change of the second preset signal, and there is a causal trigger relationship between the second signal and the second preset signal. For example, the chip to be detected includes a transmission enable signal for controlling the start or shutdown of the data transmission function. The second preset signal is a transmission bandwidth signal for determining the bandwidth used for transmitting data. The transmission enable signal is a trigger signal of the second preset signal. When the transmission enable signal changes from 0 to 1, that is, the data transmission function changes from shutdown to startup, the second preset signal is triggered to change from 1Gbps to 10Gbps. In this case, the recording information further includes the signal value of the second preset signal at the current time, that is, 10Gbps.

[0121] Since there is a trigger relationship between the second preset signal and the second signal, recording the signal value of the second preset signal at the current time can supplement the associated information between the signals, help trace the entire process of the signal change in the chip to be detected, and record the signal value of the second preset signal to verify whether the trigger logic in the chip to be detected is normal (for example, whether the transmission bandwidth signal changes as expected after the transmission enable signal is activated), thereby improving the comprehensiveness of chip function verification. In addition, when the second signal is abnormal, the signal value of the second preset signal can also provide additional information for abnormal analysis. Taking the second preset signal as the response signal of the transmission enable signal as an example, the signal value of the second preset signal at the current time is used to determine whether the data transmission abnormality is related to the signal value corresponding to the second preset signal.

[0122] In some embodiments, on the basis of any of the preceding embodiments, the method provided by the embodiments of the present application further includes the following content:

[0123] First, the preset configuration information is modified to obtain modified configuration information.

[0124] Then, according to the modified configuration information, the trigger recording condition corresponding to the first signal set is adjusted.

[0125] Optionally, continuing to take the signal recording device as an example, the submodule in Zebu includes three preset ports, which are respectively used to obtain the trigger recording condition, the port information (such as the port address) corresponding to the trigger recording condition and the recording content (such as the first type of signal value or the second type of signal value in the recording information or the counting value in the counter) in the preset configuration information. The trigger recording condition, the port information and the recording content are controlled by entering the relevant Tool Command Language (Tcl) instruction through the interactive command line to control the preset configuration information. For example, the three ports of the configuration toggle (cfg_toggle) port, the configuration address (cfg_addr) port and the configuration data input (cfg_datain) port in the submodule are respectively used as the configuration trigger recording condition behavior, the port address and the recording content. When the Zebu project is compiled, the force function is added to the three ports, and when the Zebu project is run, the preset configuration information in the submodule can be controlled through the three ports.

[0126] In this way, considering that the working scene of the chip to be detected may change continuously according to the application requirements, the trigger recording condition is adjusted by modifying the configuration information, such as dynamically adding or deleting the signal or the reference value in the trigger recording condition, so that the information recording device can quickly adapt to the new test scene and improve the flexibility of signal recording.

[0127] In some embodiments, the method provided by the embodiment of the application further includes the following content:

[0128] c1, obtaining the function information, the trigger information and the dependency relationship information between the signals corresponding to a plurality of signals in the chip to be detected.

[0129] Specifically, the plurality of signals in the chip to be detected refer to the electrical signals or the logic signals used for transmitting data, controlling logic or indicating state, which are the basic units of chip function implementation. For example, the clock signal, the data read / write signal, the address signal and the like.

[0130] The function information is used to describe the specific function or role of the signal in the chip. For example, the write data enable signal is an enable signal used for indicating the data write operation. For example, the function information of each signal is parsed through the hardware description code, the design document or the data manual of the chip to be detected, and the purpose of the signal is obtained.

[0131] The trigger information is used to describe the condition of the signal being activated (e.g. level jump) value change. Taking the signals in the chip to be detected including indicating whether the write command is valid (awvalid), whether the receiver confirms receiving the write command (awready) as an example, when the receiver detects that awvalid is high (i.e. the write command is valid), and itself is ready to receive the command (e.g. the internal register is idle), awready is triggered to be high. For example, the condition and timing of triggering each signal are determined by the logic expression (e.g. "tx_start=data_valid&addr_ready") or the timing constraint (e.g. "addr is latched on the rising edge of clk") in the hardware description of the chip to be detected.

[0132] The dependency relationship between the signals refers to the causal relationship or the timing relationship between the signals, which can reflect the interaction logic between the signals, for example, the A signal causes the B signal to change. For example, the causal relationship between the signals is identified by a code form analysis tool, such as the A signal is the input of the B signal, and the B signal fluctuates after the A signal changes, so as to obtain the dependency relationship between the signals.

[0133] c2, grouping the signals according to the function information and the trigger information corresponding to each signal respectively, and the dependency relationship information between the signals, to obtain a plurality of signal sets in the chip to be detected.

[0134] In a possible implementation, the signals are grouped according to the function information and the trigger information corresponding to each signal respectively, and the dependency relationship information between the signals, to obtain a plurality of signal sets in the chip to be detected, and specifically includes the following steps:

[0135] First, the signals are grouped according to the function information corresponding to each signal respectively to obtain at least one candidate set.

[0136] For example, according to the function information corresponding to each signal respectively, the signals with a function information similarity higher than a preset threshold are divided into a group, that is, a candidate set is formed. For example, the signals in the chip to be detected include: a write address signal (awaddr), a write command valid signal (awvalid), a write data signal (wdata), a write completion feedback signal (bvalid), a read address signal (rdaddr), and a read data signal (rdata). The signals related to the write operation "awaddr, awvalid, wdata, bvalid" are divided into a group to obtain a candidate set related to the write operation, and the signals related to the read operation "rdaddr, rdata" are divided into a group to obtain a candidate set related to the read operation.

[0137] Then, according to the trigger information corresponding to each signal in the first candidate set, the signals in the first candidate set are grouped to obtain at least one candidate sub-set corresponding to the first candidate set.

[0138] The first candidate set is any one of the at least one candidate set.

[0139] For example, according to the trigger information corresponding to each signal, the signals sharing the same pre-signal or timing characteristics are divided into a candidate sub-set. For example, taking the candidate set as the signals related to the write operation, assuming that the trigger information of awaddr is "effective when the sender is ready to send the address", the trigger information of awvalid is "awvalid is high when awaddr is valid", the trigger information of wdata is "effective 1 clock cycle after awvalid is high", and the trigger information of bvalid is "effective after the receiver completes the write operation". awaddr, awvalid, and wdata share the trigger timing of the "write command initiation stage", so awaddr, awvalid, and wdata are divided into a candidate sub-set, and bvalid belongs to the trigger timing of the "write operation completion stage", so bvalid is divided into a candidate sub-set.

[0140] Finally, according to the dependency information between the signals in the first candidate sub-set, the signals in the first candidate sub-set are grouped to obtain at least one signal set corresponding to the first candidate sub-set.

[0141] The first candidate sub-set is any one of the at least one candidate sub-set.

[0142] Optionally, the signals in the first candidate sub-set that have a dependency relationship form a signal set corresponding to the first candidate sub-set.

[0143] For example, taking the candidate sub-set to include awaddr, awvalid, and wdata, the dependency relationship between the signals in the candidate sub-set is that awvalid depends on awaddr (awvalid cannot be high if awaddr is invalid); wdata depends on awvalid (wdata does not take effect if awvalid is not high), and awaddr, awvalid, and wdata form a complete data link from the initiation of the write command to the transmission of data, so awaddr, awvalid, and wdata are taken as a signal set.

[0144] For example, a signal in the first candidate subset is randomly selected as a starting signal, all subsequent signals dependent on the starting signal are found, and then the dependency relationship of the subsequent signals is recursively tracked until there is no new dependent signal. Then, the precursor signals dependent on the starting signal are found, the dependency relationship of the precursor signals is recursively tracked, and when there is no new precursor signal, a signal set is formed.

[0145] In the embodiments of the present application, by grouping each signal in the to-be-detected chip according to the function information, trigger information, and dependency relationship information, missing of key signals during signal detection is avoided, and the logic of signals in the chip is more clear, for example, a data transmission set can intuitively reflect a complete signal chain of chip read / write operation. In addition, the signal set is a prerequisite for setting a trigger recording condition, and grouping can ensure that the trigger recording condition covers all associated signals, avoiding inaccurate signal detection and analysis due to signal isolation.

[0146] In another possible implementation, the signals are grouped according to the function information and trigger information respectively corresponding to each signal, and the dependency relationship information between the signals, to obtain a plurality of signal sets in the to-be-detected chip, and specifically includes the following steps:

[0147] First, the first semantic similarity between each two signals in the signals is determined according to the function information respectively corresponding to the signals.

[0148] Then, the second semantic similarity between each two signals in the signals is determined according to the trigger information respectively corresponding to the signals.

[0149] Next, the third semantic similarity between each two signals in the signals is determined according to the dependency relationship information respectively corresponding to the signals.

[0150] Finally, the signals are divided according to the first semantic similarity, the second semantic similarity, and the third semantic similarity between each two signals in the signals, to obtain a plurality of signal sets.

[0151] For example, for a group of two signals, the first semantic similarity, the second semantic similarity, and the third semantic similarity are weighted and summed to obtain a comprehensive similarity corresponding to the two signals. Two signals with a comprehensive similarity greater than a preset threshold are divided into a group, thereby obtaining a plurality of signal sets.

[0152] The signal recording device can be used for circuit performance monitoring and statistics in Zebu and Electronic Design Automation Simulation (EDA). In the following embodiments, Zebu will be exemplarily described.

[0153] Figure 2Fig. 1 is a structural schematic diagram of a signal recording device and a Zebu hardware simulator. In Figure 2 The signal recording device is a submodule in the Zebu hardware simulator. The Zebu hardware simulator obtains a hardware design program corresponding to a chip to be tested, automatically compiles the hardware design program into hardware units, and tests the chip to be tested based on a test case. In the testing process, the signal recording device records key signal values (e.g., first-type signal values and second-type signal values) and related information (total triggering times) and generates a log. The recording operation depends on functions supported by Zebu, such as $fdisplay, $fwrite, $fopen, $fclose, and the like, which are allowed to appear in hardware code.

[0154] The preset configuration information in the signal recording device can be determined by a tester according to a test target of the chip to be tested. The tester can determine a configuration table according to a performance detection requirement, and then convert the configuration table into configuration data flow recognizable by the signal recording device, so as to make the signal recording device generate the preset configuration information.

[0155] For example, the configuration table is shown in Table 1.

[0156] Table 1

[0157]

[0158] In Table 1, the column of "signal" is a signal to be tested in the chip to be tested. In order to better organize and utilize the monitoring logic of a large number of signals, the signals can be divided into multiple instances for implementation. The number here is the instance number where the current row signal is located after organization.

[0159] As can be seen in Table 1, the signal top.dut.cpu.awaddr, the signal top.dut.cpu.awid, the signal top.dut.cpu.awvalid, and the signal top.dut.cpu.awready belong to the signal set cpu-aw. The signal top.dut.cpu.bid, the signal top.dut.cpu.bvalid, and the signal top.dut.cpu.bready belong to the signal set cpu-b. The signal top.dut.uart.cur_state and the signal top.dut.dma.core.cur_state belong to the signal set state1. The signal top.dut.cpu.dbg_state belongs to the signal set state0. The bit width refers to the number of bits in the signal. The most significant bit (MSB) refers to the position of the highest bit of the signal in the signal value sequence when all signal values corresponding to the signals are concatenated in sequence. The least significant bit (LSB) refers to the position of the lowest bit of the signal in the signal value sequence when all signal values corresponding to the signals are concatenated in sequence. In addition to recording the first type of signal value, the second type of signal value, and the number of times, the signal recording device also records the recording time stamp. The clock identifiers corresponding to the signal sets cpu-a and cpu-b are both 0, and the clock identifiers corresponding to the signal sets state1 and state0 are both 1, that is, the signal sets cpu-a and cpu-b use the clock with clock identifier 0 to record the time stamp, and the signal sets state1 and state0 use the clock with clock identifier 1 to record the time stamp.

[0160] In Table 1, the trigger recording type raise is the “new value arrives” scenario, the trigger recording type shift is the “specific value changes” scenario, and the trigger recording type trace is the “arbitrary change tracking” scenario.

[0161] Based on the above configuration table, the ports of the signal recording device are connected to the hardware units corresponding to the chip to be detected, and the connection relationship can be represented as follows:

[0162] “.trig0( / / cpu-aw

[0163] top.dut.cpu.awaddr, / / [73:10]

[0164] top.dut.cpu.awid, / / [9:2]

[0165] top.dut.cpu.awvalid, / / [1:1]

[0166] top.dut.cpu.awready / / [0:0]

[0167] ),

[0168] .trig1( / / cpu-b

[0169] top.dut.cpu.bid, / / [9:2]

[0170] top.dut.cpu.bvalid, / / [1:1]

[0171] top.dut.cpu.bready / / [0:0]

[0172] ),

[0173] trig2( / / state1

[0174] top.dut.uart.cur_state, / / [7:4]

[0175] top.dut.dma.core.cur_state / / [3:0]

[0176] ),

[0177] trig3( / / stateθ

[0178] top.dut.cpu.dbg_state / / [5:0]

[0179] )”。

[0180] Based on the above configuration table, the test personnel converts into a format recognizable by the signal recording device to obtain the configuration data stream as shown in Table 2.

[0181] Table 2

[0182]

[0183] In a signal recording device, there can be multiple monitoring channels, and each channel needs its own configuration information. In the embodiment of the present application, the configuration information is planned into a unified format, called a configuration data stream, as shown in the above table. The configuration section of each monitoring channel consists of TW_MAX*4 bits. TW_MAX is the maximum value of all port bit widths. The explanation of each part in the configuration data stream is as follows.

[0184] targ_value_old, corresponding to the second type of reference value in the configuration table, in the embodiment of the present application, the second type of reference value can be spliced to obtain a signal value sequence.

[0185] targ_value_new, corresponding to the first type of reference value in the configuration table.

[0186] targ_igno_old or last_trig_sel, corresponding to the second type of mask bit in the configuration table.

[0187] targ_igno_new, corresponding to the first type of mask bit in the configuration table.

[0188] timer_rcd (timer record), information record control, determines whether to print the time stamp to the log (log), that is, whether to record the time stamp.

[0189] payld_rcd (payload record), information record control, determines whether to print the payload data (that is, the signal value corresponding to the second preset signal at the current time) attached by the channel to the log.

[0190] trig_rcd (trigger record), information record control, determines whether to print the first type of signal value or the second type of signal value at the trigger time to the log.

[0191] chng_trc (change trace), that is, change trace, trigger record type control, indicating that the channel works in the trigger record type of trace.

[0192] timer_sel (timer selection), timer selection, determines the timer number used when printing the time stamp.

[0193] crs_targ (cross target), special trigger record type control, indicating that the first type of reference value of the channel comes from the reference value of the first preset signal recorded by the last channel at the previous time.

[0194] Each row of the above configuration data stream is accompanied by a valid bit, and according to the combination of the valid values of targ_value_new and targ_value_old, the channel will exhibit different trigger record types. Specifically:

[0195] targ_value_new valid, targ_value_old invalid, the trigger record type is raise;

[0196] targ_value_new invalid, targ_value_old valid, the trigger record type is drop;

[0197] targ_value_new valid, targ_value_old valid, trigger record type is shift;

[0198] targ_value_new invalid, targ_value_old invalid, trigger record is off;

[0199] targ_value_new invalid, targ_value_old invalid, chng_trc valid, trigger record type is trace.

[0200] The information recording device uses an array to save the configuration segment of all channels.

[0201] The input of the monitoring channel has three parts, the first is the port to be monitored and triggered at any time, the second is the configuration segment for comparison and control, and the third is the data input port that can be used for additional printing to the log file, that is, the signal value of the second preset signal at the current time. The monitoring channel will compare whether the first type of signal value is equal to the configured first type of reference value at each clock, and whether the registered last period second type of signal value is equal to the configured second type of reference value. According to whether the two parts are equal, it may meet the conditions of different trigger record types:

[0202] The first type of signal value is equal to the first type of reference value, and the second type of signal value is not equal to the second type of reference value, at this time, the raise condition is hit, that is, the signal value first reaches the target value, if the channel is configured as raise, the event record can be triggered;

[0203] The first type of signal value is not equal to the first type of reference value, and the second type of signal value is equal to the second type of reference value, at this time, the drop condition is hit, that is, the signal value leaves the target value, if the channel is configured as drop, the event record can be triggered;

[0204] The first type of signal value is equal to the first type of reference value, and the second type of signal value is also equal to the second type of reference value, at this time, the shift condition is hit, that is, the signal value has a specific value change, if the channel is configured as shift, the event record can be triggered;

[0205] The first type of signal value is not equal to the first type of reference value, and the second type of signal value is not equal to the second type of reference value, at this time, the trace condition is hit, that is, the signal value has an arbitrary value change, if the channel is configured as trace, the event record can be triggered.

[0206] When comparing the signal value with the corresponding reference value, both parties will be filtered by the mask bit in the configuration segment.

[0207] Generally, if the accompanying valid bit of targ_igno_new is high, i.e. the mask bit is high, the signal value will be flipped, then bitwise AND with the value of targ_value_new, and then the bitwise AND data is compared.

[0208] There is another case that the first type reference value of one channel should come from the reference value (also the signal value) of the preset signal of the previous time recorded by another channel. For example, if the response speed of AXI write transaction is tested, it is needed to find the AXI write command of a specific AWID in one trigger channel, and then wait for the response of the specific ID as BID returned in another channel. This function is called cross target in zsigmon. If the crs_targ control bit of the configuration section is valid, the part selected by last_trig_sel in the final targ_value_new used for the monitoring channel will be replaced by the corresponding part of the reference value (also the signal value) recorded by the previous monitoring channel. In this way, part of the bits of one signal is allowed to be used as the trigger target of another signal, which is used for complex signal correlation monitoring and supports more complex verification scenarios.

[0209] Since Zebu supports adding $fdisplay, $fwrite, $fopen, $fclose system functions in the project, and takes effect when the Zebu project is running, the log can be output to the text file in time.

[0210] Each record information is a line in the Log file, mainly including three parts:

[0211] <TRIGN_M=0xVALUE>, which indicates that the Nth event occurs in the Mth channel, and the trig value (signal value) is 0xVALUE. Whether the =0xVALUE part of this field is printed or not is controlled by trig_rcd;

[0212] <TIMEN_M=TIMESTAMP@CLKA>, which indicates that the time of the Mth event occurring in the Nth channel is the timer value driven by the A number clock, which is TIMESTAMP. Whether this field is printed or not is controlled by timer_rcd.

[0213] <PAYLOADN_M=0xVALUE>, which indicates that the value of the payload port of the Nth channel when the Mth event occurs in the channel is 0xVALUE. Whether this field is printed or not is controlled by payld_rcd.

[0214] After hitting under different conditions, the signal values printed to the Log file will also be different according to the different control bits in the configuration segment. After triggering raise, if trig_rcd is enabled, the first type of signal value will be printed; after triggering drop, if trig_rcd is enabled, the second type of signal value will be printed; after triggering shift, if trig_rcd is enabled, the first type of signal value will be printed; after triggering trace, if trig_rcd is enabled, the first type of signal value will be printed.

[0215] Figure 3 is an application diagram of a signal recording device. In Figure 3 , the signal recording device receives the first type of signal value and the second type of signal value, compares the first type of signal value with the first type of reference value, and compares the second type of signal value with the second type of reference value. When the comparison result meets the trigger recording condition, if the counting function is turned on, the counter is used to count the number of times that the trigger recording condition is met; if the recording preset signal value (i.e., the signal value corresponding to the second preset signal at the current time) function is turned on, the preset signal value is recorded; and if the time stamp function is turned on, the clock corresponding to the signal set is selected to obtain the time stamp of the current time. In this way, the log is generated based on the counting value in the counter, the preset signal value, the time stamp, and the like.

[0216] In the embodiments of the present application, in a first aspect, signal monitoring is realized through a hardware module, avoiding the cumbersome process of traditional waveform capture and analysis tools, significantly reducing the monitoring time, and improving the verification efficiency. In a second aspect, relevant information can be recorded immediately when the signal is triggered, facilitating engineers to monitor and debug in real time, and discovering and solving problems in a timely manner. In a third aspect, the monitoring conditions can be dynamically adjusted during simulation running, flexibly adapting to different testing requirements without the need to recompile or modify the hardware design. The signal recording device records detailed log information, including but not limited to the number of times that the trigger recording condition is met, the time stamp, and the corresponding data (such as the first type of signal value and the second type of signal value), facilitating subsequent analysis and optimization, and providing strong support for the improvement of circuit design. In a fourth aspect, it is applicable to various signal monitoring scenarios, including new value arrival, old value departure, specific value change, and arbitrary change tracking, meeting different design and verification requirements.

[0217] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better implementation.

[0218] The embodiments of the present application also provide a signal recording device, which is used to implement the above-mentioned embodiments and preferred embodiments, and has been described above. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0219] The embodiments of the present application provide a signal recording device, as shown in the accompanying drawings, comprising: Figure 4

[0220] The acquisition module 401 is configured to acquire first type signal values respectively corresponding to all signals in the first signal set in the chip to be detected at a current time and second type signal values respectively corresponding to all signals in the first signal set at a previous time.

[0221] The determination module 402 is configured to determine whether to record all first type signal values or all second type signal values according to the first type signal values and the second type signal values respectively corresponding to all signals and a preconfigured trigger recording condition.

[0222] In a possible implementation, the signal recording device comprises at least one port, and the at least one port is respectively used to acquire all signals in a signal set corresponding to the at least one port in the chip to be detected. The acquisition module 401 is further configured to acquire a port address corresponding to the first signal set and preset configuration information in the signal recording device, wherein the preset configuration information comprises a port address and a trigger recording condition respectively corresponding to the at least one port.

[0223] The port in the preset configuration information, of which the port address is consistent with the port address corresponding to the first signal set, is taken as a target port.

[0224] The trigger recording condition corresponding to the target port is determined as the trigger recording condition corresponding to the first signal set.

[0225] In a possible implementation, the trigger recording condition comprises first type reference values respectively corresponding to all first type signal values, second type reference values respectively corresponding to all second type signal values, a first matching identifier and a second matching identifier. The first matching identifier is used to indicate whether all first type signal values match the respective first type reference values, and the second matching identifier is used to indicate whether all second type signal values match the respective second type reference values.

[0226] In a possible implementation, the determination module 402 is specifically configured to determine whether all signals match the first matching identifier according to the first type signal values and the first type reference values respectively corresponding to all signals.

[0227] ​determine whether all the signals match the second matching identifier according to the second type signal values respectively corresponding to all the signals and the second type reference values;

[0228] when all the signals match the first matching identifier and all the signals match the second matching identifier, determine that the first signal set meets the trigger recording condition;

[0229] determine to record all the first type signal values or all the second type signal values according to the first matching identifier and the second matching identifier in the trigger recording condition.

[0230] In a possible implementation, the determining module 402 is specifically configured to splice the first type signal values respectively corresponding to all the signals in sequence according to a preset signal order to generate a first signal value sequence;

[0231] splice the first type reference values respectively corresponding to all the signals in sequence according to the preset signal order to generate a second signal value sequence;

[0232] determine whether all the signals match the first matching identifier according to the first signal value sequence and the second signal value sequence.

[0233] In a possible implementation, each signal includes a plurality of bit positions, and the trigger recording condition further includes a first type mask bit respectively corresponding to each signal at a current time; the apparatus further includes a determining module configured to determine a masked first signal value sequence according to the first signal value sequence and the first type mask bit respectively corresponding to each signal;

[0234] determine a masked second signal value sequence according to the second signal value sequence and the first type mask bit respectively corresponding to each signal;

[0235] determine whether all the signals match the first matching identifier at the current time according to the masked first signal value sequence and the masked second signal value sequence.

[0236] In a possible implementation, the determining module 402 is specifically configured to determine to record all the second type signal values when the first matching identifier indicates that there is at least one signal respectively corresponding to a first type signal value and a first reference value that do not match, and the second matching identifier indicates that all the signals respectively corresponding to the second type signal values and the second type reference values all match.

[0237] In a possible implementation, the determining module 402 is specifically configured to determine to record all the first type signal values when the first matching identifier indicates that all the signals respectively corresponding to the first type signal values and the first reference values all match, and the second matching identifier indicates that there is at least one signal respectively corresponding to a second type signal value and a second reference value that do not match,

[0238] or,

[0239] When the first matching indication indicates that all the first-type signal values corresponding to all the signals respectively match the first reference values, and the second matching indication indicates that all the second-type signal values corresponding to all the signals match the second reference values,

[0240] Or,

[0241] When the first matching indication indicates that there is at least one signal whose first-type signal value does not match the first reference value, and the second matching indication indicates that there is at least one signal whose second-type signal value does not match the second reference value,

[0242] determining to record all the first-type signal values.

[0243] In a possible implementation, the previous time is a triggering time at which a signal value of a first preset signal in the chip to be detected is converted into a reference value corresponding to the signal value, the first preset signal is a signal other than the signals in the first signal set, and the first signal is a response signal of the first preset signal, where the first signal is any signal in the first signal set; the apparatus further includes an obtaining module configured to obtain the reference value of the first preset signal at the previous time;

[0244] The reference value of the first preset signal at the previous time is determined as the first-type reference value corresponding to the first signal.

[0245] In a possible implementation, the apparatus further includes a counting module configured to, when the first signal set satisfies the triggering recording condition, count a number of times that the first signal set satisfies the triggering recording condition within a preset historical time period, with the current time as a reference.

[0246] The recording information of the first signal set is generated according to the number.

[0247] In a possible implementation, the signal recording apparatus includes at least one clock; the preset configuration information further includes clock identifiers corresponding to at least one port respectively; and the apparatus is further configured to determine, according to a clock identifier corresponding to a target port, a target clock corresponding to the first signal set from the at least one clock.

[0248] When the first signal set satisfies the triggering recording condition, a time stamp corresponding to the first signal set is recorded by using the target clock.

[0249] In a possible implementation, the recording information further includes a signal value of a second preset signal corresponding to the current time, where the second preset signal is a signal other than the signals in the first signal set in the chip to be detected, and the second signal is a triggering signal of the second preset signal, where the second signal is any signal in the first signal set.

[0250] In a possible implementation, the apparatus further includes a modifying module configured to modify the preset configuration information to obtain modified configuration information.

[0251] According to the modified configuration information, the trigger record condition corresponding to the first signal set is adjusted.

[0252] In a possible implementation, the obtaining module 401 is further configured to obtain function information, trigger information corresponding to each signal in the to-be-detected chip respectively, and dependency relationship information among the signals.

[0253] According to the function information and the trigger information corresponding to each signal respectively and the dependency relationship information among the signals, the signals are grouped to obtain a plurality of signal sets in the to-be-detected chip.

[0254] In a possible implementation, the obtaining module 401 is specifically configured to group the signals according to the function information corresponding to each signal to obtain at least one candidate set.

[0255] According to the trigger information corresponding to each signal in the first candidate set, the signals in the first candidate set are grouped to obtain at least one candidate sub-set corresponding to the first candidate set, wherein the first candidate set is any one of the at least one candidate set.

[0256] According to the dependency relationship information among the signals in the first candidate sub-set, the signals in the first candidate sub-set are grouped to obtain at least one signal set corresponding to the first candidate sub-set, wherein the first candidate sub-set is any one of the at least one candidate sub-set.

[0257] In a possible implementation, the obtaining module 401 is specifically configured to group the signals having the dependency relationship in the first candidate sub-set to form the signal set corresponding to the first candidate sub-set.

[0258] The features of the embodiments of the signal recording apparatus can be referred to the related descriptions of the embodiments of the signal recording method, which will not be repeated here.

[0259] The embodiments of the present application further provide an electronic device, as shown in the accompanying drawings, which comprises a memory 10 and a processor 20, the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above signal recording method embodiments. Figure 5

[0260] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above signal recording method embodiments when running. ​

[0261] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0262] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program, when executed by a processor, implements the steps in any of the signal recording method embodiments described above.

[0263] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps in any of the signal recording method embodiments described above.

[0264] The skilled person can further realize that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0265] The above provides a detailed description of a signal recording method, device, electronic equipment and medium provided by the present application. The principles and implementation modes of the present application are described by applying specific examples in this paper. The above description of the examples is only applicable to help understand the method and core idea of the present application. It should be noted that for ordinary skilled persons in the technical field, without departing from the principles of the present application, the present application can be improved and modified in several ways. These improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A signal recording method characterized by, The method is applied to a signal recording device, and comprises the following steps: Respectively acquiring first type signal values corresponding to all signals in a first signal set in a chip to be detected at a current time and second type signal values corresponding to all signals in the first signal set at a previous time; Determining whether to record all the first type signal values or all the second type signal values according to the first type signal values and the second type signal values corresponding to all the signals and a preconfigured trigger recording condition; The trigger recording condition comprises first type reference values corresponding to all the first type signal values, second type reference values corresponding to all the second type signal values, a first matching identifier and a second matching identifier, the first matching identifier is used to indicate whether all the first type signal values match the respective first type reference values, and the second matching identifier is used to indicate whether all the second type signal values match the respective second type reference values; The determining whether to record all the first type signal values or all the second type signal values according to the first type signal values and the second type signal values corresponding to all the signals and the preconfigured trigger recording condition comprises the following steps: Judging whether all the signals match the first matching identifier according to the first type signal values and the first type reference values corresponding to all the signals; Judging whether all the signals match the second matching identifier according to the second type signal values and the second type reference values corresponding to all the signals; When all the signals match the first matching identifier and all the signals match the second matching identifier, it is determined that the first signal set satisfies the trigger recording condition; Determining whether to record all the first type signal values or all the second type signal values according to the first matching identifier and the second matching identifier in the trigger recording condition; The judging whether all the signals match the first matching identifier according to the first type signal values and the first type reference values corresponding to all the signals comprises the following steps: According to a preset signal sequence, first type signal values corresponding to all the signals are sequentially spliced to generate a first signal value sequence; According to the preset signal sequence, first type reference values corresponding to all the signals are sequentially spliced to generate a second signal value sequence; According to the first signal value sequence and the second signal value sequence, it is determined whether all the signals match the first matching identifier.

2. The method of claim 1, wherein, The signal recording device comprises at least one port, and at least one of the ports is used to acquire all signals in a signal set corresponding to the port in the chip to be detected; the method further comprises the following steps: Acquiring a port address corresponding to the first signal set and preset configuration information in the signal recording device, wherein the preset configuration information comprises port addresses corresponding to the at least one port and trigger recording conditions; Taking a port in the preset configuration information as a target port, wherein the port has a port address consistent with the port address corresponding to the first signal set; Determining a trigger recording condition corresponding to the target port as a trigger recording condition corresponding to the first signal set.

3. The method of claim 1, wherein, Each of the signals comprises a plurality of bits, and the trigger recording condition further comprises a first type of mask bit corresponding to each of the signals at the current time; the method further comprises: determining a first signal value sequence after masking according to the first signal value sequence and the first type of mask bit corresponding to each of the signals; determining a second signal value sequence after masking according to the second signal value sequence and the first type of mask bit corresponding to each of the signals; determining whether all of the signals match the first matching identifier at the current time according to the first signal value sequence after masking and the second signal value sequence after masking.

4. The method of claim 1, wherein, The determining of recording all of the first type of signal values or all of the second type of signal values according to the first matching identifier and the second matching identifier in the trigger recording condition comprises: when the first matching identifier indicates that there is at least one first type of signal value corresponding to each of the signals that does not match the first reference value, and the second matching identifier indicates that all of the second type of signal values corresponding to the signals match the second type of reference value, determining to record all of the second type of signal values.

5. The method of claim 1, wherein, The determining of recording all of the first type of signal values or all of the second type of signal values according to the first matching identifier and the second matching identifier in the trigger recording condition comprises: when the first matching identifier indicates that all of the first type of signal values corresponding to each of the signals match the first reference value, and the second matching identifier indicates that there is at least one second type of signal value corresponding to each of the signals that does not match the second type of reference value, or, when the first matching identifier indicates that all of the first type of signal values corresponding to each of the signals match the first reference value, and the second matching identifier indicates that all of the second type of signal values corresponding to the signals match the second type of reference value, or, when the first matching identifier indicates that there is at least one first type of signal value corresponding to each of the signals that does not match the first reference value, and the second matching identifier indicates that there is at least one second type of signal value corresponding to each of the signals that does not match the second type of reference value, determining to record all of the first type of signal values.

6. The method of claim 1, wherein, The previous time is a trigger time at which a signal value corresponding to a first preset signal in the chip to be detected is converted into a reference value corresponding thereto, the first preset signal is a signal other than the signals in the first signal set, and the first signal is a response signal of the first preset signal, wherein the first signal is any signal in the first signal set; the method further comprises: obtaining a reference value of the first preset signal at the previous time; determining the reference value of the first preset signal at the previous time as the first type of reference value corresponding to the first signal.

7. The method of claim 1, wherein, The method further comprises: when the first signal set satisfies the trigger recording condition, counting the number of times that the first signal set satisfies the trigger recording condition within a preset historical time period based on the current time as a reference; generating recording information of the first signal set according to the number of times.

8. The method of claim 2, wherein, The signal recording device comprises at least one clock; the preset configuration information further comprises at least one clock identifier corresponding to each of the ports; the method further comprises: determining a target clock corresponding to the first signal set from the at least one clock according to the clock identifier corresponding to the target port; recording a timestamp corresponding to the first signal set by the target clock when the first signal set meets the trigger recording condition.

9. The method of claim 7, wherein, The recording information further comprises a signal value of a second preset signal corresponding to a current time, wherein the second preset signal is a signal other than the signals in the first signal set in the chip to be detected, and the second signal is a trigger signal of the second preset signal, wherein the second signal is any signal in the first signal set.

10. The method of claim 2 or 8, wherein, The method further comprises: modifying the preset configuration information to obtain modified configuration information; adjusting the trigger recording condition corresponding to the first signal set according to the modified configuration information.

11. The method of any one of claims 1, 2, 7-9, wherein, The method further comprises: obtaining function information, trigger information corresponding to each of the signals in the chip to be detected, and dependency relationship information between the signals; grouping each of the signals according to the function information and the trigger information corresponding to each of the signals and the dependency relationship information between the signals to obtain a plurality of signal sets in the chip to be detected.

12. The method of claim 11, wherein, The grouping of each of the signals according to the function information and the trigger information corresponding to each of the signals and the dependency relationship information between the signals to obtain a plurality of signal sets in the chip to be detected comprises: grouping each of the signals according to the function information corresponding to each of the signals to obtain at least one candidate set; grouping the signals in the first candidate set according to the trigger information corresponding to each of the signals in the first candidate set to obtain at least one candidate sub-set corresponding to the first candidate set, wherein the first candidate set is any one of the at least one candidate set; grouping the signals in the first candidate sub-set according to the dependency relationship information between the signals in the first candidate sub-set to obtain at least one signal set corresponding to the first candidate sub-set, wherein the first candidate sub-set is any one of the at least one candidate sub-set.

13. The method of claim 12, wherein, The grouping of the signals in the first candidate sub-set according to the dependency relationship information between the signals in the first candidate sub-set to obtain at least one signal set corresponding to the first candidate sub-set comprises: constructing the signal set corresponding to the first candidate sub-set from the signals having a dependency relationship in the first candidate sub-set.

14. A signal recording apparatus characterized by comprising: The device comprises: an acquisition module configured to acquire a first type of signal value corresponding to each of the signals in the first signal set in the chip to be detected at a current time and a second type of signal value corresponding to each of the signals at a previous time, respectively; determining, according to the first type signal values and the second type signal values corresponding to all the signals respectively and a preconfigured trigger record condition, whether to record all the first type signal values or all the second type signal values; the trigger record condition comprises first type reference values corresponding to all the first type signal values respectively, second type reference values corresponding to all the second type signal values respectively, a first match identifier and a second match identifier, the first match identifier is used to indicate whether all the first type signal values match the respective first type reference values, and the second match identifier is used to indicate whether all the second type signal values match the respective second type reference values; the determining, according to the first type signal values and the second type signal values corresponding to all the signals respectively and a preconfigured trigger record condition, whether to record all the first type signal values or all the second type signal values, comprises: judging, according to the first type signal values and the first type reference values corresponding to all the signals respectively, whether all the signals match the first match identifier; judging, according to the second type signal values and the second type reference values corresponding to all the signals respectively, whether all the signals match the second match identifier; when all the signals match the first match identifier and all the signals match the second match identifier, determining that the first signal set meets the trigger record condition; determining, according to the first match identifier and the second match identifier in the trigger record condition, whether to record all the first type signal values or all the second type signal values; the judging, according to the first type signal values and the first type reference values corresponding to all the signals respectively, whether all the signals match the first match identifier, comprises: sequentially concatenating the first type signal values corresponding to all the signals respectively according to a preset signal order to generate a first signal value sequence; sequentially concatenating the first type reference values corresponding to all the signals respectively according to the preset signal order to generate a second signal value sequence; judging, according to the first signal value sequence and the second signal value sequence, whether all the signals match the first match identifier.

15. An electronic device, comprising: comprises: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the signal record method according to any one of claims 1-13.

16. A computer-readable storage medium, characterized in that, the computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the signal record method according to any one of claims 1-13.

17. A computer program product comprising a computer program, characterized in that, the computer program is executed by the processor to implement the steps of the signal record method according to any one of claims 1-13.

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