Logic comprehensive cutting delay prediction method based on graph neural network

Abstract

The invention provides a logic synthesis cutting delay prediction method based on a graph neural network, which comprises the following steps of: firstly, constructing a cutting (Cut) delay prediction data set of a logic synthesis circuit, then extracting structural and functional features of nodes in a cutting sub-graph, constructing a heterogeneous cutting level graph taking a cutting super node as a center, and finally, carrying out segmentation on the heterogeneous cutting level graph. And packaging into a graph neural network input format. Then, a delay prediction model is constructed, the delay prediction model comprises a graph neural network module and a multi-layer perceptron module, the graph neural network module extracts circuit structure features and pointer attention mechanism dynamic association standard cell library features through SAGE convolution, and enhanced cutting representation is formed; and finally, carrying out delay prediction on cutting in a new circuit by utilizing the trained model. According to the method, the cutting structure modeling capability and the delay prediction precision are effectively improved, the method can be used for optimizing a cutting selection strategy in a synthesizer, and the logic comprehensive quality is improved.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation, specifically a logic synthesis and segmentation delay prediction method based on graph neural networks. Background Technology

[0002] In logic synthesis, a Boolean network is a network composed of logic gates (such as AND gates, OR gates, NOT gates, etc.) and signal lines, representing the logical function of a circuit. To generate high-quality synthesis results, appropriate substructures need to be selected from the Boolean network for mapping; these substructures are called "cuts," and each cut represents a possible logical partitioning method. During synthesis, each cut needs to be mapped to one or more standard cells to implement its logical function. Therefore, the standard cell library provides crucial implementation resources and timing references for the performance evaluation of cuts. Logic synthesis plays a vital role in the Electronic Design Automation (EDA) process. Its goal is to generate a gate-level netlist with good performance in terms of area and delay, through a series of logic transformations and optimization operations, while meeting functional constraints. To achieve high-quality synthesis results, modern synthesizers typically use a "cut-based mapping" strategy. This involves extracting multiple optional cuts from the Boolean network as candidate structures and evaluating their performance under the target cost function (e.g., area, timing, power consumption) to select the optimal mapping structure and generate a gate-level netlist that meets the design requirements. During the cut selection process, predicting the timing performance after the cut mapping is a key factor affecting the synthesis quality. However, current industrial synthesis tools typically use simple heuristics such as logic hierarchy, number of nodes, and reverse fan-out to approximate the latency performance of slicing. This approach cannot accurately model the dependencies between logical structures, is prone to evaluation bias, and thus leads to unsatisfactory synthesis results, and may even increase the timing repair costs in back-end placement and routing.

[0003] With the development of Graph Neural Networks (GNN) technology, its expressive power in processing graph-structured data has gradually attracted attention in the field of hardware design. Existing research has attempted to apply GNNs to circuit diagram quality assessment tasks, achieving some success. However, most of these methods are based on full graph modeling, which cannot accurately depict structural details at the cut level, making it difficult to meet the need for rapid evaluation of large-scale cut candidate structures during the synthesis stage. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a logic synthesis cut delay prediction method based on graph neural networks. This method solves the problems of traditional logic synthesis process where cut delay estimation relies on simple surrogate indicators, has insufficient prediction accuracy, and cannot effectively guide the selection of optimization strategies.

[0005] To solve the above problems, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a logic synthesis segmentation delay prediction method based on graph neural networks, comprising:

[0007] Step S1: Construct a logic synthesis circuit cutting delay prediction dataset and divide the dataset into a training set and a test set;

[0008] The dataset contains input data and label data; the input data contains circuits described by RTL Verilog and a standard cell library for mapping, and the label data is the maximum path delay value obtained by a static timing analysis tool for each cut root node in the mapped circuit.

[0009] Step S2: Preprocess the input data and label data;

[0010] Step S3: Construct a segmentation delay prediction model based on graph neural networks, and train and test it using the preprocessed dataset;

[0011] The segmentation delay prediction model based on graph neural networks includes a pointer attention-graph neural network (GNN-Attn) module and a multilayer perceptron module;

[0012] The pointer attention-graph neural network module is used to preprocess the input data, independently process the circuit diagram node features and standard cell library feature embeddings, and concatenate the processed features to obtain the segmented node feature embeddings.

[0013] The multilayer perceptron module is used to receive the feature embedding of the cut node generated by the pointer attention-graph neural network module, and regress and output the corresponding delay prediction value;

[0014] Step S4: Use the trained graph neural network segmentation delay prediction model to predict the delay of each segment in the circuit to be synthesized.

[0015] Preferably, the pointer attention-graph neural network module includes a circuit node feature processing submodule, a standard cell library feature processing submodule, and a feature enhancement submodule;

[0016] The circuit node feature processing submodule receives the initial node feature embedding of each node in the heterogeneous cut-level graph, passes it sequentially through two graph convolutional blocks and one pooling layer to extract local neighborhood information of the nodes and generate preliminary cut feature embeddings. The graph convolutional block consists of one graph convolution operation (SAGEConv) and one activation function operation (SiLU). The input to the first graph convolutional block is the initial node feature embedding, and the input to the second graph convolutional block is the activation result output by the first graph convolutional block. The pooling layer performs a pooling operation on the feature embeddings of all nodes within the Cone region corresponding to each cut node to obtain the preliminary feature embedding representation of that cut node. The Cone region is defined as a sub-network region centered on a cut node, containing that node and all its downstream (or upstream) logic gates and signal paths.

[0017] The node feature update process in the graph convolution block consists of graph convolution operation (SAGEConv) and activation function operation (SiLU) in sequence, and its overall calculation process can be described by the following formula:

[0018]

[0019] in, Let i represent the embedding representation of node i at level l. Let represent the set of neighboring nodes of node i, AGG(·) represent the aggregation operation using the mean function, W represent the learnable linear transformation weight matrix, and σ(·) represent the SiLU activation function.

[0020] The standard cell library feature processing submodule is used to receive standard cell library feature embeddings, which are then passed through the first RMSNorm (Root Mean Square Normalization) layer, the first linear transformation layer, the second RMSNorm layer, and the second linear transformation layer in sequence, and output standardized standard cell library feature embeddings.

[0021] The first and second RMSNorm layers have the same structure and use root mean square normalization. Their mathematical expressions are as follows:

[0022]

[0023] The linear transformation is a fully connected linear mapping, and its mathematical expression is:

[0024]

[0025] Where h represents the input feature vector. This represents the i-th component of vector h. Let h' represent the dimension of vector h, h' represent the output feature vector after linear transformation, W be the learnable weight matrix, b be the learnable bias vector, and γ be the normalized learnable scaling factor. A small constant to prevent division by zero errors.

[0026] The feature enhancement submodule receives the initial segmentation feature embedding and the standardized standard unit library feature embedding. It dynamically establishes the feature association between the segmentation node and the standard unit library using a Pointer Attention mechanism, outputting the pointer attention-enhanced features. Then, the initial segmentation feature embedding and the pointer attention-enhanced features are concatenated to form the final segmentation node feature embedding, which is used for delayed regression prediction in the subsequent multilayer perceptron module. The mathematical description of the pointer attention mechanism is as follows:

[0027]

[0028] in This indicates the initial feature embedding for segmentation, and Lib indicates the standardized standard unit library feature embedding. These are the learnable linear transformation matrices for the query, key, and value, respectively. The softmax operation normalizes the weight distribution on the feature set of the standard cell library, where the feature dimension is the scaling factor.

[0029] Preferably, the multilayer perceptron module includes a first linear layer, a first activation function layer (SiLU), a first random deactivation (Dropout) layer, a second linear layer, a second activation function layer (SiLU), a second random deactivation layer, a third linear layer, and a third activation function layer (PReLU) cascaded together, for outputting the predicted delay value of the cut.

[0030] Preferably, step S2 includes the following sub-steps:

[0031] S201: Convert the circuit described by RTL Verilog into an And-Inverter Graph (AIG) format circuit; construct a directed acyclic graph based on the AIG format circuit. , where V is the set of nodes, including logical AND gate nodes and logical NOT gate nodes, and E is the set of edges, representing the connection relationships between nodes;

[0032] S202: Using each logical node in the directed acyclic graph as the root node, extract the logical Cone region formed by its backpropagation closure to construct several cutting subgraphs; create a cutting supernode for each cutting subgraph; wherein, the cutting subgraph refers to the directed acyclic subgraph formed by tracing back to all its predecessor nodes from a target node (i.e., the cutting root node) in the Boolean network. The input boundary of this subgraph consists of a set of predecessor nodes, called the cutting input nodes or leaf nodes; the cutting subgraph contains all the logic gates and signal paths from these input nodes to the root node. Each cutting subgraph represents a local functional structure that can be used for the construction of candidate mapping units and delay prediction.

[0033] Preferably, the cutting supernode is a high-level abstract representation of the cutting subgraph. Its initial feature embedding is obtained by concatenating the mean feature embedding of the nodes contained in the cutting subgraph with the fan-out number embedding of the root node and mapping them together. The cutting supernode is connected to the nodes inside the cutting through heterogeneous edges to form a heterogeneous graph structure centered on the cutting.

[0034] S203: The newly created cut supernode is used as a new node in the directed acyclic graph to form a heterogeneous cut-level graph; structural feature embedding and functional feature embedding are constructed for each node in the heterogeneous cut-level graph and spliced ​​together to form the initial node feature embedding.

[0035] Preferably, the functional feature embedding includes the controllability index, observability index, and type identifier of the node in the circuit logic, which are used to help the model understand the difficulty of signal propagation and the logical behavior of the node; the structural feature embedding includes node type, topology level, and fan-out number, which are used to describe the topological attributes of the node in the graph structure.

[0036] Preferably, the node type is 0 or 1, where 0 represents an AND node and 1 represents a NOT node; the topology level of the node refers to the number of nodes on the longest path from any main input to the node; and the fan-out number refers to the number of outputs of the node.

[0037] S204: Encapsulate the initial node embedding and corresponding label of each node in the heterogeneous cut-level graph into a graph neural network input data format to construct standardized graph samples.

[0038] In a second aspect, the present invention provides an electronic device including a processor and a memory, the memory storing machine-executable instructions executable by the processor, the processor executing the machine-executable instructions to implement the method.

[0039] Thirdly, the present invention provides a machine-readable storage medium, characterized in that the machine-readable storage medium stores machine-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the method.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] The graph neural network module of this invention analyzes the AIG graph structure of the logic synthesis circuit through the graph neural network convolutional layer, extracts local neighborhood features of nodes, and dynamically aggregates standard cell library features by combining pointer attention mechanism to form an enhanced cut node feature representation, which improves the model's ability to model the delay characteristics of different cut structures. The multilayer perceptron module uses this enhanced cut feature to perform regression prediction, accurately estimate the path delay after cut mapping, and accumulates sample experience through continuous training, so as to quickly and accurately predict cut delay when facing circuits of different sizes and structures, improve the decision quality of cut selection and mapping in the logic synthesis optimization stage, significantly accelerate synthesis convergence and improve the quality of results. Attached Figure Description

[0042] Figure 1 This is a flowchart of the logic synthesis and segmentation delay prediction method based on graph neural networks provided by the present invention.

[0043] Figure 2 This is the complete model framework diagram provided by the present invention.

[0044] Figure 3 This is a diagram of the Pointer Attention-Graph Neural Network (GNN-Attn) module provided by the present invention.

[0045] Figure 4 This is a schematic diagram of the multilayer perceptron module provided by the present invention. Detailed Implementation

[0046] The following detailed description, in conjunction with the accompanying drawings, further illustrates the principles and features of the logic synthesis cut delay prediction method based on graph neural networks proposed in this invention. The examples given are for illustrative purposes only and are not intended to limit the scope of the invention. It should be noted that the accompanying drawings are simplified and use non-precise scales, intended only to facilitate and clearly illustrate the embodiments of the invention. Furthermore, the structures shown in the drawings are often part of the actual structures, and different drawings may emphasize different aspects, sometimes using different scales.

[0047] This invention provides a logic synthesis cut delay prediction method based on graph neural networks, the flowchart of which is shown below. Figure 1As shown, a Cut delay prediction dataset for logic synthesis circuits is first constructed, and the circuits are pre-divided into training and testing sets. The datasets contain input data and label data. The input data includes the circuit described by RTL Verilog and a standard cell library for mapping. The label data is the maximum path delay corresponding to the Cut root node. The input data is preprocessed to generate a circuit diagram in AIG format, and the node structure and functional features are extracted to construct a heterogeneous graph structure centered on the Cut supernode. A Cut delay prediction model based on a graph neural network is constructed, which includes a GNN-Attn module and a multilayer perceptron module, and is trained on the preprocessed training set. The test set is input into the trained model to predict the delay of each Cut in the circuit, and the prediction performance is evaluated using an error metric.

[0048] Therefore, a logic synthesis cut delay prediction method based on graph neural networks specifically includes:

[0049] S1: Construct a logic synthesis circuit cut delay prediction dataset, dividing it into training and test sets according to a predetermined ratio for subsequent model training and validation. The dataset includes input data and label data; the input data includes circuits described in RTL Verilog and a standard cell library for mapping; the label data is the maximum path delay value obtained by a static timing analysis (STA) tool for each cut root node in the mapped circuit. In this embodiment, the standard cell library uses the ASAP7 standard cell library.

[0050] S2: Preprocess the input and label data. For each circuit instance in the dataset, first convert it to And-Inverter Graph (AIG) format, extract the logical cone region of each node, and form a Cut subgraph. For each node, extract structural features (such as node type, topology level, and fan-out number) and functional features (such as controllability and observability indicators), and concatenate these features to form the initial node feature embedding. Simultaneously, introduce cell features from the standard cell library to form a standardized standard cell library feature embedding.

[0051] S3: Construct a Cut delay prediction model based on a graph neural network. The overall model structure is as follows: Figure 2 As shown, it includes a pointer attention-graph neural network (GNN-Attn) module, a feature enhancement module, and a multilayer perceptron (MLP) prediction module.

[0052] The structure of GNN-Attn is as follows: Figure 3As shown, the algorithm includes a circuit node feature processing submodule, a standard cell library feature processing submodule, and a feature enhancement submodule. In the circuit node feature processing submodule, the initial feature embedding of each node in the heterogeneous cut graph is sequentially processed through two graph convolutional blocks to extract local neighborhood information. A pooling layer aggregates the features of all nodes in the Cone region corresponding to each Cut node to generate the initial Cut feature embedding. In the standard cell library feature processing submodule, the standard cell library features are processed through two RMSnorm normalization and linear transformations to generate standardized standard cell library feature embeddings. In the feature enhancement submodule, the initial Cut features and standard cell library features are dynamically associated through a PointerAttention mechanism to further enhance the Cut node features. Finally, the initial Cut features and PointerAttention-enhanced features are concatenated to form the final Cut node feature embedding.

[0053] The node feature update process in the graph convolution block consists of graph convolution operation (SAGEConv) and activation function operation (SiLU) in sequence, and its overall calculation process can be described by the following formula:

[0054]

[0055] in, Let i represent the embedding representation of node i at level l. Let represent the set of neighboring nodes of node i, AGG(·) represent the aggregation operation using the mean function, W represent the learnable linear transformation weight matrix, and σ(·) represent the SiLU activation function.

[0056] RMSNorm uses root mean square normalization, and its mathematical expression is:

[0057]

[0058] The linear transformation is a fully connected linear mapping, and its mathematical expression is:

[0059]

[0060] Where h represents the input feature vector. This represents the i-th component of vector h. Let h' represent the dimension of vector h, h' represent the output feature vector after linear transformation, W be the learnable weight matrix, b be the learnable bias vector, and γ be the normalized learnable scaling factor. A small constant to prevent division by zero errors.

[0061] The mathematical description of the Pointer Attention mechanism is as follows:

[0062]

[0063] in This represents the initial feature embedding of the Cut node, and Lib represents the standardized feature matrix of the standard cell library. These are the learnable linear transformation matrices for the query, key, and value, respectively. The softmax operation normalizes the weight distribution on the feature set of the standard cell library, where the feature dimension is the scaling factor.

[0064] The structure of a multilayer perceptron module is as follows: Figure 4 As shown, it includes a three-layer linear transformation structure, with each layer followed by SiLU activation and Dropout regularization, and finally outputs the predicted Cut node delay value through the PReLU activation function.

[0065] The first linear layer receives the final Cut node feature embeddings from the graph neural network module, transforms and maps them to the hidden feature space, as shown in the following mathematical expression:

[0066]

[0067] in The final feature embedding vector for the input Cut node. The hidden feature vectors after the first linear mapping. The first linear mapping weight matrix, For the corresponding bias term;

[0068] The second linear layer is used to map the activated and regularized feature vector input, and the mathematical expression is as follows:

[0069]

[0070] in This represents the feature vector after processing by the SiLU and Dropout layers. The hidden feature vector after the second linear mapping The second linear mapping weight matrix, For the corresponding bias term;

[0071] The PReLU layer is used to apply a parametrically learnable nonlinear transformation to the feature vector output by the third linear transformation, in order to introduce nonlinear expressive power and optimize the fitting effect in the small negative value region in the regression task. The mathematical expression of the PReLU activation function is:

[0072]

[0073] in For the i-th component of the input vector, This is the corresponding learnable slope parameter.

[0074] S4: Perform model training and prediction. Input the graph samples in the training set into the graph neural network model, and use the stochastic gradient descent (SGD) optimizer, based on the mean squared error (MSE) loss function, for iterative training until training converges. During training, the model continuously updates its parameters based on the difference between the true delay label and the predicted value.

[0075] After training, the test set is input into the model for prediction, and the error metric between the predicted latency and the actual latency is calculated to evaluate the model performance.

[0076] The testing process includes the following steps:

[0077] S501: Input the data from the test set into the trained model.

[0078] S502: Outputs the final area prediction results for each circuit and evaluates them using MAPE, mathematically described as follows:

[0079]

[0080] Where n is the number of samples, It is the actual value of the i-th sample. It is the predicted value of the i-th sample.

[0081] The experimental environment parameters for the logic synthesis cut delay prediction method based on graph neural networks proposed in this invention are shown in Table 1 below:

[0082] Table 1

[0083] category Configuration operating system Linux CPU Intel(R) Xeon(R) Gold 6348 CPU @ 2.60GHz GPU NVIDIA GeForce RTX 4090 RAM 500GB Pytorch 2.1.0 PyTorch Geometric 2.5.2

[0084] The trained model and the DeepGate2 method's logic synthesis cut delay prediction results for 9 circuits on the test set are shown in Table 2 below. It can be seen that the method of the present invention has a small error.

[0085] Table 2

[0086] Test circuit DeepGate2 Method of the present invention dft 30.3% 10.4% aes secworks 43.2% 18.2% dynamic node 36.8% 15.5% des3 area 62.2% 16.1% wb conmax 29.7% 10.4% idft 29.1% 11.1% multiplier 21.5% 10.9% ethernet 23.1% 8.1% sqrt 59.4% 29.4% MEAN 37.2% 14.4%

[0087] This invention provides an electronic device, specifically, the electronic device includes a memory and a processor, the memory stores executable code, and when the processor executes the executable code, it implements the method described in any of the embodiments.

[0088] The memory may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk drive. Communication between this system network element and at least one other network element is achieved through at least one communication interface (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0089] The bus can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0090] The memory is used to store programs. After receiving an execution instruction, the processor executes the program. The method executed by the device for defining the flow process disclosed in any of the foregoing embodiments of the present invention can be applied to the processor or implemented by the processor.

[0091] The processor may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above methods can be completed by integrated logic circuits in the processor's hardware or by software instructions. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0092] The computer program product of the readable storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the foregoing method embodiments. For specific implementation, please refer to the foregoing method embodiments, which will not be repeated here.

[0093] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0094] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for predicting delay in logical synthesis segmentation based on graph neural networks, characterized in that, The method includes the following steps: Construct a logic synthesis circuit segmentation delay prediction dataset and divide the dataset into training and test sets; The dataset contains input data and label data; the input data contains circuits described by RTL Verilog and a standard cell library for mapping, and the label data is the maximum path delay value of each cut root node in the mapped circuit; Preprocess the input data and label data; Build a delay prediction model and train and test it using the preprocessed dataset; The delay prediction model includes a pointer attention-graph neural network module and a multilayer perceptron module. The pointer attention-graph neural network module is used to preprocess the input data, independently process the circuit diagram node features and standard cell library feature embeddings, and concatenate the processed features to obtain the segmented node feature embeddings. The multilayer perceptron module is used to receive the segmented node feature embeddings generated by the pointer attention-graph neural network module and regress the corresponding delay prediction value. The trained delay prediction model is used to predict the delay of each segment in the circuit to be synthesized.

2. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 1, characterized in that, The preprocessing includes the following steps: Convert the circuit described by RTL Verilog into an AIG format circuit; construct a directed acyclic graph G=(V,E) based on the AIG format circuit, where V is the set of nodes, including AND gate nodes and NOT gate nodes, and E is the set of edges, representing the connection relationship between nodes; Using each logical node in the directed acyclic graph as the root node, extract the logical cone region formed by its backpropagation closure, construct multiple cutting subgraphs, and create a cutting supernode for each cutting subgraph. The newly created cutting supernodes are used as new nodes in the directed acyclic graph to form a heterogeneous cut-level graph; structural feature embeddings and functional feature embeddings are constructed for each node in the heterogeneous cut-level graph and spliced ​​together to form the initial node feature embedding. The initial node embedding and corresponding label of each node in the heterogeneous cut-level graph are encapsulated into a graph neural network input data format.

3. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 2, characterized in that, The pointer attention-graph neural network module includes a circuit node feature processing submodule, a standard unit library feature processing submodule, and a feature enhancement submodule; The circuit node feature processing submodule is used to receive the initial node feature embedding of each node in the heterogeneous cutting level graph, and then pass it through two graph convolutional blocks and one pooling layer to extract the local neighborhood information of the node and generate the initial cutting feature embedding. The standard unit library feature processing submodule is used to receive standard unit library feature embeddings, which are then passed through a first RMSNorm layer, a first linear transformation layer, a second RMSNorm layer, and a second linear transformation layer in sequence, and output standardized standard unit library feature embeddings. The feature enhancement submodule receives the initial feature embedding of the cut node and the standardized standard unit library feature embedding. It uses a pointer attention mechanism to dynamically establish the feature association between the cut node and the standard unit library, outputs the pointer attention enhanced feature, and then concatenates the initial feature embedding of the cut node and the pointer attention enhanced feature to form the final cut node feature embedding, which is used for delayed regression prediction of the subsequent multilayer perceptron module.

4. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 3, characterized in that, The graph convolutional block consists of one layer of graph convolution operation and one layer of activation function operation. The input of the first graph convolutional block is the initial node feature embedding, and the input of the second graph convolutional block is the activation result output by the first graph convolutional block. The pooling layer is used to perform a pooling operation on the feature embeddings of all nodes in the logical cone region corresponding to each cut node to obtain the preliminary feature embedding representation of the cut node.

5. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 3, characterized in that, The first and second RMSNorm layers have the same structure and both use root mean square normalization; both the first and second linear transformation layers use fully connected linear mapping.

6. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 2, characterized in that, The structural feature embedding includes node type, topology level, and fan-out number; the functional feature embedding includes the node's controllability index, observability index, and its type identifier in the circuit logic.

7. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 6, characterized in that, The node type is 0 or 1, where 0 represents an AND node and 1 represents a NOT node; the topology level refers to the number of nodes on the longest path from any main input to the node; the fan-out number refers to the number of outputs of the node.

8. The logic synthesis segmentation delay prediction method based on graph neural networks according to claim 1, characterized in that, The multilayer perceptron module includes a first linear layer, a first activation function layer, a first random deactivation layer, a second linear layer, a second activation function layer, a second random deactivation layer, a third linear layer, and a third activation function layer, which are cascaded together to output the predicted delay value of the cut.

9. An electronic device comprising a processor and a memory, characterized in that, The memory stores machine-executable instructions that can be executed by the processor to implement the method as described in any one of claims 1-8.

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